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Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_39 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_354 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_356 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_39( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_354 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_356 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_34 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_44 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_34( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_44 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_15 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_15 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T
module IntSyncCrossingSource_n1x1_15( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_15 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_165 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_182 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_165( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_182 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_461 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_461( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1572 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1573 = and(_T_1571, _T_1572) node _T_1574 = or(UInt<1>(0h0), _T_1573) node _T_1575 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<13>(0h1000))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = and(_T_1574, _T_1579) node _T_1581 = or(UInt<1>(0h0), _T_1580) node _T_1582 = and(_T_1570, _T_1581) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_36 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(source_ok, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(is_aligned, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1592 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(_T_1592, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1592, UInt<1>(0h1), "") : assert_39 node _T_1596 = eq(io.in.a.bits.mask, mask) node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(_T_1596, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1596, UInt<1>(0h1), "") : assert_40 node _T_1600 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1600 : node _T_1601 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1602 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1603 = and(_T_1601, _T_1602) node _T_1604 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1605 = shr(io.in.a.bits.source, 2) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) node _T_1607 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1608 = and(_T_1606, _T_1607) node _T_1609 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1610 = and(_T_1608, _T_1609) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1611 = shr(io.in.a.bits.source, 2) node _T_1612 = eq(_T_1611, UInt<1>(0h1)) node _T_1613 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1614 = and(_T_1612, _T_1613) node _T_1615 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1616 = and(_T_1614, _T_1615) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1617 = shr(io.in.a.bits.source, 2) node _T_1618 = eq(_T_1617, UInt<2>(0h2)) node _T_1619 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1620 = and(_T_1618, _T_1619) node _T_1621 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1622 = and(_T_1620, _T_1621) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1623 = shr(io.in.a.bits.source, 2) node _T_1624 = eq(_T_1623, UInt<2>(0h3)) node _T_1625 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1626 = and(_T_1624, _T_1625) node _T_1627 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1638 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1639 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1640 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1662 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1663 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1664 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1665 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1666 = or(_T_1604, _T_1610) node _T_1667 = or(_T_1666, _T_1616) node _T_1668 = or(_T_1667, _T_1622) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = or(_T_1703, _T_1663) node _T_1705 = or(_T_1704, _T_1664) node _T_1706 = or(_T_1705, _T_1665) node _T_1707 = and(_T_1603, _T_1706) node _T_1708 = or(UInt<1>(0h0), _T_1707) node _T_1709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1710 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1711 = and(_T_1709, _T_1710) node _T_1712 = or(UInt<1>(0h0), _T_1711) node _T_1713 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1714 = cvt(_T_1713) node _T_1715 = and(_T_1714, asSInt(UInt<13>(0h1000))) node _T_1716 = asSInt(_T_1715) node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0))) node _T_1718 = and(_T_1712, _T_1717) node _T_1719 = or(UInt<1>(0h0), _T_1718) node _T_1720 = and(_T_1708, _T_1719) node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(_T_1720, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1720, UInt<1>(0h1), "") : assert_41 node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(source_ok, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(is_aligned, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1730 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_44 node _T_1734 = eq(io.in.a.bits.mask, mask) node _T_1735 = asUInt(reset) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) when _T_1736 : node _T_1737 = eq(_T_1734, UInt<1>(0h0)) when _T_1737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1734, UInt<1>(0h1), "") : assert_45 node _T_1738 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1738 : node _T_1739 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1740 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1741 = and(_T_1739, _T_1740) node _T_1742 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<1>(0h1)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h2)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1761 = shr(io.in.a.bits.source, 2) node _T_1762 = eq(_T_1761, UInt<2>(0h3)) node _T_1763 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1764 = and(_T_1762, _T_1763) node _T_1765 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1766 = and(_T_1764, _T_1765) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1773 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1774 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1775 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1776 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1777 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1778 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1797 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1798 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1799 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1800 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1801 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1802 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1803 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1804 = or(_T_1742, _T_1748) node _T_1805 = or(_T_1804, _T_1754) node _T_1806 = or(_T_1805, _T_1760) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = or(_T_1838, _T_1798) node _T_1840 = or(_T_1839, _T_1799) node _T_1841 = or(_T_1840, _T_1800) node _T_1842 = or(_T_1841, _T_1801) node _T_1843 = or(_T_1842, _T_1802) node _T_1844 = or(_T_1843, _T_1803) node _T_1845 = and(_T_1741, _T_1844) node _T_1846 = or(UInt<1>(0h0), _T_1845) node _T_1847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = or(UInt<1>(0h0), _T_1849) node _T_1851 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1852 = cvt(_T_1851) node _T_1853 = and(_T_1852, asSInt(UInt<13>(0h1000))) node _T_1854 = asSInt(_T_1853) node _T_1855 = eq(_T_1854, asSInt(UInt<1>(0h0))) node _T_1856 = and(_T_1850, _T_1855) node _T_1857 = or(UInt<1>(0h0), _T_1856) node _T_1858 = and(_T_1846, _T_1857) node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(_T_1858, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1858, UInt<1>(0h1), "") : assert_46 node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(source_ok, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1868 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_49 node _T_1872 = eq(io.in.a.bits.mask, mask) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_50 node _T_1876 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1877 = asUInt(reset) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : node _T_1879 = eq(_T_1876, UInt<1>(0h0)) when _T_1879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1876, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1880 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1881 = asUInt(reset) node _T_1882 = eq(_T_1881, UInt<1>(0h0)) when _T_1882 : node _T_1883 = eq(_T_1880, UInt<1>(0h0)) when _T_1883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1880, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1884 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1884 : node _T_1885 = asUInt(reset) node _T_1886 = eq(_T_1885, UInt<1>(0h0)) when _T_1886 : node _T_1887 = eq(source_ok_1, UInt<1>(0h0)) when _T_1887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1888 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1889 = asUInt(reset) node _T_1890 = eq(_T_1889, UInt<1>(0h0)) when _T_1890 : node _T_1891 = eq(_T_1888, UInt<1>(0h0)) when _T_1891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1888, UInt<1>(0h1), "") : assert_54 node _T_1892 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1893 = asUInt(reset) node _T_1894 = eq(_T_1893, UInt<1>(0h0)) when _T_1894 : node _T_1895 = eq(_T_1892, UInt<1>(0h0)) when _T_1895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1892, UInt<1>(0h1), "") : assert_55 node _T_1896 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1897 = asUInt(reset) node _T_1898 = eq(_T_1897, UInt<1>(0h0)) when _T_1898 : node _T_1899 = eq(_T_1896, UInt<1>(0h0)) when _T_1899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1896, UInt<1>(0h1), "") : assert_56 node _T_1900 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1901 = asUInt(reset) node _T_1902 = eq(_T_1901, UInt<1>(0h0)) when _T_1902 : node _T_1903 = eq(_T_1900, UInt<1>(0h0)) when _T_1903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1900, UInt<1>(0h1), "") : assert_57 node _T_1904 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1904 : node _T_1905 = asUInt(reset) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) when _T_1906 : node _T_1907 = eq(source_ok_1, UInt<1>(0h0)) when _T_1907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1908 = asUInt(reset) node _T_1909 = eq(_T_1908, UInt<1>(0h0)) when _T_1909 : node _T_1910 = eq(sink_ok, UInt<1>(0h0)) when _T_1910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1911 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1912 = asUInt(reset) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) when _T_1913 : node _T_1914 = eq(_T_1911, UInt<1>(0h0)) when _T_1914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1911, UInt<1>(0h1), "") : assert_60 node _T_1915 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(_T_1915, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1915, UInt<1>(0h1), "") : assert_61 node _T_1919 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_62 node _T_1923 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_63 node _T_1927 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1928 = or(UInt<1>(0h1), _T_1927) node _T_1929 = asUInt(reset) node _T_1930 = eq(_T_1929, UInt<1>(0h0)) when _T_1930 : node _T_1931 = eq(_T_1928, UInt<1>(0h0)) when _T_1931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1928, UInt<1>(0h1), "") : assert_64 node _T_1932 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1932 : node _T_1933 = asUInt(reset) node _T_1934 = eq(_T_1933, UInt<1>(0h0)) when _T_1934 : node _T_1935 = eq(source_ok_1, UInt<1>(0h0)) when _T_1935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1936 = asUInt(reset) node _T_1937 = eq(_T_1936, UInt<1>(0h0)) when _T_1937 : node _T_1938 = eq(sink_ok, UInt<1>(0h0)) when _T_1938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1939 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_67 node _T_1943 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_68 node _T_1947 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1948 = asUInt(reset) node _T_1949 = eq(_T_1948, UInt<1>(0h0)) when _T_1949 : node _T_1950 = eq(_T_1947, UInt<1>(0h0)) when _T_1950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1947, UInt<1>(0h1), "") : assert_69 node _T_1951 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1952 = or(_T_1951, io.in.d.bits.corrupt) node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(_T_1952, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1952, UInt<1>(0h1), "") : assert_70 node _T_1956 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1957 = or(UInt<1>(0h1), _T_1956) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_71 node _T_1961 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1961 : node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(source_ok_1, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1965 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_73 node _T_1969 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_74 node _T_1973 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1974 = or(UInt<1>(0h1), _T_1973) node _T_1975 = asUInt(reset) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : node _T_1977 = eq(_T_1974, UInt<1>(0h0)) when _T_1977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1974, UInt<1>(0h1), "") : assert_75 node _T_1978 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1978 : node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(source_ok_1, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1982 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1983 = asUInt(reset) node _T_1984 = eq(_T_1983, UInt<1>(0h0)) when _T_1984 : node _T_1985 = eq(_T_1982, UInt<1>(0h0)) when _T_1985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1982, UInt<1>(0h1), "") : assert_77 node _T_1986 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1987 = or(_T_1986, io.in.d.bits.corrupt) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_78 node _T_1991 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1992 = or(UInt<1>(0h1), _T_1991) node _T_1993 = asUInt(reset) node _T_1994 = eq(_T_1993, UInt<1>(0h0)) when _T_1994 : node _T_1995 = eq(_T_1992, UInt<1>(0h0)) when _T_1995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1992, UInt<1>(0h1), "") : assert_79 node _T_1996 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1996 : node _T_1997 = asUInt(reset) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(source_ok_1, UInt<1>(0h0)) when _T_1999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2000 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_81 node _T_2004 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_82 node _T_2008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2009 = or(UInt<1>(0h1), _T_2008) node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(_T_2009, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2009, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2013 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2017 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2021 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2025 = eq(a_first, UInt<1>(0h0)) node _T_2026 = and(io.in.a.valid, _T_2025) when _T_2026 : node _T_2027 = eq(io.in.a.bits.opcode, opcode) node _T_2028 = asUInt(reset) node _T_2029 = eq(_T_2028, UInt<1>(0h0)) when _T_2029 : node _T_2030 = eq(_T_2027, UInt<1>(0h0)) when _T_2030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2027, UInt<1>(0h1), "") : assert_87 node _T_2031 = eq(io.in.a.bits.param, param) node _T_2032 = asUInt(reset) node _T_2033 = eq(_T_2032, UInt<1>(0h0)) when _T_2033 : node _T_2034 = eq(_T_2031, UInt<1>(0h0)) when _T_2034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2031, UInt<1>(0h1), "") : assert_88 node _T_2035 = eq(io.in.a.bits.size, size) node _T_2036 = asUInt(reset) node _T_2037 = eq(_T_2036, UInt<1>(0h0)) when _T_2037 : node _T_2038 = eq(_T_2035, UInt<1>(0h0)) when _T_2038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2035, UInt<1>(0h1), "") : assert_89 node _T_2039 = eq(io.in.a.bits.source, source) node _T_2040 = asUInt(reset) node _T_2041 = eq(_T_2040, UInt<1>(0h0)) when _T_2041 : node _T_2042 = eq(_T_2039, UInt<1>(0h0)) when _T_2042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2039, UInt<1>(0h1), "") : assert_90 node _T_2043 = eq(io.in.a.bits.address, address) node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(_T_2043, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2043, UInt<1>(0h1), "") : assert_91 node _T_2047 = and(io.in.a.ready, io.in.a.valid) node _T_2048 = and(_T_2047, a_first) when _T_2048 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2049 = eq(d_first, UInt<1>(0h0)) node _T_2050 = and(io.in.d.valid, _T_2049) when _T_2050 : node _T_2051 = eq(io.in.d.bits.opcode, opcode_1) node _T_2052 = asUInt(reset) node _T_2053 = eq(_T_2052, UInt<1>(0h0)) when _T_2053 : node _T_2054 = eq(_T_2051, UInt<1>(0h0)) when _T_2054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2051, UInt<1>(0h1), "") : assert_92 node _T_2055 = eq(io.in.d.bits.param, param_1) node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(_T_2055, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2055, UInt<1>(0h1), "") : assert_93 node _T_2059 = eq(io.in.d.bits.size, size_1) node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(_T_2059, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2059, UInt<1>(0h1), "") : assert_94 node _T_2063 = eq(io.in.d.bits.source, source_1) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_95 node _T_2067 = eq(io.in.d.bits.sink, sink) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_96 node _T_2071 = eq(io.in.d.bits.denied, denied) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_97 node _T_2075 = and(io.in.d.ready, io.in.d.valid) node _T_2076 = and(_T_2075, d_first) when _T_2076 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2077 = and(io.in.a.valid, a_first_1) node _T_2078 = and(_T_2077, UInt<1>(0h1)) when _T_2078 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2079 = and(io.in.a.ready, io.in.a.valid) node _T_2080 = and(_T_2079, a_first_1) node _T_2081 = and(_T_2080, UInt<1>(0h1)) when _T_2081 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2082 = dshr(inflight, io.in.a.bits.source) node _T_2083 = bits(_T_2082, 0, 0) node _T_2084 = eq(_T_2083, UInt<1>(0h0)) node _T_2085 = asUInt(reset) node _T_2086 = eq(_T_2085, UInt<1>(0h0)) when _T_2086 : node _T_2087 = eq(_T_2084, UInt<1>(0h0)) when _T_2087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2084, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2092 = and(io.in.d.ready, io.in.d.valid) node _T_2093 = and(_T_2092, d_first_1) node _T_2094 = and(_T_2093, UInt<1>(0h1)) node _T_2095 = eq(d_release_ack, UInt<1>(0h0)) node _T_2096 = and(_T_2094, _T_2095) when _T_2096 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2097 = and(io.in.d.valid, d_first_1) node _T_2098 = and(_T_2097, UInt<1>(0h1)) node _T_2099 = eq(d_release_ack, UInt<1>(0h0)) node _T_2100 = and(_T_2098, _T_2099) when _T_2100 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2101 = dshr(inflight, io.in.d.bits.source) node _T_2102 = bits(_T_2101, 0, 0) node _T_2103 = or(_T_2102, same_cycle_resp) node _T_2104 = asUInt(reset) node _T_2105 = eq(_T_2104, UInt<1>(0h0)) when _T_2105 : node _T_2106 = eq(_T_2103, UInt<1>(0h0)) when _T_2106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2103, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2107 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2108 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2109 = or(_T_2107, _T_2108) node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(_T_2109, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2109, UInt<1>(0h1), "") : assert_100 node _T_2113 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_101 else : node _T_2117 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2119 = or(_T_2117, _T_2118) node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(_T_2119, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2119, UInt<1>(0h1), "") : assert_102 node _T_2123 = eq(io.in.d.bits.size, a_size_lookup) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_103 node _T_2127 = and(io.in.d.valid, d_first_1) node _T_2128 = and(_T_2127, a_first_1) node _T_2129 = and(_T_2128, io.in.a.valid) node _T_2130 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2131 = and(_T_2129, _T_2130) node _T_2132 = eq(d_release_ack, UInt<1>(0h0)) node _T_2133 = and(_T_2131, _T_2132) when _T_2133 : node _T_2134 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2135 = or(_T_2134, io.in.a.ready) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_104 node _T_2139 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2140 = orr(a_set_wo_ready) node _T_2141 = eq(_T_2140, UInt<1>(0h0)) node _T_2142 = or(_T_2139, _T_2141) node _T_2143 = asUInt(reset) node _T_2144 = eq(_T_2143, UInt<1>(0h0)) when _T_2144 : node _T_2145 = eq(_T_2142, UInt<1>(0h0)) when _T_2145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_2142, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_98 node _T_2146 = orr(inflight) node _T_2147 = eq(_T_2146, UInt<1>(0h0)) node _T_2148 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2149 = or(_T_2147, _T_2148) node _T_2150 = lt(watchdog, plusarg_reader.out) node _T_2151 = or(_T_2149, _T_2150) node _T_2152 = asUInt(reset) node _T_2153 = eq(_T_2152, UInt<1>(0h0)) when _T_2153 : node _T_2154 = eq(_T_2151, UInt<1>(0h0)) when _T_2154 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2151, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2155 = and(io.in.a.ready, io.in.a.valid) node _T_2156 = and(io.in.d.ready, io.in.d.valid) node _T_2157 = or(_T_2155, _T_2156) when _T_2157 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2158 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2159 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2160 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2161 = and(_T_2159, _T_2160) node _T_2162 = and(_T_2158, _T_2161) when _T_2162 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2163 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2164 = and(_T_2163, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2165 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2166 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2167 = and(_T_2165, _T_2166) node _T_2168 = and(_T_2164, _T_2167) when _T_2168 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2169 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2175 = and(io.in.d.valid, d_first_2) node _T_2176 = and(_T_2175, UInt<1>(0h1)) node _T_2177 = and(_T_2176, d_release_ack_1) when _T_2177 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2178 = and(io.in.d.ready, io.in.d.valid) node _T_2179 = and(_T_2178, d_first_2) node _T_2180 = and(_T_2179, UInt<1>(0h1)) node _T_2181 = and(_T_2180, d_release_ack_1) when _T_2181 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2182 = and(io.in.d.valid, d_first_2) node _T_2183 = and(_T_2182, UInt<1>(0h1)) node _T_2184 = and(_T_2183, d_release_ack_1) when _T_2184 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2185 = dshr(inflight_1, io.in.d.bits.source) node _T_2186 = bits(_T_2185, 0, 0) node _T_2187 = or(_T_2186, same_cycle_resp_1) node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(_T_2187, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2187, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2191 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2192 = asUInt(reset) node _T_2193 = eq(_T_2192, UInt<1>(0h0)) when _T_2193 : node _T_2194 = eq(_T_2191, UInt<1>(0h0)) when _T_2194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2191, UInt<1>(0h1), "") : assert_109 else : node _T_2195 = eq(io.in.d.bits.size, c_size_lookup) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_110 node _T_2199 = and(io.in.d.valid, d_first_2) node _T_2200 = and(_T_2199, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2201 = and(_T_2200, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2202 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2203 = and(_T_2201, _T_2202) node _T_2204 = and(_T_2203, d_release_ack_1) node _T_2205 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2206 = and(_T_2204, _T_2205) when _T_2206 : node _T_2207 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2208 = or(_T_2207, _WIRE_27.ready) node _T_2209 = asUInt(reset) node _T_2210 = eq(_T_2209, UInt<1>(0h0)) when _T_2210 : node _T_2211 = eq(_T_2208, UInt<1>(0h0)) when _T_2211 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_2208, UInt<1>(0h1), "") : assert_111 node _T_2212 = orr(c_set_wo_ready) when _T_2212 : node _T_2213 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : node _T_2216 = eq(_T_2213, UInt<1>(0h0)) when _T_2216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_2213, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_99 node _T_2217 = orr(inflight_1) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) node _T_2219 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2220 = or(_T_2218, _T_2219) node _T_2221 = lt(watchdog_1, plusarg_reader_1.out) node _T_2222 = or(_T_2220, _T_2221) node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(_T_2222, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_2222, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2226 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2227 = and(io.in.d.ready, io.in.d.valid) node _T_2228 = or(_T_2226, _T_2227) when _T_2228 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_4 : input clock : Clock input reset : Reset output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]} connect io.xcpt_if, UInt<1>(0h0) connect io.xcpt_ld, UInt<1>(0h0) connect io.xcpt_st, UInt<1>(0h0) connect io.debug_if, UInt<1>(0h0) connect io.debug_ld, UInt<1>(0h0) connect io.debug_st, UInt<1>(0h0)
module BreakpointUnit_4( // @[Breakpoint.scala:79:7] input clock, // @[Breakpoint.scala:79:7] input reset, // @[Breakpoint.scala:79:7] input io_status_debug, // @[Breakpoint.scala:80:14] input io_status_cease, // @[Breakpoint.scala:80:14] input io_status_wfi, // @[Breakpoint.scala:80:14] input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14] input io_status_dv, // @[Breakpoint.scala:80:14] input [1:0] io_status_prv, // @[Breakpoint.scala:80:14] input io_status_v, // @[Breakpoint.scala:80:14] input io_status_sd, // @[Breakpoint.scala:80:14] input io_status_mpv, // @[Breakpoint.scala:80:14] input io_status_gva, // @[Breakpoint.scala:80:14] input io_status_tsr, // @[Breakpoint.scala:80:14] input io_status_tw, // @[Breakpoint.scala:80:14] input io_status_tvm, // @[Breakpoint.scala:80:14] input io_status_mxr, // @[Breakpoint.scala:80:14] input io_status_sum, // @[Breakpoint.scala:80:14] input io_status_mprv, // @[Breakpoint.scala:80:14] input [1:0] io_status_fs, // @[Breakpoint.scala:80:14] input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14] input io_status_spp, // @[Breakpoint.scala:80:14] input io_status_mpie, // @[Breakpoint.scala:80:14] input io_status_spie, // @[Breakpoint.scala:80:14] input io_status_mie, // @[Breakpoint.scala:80:14] input io_status_sie, // @[Breakpoint.scala:80:14] input [38:0] io_ea // @[Breakpoint.scala:80:14] ); wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7] wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7] wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7] wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7] wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7] wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7] wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7] wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7] wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7] wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7] wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7] wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7] wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7] wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7] wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7] wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7] wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7] wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7] wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7] wire [38:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7] wire [38:0] io_pc = 39'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14] wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7] wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7] wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7] wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7] wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7] wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7] wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7] wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14] wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w2_i0_2 : input clock : Clock input reset : Reset output io : { flip d : UInt<2>, q : UInt<2>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<2>, clock, _reg_T, UInt<2>(0h0) when io.en : connect reg, io.d connect io.q, reg
module AsyncResetRegVec_w2_i0_2( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input [1:0] io_d, // @[AsyncResetReg.scala:59:14] output [1:0] io_q // @[AsyncResetReg.scala:59:14] ); wire [1:0] io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire [1:0] io_q_0; // @[AsyncResetReg.scala:56:7] reg [1:0] reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 2'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync : output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[1], hgDebugInt : UInt<1>[1], flip hartIsInReset : UInt<1>[1]} input rf_reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst dmInner of TLDebugModuleInner connect dmInner.clock, childClock connect dmInner.reset, childReset inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u connect dmiXing.clock, childClock connect dmiXing.reset, childReset connect dmInner.auto.dmi_in, dmiXing.auto.out connect dmInner.auto.tl_in, auto.dmInner_tl_in connect dmInner.auto.custom_in, auto.dmInner_custom_in connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready connect dmiXing.auto.in, auto.dmiXing_in connect childClock, io.debug_clock connect childReset, io.debug_reset inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_27 connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive wire dmactive_synced : UInt<1> connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q connect dmInner.clock, io.debug_clock connect dmInner.reset, io.debug_reset connect dmInner.io.tl_clock, io.tl_clock connect dmInner.io.tl_reset, io.tl_reset connect dmInner.io.dmactive, dmactive_synced inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq connect dmInner.io.debugUnavail[0], io.debugUnavail[0] connect io.hgDebugInt, dmInner.io.hgDebugInt connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0]
module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_bufferable = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_modifiable = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_readalloc = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_writealloc = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_fetch = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel = 1'h0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_privileged = 1'h1; // @[AsyncQueue.scala:211:22] wire auto_dmInner_sb2tlOpt_out_a_bits_user_amba_prot_secure = 1'h1; // @[AsyncQueue.scala:211:22] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask node _s0_pc_T = not(io.f0_pc) node _s0_pc_T_1 = or(_s0_pc_T, UInt<3>(0h7)) node s0_pc = not(_s0_pc_T_1) reg s1_pc : UInt, clock connect s1_pc, s0_pc reg s2_pc : UInt, clock connect s2_pc, s1_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid node _s1_update_bits_pc_T = not(io.update.bits.pc) node _s1_update_bits_pc_T_1 = or(_s1_update_bits_pc_T, UInt<3>(0h7)) node _s1_update_bits_pc_T_2 = not(_s1_update_bits_pc_T_1) connect s1_update.bits.pc, _s1_update_bits_pc_T_2 reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s1_meta : { write_way : UInt<1>} reg f3_meta_REG : { write_way : UInt<1>}, clock connect f3_meta_REG, s1_meta reg f3_meta : { write_way : UInt<1>}, clock connect f3_meta, f3_meta_REG connect io.f3_meta, f3_meta.write_way regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<29>}[4][2] wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2] wire s1_req_rebtb : UInt<40> node s1_req_tag = shr(s1_idx, 7) wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4] wire s1_is_br : UInt<1>[4] wire s1_is_jal : UInt<1>[4] node _s1_hit_ohs_T = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T) node _s1_hit_ohs_T_2 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2) wire _s1_hit_ohs_WIRE : UInt<1>[2] connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1 connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3 node _s1_hit_ohs_T_4 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4) node _s1_hit_ohs_T_6 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6) wire _s1_hit_ohs_WIRE_1 : UInt<1>[2] connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5 connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7 node _s1_hit_ohs_T_8 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8) node _s1_hit_ohs_T_10 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10) wire _s1_hit_ohs_WIRE_2 : UInt<1>[2] connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9 connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11 node _s1_hit_ohs_T_12 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12) node _s1_hit_ohs_T_14 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14) wire _s1_hit_ohs_WIRE_3 : UInt<1>[2] connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13 connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15 wire s1_hit_ohs : UInt<1>[2][4] connect s1_hit_ohs[0], _s1_hit_ohs_WIRE connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1 connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2 connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3 node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1]) node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1]) node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1]) node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1]) node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1)) wire s1_targs : UInt<40>[4][2] wire entry_btb : { offset : SInt<13>, extended : UInt<1>} connect entry_btb, s1_req_rbtb[0][0] node _s1_targs_0_0_T = asSInt(s1_pc) node _s1_targs_0_0_T_1 = add(_s1_targs_0_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_0_0_T_2 = tail(_s1_targs_0_0_T_1, 1) node _s1_targs_0_0_T_3 = asSInt(_s1_targs_0_0_T_2) node _s1_targs_0_0_T_4 = add(_s1_targs_0_0_T_3, entry_btb.offset) node _s1_targs_0_0_T_5 = tail(_s1_targs_0_0_T_4, 1) node _s1_targs_0_0_T_6 = asSInt(_s1_targs_0_0_T_5) node _s1_targs_0_0_T_7 = asUInt(_s1_targs_0_0_T_6) node _s1_targs_0_0_T_8 = mux(entry_btb.extended, s1_req_rebtb, _s1_targs_0_0_T_7) connect s1_targs[0][0], _s1_targs_0_0_T_8 wire entry_btb_1 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_1, s1_req_rbtb[1][0] node _s1_targs_1_0_T = asSInt(s1_pc) node _s1_targs_1_0_T_1 = add(_s1_targs_1_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_1_0_T_2 = tail(_s1_targs_1_0_T_1, 1) node _s1_targs_1_0_T_3 = asSInt(_s1_targs_1_0_T_2) node _s1_targs_1_0_T_4 = add(_s1_targs_1_0_T_3, entry_btb_1.offset) node _s1_targs_1_0_T_5 = tail(_s1_targs_1_0_T_4, 1) node _s1_targs_1_0_T_6 = asSInt(_s1_targs_1_0_T_5) node _s1_targs_1_0_T_7 = asUInt(_s1_targs_1_0_T_6) node _s1_targs_1_0_T_8 = mux(entry_btb_1.extended, s1_req_rebtb, _s1_targs_1_0_T_7) connect s1_targs[1][0], _s1_targs_1_0_T_8 node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid) node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0) connect s1_resp[0].valid, _s1_resp_0_valid_T_2 connect s1_resp[0].bits, s1_targs[s1_hit_ways_0][0] node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid) node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br) connect s1_is_br[0], _s1_is_br_0_T_2 node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid) node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0)) node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2) connect s1_is_jal[0], _s1_is_jal_0_T_3 connect io.resp.f1[0], io.resp_in[0].f1[0] connect io.resp.f2[0], io.resp_in[0].f2[0] connect io.resp.f3[0], io.resp_in[0].f3[0] reg REG : UInt<1>, clock connect REG, s1_hits_0 when REG : reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_0_predicted_pc_REG, s1_resp[0] connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG reg io_resp_f2_0_is_br_REG : UInt<1>, clock connect io_resp_f2_0_is_br_REG, s1_is_br[0] connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG reg io_resp_f2_0_is_jal_REG : UInt<1>, clock connect io_resp_f2_0_is_jal_REG, s1_is_jal[0] connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG reg REG_1 : UInt<1>, clock connect REG_1, s1_is_jal[0] when REG_1 : connect io.resp.f2[0].taken, UInt<1>(0h1) reg REG_2 : UInt<1>, clock connect REG_2, s1_hits_0 reg REG_3 : UInt<1>, clock connect REG_3, REG_2 when REG_3 : reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG reg io_resp_f3_0_is_br_REG : UInt<1>, clock connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG reg io_resp_f3_0_is_jal_REG : UInt<1>, clock connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG reg REG_4 : UInt<1>, clock connect REG_4, s1_is_jal[0] reg REG_5 : UInt<1>, clock connect REG_5, REG_4 when REG_5 : connect io.resp.f3[0].taken, UInt<1>(0h1) wire entry_btb_2 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_2, s1_req_rbtb[0][1] node _s1_targs_0_1_T = asSInt(s1_pc) node _s1_targs_0_1_T_1 = add(_s1_targs_0_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_0_1_T_2 = tail(_s1_targs_0_1_T_1, 1) node _s1_targs_0_1_T_3 = asSInt(_s1_targs_0_1_T_2) node _s1_targs_0_1_T_4 = add(_s1_targs_0_1_T_3, entry_btb_2.offset) node _s1_targs_0_1_T_5 = tail(_s1_targs_0_1_T_4, 1) node _s1_targs_0_1_T_6 = asSInt(_s1_targs_0_1_T_5) node _s1_targs_0_1_T_7 = asUInt(_s1_targs_0_1_T_6) node _s1_targs_0_1_T_8 = mux(entry_btb_2.extended, s1_req_rebtb, _s1_targs_0_1_T_7) connect s1_targs[0][1], _s1_targs_0_1_T_8 wire entry_btb_3 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_3, s1_req_rbtb[1][1] node _s1_targs_1_1_T = asSInt(s1_pc) node _s1_targs_1_1_T_1 = add(_s1_targs_1_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_1_1_T_2 = tail(_s1_targs_1_1_T_1, 1) node _s1_targs_1_1_T_3 = asSInt(_s1_targs_1_1_T_2) node _s1_targs_1_1_T_4 = add(_s1_targs_1_1_T_3, entry_btb_3.offset) node _s1_targs_1_1_T_5 = tail(_s1_targs_1_1_T_4, 1) node _s1_targs_1_1_T_6 = asSInt(_s1_targs_1_1_T_5) node _s1_targs_1_1_T_7 = asUInt(_s1_targs_1_1_T_6) node _s1_targs_1_1_T_8 = mux(entry_btb_3.extended, s1_req_rebtb, _s1_targs_1_1_T_7) connect s1_targs[1][1], _s1_targs_1_1_T_8 node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid) node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1) connect s1_resp[1].valid, _s1_resp_1_valid_T_2 connect s1_resp[1].bits, s1_targs[s1_hit_ways_1][1] node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid) node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br) connect s1_is_br[1], _s1_is_br_1_T_2 node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid) node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0)) node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2) connect s1_is_jal[1], _s1_is_jal_1_T_3 connect io.resp.f1[1], io.resp_in[0].f1[1] connect io.resp.f2[1], io.resp_in[0].f2[1] connect io.resp.f3[1], io.resp_in[0].f3[1] reg REG_6 : UInt<1>, clock connect REG_6, s1_hits_1 when REG_6 : reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_1_predicted_pc_REG, s1_resp[1] connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG reg io_resp_f2_1_is_br_REG : UInt<1>, clock connect io_resp_f2_1_is_br_REG, s1_is_br[1] connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG reg io_resp_f2_1_is_jal_REG : UInt<1>, clock connect io_resp_f2_1_is_jal_REG, s1_is_jal[1] connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG reg REG_7 : UInt<1>, clock connect REG_7, s1_is_jal[1] when REG_7 : connect io.resp.f2[1].taken, UInt<1>(0h1) reg REG_8 : UInt<1>, clock connect REG_8, s1_hits_1 reg REG_9 : UInt<1>, clock connect REG_9, REG_8 when REG_9 : reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG reg io_resp_f3_1_is_br_REG : UInt<1>, clock connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG reg io_resp_f3_1_is_jal_REG : UInt<1>, clock connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG reg REG_10 : UInt<1>, clock connect REG_10, s1_is_jal[1] reg REG_11 : UInt<1>, clock connect REG_11, REG_10 when REG_11 : connect io.resp.f3[1].taken, UInt<1>(0h1) wire entry_btb_4 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_4, s1_req_rbtb[0][2] node _s1_targs_0_2_T = asSInt(s1_pc) node _s1_targs_0_2_T_1 = add(_s1_targs_0_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_0_2_T_2 = tail(_s1_targs_0_2_T_1, 1) node _s1_targs_0_2_T_3 = asSInt(_s1_targs_0_2_T_2) node _s1_targs_0_2_T_4 = add(_s1_targs_0_2_T_3, entry_btb_4.offset) node _s1_targs_0_2_T_5 = tail(_s1_targs_0_2_T_4, 1) node _s1_targs_0_2_T_6 = asSInt(_s1_targs_0_2_T_5) node _s1_targs_0_2_T_7 = asUInt(_s1_targs_0_2_T_6) node _s1_targs_0_2_T_8 = mux(entry_btb_4.extended, s1_req_rebtb, _s1_targs_0_2_T_7) connect s1_targs[0][2], _s1_targs_0_2_T_8 wire entry_btb_5 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_5, s1_req_rbtb[1][2] node _s1_targs_1_2_T = asSInt(s1_pc) node _s1_targs_1_2_T_1 = add(_s1_targs_1_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_1_2_T_2 = tail(_s1_targs_1_2_T_1, 1) node _s1_targs_1_2_T_3 = asSInt(_s1_targs_1_2_T_2) node _s1_targs_1_2_T_4 = add(_s1_targs_1_2_T_3, entry_btb_5.offset) node _s1_targs_1_2_T_5 = tail(_s1_targs_1_2_T_4, 1) node _s1_targs_1_2_T_6 = asSInt(_s1_targs_1_2_T_5) node _s1_targs_1_2_T_7 = asUInt(_s1_targs_1_2_T_6) node _s1_targs_1_2_T_8 = mux(entry_btb_5.extended, s1_req_rebtb, _s1_targs_1_2_T_7) connect s1_targs[1][2], _s1_targs_1_2_T_8 node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid) node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2) connect s1_resp[2].valid, _s1_resp_2_valid_T_2 connect s1_resp[2].bits, s1_targs[s1_hit_ways_2][2] node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid) node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br) connect s1_is_br[2], _s1_is_br_2_T_2 node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid) node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0)) node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2) connect s1_is_jal[2], _s1_is_jal_2_T_3 connect io.resp.f1[2], io.resp_in[0].f1[2] connect io.resp.f2[2], io.resp_in[0].f2[2] connect io.resp.f3[2], io.resp_in[0].f3[2] reg REG_12 : UInt<1>, clock connect REG_12, s1_hits_2 when REG_12 : reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_2_predicted_pc_REG, s1_resp[2] connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG reg io_resp_f2_2_is_br_REG : UInt<1>, clock connect io_resp_f2_2_is_br_REG, s1_is_br[2] connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG reg io_resp_f2_2_is_jal_REG : UInt<1>, clock connect io_resp_f2_2_is_jal_REG, s1_is_jal[2] connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG reg REG_13 : UInt<1>, clock connect REG_13, s1_is_jal[2] when REG_13 : connect io.resp.f2[2].taken, UInt<1>(0h1) reg REG_14 : UInt<1>, clock connect REG_14, s1_hits_2 reg REG_15 : UInt<1>, clock connect REG_15, REG_14 when REG_15 : reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG reg io_resp_f3_2_is_br_REG : UInt<1>, clock connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG reg io_resp_f3_2_is_jal_REG : UInt<1>, clock connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG reg REG_16 : UInt<1>, clock connect REG_16, s1_is_jal[2] reg REG_17 : UInt<1>, clock connect REG_17, REG_16 when REG_17 : connect io.resp.f3[2].taken, UInt<1>(0h1) wire entry_btb_6 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_6, s1_req_rbtb[0][3] node _s1_targs_0_3_T = asSInt(s1_pc) node _s1_targs_0_3_T_1 = add(_s1_targs_0_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_0_3_T_2 = tail(_s1_targs_0_3_T_1, 1) node _s1_targs_0_3_T_3 = asSInt(_s1_targs_0_3_T_2) node _s1_targs_0_3_T_4 = add(_s1_targs_0_3_T_3, entry_btb_6.offset) node _s1_targs_0_3_T_5 = tail(_s1_targs_0_3_T_4, 1) node _s1_targs_0_3_T_6 = asSInt(_s1_targs_0_3_T_5) node _s1_targs_0_3_T_7 = asUInt(_s1_targs_0_3_T_6) node _s1_targs_0_3_T_8 = mux(entry_btb_6.extended, s1_req_rebtb, _s1_targs_0_3_T_7) connect s1_targs[0][3], _s1_targs_0_3_T_8 wire entry_btb_7 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_7, s1_req_rbtb[1][3] node _s1_targs_1_3_T = asSInt(s1_pc) node _s1_targs_1_3_T_1 = add(_s1_targs_1_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_1_3_T_2 = tail(_s1_targs_1_3_T_1, 1) node _s1_targs_1_3_T_3 = asSInt(_s1_targs_1_3_T_2) node _s1_targs_1_3_T_4 = add(_s1_targs_1_3_T_3, entry_btb_7.offset) node _s1_targs_1_3_T_5 = tail(_s1_targs_1_3_T_4, 1) node _s1_targs_1_3_T_6 = asSInt(_s1_targs_1_3_T_5) node _s1_targs_1_3_T_7 = asUInt(_s1_targs_1_3_T_6) node _s1_targs_1_3_T_8 = mux(entry_btb_7.extended, s1_req_rebtb, _s1_targs_1_3_T_7) connect s1_targs[1][3], _s1_targs_1_3_T_8 node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid) node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3) connect s1_resp[3].valid, _s1_resp_3_valid_T_2 connect s1_resp[3].bits, s1_targs[s1_hit_ways_3][3] node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid) node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br) connect s1_is_br[3], _s1_is_br_3_T_2 node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid) node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0)) node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2) connect s1_is_jal[3], _s1_is_jal_3_T_3 connect io.resp.f1[3], io.resp_in[0].f1[3] connect io.resp.f2[3], io.resp_in[0].f2[3] connect io.resp.f3[3], io.resp_in[0].f3[3] reg REG_18 : UInt<1>, clock connect REG_18, s1_hits_3 when REG_18 : reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_3_predicted_pc_REG, s1_resp[3] connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG reg io_resp_f2_3_is_br_REG : UInt<1>, clock connect io_resp_f2_3_is_br_REG, s1_is_br[3] connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG reg io_resp_f2_3_is_jal_REG : UInt<1>, clock connect io_resp_f2_3_is_jal_REG, s1_is_jal[3] connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG reg REG_19 : UInt<1>, clock connect REG_19, s1_is_jal[3] when REG_19 : connect io.resp.f2[3].taken, UInt<1>(0h1) reg REG_20 : UInt<1>, clock connect REG_20, s1_hits_3 reg REG_21 : UInt<1>, clock connect REG_21, REG_20 when REG_21 : reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG reg io_resp_f3_3_is_br_REG : UInt<1>, clock connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG reg io_resp_f3_3_is_jal_REG : UInt<1>, clock connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG reg REG_22 : UInt<1>, clock connect REG_22, s1_is_jal[3] reg REG_23 : UInt<1>, clock connect REG_23, REG_22 when REG_23 : connect io.resp.f3[3].taken, UInt<1>(0h1) wire _alloc_way_r_metas_WIRE : UInt<29>[4] connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag wire _alloc_way_r_metas_WIRE_1 : UInt<29>[4] connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag wire _alloc_way_r_metas_WIRE_2 : UInt<29>[4][2] connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1 node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0]) node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2]) node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo) node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0]) node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2]) node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1) node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T) node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 28, 0) node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3) node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0) node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1) node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2) node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3) node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4) node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5) node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6) node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7) node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8) node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9) node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10) node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11) node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12) node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13) node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14) node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15) node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16) node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17) node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18) node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19) node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20) node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21) node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22) node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23) node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24) node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25) node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26) node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27) node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28) node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29) node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30) node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31) node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32) node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33) node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34) node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35) node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36) node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37) node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38) node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39) node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40) node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41) node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42) node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43) node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44) node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45) node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46) node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47) node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48) node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49) node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50) node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51) node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52) node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53) node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54) node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55) node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56) node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57) node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58) node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59) node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60) node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61) node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62) node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63) node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64) node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65) node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66) node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67) node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68) node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69) node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70) node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71) node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72) node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73) node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74) node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75) node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76) node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77) node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78) node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79) node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80) node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81) node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82) node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83) node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84) node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85) node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86) node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87) node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88) node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89) node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90) node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91) node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92) node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93) node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94) node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95) node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96) node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97) node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98) node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99) node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100) node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101) node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102) node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103) node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104) node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105) node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106) node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107) node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108) node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109) node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110) node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111) node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112) node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113) node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114) node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115) node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116) node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117) node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118) node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119) node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120) node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121) node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122) node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123) node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124) node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125) node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126) node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127) node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128) node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129) node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130) node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131) node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132) node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133) node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134) node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135) node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136) node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137) node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138) node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139) node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140) node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141) node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142) node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143) node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144) node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145) node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146) node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147) node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148) node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149) node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150) node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151) node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152) node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153) node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154) node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155) node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156) node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157) node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158) node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159) node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160) node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161) node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162) node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163) node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164) node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165) node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166) node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167) node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168) node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169) node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170) node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171) node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172) node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173) node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174) node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175) node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176) node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177) node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178) node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179) node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180) node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181) node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182) node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183) node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184) node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185) node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186) node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187) node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188) node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189) node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190) node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191) node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192) node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193) node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194) node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195) node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196) node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197) node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198) node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199) node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200) node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201) node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202) node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203) node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204) node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205) node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206) node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207) node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208) node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209) node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210) node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211) node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212) node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213) node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214) node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215) node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216) node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217) node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218) node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219) node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220) node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221) node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222) node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223) node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224) node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225) node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226) node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227) node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228) node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229) node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230) node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231) node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232) node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233) node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234) node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235) node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236) node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237) node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238) node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239) node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240) node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241) node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242) node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243) node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244) node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245) node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246) node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247) node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248) node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249) node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250) node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251) node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252) node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253) node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254) node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255) node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256) node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257) node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258) node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259) node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260) node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1) node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2) node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3) node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4) node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5) node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6) node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7) node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8) node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9) node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10) node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11) node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12) node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13) node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14) node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15) node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16) node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17) node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18) node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19) node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20) node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21) node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22) node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23) node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24) node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25) node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26) node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27) node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28) node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29) node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30) node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31) node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32) node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33) node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34) node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35) node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36) node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37) node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38) node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39) node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40) node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41) node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42) node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43) node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44) node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45) node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46) node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47) node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48) node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49) node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50) node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51) node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52) node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53) node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54) node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55) node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56) node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57) node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58) node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59) node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60) node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61) node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62) node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63) node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64) node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65) node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66) node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67) node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68) node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69) node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70) node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71) node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72) node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73) node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74) node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75) node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76) node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77) node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78) node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79) node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80) node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81) node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82) node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83) node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84) node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85) node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86) node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87) node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88) node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89) node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90) node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91) node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92) node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93) node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94) node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95) node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96) node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97) node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98) node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99) node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100) node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101) node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102) node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103) node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104) node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105) node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106) node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107) node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108) node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109) node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110) node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111) node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112) node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113) node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114) node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115) node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116) node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117) node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118) node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119) node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120) node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121) node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122) node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123) node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124) node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125) node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126) node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127) node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128) node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129) node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130) node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131) node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132) node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133) node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134) node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135) node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136) node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137) node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138) node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139) node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140) node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141) node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142) node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143) node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144) node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145) node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146) node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147) node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148) node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149) node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150) node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151) node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152) node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153) node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154) node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155) node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156) node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157) node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158) node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159) node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160) node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161) node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162) node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163) node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164) node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165) node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166) node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167) node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168) node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169) node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170) node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171) node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172) node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173) node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174) node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175) node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176) node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177) node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178) node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179) node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180) node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181) node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182) node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183) node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184) node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185) node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186) node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187) node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188) node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189) node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190) node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191) node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192) node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193) node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194) node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195) node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196) node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197) node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198) node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199) node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200) node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201) node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202) node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203) node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204) node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205) node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206) node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207) node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208) node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209) node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210) node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211) node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212) node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213) node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214) node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215) node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216) node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217) node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218) node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219) node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220) node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221) node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222) node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223) node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224) node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225) node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226) node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227) node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228) node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229) node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230) node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231) node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232) node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233) node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234) node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235) node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236) node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237) node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238) node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239) node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240) node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241) node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242) node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243) node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244) node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245) node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246) node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247) node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248) node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249) node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250) node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251) node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252) node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253) node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254) node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255) node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256) node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257) node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258) node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259) node alloc_way = xor(_alloc_way_T_258, alloc_way_chunks_260) node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1) node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2) node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3) node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0]) node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0]) node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0]) node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0]) node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4) node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5) node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6) node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0) node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1) node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1)) node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way) connect s1_meta.write_way, _s1_meta_write_way_T_13 wire s1_update_meta : { write_way : UInt<1>} wire _s1_update_meta_WIRE : UInt<1> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0) connect s1_update_meta.write_way, _s1_update_meta_T node _max_offset_value_T = not(UInt<12>(0h0)) node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T) node max_offset_value = asSInt(_max_offset_value_T_1) node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0)) node min_offset_value = asSInt(_min_offset_value_T) node _new_offset_value_T = asSInt(s1_update.bits.target) node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1) node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1) node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1) node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3) node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4) node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1) node new_offset_value = asSInt(_new_offset_value_T_6) node _offset_is_extended_T = gt(new_offset_value, max_offset_value) node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value) node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1) wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>} connect s1_update_wbtb_data.extended, offset_is_extended connect s1_update_wbtb_data.offset, new_offset_value node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid) node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken) node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4) node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6) node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8) node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask) node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2) node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4) node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts) node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8) node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9) wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<29>}[4] node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0) node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1) connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2 node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0) connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1) node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1) connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2 node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1) connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2) node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1) connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2 node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2) connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3) node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1) connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2 node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3) connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T smem btb_meta_way_0 : UInt<30>[4] [128] smem btb_data_way_0 : UInt<14>[4] [128] wire _WIRE : UInt<36> invalidate _WIRE when io.f0_valid : connect _WIRE, s0_idx node _T_1 = bits(_WIRE, 6, 0) read mport MPORT = btb_meta_way_0[_T_1], clock wire _WIRE_1 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_2 : UInt<30> connect _WIRE_2, MPORT[0] node _T_2 = bits(_WIRE_2, 28, 0) connect _WIRE_1.tag, _T_2 node _T_3 = bits(_WIRE_2, 29, 29) connect _WIRE_1.is_br, _T_3 wire _WIRE_3 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_4 : UInt<30> connect _WIRE_4, MPORT[1] node _T_4 = bits(_WIRE_4, 28, 0) connect _WIRE_3.tag, _T_4 node _T_5 = bits(_WIRE_4, 29, 29) connect _WIRE_3.is_br, _T_5 wire _WIRE_5 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_6 : UInt<30> connect _WIRE_6, MPORT[2] node _T_6 = bits(_WIRE_6, 28, 0) connect _WIRE_5.tag, _T_6 node _T_7 = bits(_WIRE_6, 29, 29) connect _WIRE_5.is_br, _T_7 wire _WIRE_7 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_8 : UInt<30> connect _WIRE_8, MPORT[3] node _T_8 = bits(_WIRE_8, 28, 0) connect _WIRE_7.tag, _T_8 node _T_9 = bits(_WIRE_8, 29, 29) connect _WIRE_7.is_br, _T_9 wire _WIRE_9 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].is_br, _WIRE_1.is_br connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].is_br, _WIRE_3.is_br connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].is_br, _WIRE_5.is_br connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].is_br, _WIRE_7.is_br connect s1_req_rmeta[0], _WIRE_9 wire _WIRE_10 : UInt<36> invalidate _WIRE_10 when io.f0_valid : connect _WIRE_10, s0_idx node _T_10 = bits(_WIRE_10, 6, 0) read mport MPORT_1 = btb_data_way_0[_T_10], clock wire _WIRE_11 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_12 : UInt<14> connect _WIRE_12, MPORT_1[0] node _T_11 = bits(_WIRE_12, 0, 0) connect _WIRE_11.extended, _T_11 node _T_12 = bits(_WIRE_12, 13, 1) node _T_13 = asSInt(_T_12) connect _WIRE_11.offset, _T_13 wire _WIRE_13 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_14 : UInt<14> connect _WIRE_14, MPORT_1[1] node _T_14 = bits(_WIRE_14, 0, 0) connect _WIRE_13.extended, _T_14 node _T_15 = bits(_WIRE_14, 13, 1) node _T_16 = asSInt(_T_15) connect _WIRE_13.offset, _T_16 wire _WIRE_15 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_16 : UInt<14> connect _WIRE_16, MPORT_1[2] node _T_17 = bits(_WIRE_16, 0, 0) connect _WIRE_15.extended, _T_17 node _T_18 = bits(_WIRE_16, 13, 1) node _T_19 = asSInt(_T_18) connect _WIRE_15.offset, _T_19 wire _WIRE_17 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_18 : UInt<14> connect _WIRE_18, MPORT_1[3] node _T_20 = bits(_WIRE_18, 0, 0) connect _WIRE_17.extended, _T_20 node _T_21 = bits(_WIRE_18, 13, 1) node _T_22 = asSInt(_T_21) connect _WIRE_17.offset, _T_22 wire _WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_19[0].extended, _WIRE_11.extended connect _WIRE_19[0].offset, _WIRE_11.offset connect _WIRE_19[1].extended, _WIRE_13.extended connect _WIRE_19[1].offset, _WIRE_13.offset connect _WIRE_19[2].extended, _WIRE_15.extended connect _WIRE_19[2].offset, _WIRE_15.offset connect _WIRE_19[3].extended, _WIRE_17.extended connect _WIRE_19[3].offset, _WIRE_17.offset connect s1_req_rbtb[0], _WIRE_19 node _T_23 = eq(s1_update_meta.write_way, UInt<1>(0h0)) node _T_24 = or(doing_reset, _T_23) node _T_25 = or(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_20 : UInt<14>[4] connect _WIRE_20[0], UInt<14>(0h0) connect _WIRE_20[1], UInt<14>(0h0) connect _WIRE_20[2], UInt<14>(0h0) connect _WIRE_20[3], UInt<14>(0h0) node _T_27 = asUInt(s1_update_wbtb_data.offset) node _T_28 = cat(_T_27, s1_update_wbtb_data.extended) node _T_29 = asUInt(s1_update_wbtb_data.offset) node _T_30 = cat(_T_29, s1_update_wbtb_data.extended) node _T_31 = asUInt(s1_update_wbtb_data.offset) node _T_32 = cat(_T_31, s1_update_wbtb_data.extended) node _T_33 = asUInt(s1_update_wbtb_data.offset) node _T_34 = cat(_T_33, s1_update_wbtb_data.extended) wire _WIRE_21 : UInt<14>[4] connect _WIRE_21[0], _T_28 connect _WIRE_21[1], _T_30 connect _WIRE_21[2], _T_32 connect _WIRE_21[3], _T_34 node _T_35 = mux(doing_reset, _WIRE_20, _WIRE_21) node _T_36 = not(UInt<4>(0h0)) node _T_37 = mux(doing_reset, _T_36, s1_update_wbtb_mask) node _T_38 = bits(_T_37, 0, 0) node _T_39 = bits(_T_37, 1, 1) node _T_40 = bits(_T_37, 2, 2) node _T_41 = bits(_T_37, 3, 3) node _T_42 = or(_T_26, UInt<7>(0h0)) node _T_43 = bits(_T_42, 6, 0) write mport MPORT_2 = btb_data_way_0[_T_43], clock when _T_38 : connect MPORT_2[0], _T_35[0] when _T_39 : connect MPORT_2[1], _T_35[1] when _T_40 : connect MPORT_2[2], _T_35[2] when _T_41 : connect MPORT_2[3], _T_35[3] node _T_44 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_22 : UInt<30>[4] connect _WIRE_22[0], UInt<30>(0h0) connect _WIRE_22[1], UInt<30>(0h0) connect _WIRE_22[2], UInt<30>(0h0) connect _WIRE_22[3], UInt<30>(0h0) node _T_45 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_46 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_47 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_48 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_23 : UInt<30>[4] connect _WIRE_23[0], _T_45 connect _WIRE_23[1], _T_46 connect _WIRE_23[2], _T_47 connect _WIRE_23[3], _T_48 node _T_49 = mux(doing_reset, _WIRE_22, _WIRE_23) node _T_50 = not(UInt<4>(0h0)) node _T_51 = mux(doing_reset, _T_50, s1_update_wmeta_mask) node _T_52 = bits(_T_51, 0, 0) node _T_53 = bits(_T_51, 1, 1) node _T_54 = bits(_T_51, 2, 2) node _T_55 = bits(_T_51, 3, 3) node _T_56 = or(_T_44, UInt<7>(0h0)) node _T_57 = bits(_T_56, 6, 0) write mport MPORT_3 = btb_meta_way_0[_T_57], clock when _T_52 : connect MPORT_3[0], _T_49[0] when _T_53 : connect MPORT_3[1], _T_49[1] when _T_54 : connect MPORT_3[2], _T_49[2] when _T_55 : connect MPORT_3[3], _T_49[3] smem btb_meta_way_1 : UInt<30>[4] [128] smem btb_data_way_1 : UInt<14>[4] [128] wire _WIRE_24 : UInt<36> invalidate _WIRE_24 when io.f0_valid : connect _WIRE_24, s0_idx node _T_58 = bits(_WIRE_24, 6, 0) read mport MPORT_4 = btb_meta_way_1[_T_58], clock wire _WIRE_25 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_26 : UInt<30> connect _WIRE_26, MPORT_4[0] node _T_59 = bits(_WIRE_26, 28, 0) connect _WIRE_25.tag, _T_59 node _T_60 = bits(_WIRE_26, 29, 29) connect _WIRE_25.is_br, _T_60 wire _WIRE_27 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_28 : UInt<30> connect _WIRE_28, MPORT_4[1] node _T_61 = bits(_WIRE_28, 28, 0) connect _WIRE_27.tag, _T_61 node _T_62 = bits(_WIRE_28, 29, 29) connect _WIRE_27.is_br, _T_62 wire _WIRE_29 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_30 : UInt<30> connect _WIRE_30, MPORT_4[2] node _T_63 = bits(_WIRE_30, 28, 0) connect _WIRE_29.tag, _T_63 node _T_64 = bits(_WIRE_30, 29, 29) connect _WIRE_29.is_br, _T_64 wire _WIRE_31 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_32 : UInt<30> connect _WIRE_32, MPORT_4[3] node _T_65 = bits(_WIRE_32, 28, 0) connect _WIRE_31.tag, _T_65 node _T_66 = bits(_WIRE_32, 29, 29) connect _WIRE_31.is_br, _T_66 wire _WIRE_33 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _WIRE_33[0].tag, _WIRE_25.tag connect _WIRE_33[0].is_br, _WIRE_25.is_br connect _WIRE_33[1].tag, _WIRE_27.tag connect _WIRE_33[1].is_br, _WIRE_27.is_br connect _WIRE_33[2].tag, _WIRE_29.tag connect _WIRE_33[2].is_br, _WIRE_29.is_br connect _WIRE_33[3].tag, _WIRE_31.tag connect _WIRE_33[3].is_br, _WIRE_31.is_br connect s1_req_rmeta[1], _WIRE_33 wire _WIRE_34 : UInt<36> invalidate _WIRE_34 when io.f0_valid : connect _WIRE_34, s0_idx node _T_67 = bits(_WIRE_34, 6, 0) read mport MPORT_5 = btb_data_way_1[_T_67], clock wire _WIRE_35 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_36 : UInt<14> connect _WIRE_36, MPORT_5[0] node _T_68 = bits(_WIRE_36, 0, 0) connect _WIRE_35.extended, _T_68 node _T_69 = bits(_WIRE_36, 13, 1) node _T_70 = asSInt(_T_69) connect _WIRE_35.offset, _T_70 wire _WIRE_37 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_38 : UInt<14> connect _WIRE_38, MPORT_5[1] node _T_71 = bits(_WIRE_38, 0, 0) connect _WIRE_37.extended, _T_71 node _T_72 = bits(_WIRE_38, 13, 1) node _T_73 = asSInt(_T_72) connect _WIRE_37.offset, _T_73 wire _WIRE_39 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_40 : UInt<14> connect _WIRE_40, MPORT_5[2] node _T_74 = bits(_WIRE_40, 0, 0) connect _WIRE_39.extended, _T_74 node _T_75 = bits(_WIRE_40, 13, 1) node _T_76 = asSInt(_T_75) connect _WIRE_39.offset, _T_76 wire _WIRE_41 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_42 : UInt<14> connect _WIRE_42, MPORT_5[3] node _T_77 = bits(_WIRE_42, 0, 0) connect _WIRE_41.extended, _T_77 node _T_78 = bits(_WIRE_42, 13, 1) node _T_79 = asSInt(_T_78) connect _WIRE_41.offset, _T_79 wire _WIRE_43 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_43[0].extended, _WIRE_35.extended connect _WIRE_43[0].offset, _WIRE_35.offset connect _WIRE_43[1].extended, _WIRE_37.extended connect _WIRE_43[1].offset, _WIRE_37.offset connect _WIRE_43[2].extended, _WIRE_39.extended connect _WIRE_43[2].offset, _WIRE_39.offset connect _WIRE_43[3].extended, _WIRE_41.extended connect _WIRE_43[3].offset, _WIRE_41.offset connect s1_req_rbtb[1], _WIRE_43 node _T_80 = eq(s1_update_meta.write_way, UInt<1>(0h1)) node _T_81 = or(doing_reset, _T_80) node _T_82 = or(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_44 : UInt<14>[4] connect _WIRE_44[0], UInt<14>(0h0) connect _WIRE_44[1], UInt<14>(0h0) connect _WIRE_44[2], UInt<14>(0h0) connect _WIRE_44[3], UInt<14>(0h0) node _T_84 = asUInt(s1_update_wbtb_data.offset) node _T_85 = cat(_T_84, s1_update_wbtb_data.extended) node _T_86 = asUInt(s1_update_wbtb_data.offset) node _T_87 = cat(_T_86, s1_update_wbtb_data.extended) node _T_88 = asUInt(s1_update_wbtb_data.offset) node _T_89 = cat(_T_88, s1_update_wbtb_data.extended) node _T_90 = asUInt(s1_update_wbtb_data.offset) node _T_91 = cat(_T_90, s1_update_wbtb_data.extended) wire _WIRE_45 : UInt<14>[4] connect _WIRE_45[0], _T_85 connect _WIRE_45[1], _T_87 connect _WIRE_45[2], _T_89 connect _WIRE_45[3], _T_91 node _T_92 = mux(doing_reset, _WIRE_44, _WIRE_45) node _T_93 = not(UInt<4>(0h0)) node _T_94 = mux(doing_reset, _T_93, s1_update_wbtb_mask) node _T_95 = bits(_T_94, 0, 0) node _T_96 = bits(_T_94, 1, 1) node _T_97 = bits(_T_94, 2, 2) node _T_98 = bits(_T_94, 3, 3) node _T_99 = or(_T_83, UInt<7>(0h0)) node _T_100 = bits(_T_99, 6, 0) write mport MPORT_6 = btb_data_way_1[_T_100], clock when _T_95 : connect MPORT_6[0], _T_92[0] when _T_96 : connect MPORT_6[1], _T_92[1] when _T_97 : connect MPORT_6[2], _T_92[2] when _T_98 : connect MPORT_6[3], _T_92[3] node _T_101 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_46 : UInt<30>[4] connect _WIRE_46[0], UInt<30>(0h0) connect _WIRE_46[1], UInt<30>(0h0) connect _WIRE_46[2], UInt<30>(0h0) connect _WIRE_46[3], UInt<30>(0h0) node _T_102 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_103 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_104 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_105 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_47 : UInt<30>[4] connect _WIRE_47[0], _T_102 connect _WIRE_47[1], _T_103 connect _WIRE_47[2], _T_104 connect _WIRE_47[3], _T_105 node _T_106 = mux(doing_reset, _WIRE_46, _WIRE_47) node _T_107 = not(UInt<4>(0h0)) node _T_108 = mux(doing_reset, _T_107, s1_update_wmeta_mask) node _T_109 = bits(_T_108, 0, 0) node _T_110 = bits(_T_108, 1, 1) node _T_111 = bits(_T_108, 2, 2) node _T_112 = bits(_T_108, 3, 3) node _T_113 = or(_T_101, UInt<7>(0h0)) node _T_114 = bits(_T_113, 6, 0) write mport MPORT_7 = btb_meta_way_1[_T_114], clock when _T_109 : connect MPORT_7[0], _T_106[0] when _T_110 : connect MPORT_7[1], _T_106[1] when _T_111 : connect MPORT_7[2], _T_106[2] when _T_112 : connect MPORT_7[3], _T_106[3] smem btb_ebtb : UInt<40> [128] wire _s1_req_rebtb_WIRE : UInt<36> invalidate _s1_req_rebtb_WIRE when io.f0_valid : connect _s1_req_rebtb_WIRE, s0_idx node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0) read mport s1_req_rebtb_MPORT = btb_ebtb[_s1_req_rebtb_T], clock connect s1_req_rebtb, s1_req_rebtb_MPORT node _T_115 = neq(s1_update_wbtb_mask, UInt<1>(0h0)) node _T_116 = and(_T_115, offset_is_extended) when _T_116 : node _T_117 = or(s1_update_idx, UInt<7>(0h0)) node _T_118 = bits(_T_117, 6, 0) write mport MPORT_8 = btb_ebtb[_T_118], clock connect MPORT_8, s1_update.bits.target
module BTBBranchPredictorBank_1( // @[btb.scala:24:7] input clock, // @[btb.scala:24:7] input reset, // @[btb.scala:24:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [29:0] btb_meta_way_1_MPORT_7_data_3; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_2; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_1; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_1_MPORT_6_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_0; // @[btb.scala:201:14] wire [29:0] btb_meta_way_0_MPORT_3_data_3; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_2; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_1; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_0_MPORT_2_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_0; // @[btb.scala:201:14] wire _s1_update_meta_WIRE; // @[btb.scala:139:55] wire s1_req_rbtb_1_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_0_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_0_offset; // @[btb.scala:71:26] wire [28:0] s1_req_rmeta_1_3_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_2_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_1_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_0_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_3_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_2_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_1_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_0_tag; // @[btb.scala:70:26] wire [55:0] _btb_data_way_1_R0_data; // @[btb.scala:192:29] wire [119:0] _btb_meta_way_1_R0_data; // @[btb.scala:191:29] wire [55:0] _btb_data_way_0_R0_data; // @[btb.scala:192:29] wire [119:0] _btb_meta_way_0_R0_data; // @[btb.scala:191:29] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:24:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:24:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:24:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:24:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:24:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:24:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:24:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:24:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:24:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:24:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:24:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:24:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:24:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:24:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:24:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:24:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:24:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:24:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:24:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:141:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:141:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:141:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:142:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:142:59] wire io_f1_lhist = 1'h0; // @[btb.scala:24:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_taken_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_1_taken_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_2_taken_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_3_taken_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_0_taken_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_1_taken_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_2_taken_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_3_taken_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] wire [119:0] io_f3_meta_0; // @[btb.scala:24:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:149:35] wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:149:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] wire [39:0] _s0_pc_T = ~io_f0_pc_0; // @[frontend.scala:147:33] wire [39:0] _s0_pc_T_1 = {_s0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] s0_pc = ~_s0_pc_T_1; // @[frontend.scala:147:{31,39}] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_3_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_3_T = s1_pc; // @[predictor.scala:178:22] reg [39:0] s2_pc; // @[predictor.scala:179:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:149:35] reg s1_update_valid; // @[predictor.scala:185:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:185:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:185:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:185:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:185:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:185:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:185:30] reg s1_update_bits_lhist; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:185:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:185:30] wire [39:0] _s1_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _s1_update_bits_pc_T_1 = {_s1_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _s1_update_bits_pc_T_2 = ~_s1_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] reg [35:0] s1_update_idx; // @[predictor.scala:187:30] reg s1_update_valid_0; // @[predictor.scala:188:32] wire _s1_meta_write_way_T_13; // @[btb.scala:134:27] wire s1_meta_write_way; // @[btb.scala:53:21] reg f3_meta_REG_write_way; // @[btb.scala:54:32] reg f3_meta_write_way; // @[btb.scala:54:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:24:7, :54:24, :57:14] reg doing_reset; // @[btb.scala:61:28] reg [6:0] reset_idx; // @[btb.scala:62:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:61:28, :62:28, :63:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:63:26] wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_0_is_br; // @[btb.scala:70:26] wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_3_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_0_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_3_is_br; // @[btb.scala:70:26] wire [12:0] entry_btb_offset = s1_req_rbtb_0_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_extended = s1_req_rbtb_0_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_2_offset = s1_req_rbtb_0_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_2_extended = s1_req_rbtb_0_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_4_offset = s1_req_rbtb_0_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_4_extended = s1_req_rbtb_0_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_6_offset = s1_req_rbtb_0_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_6_extended = s1_req_rbtb_0_3_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_1_offset = s1_req_rbtb_1_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_1_extended = s1_req_rbtb_1_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_3_offset = s1_req_rbtb_1_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_3_extended = s1_req_rbtb_1_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_5_offset = s1_req_rbtb_1_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_5_extended = s1_req_rbtb_1_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_7_offset = s1_req_rbtb_1_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_7_extended = s1_req_rbtb_1_3_extended; // @[btb.scala:71:26, :90:31] wire [39:0] s1_req_rebtb; // @[btb.scala:72:26] wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29] wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:74:29, :124:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_1_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_2_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_3_valid_T_2; // @[btb.scala:97:50] wire s1_resp_0_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:76:23] wire s1_resp_1_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:76:23] wire s1_resp_2_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:76:23] wire s1_resp_3_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:76:23] wire _s1_is_br_0_T_2; // @[btb.scala:99:54] wire _s1_is_br_1_T_2; // @[btb.scala:99:54] wire _s1_is_br_2_T_2; // @[btb.scala:99:54] wire _s1_is_br_3_T_2; // @[btb.scala:99:54] wire s1_is_br_0; // @[btb.scala:77:23] wire s1_is_br_1; // @[btb.scala:77:23] wire s1_is_br_2; // @[btb.scala:77:23] wire s1_is_br_3; // @[btb.scala:77:23] wire _s1_is_jal_0_T_3; // @[btb.scala:100:54] wire _s1_is_jal_1_T_3; // @[btb.scala:100:54] wire _s1_is_jal_2_T_3; // @[btb.scala:100:54] wire _s1_is_jal_3_T_3; // @[btb.scala:100:54] wire s1_is_jal_0; // @[btb.scala:78:23] wire s1_is_jal_1; // @[btb.scala:78:23] wire s1_is_jal_2; // @[btb.scala:78:23] wire s1_is_jal_3; // @[btb.scala:78:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:80:27, :81:12] wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:80:27, :85:55] wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:80:27, :85:55] wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:80:27, :85:55] wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:80:27, :85:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire [39:0] _s1_targs_0_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_3_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_3_T_8; // @[btb.scala:91:28] wire [39:0] s1_targs_0_0; // @[btb.scala:87:25] wire [39:0] s1_targs_0_1; // @[btb.scala:87:25] wire [39:0] s1_targs_0_2; // @[btb.scala:87:25] wire [39:0] s1_targs_0_3; // @[btb.scala:87:25] wire [39:0] s1_targs_1_0; // @[btb.scala:87:25] wire [39:0] s1_targs_1_1; // @[btb.scala:87:25] wire [39:0] s1_targs_1_2; // @[btb.scala:87:25] wire [39:0] s1_targs_1_3; // @[btb.scala:87:25] wire [40:0] _s1_targs_0_0_T_1 = {_s1_targs_0_0_T[39], _s1_targs_0_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_0_T_2 = _s1_targs_0_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_0_T_3 = _s1_targs_0_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_0_T_4 = {_s1_targs_0_0_T_3[39], _s1_targs_0_0_T_3} + {{28{entry_btb_offset[12]}}, entry_btb_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_0_T_5 = _s1_targs_0_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_6 = _s1_targs_0_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_7 = _s1_targs_0_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_0_T_8 = entry_btb_extended ? s1_req_rebtb : _s1_targs_0_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_0 = _s1_targs_0_0_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_0_T_1 = {_s1_targs_1_0_T[39], _s1_targs_1_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_0_T_2 = _s1_targs_1_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_0_T_3 = _s1_targs_1_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_0_T_4 = {_s1_targs_1_0_T_3[39], _s1_targs_1_0_T_3} + {{28{entry_btb_1_offset[12]}}, entry_btb_1_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_0_T_5 = _s1_targs_1_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_6 = _s1_targs_1_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_7 = _s1_targs_1_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_0_T_8 = entry_btb_1_extended ? s1_req_rebtb : _s1_targs_1_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_0 = _s1_targs_1_0_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_0_bits = s1_hit_ways_0 ? s1_targs_1_0 : s1_targs_0_0; // @[Mux.scala:50:70] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN; // @[btb.scala:99:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:78:23, :100:54] reg REG; // @[btb.scala:105:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_1; // @[btb.scala:109:20] assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_2; // @[btb.scala:113:26] reg REG_3; // @[btb.scala:113:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_4; // @[btb.scala:117:28] reg REG_5; // @[btb.scala:117:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_1_T_1 = {_s1_targs_0_1_T[39], _s1_targs_0_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_1_T_2 = _s1_targs_0_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_1_T_3 = _s1_targs_0_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_1_T_4 = {_s1_targs_0_1_T_3[39], _s1_targs_0_1_T_3} + {{28{entry_btb_2_offset[12]}}, entry_btb_2_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_1_T_5 = _s1_targs_0_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_6 = _s1_targs_0_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_7 = _s1_targs_0_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_1_T_8 = entry_btb_2_extended ? s1_req_rebtb : _s1_targs_0_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_1 = _s1_targs_0_1_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_1_T_1 = {_s1_targs_1_1_T[39], _s1_targs_1_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_1_T_2 = _s1_targs_1_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_1_T_3 = _s1_targs_1_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_1_T_4 = {_s1_targs_1_1_T_3[39], _s1_targs_1_1_T_3} + {{28{entry_btb_3_offset[12]}}, entry_btb_3_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_1_T_5 = _s1_targs_1_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_6 = _s1_targs_1_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_7 = _s1_targs_1_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_1_T_8 = entry_btb_3_extended ? s1_req_rebtb : _s1_targs_1_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_1 = _s1_targs_1_1_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_1_bits = s1_hit_ways_1 ? s1_targs_1_1 : s1_targs_0_1; // @[Mux.scala:50:70] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_0 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_0; // @[btb.scala:99:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_0; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:78:23, :100:54] reg REG_6; // @[btb.scala:105:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_7; // @[btb.scala:109:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_8; // @[btb.scala:113:26] reg REG_9; // @[btb.scala:113:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_10; // @[btb.scala:117:28] reg REG_11; // @[btb.scala:117:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_2_T_1 = {_s1_targs_0_2_T[39], _s1_targs_0_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_2_T_2 = _s1_targs_0_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_2_T_3 = _s1_targs_0_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_2_T_4 = {_s1_targs_0_2_T_3[39], _s1_targs_0_2_T_3} + {{28{entry_btb_4_offset[12]}}, entry_btb_4_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_2_T_5 = _s1_targs_0_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_6 = _s1_targs_0_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_7 = _s1_targs_0_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_2_T_8 = entry_btb_4_extended ? s1_req_rebtb : _s1_targs_0_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_2 = _s1_targs_0_2_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_2_T_1 = {_s1_targs_1_2_T[39], _s1_targs_1_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_2_T_2 = _s1_targs_1_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_2_T_3 = _s1_targs_1_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_2_T_4 = {_s1_targs_1_2_T_3[39], _s1_targs_1_2_T_3} + {{28{entry_btb_5_offset[12]}}, entry_btb_5_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_2_T_5 = _s1_targs_1_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_6 = _s1_targs_1_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_7 = _s1_targs_1_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_2_T_8 = entry_btb_5_extended ? s1_req_rebtb : _s1_targs_1_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_2 = _s1_targs_1_2_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_2_bits = s1_hit_ways_2 ? s1_targs_1_2 : s1_targs_0_2; // @[Mux.scala:50:70] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_1 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_1; // @[btb.scala:99:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_1; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:78:23, :100:54] reg REG_12; // @[btb.scala:105:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_13; // @[btb.scala:109:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_14; // @[btb.scala:113:26] reg REG_15; // @[btb.scala:113:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_16; // @[btb.scala:117:28] reg REG_17; // @[btb.scala:117:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_3_T_1 = {_s1_targs_0_3_T[39], _s1_targs_0_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_3_T_2 = _s1_targs_0_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_3_T_3 = _s1_targs_0_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_3_T_4 = {_s1_targs_0_3_T_3[39], _s1_targs_0_3_T_3} + {{28{entry_btb_6_offset[12]}}, entry_btb_6_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_3_T_5 = _s1_targs_0_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_6 = _s1_targs_0_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_7 = _s1_targs_0_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_3_T_8 = entry_btb_6_extended ? s1_req_rebtb : _s1_targs_0_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_3 = _s1_targs_0_3_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_3_T_1 = {_s1_targs_1_3_T[39], _s1_targs_1_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_3_T_2 = _s1_targs_1_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_3_T_3 = _s1_targs_1_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_3_T_4 = {_s1_targs_1_3_T_3[39], _s1_targs_1_3_T_3} + {{28{entry_btb_7_offset[12]}}, entry_btb_7_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_3_T_5 = _s1_targs_1_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_6 = _s1_targs_1_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_7 = _s1_targs_1_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_3_T_8 = entry_btb_7_extended ? s1_req_rebtb : _s1_targs_1_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_3 = _s1_targs_1_3_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_3_bits = s1_hit_ways_3 ? s1_targs_1_3 : s1_targs_0_3; // @[Mux.scala:50:70] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_2 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_2; // @[btb.scala:99:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_2; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:78:23, :100:54] reg REG_18; // @[btb.scala:105:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_19; // @[btb.scala:109:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_20; // @[btb.scala:113:26] reg REG_21; // @[btb.scala:113:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_22; // @[btb.scala:117:28] reg REG_23; // @[btb.scala:117:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:124:{30,62}] wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:124:{30,80}] wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:124:{30,80}] wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:124:80] wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:124:{30,80}] wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:124:{30,80}] wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:124:80] wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:124:80] wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:124:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:124:22, :128:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:128:14, :130:20] wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:128:14, :130:20] wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:85:55, :134:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:135:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:53:21, :134:27] wire _s1_update_meta_T; // @[btb.scala:139:55] wire s1_update_meta_write_way; // @[btb.scala:139:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:139:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:185:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:139:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:185:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:144:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:144:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:143:{49,56}, :144:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:143:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:143:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:143:56, :145:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:143:56, :146:46] wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:145:{46,65}, :146:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:145:65, :149:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:149:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:143:56, :149:34, :151:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:185:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _GEN_3 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :185:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:153:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:185:30] wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :185:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:156:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:156:{10,74}, :157:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:155:{52,78}, :156:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:163:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:160:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:160:34, :164:62] assign s1_req_rmeta_0_0_tag = _btb_meta_way_0_R0_data[28:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_0_is_br = _btb_meta_way_0_R0_data[29]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_tag = _btb_meta_way_0_R0_data[58:30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_is_br = _btb_meta_way_0_R0_data[59]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_tag = _btb_meta_way_0_R0_data[88:60]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_is_br = _btb_meta_way_0_R0_data[89]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_tag = _btb_meta_way_0_R0_data[118:90]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_is_br = _btb_meta_way_0_R0_data[119]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_0_0_extended = _btb_data_way_0_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_0_offset = _btb_data_way_0_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_extended = _btb_data_way_0_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_offset = _btb_data_way_0_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_extended = _btb_data_way_0_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_offset = _btb_data_way_0_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_extended = _btb_data_way_0_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_offset = _btb_data_way_0_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_0_MPORT_2_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:{25,53}] wire [6:0] _T_56 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_0_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_0_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign s1_req_rmeta_1_0_tag = _btb_meta_way_1_R0_data[28:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_0_is_br = _btb_meta_way_1_R0_data[29]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_tag = _btb_meta_way_1_R0_data[58:30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_is_br = _btb_meta_way_1_R0_data[59]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_tag = _btb_meta_way_1_R0_data[88:60]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_is_br = _btb_meta_way_1_R0_data[89]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_tag = _btb_meta_way_1_R0_data[118:90]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_is_br = _btb_meta_way_1_R0_data[119]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_1_0_extended = _btb_data_way_1_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_0_offset = _btb_data_way_1_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_extended = _btb_data_way_1_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_offset = _btb_data_way_1_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_extended = _btb_data_way_1_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_offset = _btb_data_way_1_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_extended = _btb_data_way_1_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_offset = _btb_data_way_1_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_1_MPORT_6_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:25] wire [6:0] _T_113 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_1_MPORT_6_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_1_MPORT_7_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:215:30] always @(posedge clock) begin // @[btb.scala:24:7] s1_idx <= s0_idx; // @[frontend.scala:149:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= s0_pc; // @[frontend.scala:147:31] s2_pc <= s1_pc; // @[predictor.scala:178:22, :179:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:185:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:185:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:185:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:185:30] s1_update_bits_pc <= _s1_update_bits_pc_T_2; // @[frontend.scala:147:31] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:185:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:185:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:185:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:185:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:185:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:185:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:185:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:149:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:188:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:53:21, :54:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:54:{24,32}] REG <= s1_hits_0; // @[btb.scala:85:55, :105:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:77:23, :107:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:78:23, :108:44] REG_1 <= s1_is_jal_0; // @[btb.scala:78:23, :109:20] REG_2 <= s1_hits_0; // @[btb.scala:85:55, :113:26] REG_3 <= REG_2; // @[btb.scala:113:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:24:7, :116:44] REG_4 <= s1_is_jal_0; // @[btb.scala:78:23, :117:28] REG_5 <= REG_4; // @[btb.scala:117:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:85:55, :105:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:77:23, :107:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:78:23, :108:44] REG_7 <= s1_is_jal_1; // @[btb.scala:78:23, :109:20] REG_8 <= s1_hits_1; // @[btb.scala:85:55, :113:26] REG_9 <= REG_8; // @[btb.scala:113:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:24:7, :116:44] REG_10 <= s1_is_jal_1; // @[btb.scala:78:23, :117:28] REG_11 <= REG_10; // @[btb.scala:117:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:85:55, :105:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:77:23, :107:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:78:23, :108:44] REG_13 <= s1_is_jal_2; // @[btb.scala:78:23, :109:20] REG_14 <= s1_hits_2; // @[btb.scala:85:55, :113:26] REG_15 <= REG_14; // @[btb.scala:113:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:24:7, :116:44] REG_16 <= s1_is_jal_2; // @[btb.scala:78:23, :117:28] REG_17 <= REG_16; // @[btb.scala:117:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:85:55, :105:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:77:23, :107:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:78:23, :108:44] REG_19 <= s1_is_jal_3; // @[btb.scala:78:23, :109:20] REG_20 <= s1_hits_3; // @[btb.scala:85:55, :113:26] REG_21 <= REG_20; // @[btb.scala:113:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:24:7, :116:44] REG_22 <= s1_is_jal_3; // @[btb.scala:78:23, :117:28] REG_23 <= REG_22; // @[btb.scala:117:{20,28}] if (reset) begin // @[btb.scala:24:7] doing_reset <= 1'h1; // @[btb.scala:61:28] reset_idx <= 7'h0; // @[btb.scala:62:28] end else begin // @[btb.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:61:28, :62:28, :64:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:62:28, :63:26] end always @(posedge) btb_meta_way_0_0 btb_meta_way_0 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_0_MPORT_3_data_3, btb_meta_way_0_MPORT_3_data_2, btb_meta_way_0_MPORT_3_data_1, btb_meta_way_0_MPORT_3_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_0_0 btb_data_way_0 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_0_MPORT_2_data_3, btb_data_way_0_MPORT_2_data_2, btb_data_way_0_MPORT_2_data_1, btb_data_way_0_MPORT_2_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_meta_way_1_0 btb_meta_way_1 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_1_MPORT_7_data_3, btb_meta_way_1_MPORT_7_data_2, btb_meta_way_1_MPORT_7_data_1, btb_meta_way_1_MPORT_7_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_1_0 btb_data_way_1 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_1_MPORT_6_data_3, btb_data_way_1_MPORT_6_data_2, btb_data_way_1_MPORT_6_data_1, btb_data_way_1_MPORT_6_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_ebtb_0 btb_ebtb ( // @[btb.scala:213:27] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:215:30] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (s1_req_rebtb), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:187:30] .W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:145:65, :152:58, :216:{31,39}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:185:30] ); // @[btb.scala:213:27] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[13] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[7]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[8]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[9]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[10]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[11]) node source_ok = or(_source_ok_T_43, _source_ok_WIRE[12]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = and(_T_11, _T_24) node _T_129 = and(_T_128, _T_37) node _T_130 = and(_T_129, _T_50) node _T_131 = and(_T_130, _T_63) node _T_132 = and(_T_131, _T_71) node _T_133 = and(_T_132, _T_79) node _T_134 = and(_T_133, _T_87) node _T_135 = and(_T_134, _T_95) node _T_136 = and(_T_135, _T_103) node _T_137 = and(_T_136, _T_111) node _T_138 = and(_T_137, _T_119) node _T_139 = and(_T_138, _T_127) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_139, UInt<1>(0h1), "") : assert_1 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_4) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<1>(0h1)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_5) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_160 = shr(io.in.a.bits.source, 2) node _T_161 = eq(_T_160, UInt<2>(0h2)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_6) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_166 = shr(io.in.a.bits.source, 2) node _T_167 = eq(_T_166, UInt<2>(0h3)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_7) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_173 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_174 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_175 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_177 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_180 = or(_T_147, _T_153) node _T_181 = or(_T_180, _T_159) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_171) node _T_184 = or(_T_183, _T_172) node _T_185 = or(_T_184, _T_173) node _T_186 = or(_T_185, _T_174) node _T_187 = or(_T_186, _T_175) node _T_188 = or(_T_187, _T_176) node _T_189 = or(_T_188, _T_177) node _T_190 = or(_T_189, _T_178) node _T_191 = or(_T_190, _T_179) node _T_192 = and(_T_146, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_195 = or(UInt<1>(0h0), _T_194) node _T_196 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h100c0))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<29>(0h100000c0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _T_207 = and(_T_195, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = and(_T_193, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_209, UInt<1>(0h1), "") : assert_2 node _T_213 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<1>(0h0)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_8) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h1)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_9) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<2>(0h2)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_10) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h3)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_11) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[13] connect _WIRE[0], _T_213 connect _WIRE[1], _T_219 connect _WIRE[2], _T_225 connect _WIRE[3], _T_231 connect _WIRE[4], _T_237 connect _WIRE[5], _T_238 connect _WIRE[6], _T_239 connect _WIRE[7], _T_240 connect _WIRE[8], _T_241 connect _WIRE[9], _T_242 connect _WIRE[10], _T_243 connect _WIRE[11], _T_244 connect _WIRE[12], _T_245 node _T_246 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_247 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_249 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_250 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_252 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[5], _T_246, UInt<1>(0h0)) node _T_256 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = mux(_WIRE[7], _T_247, UInt<1>(0h0)) node _T_258 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[9], _T_248, UInt<1>(0h0)) node _T_260 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_261 = mux(_WIRE[11], _T_249, UInt<1>(0h0)) node _T_262 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = or(_T_250, _T_251) node _T_264 = or(_T_263, _T_252) node _T_265 = or(_T_264, _T_253) node _T_266 = or(_T_265, _T_254) node _T_267 = or(_T_266, _T_255) node _T_268 = or(_T_267, _T_256) node _T_269 = or(_T_268, _T_257) node _T_270 = or(_T_269, _T_258) node _T_271 = or(_T_270, _T_259) node _T_272 = or(_T_271, _T_260) node _T_273 = or(_T_272, _T_261) node _T_274 = or(_T_273, _T_262) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_274 node _T_275 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_276 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<17>(0h100c0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<29>(0h100000c0))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_283, _T_288) node _T_290 = and(_T_278, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = and(_WIRE_1, _T_291) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_292, UInt<1>(0h1), "") : assert_3 node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(source_ok, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_299 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_299, UInt<1>(0h1), "") : assert_5 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_306 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_306, UInt<1>(0h1), "") : assert_7 node _T_310 = not(io.in.a.bits.mask) node _T_311 = eq(_T_310, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_311, UInt<1>(0h1), "") : assert_8 node _T_315 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_315, UInt<1>(0h1), "") : assert_9 node _T_319 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_319 : node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_12) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_13) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_14) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_15) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_349 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_352 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_356 = or(_T_323, _T_329) node _T_357 = or(_T_356, _T_335) node _T_358 = or(_T_357, _T_341) node _T_359 = or(_T_358, _T_347) node _T_360 = or(_T_359, _T_348) node _T_361 = or(_T_360, _T_349) node _T_362 = or(_T_361, _T_350) node _T_363 = or(_T_362, _T_351) node _T_364 = or(_T_363, _T_352) node _T_365 = or(_T_364, _T_353) node _T_366 = or(_T_365, _T_354) node _T_367 = or(_T_366, _T_355) node _T_368 = and(_T_322, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h100c0))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h100000c0))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_376, _T_381) node _T_383 = and(_T_371, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_T_369, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_385, UInt<1>(0h1), "") : assert_10 node _T_389 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_390 = shr(io.in.a.bits.source, 2) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = leq(UInt<1>(0h0), uncommonBits_16) node _T_393 = and(_T_391, _T_392) node _T_394 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_395 = and(_T_393, _T_394) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h1)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_17) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<2>(0h2)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_18) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h3)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_19) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_415 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_416 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[13] connect _WIRE_2[0], _T_389 connect _WIRE_2[1], _T_395 connect _WIRE_2[2], _T_401 connect _WIRE_2[3], _T_407 connect _WIRE_2[4], _T_413 connect _WIRE_2[5], _T_414 connect _WIRE_2[6], _T_415 connect _WIRE_2[7], _T_416 connect _WIRE_2[8], _T_417 connect _WIRE_2[9], _T_418 connect _WIRE_2[10], _T_419 connect _WIRE_2[11], _T_420 connect _WIRE_2[12], _T_421 node _T_422 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_423 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_424 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_425 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_426 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_428 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_429 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = mux(_WIRE_2[5], _T_422, UInt<1>(0h0)) node _T_432 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_433 = mux(_WIRE_2[7], _T_423, UInt<1>(0h0)) node _T_434 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = mux(_WIRE_2[9], _T_424, UInt<1>(0h0)) node _T_436 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_437 = mux(_WIRE_2[11], _T_425, UInt<1>(0h0)) node _T_438 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_439 = or(_T_426, _T_427) node _T_440 = or(_T_439, _T_428) node _T_441 = or(_T_440, _T_429) node _T_442 = or(_T_441, _T_430) node _T_443 = or(_T_442, _T_431) node _T_444 = or(_T_443, _T_432) node _T_445 = or(_T_444, _T_433) node _T_446 = or(_T_445, _T_434) node _T_447 = or(_T_446, _T_435) node _T_448 = or(_T_447, _T_436) node _T_449 = or(_T_448, _T_437) node _T_450 = or(_T_449, _T_438) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_450 node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<17>(0h100c0))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<29>(0h100000c0))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = or(_T_459, _T_464) node _T_466 = and(_T_454, _T_465) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = and(_WIRE_3, _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_468, UInt<1>(0h1), "") : assert_11 node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(source_ok, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_475 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_475, UInt<1>(0h1), "") : assert_13 node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(is_aligned, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_482 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_482, UInt<1>(0h1), "") : assert_15 node _T_486 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_486, UInt<1>(0h1), "") : assert_16 node _T_490 = not(io.in.a.bits.mask) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_491, UInt<1>(0h1), "") : assert_17 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_495, UInt<1>(0h1), "") : assert_18 node _T_499 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_20) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_21) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_22) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_23) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_529 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_530 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_536 = or(_T_503, _T_509) node _T_537 = or(_T_536, _T_515) node _T_538 = or(_T_537, _T_521) node _T_539 = or(_T_538, _T_527) node _T_540 = or(_T_539, _T_528) node _T_541 = or(_T_540, _T_529) node _T_542 = or(_T_541, _T_530) node _T_543 = or(_T_542, _T_531) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_533) node _T_546 = or(_T_545, _T_534) node _T_547 = or(_T_546, _T_535) node _T_548 = and(_T_502, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_549, UInt<1>(0h1), "") : assert_19 node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_554 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_555 = and(_T_553, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<17>(0h100c0))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<29>(0h100000c0))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = or(_T_561, _T_566) node _T_568 = and(_T_556, _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_569, UInt<1>(0h1), "") : assert_20 node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(source_ok, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_576 = asUInt(reset) node _T_577 = eq(_T_576, UInt<1>(0h0)) when _T_577 : node _T_578 = eq(is_aligned, UInt<1>(0h0)) when _T_578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_579 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_579, UInt<1>(0h1), "") : assert_23 node _T_583 = eq(io.in.a.bits.mask, mask) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_583, UInt<1>(0h1), "") : assert_24 node _T_587 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_587, UInt<1>(0h1), "") : assert_25 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_24) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_25) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_26) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_27) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_620) node _T_633 = or(_T_632, _T_621) node _T_634 = or(_T_633, _T_622) node _T_635 = or(_T_634, _T_623) node _T_636 = or(_T_635, _T_624) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_626) node _T_639 = or(_T_638, _T_627) node _T_640 = and(_T_594, _T_639) node _T_641 = or(UInt<1>(0h0), _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<17>(0h100c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<29>(0h100000c0))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = or(_T_650, _T_655) node _T_657 = and(_T_645, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = and(_T_641, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_659, UInt<1>(0h1), "") : assert_26 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(source_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(is_aligned, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_669, UInt<1>(0h1), "") : assert_29 node _T_673 = eq(io.in.a.bits.mask, mask) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_673, UInt<1>(0h1), "") : assert_30 node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_28) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_29) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_30) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_31) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_708 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_711 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_712 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = or(_T_681, _T_687) node _T_715 = or(_T_714, _T_693) node _T_716 = or(_T_715, _T_699) node _T_717 = or(_T_716, _T_705) node _T_718 = or(_T_717, _T_706) node _T_719 = or(_T_718, _T_707) node _T_720 = or(_T_719, _T_708) node _T_721 = or(_T_720, _T_709) node _T_722 = or(_T_721, _T_710) node _T_723 = or(_T_722, _T_711) node _T_724 = or(_T_723, _T_712) node _T_725 = or(_T_724, _T_713) node _T_726 = and(_T_680, _T_725) node _T_727 = or(UInt<1>(0h0), _T_726) node _T_728 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_729 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_730 = and(_T_728, _T_729) node _T_731 = or(UInt<1>(0h0), _T_730) node _T_732 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_733 = cvt(_T_732) node _T_734 = and(_T_733, asSInt(UInt<17>(0h100c0))) node _T_735 = asSInt(_T_734) node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0))) node _T_737 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_738 = cvt(_T_737) node _T_739 = and(_T_738, asSInt(UInt<29>(0h100000c0))) node _T_740 = asSInt(_T_739) node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0))) node _T_742 = or(_T_736, _T_741) node _T_743 = and(_T_731, _T_742) node _T_744 = or(UInt<1>(0h0), _T_743) node _T_745 = and(_T_727, _T_744) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_745, UInt<1>(0h1), "") : assert_31 node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(source_ok, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(is_aligned, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_755, UInt<1>(0h1), "") : assert_34 node _T_759 = not(mask) node _T_760 = and(io.in.a.bits.mask, _T_759) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_761, UInt<1>(0h1), "") : assert_35 node _T_765 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<1>(0h0)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_32) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_33) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_34) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<2>(0h3)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_35) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = or(_T_769, _T_775) node _T_803 = or(_T_802, _T_781) node _T_804 = or(_T_803, _T_787) node _T_805 = or(_T_804, _T_793) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_795) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_797) node _T_810 = or(_T_809, _T_798) node _T_811 = or(_T_810, _T_799) node _T_812 = or(_T_811, _T_800) node _T_813 = or(_T_812, _T_801) node _T_814 = and(_T_768, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h100c0))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<29>(0h100000c0))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = or(_T_824, _T_829) node _T_831 = and(_T_819, _T_830) node _T_832 = or(UInt<1>(0h0), _T_831) node _T_833 = and(_T_815, _T_832) node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(_T_833, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_833, UInt<1>(0h1), "") : assert_36 node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(source_ok, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(is_aligned, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_843 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_844 = asUInt(reset) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(_T_843, UInt<1>(0h0)) when _T_846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_843, UInt<1>(0h1), "") : assert_39 node _T_847 = eq(io.in.a.bits.mask, mask) node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(_T_847, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_847, UInt<1>(0h1), "") : assert_40 node _T_851 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_851 : node _T_852 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_853 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_854 = and(_T_852, _T_853) node _T_855 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_856 = shr(io.in.a.bits.source, 2) node _T_857 = eq(_T_856, UInt<1>(0h0)) node _T_858 = leq(UInt<1>(0h0), uncommonBits_36) node _T_859 = and(_T_857, _T_858) node _T_860 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_861 = and(_T_859, _T_860) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_862 = shr(io.in.a.bits.source, 2) node _T_863 = eq(_T_862, UInt<1>(0h1)) node _T_864 = leq(UInt<1>(0h0), uncommonBits_37) node _T_865 = and(_T_863, _T_864) node _T_866 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_868 = shr(io.in.a.bits.source, 2) node _T_869 = eq(_T_868, UInt<2>(0h2)) node _T_870 = leq(UInt<1>(0h0), uncommonBits_38) node _T_871 = and(_T_869, _T_870) node _T_872 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_873 = and(_T_871, _T_872) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<2>(0h3)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_39) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_888 = or(_T_855, _T_861) node _T_889 = or(_T_888, _T_867) node _T_890 = or(_T_889, _T_873) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_880) node _T_893 = or(_T_892, _T_881) node _T_894 = or(_T_893, _T_882) node _T_895 = or(_T_894, _T_883) node _T_896 = or(_T_895, _T_884) node _T_897 = or(_T_896, _T_885) node _T_898 = or(_T_897, _T_886) node _T_899 = or(_T_898, _T_887) node _T_900 = and(_T_854, _T_899) node _T_901 = or(UInt<1>(0h0), _T_900) node _T_902 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_903 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_904 = and(_T_902, _T_903) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h100c0))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<29>(0h100000c0))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = or(_T_910, _T_915) node _T_917 = and(_T_905, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(_T_901, _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_919, UInt<1>(0h1), "") : assert_41 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(source_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(is_aligned, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_929 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_929, UInt<1>(0h1), "") : assert_44 node _T_933 = eq(io.in.a.bits.mask, mask) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_933, UInt<1>(0h1), "") : assert_45 node _T_937 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_937 : node _T_938 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_939 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_940 = and(_T_938, _T_939) node _T_941 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_942 = shr(io.in.a.bits.source, 2) node _T_943 = eq(_T_942, UInt<1>(0h0)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_40) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<1>(0h1)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_41) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<2>(0h2)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_42) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<2>(0h3)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_43) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_974 = or(_T_941, _T_947) node _T_975 = or(_T_974, _T_953) node _T_976 = or(_T_975, _T_959) node _T_977 = or(_T_976, _T_965) node _T_978 = or(_T_977, _T_966) node _T_979 = or(_T_978, _T_967) node _T_980 = or(_T_979, _T_968) node _T_981 = or(_T_980, _T_969) node _T_982 = or(_T_981, _T_970) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_972) node _T_985 = or(_T_984, _T_973) node _T_986 = and(_T_940, _T_985) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h100c0))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h100000c0))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_987, _T_1004) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_46 node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(source_ok, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(is_aligned, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1015 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_49 node _T_1019 = eq(io.in.a.bits.mask, mask) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_50 node _T_1023 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1027 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_52 node _source_ok_T_44 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h0)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<1>(0h1)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h2)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<2>(0h3)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[13] connect _source_ok_WIRE_1[0], _source_ok_T_44 connect _source_ok_WIRE_1[1], _source_ok_T_50 connect _source_ok_WIRE_1[2], _source_ok_T_56 connect _source_ok_WIRE_1[3], _source_ok_T_62 connect _source_ok_WIRE_1[4], _source_ok_T_68 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 connect _source_ok_WIRE_1[8], _source_ok_T_72 connect _source_ok_WIRE_1[9], _source_ok_T_73 connect _source_ok_WIRE_1[10], _source_ok_T_74 connect _source_ok_WIRE_1[11], _source_ok_T_75 connect _source_ok_WIRE_1[12], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[11]) node source_ok_1 = or(_source_ok_T_87, _source_ok_WIRE_1[12]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1031 : node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(source_ok_1, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1035 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_54 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_55 node _T_1043 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_56 node _T_1047 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_57 node _T_1051 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1051 : node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok_1, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(sink_ok, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1058 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_60 node _T_1062 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_61 node _T_1066 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_62 node _T_1070 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_63 node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1075 = or(UInt<1>(0h1), _T_1074) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_64 node _T_1079 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1079 : node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(source_ok_1, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(sink_ok, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1086 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_67 node _T_1090 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_68 node _T_1094 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_69 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(_T_1098, io.in.d.bits.corrupt) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_70 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(UInt<1>(0h1), _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_71 node _T_1108 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1108 : node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(source_ok_1, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_73 node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_74 node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1121 = or(UInt<1>(0h1), _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_75 node _T_1125 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1125 : node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(source_ok_1, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1129 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_77 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(_T_1133, io.in.d.bits.corrupt) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_78 node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1139 = or(UInt<1>(0h1), _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_79 node _T_1143 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1143 : node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(source_ok_1, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_81 node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_82 node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1156 = or(UInt<1>(0h1), _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1160 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_84 node _T_1164 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) node _T_1166 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1167 = cvt(_T_1166) node _T_1168 = and(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = asSInt(_T_1168) node _T_1170 = eq(_T_1169, asSInt(UInt<1>(0h0))) node _T_1171 = or(_T_1165, _T_1170) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1172 = shr(io.in.b.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) node _T_1179 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1180 = cvt(_T_1179) node _T_1181 = and(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = asSInt(_T_1181) node _T_1183 = eq(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = or(_T_1178, _T_1183) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1185 = shr(io.in.b.bits.source, 2) node _T_1186 = eq(_T_1185, UInt<1>(0h1)) node _T_1187 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) node _T_1192 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1193 = cvt(_T_1192) node _T_1194 = and(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = asSInt(_T_1194) node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0))) node _T_1197 = or(_T_1191, _T_1196) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1198 = shr(io.in.b.bits.source, 2) node _T_1199 = eq(_T_1198, UInt<2>(0h2)) node _T_1200 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<1>(0h0))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = or(_T_1204, _T_1209) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1211 = shr(io.in.b.bits.source, 2) node _T_1212 = eq(_T_1211, UInt<2>(0h3)) node _T_1213 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) node _T_1218 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1219 = cvt(_T_1218) node _T_1220 = and(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = asSInt(_T_1220) node _T_1222 = eq(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = or(_T_1217, _T_1222) node _T_1224 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) node _T_1226 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1227 = cvt(_T_1226) node _T_1228 = and(_T_1227, asSInt(UInt<1>(0h0))) node _T_1229 = asSInt(_T_1228) node _T_1230 = eq(_T_1229, asSInt(UInt<1>(0h0))) node _T_1231 = or(_T_1225, _T_1230) node _T_1232 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) node _T_1234 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1235 = cvt(_T_1234) node _T_1236 = and(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = asSInt(_T_1236) node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0))) node _T_1239 = or(_T_1233, _T_1238) node _T_1240 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) node _T_1242 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = or(_T_1241, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = or(_T_1249, _T_1254) node _T_1256 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) node _T_1258 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = or(_T_1257, _T_1262) node _T_1264 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) node _T_1266 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1267 = cvt(_T_1266) node _T_1268 = and(_T_1267, asSInt(UInt<1>(0h0))) node _T_1269 = asSInt(_T_1268) node _T_1270 = eq(_T_1269, asSInt(UInt<1>(0h0))) node _T_1271 = or(_T_1265, _T_1270) node _T_1272 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = or(_T_1273, _T_1278) node _T_1280 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) node _T_1282 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = or(_T_1281, _T_1286) node _T_1288 = and(_T_1171, _T_1184) node _T_1289 = and(_T_1288, _T_1197) node _T_1290 = and(_T_1289, _T_1210) node _T_1291 = and(_T_1290, _T_1223) node _T_1292 = and(_T_1291, _T_1231) node _T_1293 = and(_T_1292, _T_1239) node _T_1294 = and(_T_1293, _T_1247) node _T_1295 = and(_T_1294, _T_1255) node _T_1296 = and(_T_1295, _T_1263) node _T_1297 = and(_T_1296, _T_1271) node _T_1298 = and(_T_1297, _T_1279) node _T_1299 = and(_T_1298, _T_1287) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[13] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_41 = mux(_legal_source_WIRE[8], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[9], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[10], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[11], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[12], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_46 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_35) node _legal_source_T_48 = or(_legal_source_T_47, _legal_source_T_36) node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_37) node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_38) node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_39) node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_40) node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_41) node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_42) node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_43) node _legal_source_T_56 = or(_legal_source_T_55, _legal_source_T_44) node _legal_source_T_57 = or(_legal_source_T_56, _legal_source_T_45) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_57 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1303 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1303 : node _T_1304 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1305 = shr(io.in.b.bits.source, 2) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) node _T_1307 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1310 = and(_T_1308, _T_1309) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1311 = shr(io.in.b.bits.source, 2) node _T_1312 = eq(_T_1311, UInt<1>(0h1)) node _T_1313 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1314 = and(_T_1312, _T_1313) node _T_1315 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1316 = and(_T_1314, _T_1315) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1317 = shr(io.in.b.bits.source, 2) node _T_1318 = eq(_T_1317, UInt<2>(0h2)) node _T_1319 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1322 = and(_T_1320, _T_1321) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1323 = shr(io.in.b.bits.source, 2) node _T_1324 = eq(_T_1323, UInt<2>(0h3)) node _T_1325 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1326 = and(_T_1324, _T_1325) node _T_1327 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1330 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1331 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1332 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1333 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1334 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1335 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1336 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[13] connect _WIRE_4[0], _T_1304 connect _WIRE_4[1], _T_1310 connect _WIRE_4[2], _T_1316 connect _WIRE_4[3], _T_1322 connect _WIRE_4[4], _T_1328 connect _WIRE_4[5], _T_1329 connect _WIRE_4[6], _T_1330 connect _WIRE_4[7], _T_1331 connect _WIRE_4[8], _T_1332 connect _WIRE_4[9], _T_1333 connect _WIRE_4[10], _T_1334 connect _WIRE_4[11], _T_1335 connect _WIRE_4[12], _T_1336 node _T_1337 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1338 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1339 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1340 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1341 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1342 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1343 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1344 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1346 = mux(_WIRE_4[5], _T_1337, UInt<1>(0h0)) node _T_1347 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = mux(_WIRE_4[7], _T_1338, UInt<1>(0h0)) node _T_1349 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1350 = mux(_WIRE_4[9], _T_1339, UInt<1>(0h0)) node _T_1351 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1352 = mux(_WIRE_4[11], _T_1340, UInt<1>(0h0)) node _T_1353 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1354 = or(_T_1341, _T_1342) node _T_1355 = or(_T_1354, _T_1343) node _T_1356 = or(_T_1355, _T_1344) node _T_1357 = or(_T_1356, _T_1345) node _T_1358 = or(_T_1357, _T_1346) node _T_1359 = or(_T_1358, _T_1347) node _T_1360 = or(_T_1359, _T_1348) node _T_1361 = or(_T_1360, _T_1349) node _T_1362 = or(_T_1361, _T_1350) node _T_1363 = or(_T_1362, _T_1351) node _T_1364 = or(_T_1363, _T_1352) node _T_1365 = or(_T_1364, _T_1353) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1365 node _T_1366 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1367 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1368 = and(_T_1366, _T_1367) node _T_1369 = or(UInt<1>(0h0), _T_1368) node _T_1370 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<17>(0h100c0))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1376 = cvt(_T_1375) node _T_1377 = and(_T_1376, asSInt(UInt<29>(0h100000c0))) node _T_1378 = asSInt(_T_1377) node _T_1379 = eq(_T_1378, asSInt(UInt<1>(0h0))) node _T_1380 = or(_T_1374, _T_1379) node _T_1381 = and(_T_1369, _T_1380) node _T_1382 = or(UInt<1>(0h0), _T_1381) node _T_1383 = and(_WIRE_5, _T_1382) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_86 node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(address_ok, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(legal_source, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1396 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_90 node _T_1400 = eq(io.in.b.bits.mask, mask_1) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_91 node _T_1404 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_92 node _T_1408 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1408 : node _T_1409 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1410 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = or(UInt<1>(0h0), _T_1411) node _T_1413 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1414 = cvt(_T_1413) node _T_1415 = and(_T_1414, asSInt(UInt<17>(0h100c0))) node _T_1416 = asSInt(_T_1415) node _T_1417 = eq(_T_1416, asSInt(UInt<1>(0h0))) node _T_1418 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<29>(0h100000c0))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = or(_T_1417, _T_1422) node _T_1424 = and(_T_1412, _T_1423) node _T_1425 = or(UInt<1>(0h0), _T_1424) node _T_1426 = and(UInt<1>(0h0), _T_1425) node _T_1427 = asUInt(reset) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) when _T_1428 : node _T_1429 = eq(_T_1426, UInt<1>(0h0)) when _T_1429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1426, UInt<1>(0h1), "") : assert_93 node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(address_ok, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(legal_source, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1439 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_97 node _T_1443 = eq(io.in.b.bits.mask, mask_1) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_98 node _T_1447 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_99 node _T_1451 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1451 : node _T_1452 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1453 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1454 = and(_T_1452, _T_1453) node _T_1455 = or(UInt<1>(0h0), _T_1454) node _T_1456 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<17>(0h100c0))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<29>(0h100000c0))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = or(_T_1460, _T_1465) node _T_1467 = and(_T_1455, _T_1466) node _T_1468 = or(UInt<1>(0h0), _T_1467) node _T_1469 = and(UInt<1>(0h0), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_100 node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(address_ok, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(legal_source, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1482 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = eq(io.in.b.bits.mask, mask_1) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_105 node _T_1490 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1492 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h100c0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h100000c0))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1506) node _T_1508 = and(UInt<1>(0h0), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_106 node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(address_ok, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(legal_source, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1521 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_110 node _T_1525 = not(mask_1) node _T_1526 = and(io.in.b.bits.mask, _T_1525) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_111 node _T_1531 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1531 : node _T_1532 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1533 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1534 = and(_T_1532, _T_1533) node _T_1535 = or(UInt<1>(0h0), _T_1534) node _T_1536 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<17>(0h100c0))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1542 = cvt(_T_1541) node _T_1543 = and(_T_1542, asSInt(UInt<29>(0h100000c0))) node _T_1544 = asSInt(_T_1543) node _T_1545 = eq(_T_1544, asSInt(UInt<1>(0h0))) node _T_1546 = or(_T_1540, _T_1545) node _T_1547 = and(_T_1535, _T_1546) node _T_1548 = or(UInt<1>(0h0), _T_1547) node _T_1549 = and(UInt<1>(0h0), _T_1548) node _T_1550 = asUInt(reset) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) when _T_1551 : node _T_1552 = eq(_T_1549, UInt<1>(0h0)) when _T_1552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1549, UInt<1>(0h1), "") : assert_112 node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(address_ok, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(legal_source, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1562 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_116 node _T_1566 = eq(io.in.b.bits.mask, mask_1) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_117 node _T_1570 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1570 : node _T_1571 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1572 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1573 = and(_T_1571, _T_1572) node _T_1574 = or(UInt<1>(0h0), _T_1573) node _T_1575 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h100c0))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<29>(0h100000c0))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = or(_T_1579, _T_1584) node _T_1586 = and(_T_1574, _T_1585) node _T_1587 = or(UInt<1>(0h0), _T_1586) node _T_1588 = and(UInt<1>(0h0), _T_1587) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_118 node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(address_ok, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(legal_source, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1601 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1602 = asUInt(reset) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) when _T_1603 : node _T_1604 = eq(_T_1601, UInt<1>(0h0)) when _T_1604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1601, UInt<1>(0h1), "") : assert_122 node _T_1605 = eq(io.in.b.bits.mask, mask_1) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_123 node _T_1609 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1609 : node _T_1610 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1611 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1612 = and(_T_1610, _T_1611) node _T_1613 = or(UInt<1>(0h0), _T_1612) node _T_1614 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h100c0))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<29>(0h100000c0))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = or(_T_1618, _T_1623) node _T_1625 = and(_T_1613, _T_1624) node _T_1626 = or(UInt<1>(0h0), _T_1625) node _T_1627 = and(UInt<1>(0h0), _T_1626) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_124 node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(address_ok, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(legal_source, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1640 = eq(io.in.b.bits.mask, mask_1) node _T_1641 = asUInt(reset) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) when _T_1642 : node _T_1643 = eq(_T_1640, UInt<1>(0h0)) when _T_1643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1640, UInt<1>(0h1), "") : assert_128 node _T_1644 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1648 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_130 node _source_ok_T_88 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_89 = shr(io.in.c.bits.source, 2) node _source_ok_T_90 = eq(_source_ok_T_89, UInt<1>(0h0)) node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91) node _source_ok_T_93 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_95 = shr(io.in.c.bits.source, 2) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<1>(0h1)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_101 = shr(io.in.c.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<2>(0h2)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_107 = shr(io.in.c.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<2>(0h3)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_114 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_115 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_116 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_117 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_118 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_119 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[13] connect _source_ok_WIRE_2[0], _source_ok_T_88 connect _source_ok_WIRE_2[1], _source_ok_T_94 connect _source_ok_WIRE_2[2], _source_ok_T_100 connect _source_ok_WIRE_2[3], _source_ok_T_106 connect _source_ok_WIRE_2[4], _source_ok_T_112 connect _source_ok_WIRE_2[5], _source_ok_T_113 connect _source_ok_WIRE_2[6], _source_ok_T_114 connect _source_ok_WIRE_2[7], _source_ok_T_115 connect _source_ok_WIRE_2[8], _source_ok_T_116 connect _source_ok_WIRE_2[9], _source_ok_T_117 connect _source_ok_WIRE_2[10], _source_ok_T_118 connect _source_ok_WIRE_2[11], _source_ok_T_119 connect _source_ok_WIRE_2[12], _source_ok_T_120 node _source_ok_T_121 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_2[2]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_2[3]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_2[4]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_2[5]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_2[6]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_2[7]) node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_2[8]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_2[9]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_2[10]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_2[11]) node source_ok_2 = or(_source_ok_T_131, _source_ok_WIRE_2[12]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1652 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) node _T_1654 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1655 = cvt(_T_1654) node _T_1656 = and(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = asSInt(_T_1656) node _T_1658 = eq(_T_1657, asSInt(UInt<1>(0h0))) node _T_1659 = or(_T_1653, _T_1658) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1660 = shr(io.in.c.bits.source, 2) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) node _T_1662 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1663 = and(_T_1661, _T_1662) node _T_1664 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) node _T_1667 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = or(_T_1666, _T_1671) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1673 = shr(io.in.c.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<1>(0h1)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) node _T_1680 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<1>(0h0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = or(_T_1679, _T_1684) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1686 = shr(io.in.c.bits.source, 2) node _T_1687 = eq(_T_1686, UInt<2>(0h2)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1691 = and(_T_1689, _T_1690) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) node _T_1693 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<1>(0h0))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = or(_T_1692, _T_1697) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1699 = shr(io.in.c.bits.source, 2) node _T_1700 = eq(_T_1699, UInt<2>(0h3)) node _T_1701 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1704 = and(_T_1702, _T_1703) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) node _T_1706 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1707 = cvt(_T_1706) node _T_1708 = and(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = asSInt(_T_1708) node _T_1710 = eq(_T_1709, asSInt(UInt<1>(0h0))) node _T_1711 = or(_T_1705, _T_1710) node _T_1712 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) node _T_1714 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = or(_T_1713, _T_1718) node _T_1720 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) node _T_1722 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = or(_T_1721, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) node _T_1730 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = or(_T_1729, _T_1734) node _T_1736 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) node _T_1738 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1737, _T_1742) node _T_1744 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) node _T_1746 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = or(_T_1745, _T_1750) node _T_1752 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) node _T_1754 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = or(_T_1753, _T_1758) node _T_1760 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1659, _T_1672) node _T_1777 = and(_T_1776, _T_1685) node _T_1778 = and(_T_1777, _T_1698) node _T_1779 = and(_T_1778, _T_1711) node _T_1780 = and(_T_1779, _T_1719) node _T_1781 = and(_T_1780, _T_1727) node _T_1782 = and(_T_1781, _T_1735) node _T_1783 = and(_T_1782, _T_1743) node _T_1784 = and(_T_1783, _T_1751) node _T_1785 = and(_T_1784, _T_1759) node _T_1786 = and(_T_1785, _T_1767) node _T_1787 = and(_T_1786, _T_1775) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_131 node _T_1791 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1791 : node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(address_ok_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(source_ok_2, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1798 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_134 node _T_1802 = asUInt(reset) node _T_1803 = eq(_T_1802, UInt<1>(0h0)) when _T_1803 : node _T_1804 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1805 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(_T_1805, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1805, UInt<1>(0h1), "") : assert_136 node _T_1809 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_137 node _T_1813 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1813 : node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(address_ok_1, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(source_ok_2, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1820 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1821 = asUInt(reset) node _T_1822 = eq(_T_1821, UInt<1>(0h0)) when _T_1822 : node _T_1823 = eq(_T_1820, UInt<1>(0h0)) when _T_1823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1820, UInt<1>(0h1), "") : assert_140 node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1827 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1828 = asUInt(reset) node _T_1829 = eq(_T_1828, UInt<1>(0h0)) when _T_1829 : node _T_1830 = eq(_T_1827, UInt<1>(0h0)) when _T_1830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1827, UInt<1>(0h1), "") : assert_142 node _T_1831 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1831 : node _T_1832 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1833 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1834 = and(_T_1832, _T_1833) node _T_1835 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1836 = shr(io.in.c.bits.source, 2) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) node _T_1838 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1839 = and(_T_1837, _T_1838) node _T_1840 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1841 = and(_T_1839, _T_1840) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1842 = shr(io.in.c.bits.source, 2) node _T_1843 = eq(_T_1842, UInt<1>(0h1)) node _T_1844 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1845 = and(_T_1843, _T_1844) node _T_1846 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1847 = and(_T_1845, _T_1846) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1848 = shr(io.in.c.bits.source, 2) node _T_1849 = eq(_T_1848, UInt<2>(0h2)) node _T_1850 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1851 = and(_T_1849, _T_1850) node _T_1852 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1853 = and(_T_1851, _T_1852) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1854 = shr(io.in.c.bits.source, 2) node _T_1855 = eq(_T_1854, UInt<2>(0h3)) node _T_1856 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1857 = and(_T_1855, _T_1856) node _T_1858 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1861 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1862 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1863 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1864 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1865 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1866 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1867 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1868 = or(_T_1835, _T_1841) node _T_1869 = or(_T_1868, _T_1847) node _T_1870 = or(_T_1869, _T_1853) node _T_1871 = or(_T_1870, _T_1859) node _T_1872 = or(_T_1871, _T_1860) node _T_1873 = or(_T_1872, _T_1861) node _T_1874 = or(_T_1873, _T_1862) node _T_1875 = or(_T_1874, _T_1863) node _T_1876 = or(_T_1875, _T_1864) node _T_1877 = or(_T_1876, _T_1865) node _T_1878 = or(_T_1877, _T_1866) node _T_1879 = or(_T_1878, _T_1867) node _T_1880 = and(_T_1834, _T_1879) node _T_1881 = or(UInt<1>(0h0), _T_1880) node _T_1882 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1883 = or(UInt<1>(0h0), _T_1882) node _T_1884 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h100c0))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<29>(0h100000c0))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = or(_T_1888, _T_1893) node _T_1895 = and(_T_1883, _T_1894) node _T_1896 = or(UInt<1>(0h0), _T_1895) node _T_1897 = and(_T_1881, _T_1896) node _T_1898 = asUInt(reset) node _T_1899 = eq(_T_1898, UInt<1>(0h0)) when _T_1899 : node _T_1900 = eq(_T_1897, UInt<1>(0h0)) when _T_1900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1897, UInt<1>(0h1), "") : assert_143 node _T_1901 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1902 = shr(io.in.c.bits.source, 2) node _T_1903 = eq(_T_1902, UInt<1>(0h0)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1908 = shr(io.in.c.bits.source, 2) node _T_1909 = eq(_T_1908, UInt<1>(0h1)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1914 = shr(io.in.c.bits.source, 2) node _T_1915 = eq(_T_1914, UInt<2>(0h2)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1920 = shr(io.in.c.bits.source, 2) node _T_1921 = eq(_T_1920, UInt<2>(0h3)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1927 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1928 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1929 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1930 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1931 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1932 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1933 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[13] connect _WIRE_6[0], _T_1901 connect _WIRE_6[1], _T_1907 connect _WIRE_6[2], _T_1913 connect _WIRE_6[3], _T_1919 connect _WIRE_6[4], _T_1925 connect _WIRE_6[5], _T_1926 connect _WIRE_6[6], _T_1927 connect _WIRE_6[7], _T_1928 connect _WIRE_6[8], _T_1929 connect _WIRE_6[9], _T_1930 connect _WIRE_6[10], _T_1931 connect _WIRE_6[11], _T_1932 connect _WIRE_6[12], _T_1933 node _T_1934 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1935 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1936 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1937 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1938 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1939 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1940 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1941 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1942 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1943 = mux(_WIRE_6[5], _T_1934, UInt<1>(0h0)) node _T_1944 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1945 = mux(_WIRE_6[7], _T_1935, UInt<1>(0h0)) node _T_1946 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1947 = mux(_WIRE_6[9], _T_1936, UInt<1>(0h0)) node _T_1948 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1949 = mux(_WIRE_6[11], _T_1937, UInt<1>(0h0)) node _T_1950 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1951 = or(_T_1938, _T_1939) node _T_1952 = or(_T_1951, _T_1940) node _T_1953 = or(_T_1952, _T_1941) node _T_1954 = or(_T_1953, _T_1942) node _T_1955 = or(_T_1954, _T_1943) node _T_1956 = or(_T_1955, _T_1944) node _T_1957 = or(_T_1956, _T_1945) node _T_1958 = or(_T_1957, _T_1946) node _T_1959 = or(_T_1958, _T_1947) node _T_1960 = or(_T_1959, _T_1948) node _T_1961 = or(_T_1960, _T_1949) node _T_1962 = or(_T_1961, _T_1950) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1962 node _T_1963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1965 = and(_T_1963, _T_1964) node _T_1966 = or(UInt<1>(0h0), _T_1965) node _T_1967 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1968 = cvt(_T_1967) node _T_1969 = and(_T_1968, asSInt(UInt<17>(0h100c0))) node _T_1970 = asSInt(_T_1969) node _T_1971 = eq(_T_1970, asSInt(UInt<1>(0h0))) node _T_1972 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1973 = cvt(_T_1972) node _T_1974 = and(_T_1973, asSInt(UInt<29>(0h100000c0))) node _T_1975 = asSInt(_T_1974) node _T_1976 = eq(_T_1975, asSInt(UInt<1>(0h0))) node _T_1977 = or(_T_1971, _T_1976) node _T_1978 = and(_T_1966, _T_1977) node _T_1979 = or(UInt<1>(0h0), _T_1978) node _T_1980 = and(_WIRE_7, _T_1979) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_144 node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(source_ok_2, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1987 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_146 node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1994 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_148 node _T_1998 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_149 node _T_2002 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2002 : node _T_2003 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2004 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2005 = and(_T_2003, _T_2004) node _T_2006 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2007 = shr(io.in.c.bits.source, 2) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) node _T_2009 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2010 = and(_T_2008, _T_2009) node _T_2011 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2012 = and(_T_2010, _T_2011) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2013 = shr(io.in.c.bits.source, 2) node _T_2014 = eq(_T_2013, UInt<1>(0h1)) node _T_2015 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2016 = and(_T_2014, _T_2015) node _T_2017 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2018 = and(_T_2016, _T_2017) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2019 = shr(io.in.c.bits.source, 2) node _T_2020 = eq(_T_2019, UInt<2>(0h2)) node _T_2021 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2022 = and(_T_2020, _T_2021) node _T_2023 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2024 = and(_T_2022, _T_2023) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2025 = shr(io.in.c.bits.source, 2) node _T_2026 = eq(_T_2025, UInt<2>(0h3)) node _T_2027 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2028 = and(_T_2026, _T_2027) node _T_2029 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2032 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2033 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2034 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2035 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2036 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2037 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2038 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2039 = or(_T_2006, _T_2012) node _T_2040 = or(_T_2039, _T_2018) node _T_2041 = or(_T_2040, _T_2024) node _T_2042 = or(_T_2041, _T_2030) node _T_2043 = or(_T_2042, _T_2031) node _T_2044 = or(_T_2043, _T_2032) node _T_2045 = or(_T_2044, _T_2033) node _T_2046 = or(_T_2045, _T_2034) node _T_2047 = or(_T_2046, _T_2035) node _T_2048 = or(_T_2047, _T_2036) node _T_2049 = or(_T_2048, _T_2037) node _T_2050 = or(_T_2049, _T_2038) node _T_2051 = and(_T_2005, _T_2050) node _T_2052 = or(UInt<1>(0h0), _T_2051) node _T_2053 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h100c0))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<29>(0h100000c0))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = or(_T_2059, _T_2064) node _T_2066 = and(_T_2054, _T_2065) node _T_2067 = or(UInt<1>(0h0), _T_2066) node _T_2068 = and(_T_2052, _T_2067) node _T_2069 = asUInt(reset) node _T_2070 = eq(_T_2069, UInt<1>(0h0)) when _T_2070 : node _T_2071 = eq(_T_2068, UInt<1>(0h0)) when _T_2071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2068, UInt<1>(0h1), "") : assert_150 node _T_2072 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2073 = shr(io.in.c.bits.source, 2) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) node _T_2075 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2076 = and(_T_2074, _T_2075) node _T_2077 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2078 = and(_T_2076, _T_2077) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2079 = shr(io.in.c.bits.source, 2) node _T_2080 = eq(_T_2079, UInt<1>(0h1)) node _T_2081 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2082 = and(_T_2080, _T_2081) node _T_2083 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2084 = and(_T_2082, _T_2083) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2085 = shr(io.in.c.bits.source, 2) node _T_2086 = eq(_T_2085, UInt<2>(0h2)) node _T_2087 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2088 = and(_T_2086, _T_2087) node _T_2089 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2090 = and(_T_2088, _T_2089) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2091 = shr(io.in.c.bits.source, 2) node _T_2092 = eq(_T_2091, UInt<2>(0h3)) node _T_2093 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2094 = and(_T_2092, _T_2093) node _T_2095 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2098 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2099 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2101 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2102 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2103 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2104 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[13] connect _WIRE_8[0], _T_2072 connect _WIRE_8[1], _T_2078 connect _WIRE_8[2], _T_2084 connect _WIRE_8[3], _T_2090 connect _WIRE_8[4], _T_2096 connect _WIRE_8[5], _T_2097 connect _WIRE_8[6], _T_2098 connect _WIRE_8[7], _T_2099 connect _WIRE_8[8], _T_2100 connect _WIRE_8[9], _T_2101 connect _WIRE_8[10], _T_2102 connect _WIRE_8[11], _T_2103 connect _WIRE_8[12], _T_2104 node _T_2105 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2106 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2107 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2110 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2111 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2112 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2113 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2114 = mux(_WIRE_8[5], _T_2105, UInt<1>(0h0)) node _T_2115 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2116 = mux(_WIRE_8[7], _T_2106, UInt<1>(0h0)) node _T_2117 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2118 = mux(_WIRE_8[9], _T_2107, UInt<1>(0h0)) node _T_2119 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2120 = mux(_WIRE_8[11], _T_2108, UInt<1>(0h0)) node _T_2121 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2122 = or(_T_2109, _T_2110) node _T_2123 = or(_T_2122, _T_2111) node _T_2124 = or(_T_2123, _T_2112) node _T_2125 = or(_T_2124, _T_2113) node _T_2126 = or(_T_2125, _T_2114) node _T_2127 = or(_T_2126, _T_2115) node _T_2128 = or(_T_2127, _T_2116) node _T_2129 = or(_T_2128, _T_2117) node _T_2130 = or(_T_2129, _T_2118) node _T_2131 = or(_T_2130, _T_2119) node _T_2132 = or(_T_2131, _T_2120) node _T_2133 = or(_T_2132, _T_2121) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2133 node _T_2134 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2135 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2136 = and(_T_2134, _T_2135) node _T_2137 = or(UInt<1>(0h0), _T_2136) node _T_2138 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2139 = cvt(_T_2138) node _T_2140 = and(_T_2139, asSInt(UInt<17>(0h100c0))) node _T_2141 = asSInt(_T_2140) node _T_2142 = eq(_T_2141, asSInt(UInt<1>(0h0))) node _T_2143 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2144 = cvt(_T_2143) node _T_2145 = and(_T_2144, asSInt(UInt<29>(0h100000c0))) node _T_2146 = asSInt(_T_2145) node _T_2147 = eq(_T_2146, asSInt(UInt<1>(0h0))) node _T_2148 = or(_T_2142, _T_2147) node _T_2149 = and(_T_2137, _T_2148) node _T_2150 = or(UInt<1>(0h0), _T_2149) node _T_2151 = and(_WIRE_9, _T_2150) node _T_2152 = asUInt(reset) node _T_2153 = eq(_T_2152, UInt<1>(0h0)) when _T_2153 : node _T_2154 = eq(_T_2151, UInt<1>(0h0)) when _T_2154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2151, UInt<1>(0h1), "") : assert_151 node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(source_ok_2, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2158 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(_T_2158, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2158, UInt<1>(0h1), "") : assert_153 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2165 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_155 node _T_2169 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2169 : node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(address_ok_1, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(source_ok_2, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2179 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_159 node _T_2183 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_160 node _T_2187 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2187 : node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(address_ok_1, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(source_ok_2, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2197 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_164 node _T_2201 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2201 : node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(address_ok_1, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(source_ok_2, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2211 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_168 node _T_2215 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2222 = eq(a_first, UInt<1>(0h0)) node _T_2223 = and(io.in.a.valid, _T_2222) when _T_2223 : node _T_2224 = eq(io.in.a.bits.opcode, opcode) node _T_2225 = asUInt(reset) node _T_2226 = eq(_T_2225, UInt<1>(0h0)) when _T_2226 : node _T_2227 = eq(_T_2224, UInt<1>(0h0)) when _T_2227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2224, UInt<1>(0h1), "") : assert_171 node _T_2228 = eq(io.in.a.bits.param, param) node _T_2229 = asUInt(reset) node _T_2230 = eq(_T_2229, UInt<1>(0h0)) when _T_2230 : node _T_2231 = eq(_T_2228, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2228, UInt<1>(0h1), "") : assert_172 node _T_2232 = eq(io.in.a.bits.size, size) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_173 node _T_2236 = eq(io.in.a.bits.source, source) node _T_2237 = asUInt(reset) node _T_2238 = eq(_T_2237, UInt<1>(0h0)) when _T_2238 : node _T_2239 = eq(_T_2236, UInt<1>(0h0)) when _T_2239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2236, UInt<1>(0h1), "") : assert_174 node _T_2240 = eq(io.in.a.bits.address, address) node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(_T_2240, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2240, UInt<1>(0h1), "") : assert_175 node _T_2244 = and(io.in.a.ready, io.in.a.valid) node _T_2245 = and(_T_2244, a_first) when _T_2245 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2246 = eq(d_first, UInt<1>(0h0)) node _T_2247 = and(io.in.d.valid, _T_2246) when _T_2247 : node _T_2248 = eq(io.in.d.bits.opcode, opcode_1) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_176 node _T_2252 = eq(io.in.d.bits.param, param_1) node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(_T_2252, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2252, UInt<1>(0h1), "") : assert_177 node _T_2256 = eq(io.in.d.bits.size, size_1) node _T_2257 = asUInt(reset) node _T_2258 = eq(_T_2257, UInt<1>(0h0)) when _T_2258 : node _T_2259 = eq(_T_2256, UInt<1>(0h0)) when _T_2259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2256, UInt<1>(0h1), "") : assert_178 node _T_2260 = eq(io.in.d.bits.source, source_1) node _T_2261 = asUInt(reset) node _T_2262 = eq(_T_2261, UInt<1>(0h0)) when _T_2262 : node _T_2263 = eq(_T_2260, UInt<1>(0h0)) when _T_2263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2260, UInt<1>(0h1), "") : assert_179 node _T_2264 = eq(io.in.d.bits.sink, sink) node _T_2265 = asUInt(reset) node _T_2266 = eq(_T_2265, UInt<1>(0h0)) when _T_2266 : node _T_2267 = eq(_T_2264, UInt<1>(0h0)) when _T_2267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2264, UInt<1>(0h1), "") : assert_180 node _T_2268 = eq(io.in.d.bits.denied, denied) node _T_2269 = asUInt(reset) node _T_2270 = eq(_T_2269, UInt<1>(0h0)) when _T_2270 : node _T_2271 = eq(_T_2268, UInt<1>(0h0)) when _T_2271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2268, UInt<1>(0h1), "") : assert_181 node _T_2272 = and(io.in.d.ready, io.in.d.valid) node _T_2273 = and(_T_2272, d_first) when _T_2273 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2274 = eq(b_first, UInt<1>(0h0)) node _T_2275 = and(io.in.b.valid, _T_2274) when _T_2275 : node _T_2276 = eq(io.in.b.bits.opcode, opcode_2) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_182 node _T_2280 = eq(io.in.b.bits.param, param_2) node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(_T_2280, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2280, UInt<1>(0h1), "") : assert_183 node _T_2284 = eq(io.in.b.bits.size, size_2) node _T_2285 = asUInt(reset) node _T_2286 = eq(_T_2285, UInt<1>(0h0)) when _T_2286 : node _T_2287 = eq(_T_2284, UInt<1>(0h0)) when _T_2287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2284, UInt<1>(0h1), "") : assert_184 node _T_2288 = eq(io.in.b.bits.source, source_2) node _T_2289 = asUInt(reset) node _T_2290 = eq(_T_2289, UInt<1>(0h0)) when _T_2290 : node _T_2291 = eq(_T_2288, UInt<1>(0h0)) when _T_2291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2288, UInt<1>(0h1), "") : assert_185 node _T_2292 = eq(io.in.b.bits.address, address_1) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_186 node _T_2296 = and(io.in.b.ready, io.in.b.valid) node _T_2297 = and(_T_2296, b_first) when _T_2297 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2298 = eq(c_first, UInt<1>(0h0)) node _T_2299 = and(io.in.c.valid, _T_2298) when _T_2299 : node _T_2300 = eq(io.in.c.bits.opcode, opcode_3) node _T_2301 = asUInt(reset) node _T_2302 = eq(_T_2301, UInt<1>(0h0)) when _T_2302 : node _T_2303 = eq(_T_2300, UInt<1>(0h0)) when _T_2303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2300, UInt<1>(0h1), "") : assert_187 node _T_2304 = eq(io.in.c.bits.param, param_3) node _T_2305 = asUInt(reset) node _T_2306 = eq(_T_2305, UInt<1>(0h0)) when _T_2306 : node _T_2307 = eq(_T_2304, UInt<1>(0h0)) when _T_2307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2304, UInt<1>(0h1), "") : assert_188 node _T_2308 = eq(io.in.c.bits.size, size_3) node _T_2309 = asUInt(reset) node _T_2310 = eq(_T_2309, UInt<1>(0h0)) when _T_2310 : node _T_2311 = eq(_T_2308, UInt<1>(0h0)) when _T_2311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2308, UInt<1>(0h1), "") : assert_189 node _T_2312 = eq(io.in.c.bits.source, source_3) node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(_T_2312, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2312, UInt<1>(0h1), "") : assert_190 node _T_2316 = eq(io.in.c.bits.address, address_2) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_191 node _T_2320 = and(io.in.c.ready, io.in.c.valid) node _T_2321 = and(_T_2320, c_first) when _T_2321 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes : UInt<188>, clock, reset, UInt<188>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<47> connect a_set, UInt<47>(0h0) wire a_set_wo_ready : UInt<47> connect a_set_wo_ready, UInt<47>(0h0) wire a_opcodes_set : UInt<188> connect a_opcodes_set, UInt<188>(0h0) wire a_sizes_set : UInt<188> connect a_sizes_set, UInt<188>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2322 = and(io.in.a.valid, a_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) when _T_2323 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2324 = and(io.in.a.ready, io.in.a.valid) node _T_2325 = and(_T_2324, a_first_1) node _T_2326 = and(_T_2325, UInt<1>(0h1)) when _T_2326 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2327 = dshr(inflight, io.in.a.bits.source) node _T_2328 = bits(_T_2327, 0, 0) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(_T_2329, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2329, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<47> connect d_clr, UInt<47>(0h0) wire d_clr_wo_ready : UInt<47> connect d_clr_wo_ready, UInt<47>(0h0) wire d_opcodes_clr : UInt<188> connect d_opcodes_clr, UInt<188>(0h0) wire d_sizes_clr : UInt<188> connect d_sizes_clr, UInt<188>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2333 = and(io.in.d.valid, d_first_1) node _T_2334 = and(_T_2333, UInt<1>(0h1)) node _T_2335 = eq(d_release_ack, UInt<1>(0h0)) node _T_2336 = and(_T_2334, _T_2335) when _T_2336 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2337 = and(io.in.d.ready, io.in.d.valid) node _T_2338 = and(_T_2337, d_first_1) node _T_2339 = and(_T_2338, UInt<1>(0h1)) node _T_2340 = eq(d_release_ack, UInt<1>(0h0)) node _T_2341 = and(_T_2339, _T_2340) when _T_2341 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2342 = and(io.in.d.valid, d_first_1) node _T_2343 = and(_T_2342, UInt<1>(0h1)) node _T_2344 = eq(d_release_ack, UInt<1>(0h0)) node _T_2345 = and(_T_2343, _T_2344) when _T_2345 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2346 = dshr(inflight, io.in.d.bits.source) node _T_2347 = bits(_T_2346, 0, 0) node _T_2348 = or(_T_2347, same_cycle_resp) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2352 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2353 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2354 = or(_T_2352, _T_2353) node _T_2355 = asUInt(reset) node _T_2356 = eq(_T_2355, UInt<1>(0h0)) when _T_2356 : node _T_2357 = eq(_T_2354, UInt<1>(0h0)) when _T_2357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2354, UInt<1>(0h1), "") : assert_194 node _T_2358 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_195 else : node _T_2362 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2363 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2364 = or(_T_2362, _T_2363) node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(_T_2364, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2364, UInt<1>(0h1), "") : assert_196 node _T_2368 = eq(io.in.d.bits.size, a_size_lookup) node _T_2369 = asUInt(reset) node _T_2370 = eq(_T_2369, UInt<1>(0h0)) when _T_2370 : node _T_2371 = eq(_T_2368, UInt<1>(0h0)) when _T_2371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2368, UInt<1>(0h1), "") : assert_197 node _T_2372 = and(io.in.d.valid, d_first_1) node _T_2373 = and(_T_2372, a_first_1) node _T_2374 = and(_T_2373, io.in.a.valid) node _T_2375 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2376 = and(_T_2374, _T_2375) node _T_2377 = eq(d_release_ack, UInt<1>(0h0)) node _T_2378 = and(_T_2376, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2380 = or(_T_2379, io.in.a.ready) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_198 node _T_2384 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2385 = orr(a_set_wo_ready) node _T_2386 = eq(_T_2385, UInt<1>(0h0)) node _T_2387 = or(_T_2384, _T_2386) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_97 node _T_2391 = orr(inflight) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) node _T_2393 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2394 = or(_T_2392, _T_2393) node _T_2395 = lt(watchdog, plusarg_reader.out) node _T_2396 = or(_T_2394, _T_2395) node _T_2397 = asUInt(reset) node _T_2398 = eq(_T_2397, UInt<1>(0h0)) when _T_2398 : node _T_2399 = eq(_T_2396, UInt<1>(0h0)) when _T_2399 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2396, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2400 = and(io.in.a.ready, io.in.a.valid) node _T_2401 = and(io.in.d.ready, io.in.d.valid) node _T_2402 = or(_T_2400, _T_2401) when _T_2402 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes_1 : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes_1 : UInt<188>, clock, reset, UInt<188>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<47> connect c_set, UInt<47>(0h0) wire c_set_wo_ready : UInt<47> connect c_set_wo_ready, UInt<47>(0h0) wire c_opcodes_set : UInt<188> connect c_opcodes_set, UInt<188>(0h0) wire c_sizes_set : UInt<188> connect c_sizes_set, UInt<188>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2403 = and(io.in.c.valid, c_first_1) node _T_2404 = bits(io.in.c.bits.opcode, 2, 2) node _T_2405 = bits(io.in.c.bits.opcode, 1, 1) node _T_2406 = and(_T_2404, _T_2405) node _T_2407 = and(_T_2403, _T_2406) when _T_2407 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2408 = and(io.in.c.ready, io.in.c.valid) node _T_2409 = and(_T_2408, c_first_1) node _T_2410 = bits(io.in.c.bits.opcode, 2, 2) node _T_2411 = bits(io.in.c.bits.opcode, 1, 1) node _T_2412 = and(_T_2410, _T_2411) node _T_2413 = and(_T_2409, _T_2412) when _T_2413 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2414 = dshr(inflight_1, io.in.c.bits.source) node _T_2415 = bits(_T_2414, 0, 0) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) node _T_2417 = asUInt(reset) node _T_2418 = eq(_T_2417, UInt<1>(0h0)) when _T_2418 : node _T_2419 = eq(_T_2416, UInt<1>(0h0)) when _T_2419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2416, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<47> connect d_clr_1, UInt<47>(0h0) wire d_clr_wo_ready_1 : UInt<47> connect d_clr_wo_ready_1, UInt<47>(0h0) wire d_opcodes_clr_1 : UInt<188> connect d_opcodes_clr_1, UInt<188>(0h0) wire d_sizes_clr_1 : UInt<188> connect d_sizes_clr_1, UInt<188>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2420 = and(io.in.d.valid, d_first_2) node _T_2421 = and(_T_2420, UInt<1>(0h1)) node _T_2422 = and(_T_2421, d_release_ack_1) when _T_2422 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first_2) node _T_2425 = and(_T_2424, UInt<1>(0h1)) node _T_2426 = and(_T_2425, d_release_ack_1) when _T_2426 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2427 = and(io.in.d.valid, d_first_2) node _T_2428 = and(_T_2427, UInt<1>(0h1)) node _T_2429 = and(_T_2428, d_release_ack_1) when _T_2429 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2430 = dshr(inflight_1, io.in.d.bits.source) node _T_2431 = bits(_T_2430, 0, 0) node _T_2432 = or(_T_2431, same_cycle_resp_1) node _T_2433 = asUInt(reset) node _T_2434 = eq(_T_2433, UInt<1>(0h0)) when _T_2434 : node _T_2435 = eq(_T_2432, UInt<1>(0h0)) when _T_2435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2432, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2436 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2437 = asUInt(reset) node _T_2438 = eq(_T_2437, UInt<1>(0h0)) when _T_2438 : node _T_2439 = eq(_T_2436, UInt<1>(0h0)) when _T_2439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2436, UInt<1>(0h1), "") : assert_203 else : node _T_2440 = eq(io.in.d.bits.size, c_size_lookup) node _T_2441 = asUInt(reset) node _T_2442 = eq(_T_2441, UInt<1>(0h0)) when _T_2442 : node _T_2443 = eq(_T_2440, UInt<1>(0h0)) when _T_2443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2440, UInt<1>(0h1), "") : assert_204 node _T_2444 = and(io.in.d.valid, d_first_2) node _T_2445 = and(_T_2444, c_first_1) node _T_2446 = and(_T_2445, io.in.c.valid) node _T_2447 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2448 = and(_T_2446, _T_2447) node _T_2449 = and(_T_2448, d_release_ack_1) node _T_2450 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2451 = and(_T_2449, _T_2450) when _T_2451 : node _T_2452 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2453 = or(_T_2452, io.in.c.ready) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_205 node _T_2457 = orr(c_set_wo_ready) when _T_2457 : node _T_2458 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2459 = asUInt(reset) node _T_2460 = eq(_T_2459, UInt<1>(0h0)) when _T_2460 : node _T_2461 = eq(_T_2458, UInt<1>(0h0)) when _T_2461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2458, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_98 node _T_2462 = orr(inflight_1) node _T_2463 = eq(_T_2462, UInt<1>(0h0)) node _T_2464 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2465 = or(_T_2463, _T_2464) node _T_2466 = lt(watchdog_1, plusarg_reader_1.out) node _T_2467 = or(_T_2465, _T_2466) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(io.in.d.ready, io.in.d.valid) node _T_2473 = or(_T_2471, _T_2472) when _T_2473 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_3) node _T_2476 = bits(io.in.d.bits.opcode, 2, 2) node _T_2477 = bits(io.in.d.bits.opcode, 1, 1) node _T_2478 = eq(_T_2477, UInt<1>(0h0)) node _T_2479 = and(_T_2476, _T_2478) node _T_2480 = and(_T_2475, _T_2479) when _T_2480 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2481 = dshr(inflight_2, io.in.d.bits.sink) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2487 = and(io.in.e.ready, io.in.e.valid) node _T_2488 = and(_T_2487, UInt<1>(0h1)) node _T_2489 = and(_T_2488, UInt<1>(0h1)) when _T_2489 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2490 = or(d_set, inflight_2) node _T_2491 = dshr(_T_2490, io.in.e.bits.sink) node _T_2492 = bits(_T_2491, 0, 0) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_100 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [46:0] inflight; // @[Monitor.scala:614:27] reg [187:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [187:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [46:0] inflight_1; // @[Monitor.scala:726:35] reg [187:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_11 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_88 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_91 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_11( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_88 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_91 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ICache_1 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<64>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, perf : { acquire : UInt<1>}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut node s0_valid = and(io.req.ready, io.req.valid) reg s1_valid : UInt<1>, clock connect s1_valid, s0_valid wire s1_tag_hit : UInt<1>[4] node _s1_hit_T = or(s1_tag_hit[0], s1_tag_hit[1]) node _s1_hit_T_1 = or(_s1_hit_T, s1_tag_hit[2]) node s1_hit = or(_s1_hit_T_1, s1_tag_hit[3]) node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) reg s2_valid : UInt<1>, clock connect s2_valid, _s2_valid_T_1 reg s2_hit : UInt<1>, clock connect s2_hit, s1_hit reg invalidated : UInt<1>, clock regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0) node refill_fire = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _s2_miss_T = eq(s2_hit, UInt<1>(0h0)) node _s2_miss_T_1 = and(s2_valid, _s2_miss_T) reg s2_miss_REG : UInt<1>, clock connect s2_miss_REG, refill_valid node _s2_miss_T_2 = eq(s2_miss_REG, UInt<1>(0h0)) node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2) node _refill_paddr_T = or(refill_valid, s2_miss) node _refill_paddr_T_1 = eq(_refill_paddr_T, UInt<1>(0h0)) node _refill_paddr_T_2 = and(s1_valid, _refill_paddr_T_1) reg refill_paddr : UInt<32>, clock when _refill_paddr_T_2 : connect refill_paddr, io.s1_paddr node refill_tag = bits(refill_paddr, 31, 12) node refill_idx = bits(refill_paddr, 11, 6) node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata) node _io_req_ready_T = eq(refill_one_beat, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node d_done = and(r_2, _T) node _r_count_T = not(r_counter1) node refill_cnt = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_done = and(refill_one_beat, d_done) connect masterNodeOut.d.ready, UInt<1>(0h1) inst repl_way_prng of MaxPeriodFibonacciLFSR_8 connect repl_way_prng.clock, clock connect repl_way_prng.reset, reset connect repl_way_prng.io.seed.valid, UInt<1>(0h0) invalidate repl_way_prng.io.seed.bits[0] invalidate repl_way_prng.io.seed.bits[1] invalidate repl_way_prng.io.seed.bits[2] invalidate repl_way_prng.io.seed.bits[3] invalidate repl_way_prng.io.seed.bits[4] invalidate repl_way_prng.io.seed.bits[5] invalidate repl_way_prng.io.seed.bits[6] invalidate repl_way_prng.io.seed.bits[7] invalidate repl_way_prng.io.seed.bits[8] invalidate repl_way_prng.io.seed.bits[9] invalidate repl_way_prng.io.seed.bits[10] invalidate repl_way_prng.io.seed.bits[11] invalidate repl_way_prng.io.seed.bits[12] invalidate repl_way_prng.io.seed.bits[13] invalidate repl_way_prng.io.seed.bits[14] invalidate repl_way_prng.io.seed.bits[15] connect repl_way_prng.io.increment, refill_fire node repl_way_lo_lo_lo = cat(repl_way_prng.io.out[1], repl_way_prng.io.out[0]) node repl_way_lo_lo_hi = cat(repl_way_prng.io.out[3], repl_way_prng.io.out[2]) node repl_way_lo_lo = cat(repl_way_lo_lo_hi, repl_way_lo_lo_lo) node repl_way_lo_hi_lo = cat(repl_way_prng.io.out[5], repl_way_prng.io.out[4]) node repl_way_lo_hi_hi = cat(repl_way_prng.io.out[7], repl_way_prng.io.out[6]) node repl_way_lo_hi = cat(repl_way_lo_hi_hi, repl_way_lo_hi_lo) node repl_way_lo = cat(repl_way_lo_hi, repl_way_lo_lo) node repl_way_hi_lo_lo = cat(repl_way_prng.io.out[9], repl_way_prng.io.out[8]) node repl_way_hi_lo_hi = cat(repl_way_prng.io.out[11], repl_way_prng.io.out[10]) node repl_way_hi_lo = cat(repl_way_hi_lo_hi, repl_way_hi_lo_lo) node repl_way_hi_hi_lo = cat(repl_way_prng.io.out[13], repl_way_prng.io.out[12]) node repl_way_hi_hi_hi = cat(repl_way_prng.io.out[15], repl_way_prng.io.out[14]) node repl_way_hi_hi = cat(repl_way_hi_hi_hi, repl_way_hi_hi_lo) node repl_way_hi = cat(repl_way_hi_hi, repl_way_hi_lo) node _repl_way_T = cat(repl_way_hi, repl_way_lo) node repl_way = bits(_repl_way_T, 1, 0) smem tag_array : UInt<20>[4] [64] node _tag_rdata_T = bits(io.req.bits.addr, 11, 6) node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0)) node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid) wire _tag_rdata_WIRE : UInt<6> invalidate _tag_rdata_WIRE when _tag_rdata_T_2 : connect _tag_rdata_WIRE, _tag_rdata_T read mport tag_rdata = tag_array[_tag_rdata_WIRE], clock when refill_done : wire _WIRE : UInt<20>[4] connect _WIRE[0], refill_tag connect _WIRE[1], refill_tag connect _WIRE[2], refill_tag connect _WIRE[3], refill_tag node _T_1 = eq(repl_way, UInt<1>(0h0)) node _T_2 = eq(repl_way, UInt<1>(0h1)) node _T_3 = eq(repl_way, UInt<2>(0h2)) node _T_4 = eq(repl_way, UInt<2>(0h3)) write mport MPORT = tag_array[refill_idx], clock when _T_1 : connect MPORT[0], _WIRE[0] when _T_2 : connect MPORT[1], _WIRE[1] when _T_3 : connect MPORT[2], _WIRE[2] when _T_4 : connect MPORT[3], _WIRE[3] regreset vb_array : UInt<256>, clock, reset, UInt<256>(0h0) when refill_one_beat : node _vb_array_T = cat(repl_way, refill_idx) node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0)) node _vb_array_T_2 = and(refill_done, _vb_array_T_1) node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T) node _vb_array_T_4 = or(vb_array, _vb_array_T_3) node _vb_array_T_5 = not(vb_array) node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3) node _vb_array_T_7 = not(_vb_array_T_6) node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7) connect vb_array, _vb_array_T_8 when io.invalidate : connect vb_array, UInt<1>(0h0) connect invalidated, UInt<1>(0h1) wire s2_dout : UInt<64>[4] wire s1_bankid : UInt<1> node s1_idx = bits(io.s1_paddr, 11, 6) node s1_tag = bits(io.s1_paddr, 31, 12) node _s1_vb_T = cat(UInt<1>(0h0), s1_idx) node _s1_vb_T_1 = dshr(vb_array, _s1_vb_T) node s1_vb = bits(_s1_vb_T_1, 0, 0) node _s1_tag_hit_0_T = eq(tag_rdata[0], s1_tag) node _s1_tag_hit_0_T_1 = and(s1_vb, _s1_tag_hit_0_T) connect s1_tag_hit[0], _s1_tag_hit_0_T_1 node s1_idx_1 = bits(io.s1_paddr, 11, 6) node s1_tag_1 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_2 = cat(UInt<1>(0h1), s1_idx_1) node _s1_vb_T_3 = dshr(vb_array, _s1_vb_T_2) node s1_vb_1 = bits(_s1_vb_T_3, 0, 0) node _s1_tag_hit_1_T = eq(tag_rdata[1], s1_tag_1) node _s1_tag_hit_1_T_1 = and(s1_vb_1, _s1_tag_hit_1_T) connect s1_tag_hit[1], _s1_tag_hit_1_T_1 node s1_idx_2 = bits(io.s1_paddr, 11, 6) node s1_tag_2 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_4 = cat(UInt<2>(0h2), s1_idx_2) node _s1_vb_T_5 = dshr(vb_array, _s1_vb_T_4) node s1_vb_2 = bits(_s1_vb_T_5, 0, 0) node _s1_tag_hit_2_T = eq(tag_rdata[2], s1_tag_2) node _s1_tag_hit_2_T_1 = and(s1_vb_2, _s1_tag_hit_2_T) connect s1_tag_hit[2], _s1_tag_hit_2_T_1 node s1_idx_3 = bits(io.s1_paddr, 11, 6) node s1_tag_3 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_6 = cat(UInt<2>(0h3), s1_idx_3) node _s1_vb_T_7 = dshr(vb_array, _s1_vb_T_6) node s1_vb_3 = bits(_s1_vb_T_7, 0, 0) node _s1_tag_hit_3_T = eq(tag_rdata[3], s1_tag_3) node _s1_tag_hit_3_T_1 = and(s1_vb_3, _s1_tag_hit_3_T) connect s1_tag_hit[3], _s1_tag_hit_3_T_1 node _T_5 = add(s1_tag_hit[0], s1_tag_hit[1]) node _T_6 = bits(_T_5, 1, 0) node _T_7 = add(s1_tag_hit[2], s1_tag_hit[3]) node _T_8 = bits(_T_7, 1, 0) node _T_9 = add(_T_6, _T_8) node _T_10 = bits(_T_9, 2, 0) node _T_11 = leq(_T_10, UInt<1>(0h1)) node _T_12 = eq(s1_valid, UInt<1>(0h0)) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at icache.scala:179 assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n") : printf assert(clock, _T_13, UInt<1>(0h1), "") : assert smem dataArrayWay_0 : UInt<64> [512] smem dataArrayWay_1 : UInt<64> [512] smem dataArrayWay_2 : UInt<64> [512] smem dataArrayWay_3 : UInt<64> [512] connect s1_bankid, UInt<1>(0h0) node _wen_T = eq(invalidated, UInt<1>(0h0)) node _wen_T_1 = and(refill_one_beat, _wen_T) node _wen_T_2 = eq(repl_way, UInt<1>(0h0)) node wen = and(_wen_T_1, _wen_T_2) node _mem_idx_T = shl(refill_idx, 3) node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt) node _mem_idx_T_2 = bits(io.req.bits.addr, 11, 3) node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_2) when wen : write mport MPORT_1 = dataArrayWay_0[mem_idx], clock connect MPORT_1, masterNodeOut.d.bits.data node _s2_dout_0_T = eq(wen, UInt<1>(0h0)) node _s2_dout_0_T_1 = and(_s2_dout_0_T, s0_valid) wire _s2_dout_0_WIRE : UInt<9> invalidate _s2_dout_0_WIRE when _s2_dout_0_T_1 : connect _s2_dout_0_WIRE, mem_idx read mport s2_dout_0_MPORT = dataArrayWay_0[_s2_dout_0_WIRE], clock reg s2_dout_0_REG : UInt, clock connect s2_dout_0_REG, s2_dout_0_MPORT connect s2_dout[0], s2_dout_0_REG node _wen_T_3 = eq(invalidated, UInt<1>(0h0)) node _wen_T_4 = and(refill_one_beat, _wen_T_3) node _wen_T_5 = eq(repl_way, UInt<1>(0h1)) node wen_1 = and(_wen_T_4, _wen_T_5) node _mem_idx_T_3 = shl(refill_idx, 3) node _mem_idx_T_4 = or(_mem_idx_T_3, refill_cnt) node _mem_idx_T_5 = bits(io.req.bits.addr, 11, 3) node mem_idx_1 = mux(refill_one_beat, _mem_idx_T_4, _mem_idx_T_5) when wen_1 : write mport MPORT_2 = dataArrayWay_1[mem_idx_1], clock connect MPORT_2, masterNodeOut.d.bits.data node _s2_dout_1_T = eq(wen_1, UInt<1>(0h0)) node _s2_dout_1_T_1 = and(_s2_dout_1_T, s0_valid) wire _s2_dout_1_WIRE : UInt<9> invalidate _s2_dout_1_WIRE when _s2_dout_1_T_1 : connect _s2_dout_1_WIRE, mem_idx_1 read mport s2_dout_1_MPORT = dataArrayWay_1[_s2_dout_1_WIRE], clock reg s2_dout_1_REG : UInt, clock connect s2_dout_1_REG, s2_dout_1_MPORT connect s2_dout[1], s2_dout_1_REG node _wen_T_6 = eq(invalidated, UInt<1>(0h0)) node _wen_T_7 = and(refill_one_beat, _wen_T_6) node _wen_T_8 = eq(repl_way, UInt<2>(0h2)) node wen_2 = and(_wen_T_7, _wen_T_8) node _mem_idx_T_6 = shl(refill_idx, 3) node _mem_idx_T_7 = or(_mem_idx_T_6, refill_cnt) node _mem_idx_T_8 = bits(io.req.bits.addr, 11, 3) node mem_idx_2 = mux(refill_one_beat, _mem_idx_T_7, _mem_idx_T_8) when wen_2 : write mport MPORT_3 = dataArrayWay_2[mem_idx_2], clock connect MPORT_3, masterNodeOut.d.bits.data node _s2_dout_2_T = eq(wen_2, UInt<1>(0h0)) node _s2_dout_2_T_1 = and(_s2_dout_2_T, s0_valid) wire _s2_dout_2_WIRE : UInt<9> invalidate _s2_dout_2_WIRE when _s2_dout_2_T_1 : connect _s2_dout_2_WIRE, mem_idx_2 read mport s2_dout_2_MPORT = dataArrayWay_2[_s2_dout_2_WIRE], clock reg s2_dout_2_REG : UInt, clock connect s2_dout_2_REG, s2_dout_2_MPORT connect s2_dout[2], s2_dout_2_REG node _wen_T_9 = eq(invalidated, UInt<1>(0h0)) node _wen_T_10 = and(refill_one_beat, _wen_T_9) node _wen_T_11 = eq(repl_way, UInt<2>(0h3)) node wen_3 = and(_wen_T_10, _wen_T_11) node _mem_idx_T_9 = shl(refill_idx, 3) node _mem_idx_T_10 = or(_mem_idx_T_9, refill_cnt) node _mem_idx_T_11 = bits(io.req.bits.addr, 11, 3) node mem_idx_3 = mux(refill_one_beat, _mem_idx_T_10, _mem_idx_T_11) when wen_3 : write mport MPORT_4 = dataArrayWay_3[mem_idx_3], clock connect MPORT_4, masterNodeOut.d.bits.data node _s2_dout_3_T = eq(wen_3, UInt<1>(0h0)) node _s2_dout_3_T_1 = and(_s2_dout_3_T, s0_valid) wire _s2_dout_3_WIRE : UInt<9> invalidate _s2_dout_3_WIRE when _s2_dout_3_T_1 : connect _s2_dout_3_WIRE, mem_idx_3 read mport s2_dout_3_MPORT = dataArrayWay_3[_s2_dout_3_WIRE], clock reg s2_dout_3_REG : UInt, clock connect s2_dout_3_REG, s2_dout_3_MPORT connect s2_dout[3], s2_dout_3_REG reg s2_tag_hit : UInt<1>[4], clock connect s2_tag_hit, s1_tag_hit node s2_hit_way_lo = cat(s2_tag_hit[1], s2_tag_hit[0]) node s2_hit_way_hi = cat(s2_tag_hit[3], s2_tag_hit[2]) node _s2_hit_way_T = cat(s2_hit_way_hi, s2_hit_way_lo) node s2_hit_way_hi_1 = bits(_s2_hit_way_T, 3, 2) node s2_hit_way_lo_1 = bits(_s2_hit_way_T, 1, 0) node _s2_hit_way_T_1 = orr(s2_hit_way_hi_1) node _s2_hit_way_T_2 = or(s2_hit_way_hi_1, s2_hit_way_lo_1) node _s2_hit_way_T_3 = bits(_s2_hit_way_T_2, 1, 1) node s2_hit_way = cat(_s2_hit_way_T_1, _s2_hit_way_T_3) reg s2_bankid : UInt<1>, clock connect s2_bankid, s1_bankid node _s2_way_mux_T = mux(s2_tag_hit[0], s2_dout[0], UInt<1>(0h0)) node _s2_way_mux_T_1 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>(0h0)) node _s2_way_mux_T_2 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>(0h0)) node _s2_way_mux_T_3 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>(0h0)) node _s2_way_mux_T_4 = or(_s2_way_mux_T, _s2_way_mux_T_1) node _s2_way_mux_T_5 = or(_s2_way_mux_T_4, _s2_way_mux_T_2) node _s2_way_mux_T_6 = or(_s2_way_mux_T_5, _s2_way_mux_T_3) wire s2_way_mux : UInt<64> connect s2_way_mux, _s2_way_mux_T_6 node s2_bank0_data = bits(s2_way_mux, 31, 0) node s2_bank1_data = bits(s2_way_mux, 63, 32) invalidate io.resp.bits.ae invalidate io.resp.bits.replay connect io.resp.bits.data, s2_way_mux node _io_resp_valid_T = and(s2_valid, s2_hit) connect io.resp.valid, _io_resp_valid_T node _masterNodeOut_a_valid_T = eq(refill_valid, UInt<1>(0h0)) node _masterNodeOut_a_valid_T_1 = and(s2_miss, _masterNodeOut_a_valid_T) node _masterNodeOut_a_valid_T_2 = eq(io.s2_kill, UInt<1>(0h0)) node _masterNodeOut_a_valid_T_3 = and(_masterNodeOut_a_valid_T_1, _masterNodeOut_a_valid_T_2) connect masterNodeOut.a.valid, _masterNodeOut_a_valid_T_3 node _masterNodeOut_a_bits_T = shr(refill_paddr, 6) node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6) node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc)) node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1) node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2) node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h3000)) node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4) node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6) node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8) node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11) node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12) node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0)) node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14) node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16) node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19) node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h98013000))) node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21) node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24) node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26) node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000)) node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29) node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31) node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34) node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h98000000))) node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36) node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39) node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41) node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000)) node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44) node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46) node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000)) node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49) node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0h90000000))) node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51) node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_54 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23) node _masterNodeOut_a_bits_legal_T_55 = or(_masterNodeOut_a_bits_legal_T_54, _masterNodeOut_a_bits_legal_T_28) node _masterNodeOut_a_bits_legal_T_56 = or(_masterNodeOut_a_bits_legal_T_55, _masterNodeOut_a_bits_legal_T_33) node _masterNodeOut_a_bits_legal_T_57 = or(_masterNodeOut_a_bits_legal_T_56, _masterNodeOut_a_bits_legal_T_38) node _masterNodeOut_a_bits_legal_T_58 = or(_masterNodeOut_a_bits_legal_T_57, _masterNodeOut_a_bits_legal_T_43) node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_58, _masterNodeOut_a_bits_legal_T_48) node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_53) node _masterNodeOut_a_bits_legal_T_61 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_60) node _masterNodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9) node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_61) wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4) connect masterNodeOut_a_bits_a.param, UInt<1>(0h0) connect masterNodeOut_a_bits_a.size, UInt<3>(0h6) connect masterNodeOut_a_bits_a.source, UInt<1>(0h0) connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1 node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0) node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount) node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0) node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1) node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1) node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0) node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0) node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq) node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T) node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1) node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1) node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2) node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2) node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3) node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3) node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4) node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4) node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5) node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5) node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6) node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6) node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7) node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7) node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc) node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2) node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo) node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4) node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6) node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo) node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo) connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T invalidate masterNodeOut_a_bits_a.data connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0) connect masterNodeOut.a.bits, masterNodeOut_a_bits_a wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits.corrupt, UInt<1>(0h0) connect _WIRE_1.bits.data, UInt<64>(0h0) connect _WIRE_1.bits.mask, UInt<8>(0h0) connect _WIRE_1.bits.address, UInt<32>(0h0) connect _WIRE_1.bits.source, UInt<1>(0h0) connect _WIRE_1.bits.size, UInt<4>(0h0) connect _WIRE_1.bits.param, UInt<2>(0h0) connect _WIRE_1.bits.opcode, UInt<3>(0h0) connect _WIRE_1.valid, UInt<1>(0h0) connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits, _WIRE_1.bits connect _WIRE_2.valid, _WIRE_1.valid connect _WIRE_2.ready, _WIRE_1.ready connect _WIRE_2.ready, UInt<1>(0h1) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits.corrupt, UInt<1>(0h0) connect _WIRE_3.bits.data, UInt<64>(0h0) connect _WIRE_3.bits.address, UInt<32>(0h0) connect _WIRE_3.bits.source, UInt<1>(0h0) connect _WIRE_3.bits.size, UInt<4>(0h0) connect _WIRE_3.bits.param, UInt<3>(0h0) connect _WIRE_3.bits.opcode, UInt<3>(0h0) connect _WIRE_3.valid, UInt<1>(0h0) connect _WIRE_3.ready, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits, _WIRE_3.bits connect _WIRE_4.valid, _WIRE_3.valid connect _WIRE_4.ready, _WIRE_3.ready connect _WIRE_4.valid, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits.sink, UInt<3>(0h0) connect _WIRE_5.valid, UInt<1>(0h0) connect _WIRE_5.ready, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_6.bits, _WIRE_5.bits connect _WIRE_6.valid, _WIRE_5.valid connect _WIRE_6.ready, _WIRE_5.ready connect _WIRE_6.valid, UInt<1>(0h0) node _io_perf_acquire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid) connect io.perf.acquire, _io_perf_acquire_T node _T_17 = eq(refill_valid, UInt<1>(0h0)) when _T_17 : connect invalidated, UInt<1>(0h0) when refill_fire : connect refill_valid, UInt<1>(0h1) when refill_done : connect refill_valid, UInt<1>(0h0)
module ICache_1( // @[icache.scala:103:7] input clock, // @[icache.scala:103:7] input reset, // @[icache.scala:103:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_req_valid, // @[icache.scala:107:14] input [38:0] io_req_bits_addr, // @[icache.scala:107:14] input [31:0] io_s1_paddr, // @[icache.scala:107:14] input io_s1_kill, // @[icache.scala:107:14] input io_s2_kill, // @[icache.scala:107:14] output io_resp_valid, // @[icache.scala:107:14] output [63:0] io_resp_bits_data, // @[icache.scala:107:14] input io_invalidate, // @[icache.scala:107:14] output io_perf_acquire // @[icache.scala:107:14] ); wire tag_array_MPORT_mask_3; // @[icache.scala:156:100] wire tag_array_MPORT_mask_2; // @[icache.scala:156:100] wire tag_array_MPORT_mask_1; // @[icache.scala:156:100] wire tag_array_MPORT_mask_0; // @[icache.scala:156:100] wire [63:0] _dataArrayWay_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayWay_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayWay_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayWay_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [79:0] _tag_array_RW0_rdata; // @[icache.scala:153:30] wire _repl_way_prng_io_out_0; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_1; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_2; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_3; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_4; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_5; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_6; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_7; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_8; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_9; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_10; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_11; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_12; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_13; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_14; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_15; // @[PRNG.scala:91:22] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[icache.scala:103:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[icache.scala:103:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[icache.scala:103:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[icache.scala:103:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[icache.scala:103:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[icache.scala:103:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[icache.scala:103:7] wire [63:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[icache.scala:103:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[icache.scala:103:7] wire io_req_valid_0 = io_req_valid; // @[icache.scala:103:7] wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[icache.scala:103:7] wire [31:0] io_s1_paddr_0 = io_s1_paddr; // @[icache.scala:103:7] wire io_s1_kill_0 = io_s1_kill; // @[icache.scala:103:7] wire io_s2_kill_0 = io_s2_kill; // @[icache.scala:103:7] wire io_invalidate_0 = io_invalidate; // @[icache.scala:103:7] wire auto_master_out_a_bits_source = 1'h0; // @[icache.scala:103:7] wire auto_master_out_a_bits_corrupt = 1'h0; // @[icache.scala:103:7] wire auto_master_out_d_bits_source = 1'h0; // @[icache.scala:103:7] wire io_resp_bits_replay = 1'h0; // @[icache.scala:103:7] wire io_resp_bits_ae = 1'h0; // @[icache.scala:103:7] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire s1_bankid = 1'h0; // @[icache.scala:170:23] wire masterNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [2:0] auto_master_out_a_bits_opcode = 3'h4; // @[icache.scala:103:7] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[icache.scala:103:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17] wire [3:0] auto_master_out_a_bits_size = 4'h6; // @[icache.scala:103:7] wire [3:0] masterNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17] wire [7:0] auto_master_out_a_bits_mask = 8'hFF; // @[icache.scala:103:7] wire [7:0] masterNodeOut_a_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] masterNodeOut_a_bits_a_mask = 8'hFF; // @[Edges.scala:460:17] wire [7:0] _masterNodeOut_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [63:0] auto_master_out_a_bits_data = 64'h0; // @[icache.scala:103:7] wire [63:0] masterNodeOut_a_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] masterNodeOut_a_bits_a_data = 64'h0; // @[Edges.scala:460:17] wire auto_master_out_d_ready = 1'h1; // @[icache.scala:103:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _masterNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _masterNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire masterNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire [3:0] masterNodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [2:0] masterNodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [1:0] masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire _io_req_ready_T; // @[icache.scala:144:19] wire _io_resp_valid_T; // @[icache.scala:324:29] wire [63:0] s2_way_mux; // @[Mux.scala:30:73] wire _io_perf_acquire_T; // @[Decoupled.scala:51:35] wire [31:0] auto_master_out_a_bits_address_0; // @[icache.scala:103:7] wire auto_master_out_a_valid_0; // @[icache.scala:103:7] wire io_req_ready; // @[icache.scala:103:7] wire [63:0] io_resp_bits_data_0; // @[icache.scala:103:7] wire io_resp_valid_0; // @[icache.scala:103:7] wire io_perf_acquire_0; // @[icache.scala:103:7] wire _masterNodeOut_a_valid_T_3; // @[icache.scala:326:46] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire _refill_one_beat_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire s0_valid = io_req_ready & io_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[icache.scala:128:25] wire _s1_tag_hit_0_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_1_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_2_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_3_T_1; // @[icache.scala:177:28] wire s1_tag_hit_0; // @[icache.scala:129:24] wire s1_tag_hit_1; // @[icache.scala:129:24] wire s1_tag_hit_2; // @[icache.scala:129:24] wire s1_tag_hit_3; // @[icache.scala:129:24] wire _s1_hit_T = s1_tag_hit_0 | s1_tag_hit_1; // @[icache.scala:129:24, :130:35] wire _s1_hit_T_1 = _s1_hit_T | s1_tag_hit_2; // @[icache.scala:129:24, :130:35] wire s1_hit = _s1_hit_T_1 | s1_tag_hit_3; // @[icache.scala:129:24, :130:35] wire _s2_valid_T = ~io_s1_kill_0; // @[icache.scala:103:7, :131:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[icache.scala:128:25, :131:{35,38}] reg s2_valid; // @[icache.scala:131:25] reg s2_hit; // @[icache.scala:132:23] reg invalidated; // @[icache.scala:135:24] reg refill_valid; // @[icache.scala:136:29] wire _GEN = masterNodeOut_a_ready & masterNodeOut_a_valid; // @[Decoupled.scala:51:35] wire refill_fire; // @[Decoupled.scala:51:35] assign refill_fire = _GEN; // @[Decoupled.scala:51:35] assign _io_perf_acquire_T = _GEN; // @[Decoupled.scala:51:35] wire _s2_miss_T = ~s2_hit; // @[icache.scala:132:23, :138:29] wire _s2_miss_T_1 = s2_valid & _s2_miss_T; // @[icache.scala:131:25, :138:{26,29}] reg s2_miss_REG; // @[icache.scala:138:48] wire _s2_miss_T_2 = ~s2_miss_REG; // @[icache.scala:138:{40,48}] wire s2_miss = _s2_miss_T_1 & _s2_miss_T_2; // @[icache.scala:138:{26,37,40}] wire _refill_paddr_T = refill_valid | s2_miss; // @[icache.scala:136:29, :138:37, :139:72] wire _refill_paddr_T_1 = ~_refill_paddr_T; // @[icache.scala:139:{57,72}] wire _refill_paddr_T_2 = s1_valid & _refill_paddr_T_1; // @[icache.scala:128:25, :139:{54,57}] reg [31:0] refill_paddr; // @[icache.scala:139:31] wire [19:0] refill_tag = refill_paddr[31:12]; // @[icache.scala:139:31, :140:32] wire [5:0] refill_idx = refill_paddr[11:6]; // @[icache.scala:139:31, :141:32] wire refill_one_beat_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire r_beats1_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[Decoupled.scala:51:35] assign _io_req_ready_T = ~refill_one_beat; // @[icache.scala:142:39, :144:19] assign io_req_ready = _io_req_ready_T; // @[icache.scala:103:7, :144:19] wire [26:0] _r_beats1_decode_T = 27'hFFF << masterNodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = r_2 & masterNodeOut_d_valid; // @[Edges.scala:232:33, :233:22] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] refill_cnt = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire refill_done = refill_one_beat & d_done; // @[Edges.scala:233:22] wire [1:0] repl_way_lo_lo_lo = {_repl_way_prng_io_out_1, _repl_way_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_lo_lo_hi = {_repl_way_prng_io_out_3, _repl_way_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_lo_lo = {repl_way_lo_lo_hi, repl_way_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_lo_hi_lo = {_repl_way_prng_io_out_5, _repl_way_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_lo_hi_hi = {_repl_way_prng_io_out_7, _repl_way_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_lo_hi = {repl_way_lo_hi_hi, repl_way_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_lo = {repl_way_lo_hi, repl_way_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_hi_lo_lo = {_repl_way_prng_io_out_9, _repl_way_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_hi_lo_hi = {_repl_way_prng_io_out_11, _repl_way_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_hi_lo = {repl_way_hi_lo_hi, repl_way_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_hi_hi_lo = {_repl_way_prng_io_out_13, _repl_way_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_hi_hi_hi = {_repl_way_prng_io_out_15, _repl_way_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_hi_hi = {repl_way_hi_hi_hi, repl_way_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_hi = {repl_way_hi_hi, repl_way_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _repl_way_T = {repl_way_hi, repl_way_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way = _repl_way_T[1:0]; // @[PRNG.scala:95:17] wire [5:0] _tag_rdata_WIRE; // @[icache.scala:154:33] wire _tag_rdata_T_2; // @[icache.scala:154:84] wire [5:0] _tag_rdata_T = io_req_bits_addr_0[11:6]; // @[icache.scala:103:7, :154:42] assign _tag_rdata_WIRE = _tag_rdata_T; // @[icache.scala:154:{33,42}] wire _tag_rdata_T_1 = ~refill_done; // @[icache.scala:147:37, :154:71] assign _tag_rdata_T_2 = _tag_rdata_T_1 & s0_valid; // @[Decoupled.scala:51:35] assign tag_array_MPORT_mask_0 = ~(|repl_way); // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_1 = repl_way == 2'h1; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_2 = repl_way == 2'h2; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_3 = &repl_way; // @[icache.scala:151:58, :156:100] reg [255:0] vb_array; // @[icache.scala:159:25] wire [7:0] _vb_array_T = {repl_way, refill_idx}; // @[icache.scala:141:32, :151:58, :161:36] wire _vb_array_T_1 = ~invalidated; // @[icache.scala:135:24, :161:75] wire _vb_array_T_2 = refill_done & _vb_array_T_1; // @[icache.scala:147:37, :161:{72,75}] wire [255:0] _vb_array_T_3 = 256'h1 << _vb_array_T; // @[icache.scala:161:{32,36}] wire [255:0] _vb_array_T_4 = vb_array | _vb_array_T_3; // @[icache.scala:159:25, :161:32] wire [255:0] _vb_array_T_5 = ~vb_array; // @[icache.scala:159:25, :161:32] wire [255:0] _vb_array_T_6 = _vb_array_T_5 | _vb_array_T_3; // @[icache.scala:161:32] wire [255:0] _vb_array_T_7 = ~_vb_array_T_6; // @[icache.scala:161:32] wire [255:0] _vb_array_T_8 = _vb_array_T_2 ? _vb_array_T_4 : _vb_array_T_7; // @[icache.scala:161:{32,72}] wire [63:0] s2_dout_0; // @[icache.scala:169:23] wire [63:0] s2_dout_1; // @[icache.scala:169:23] wire [63:0] s2_dout_2; // @[icache.scala:169:23] wire [63:0] s2_dout_3; // @[icache.scala:169:23] wire [5:0] s1_idx = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_1 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_2 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_3 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [19:0] s1_tag = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_1 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_2 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_3 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [6:0] _s1_vb_T = {1'h0, s1_idx}; // @[icache.scala:173:29, :175:29] wire [255:0] _s1_vb_T_1 = vb_array >> _s1_vb_T; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb = _s1_vb_T_1[0]; // @[icache.scala:175:25] wire _s1_tag_hit_0_T = _tag_array_RW0_rdata[19:0] == s1_tag; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_0_T_1 = s1_vb & _s1_tag_hit_0_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_0 = _s1_tag_hit_0_T_1; // @[icache.scala:129:24, :177:28] wire [6:0] _s1_vb_T_2 = {1'h1, s1_idx_1}; // @[icache.scala:173:29, :175:29] wire [255:0] _s1_vb_T_3 = vb_array >> _s1_vb_T_2; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_1 = _s1_vb_T_3[0]; // @[icache.scala:175:25] wire _s1_tag_hit_1_T = _tag_array_RW0_rdata[39:20] == s1_tag_1; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_1_T_1 = s1_vb_1 & _s1_tag_hit_1_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_1 = _s1_tag_hit_1_T_1; // @[icache.scala:129:24, :177:28] wire [7:0] _s1_vb_T_4 = {2'h2, s1_idx_2}; // @[icache.scala:173:29, :175:29] wire [255:0] _s1_vb_T_5 = vb_array >> _s1_vb_T_4; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_2 = _s1_vb_T_5[0]; // @[icache.scala:175:25] wire _s1_tag_hit_2_T = _tag_array_RW0_rdata[59:40] == s1_tag_2; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_2_T_1 = s1_vb_2 & _s1_tag_hit_2_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_2 = _s1_tag_hit_2_T_1; // @[icache.scala:129:24, :177:28] wire [7:0] _s1_vb_T_6 = {2'h3, s1_idx_3}; // @[icache.scala:173:29, :175:29] wire [255:0] _s1_vb_T_7 = vb_array >> _s1_vb_T_6; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_3 = _s1_vb_T_7[0]; // @[icache.scala:175:25] wire _s1_tag_hit_3_T = _tag_array_RW0_rdata[79:60] == s1_tag_3; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_3_T_1 = s1_vb_3 & _s1_tag_hit_3_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_3 = _s1_tag_hit_3_T_1; // @[icache.scala:129:24, :177:28]
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} [15] wire _valids_WIRE : UInt<1>[15] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) regreset valids : UInt<1>[15], clock, reset, _valids_WIRE reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[15], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask) node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0)) node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0)) node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0)) node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4) node _do_enq_T_6 = and(io.flush, io.enq.bits.uop.uses_ldq) node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0)) node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7) wire do_enq : UInt<1> connect do_enq, _do_enq_T_8 node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0)) node _valids_0_T_4 = and(valids[0], _valids_0_T_3) node _valids_0_T_5 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0)) node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6) connect valids[0], _valids_0_T_7 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0)) node _valids_1_T_4 = and(valids[1], _valids_1_T_3) node _valids_1_T_5 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0)) node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6) connect valids[1], _valids_1_T_7 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0)) node _valids_2_T_4 = and(valids[2], _valids_2_T_3) node _valids_2_T_5 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0)) node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6) connect valids[2], _valids_2_T_7 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0)) node _valids_3_T_4 = and(valids[3], _valids_3_T_3) node _valids_3_T_5 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0)) node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6) connect valids[3], _valids_3_T_7 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0)) node _valids_4_T_4 = and(valids[4], _valids_4_T_3) node _valids_4_T_5 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0)) node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6) connect valids[4], _valids_4_T_7 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0)) node _valids_5_T_4 = and(valids[5], _valids_5_T_3) node _valids_5_T_5 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0)) node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6) connect valids[5], _valids_5_T_7 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0)) node _valids_6_T_4 = and(valids[6], _valids_6_T_3) node _valids_6_T_5 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0)) node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6) connect valids[6], _valids_6_T_7 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0)) node _valids_7_T_4 = and(valids[7], _valids_7_T_3) node _valids_7_T_5 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0)) node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6) connect valids[7], _valids_7_T_7 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = or(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = eq(_valids_8_T_2, UInt<1>(0h0)) node _valids_8_T_4 = and(valids[8], _valids_8_T_3) node _valids_8_T_5 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_6 = eq(_valids_8_T_5, UInt<1>(0h0)) node _valids_8_T_7 = and(_valids_8_T_4, _valids_8_T_6) connect valids[8], _valids_8_T_7 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = or(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = eq(_valids_9_T_2, UInt<1>(0h0)) node _valids_9_T_4 = and(valids[9], _valids_9_T_3) node _valids_9_T_5 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_6 = eq(_valids_9_T_5, UInt<1>(0h0)) node _valids_9_T_7 = and(_valids_9_T_4, _valids_9_T_6) connect valids[9], _valids_9_T_7 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = or(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = eq(_valids_10_T_2, UInt<1>(0h0)) node _valids_10_T_4 = and(valids[10], _valids_10_T_3) node _valids_10_T_5 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_6 = eq(_valids_10_T_5, UInt<1>(0h0)) node _valids_10_T_7 = and(_valids_10_T_4, _valids_10_T_6) connect valids[10], _valids_10_T_7 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = or(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = eq(_valids_11_T_2, UInt<1>(0h0)) node _valids_11_T_4 = and(valids[11], _valids_11_T_3) node _valids_11_T_5 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_6 = eq(_valids_11_T_5, UInt<1>(0h0)) node _valids_11_T_7 = and(_valids_11_T_4, _valids_11_T_6) connect valids[11], _valids_11_T_7 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = or(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = eq(_valids_12_T_2, UInt<1>(0h0)) node _valids_12_T_4 = and(valids[12], _valids_12_T_3) node _valids_12_T_5 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_6 = eq(_valids_12_T_5, UInt<1>(0h0)) node _valids_12_T_7 = and(_valids_12_T_4, _valids_12_T_6) connect valids[12], _valids_12_T_7 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = or(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = eq(_valids_13_T_2, UInt<1>(0h0)) node _valids_13_T_4 = and(valids[13], _valids_13_T_3) node _valids_13_T_5 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_6 = eq(_valids_13_T_5, UInt<1>(0h0)) node _valids_13_T_7 = and(_valids_13_T_4, _valids_13_T_6) connect valids[13], _valids_13_T_7 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = or(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = eq(_valids_14_T_2, UInt<1>(0h0)) node _valids_14_T_4 = and(valids[14], _valids_14_T_3) node _valids_14_T_5 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_6 = eq(_valids_14_T_5, UInt<1>(0h0)) node _valids_14_T_7 = and(_valids_14_T_4, _valids_14_T_6) connect valids[14], _valids_14_T_7 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0he)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when wrap : connect enq_ptr_value, UInt<1>(0h0) when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0he)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 when wrap_1 : connect deq_ptr_value, UInt<1>(0h0) node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) connect io.deq.valid, _io_deq_valid_T_1 connect io.deq.bits, out node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = mux(maybe_full, UInt<4>(0hf), UInt<1>(0h0)) node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value) node _io_count_T_2 = add(UInt<4>(0hf), ptr_diff) node _io_count_T_3 = tail(_io_count_T_2, 1) node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff) node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4) connect io.count, _io_count_T_5
module BranchKillableQueue( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_116 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_116( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_77 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T
module MulAddRecFNToRaw_preMul_e8_s24_77( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h1)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h7)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 node _source_ok_T_44 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[2]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[3]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[4]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[5]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[6]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_50, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<4>(0h8)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<4>(0h9)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<4>(0ha)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<4>(0hb)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h2)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<1>(0h1)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h7)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = and(_T_11, _T_24) node _T_112 = and(_T_111, _T_37) node _T_113 = and(_T_112, _T_50) node _T_114 = and(_T_113, _T_63) node _T_115 = and(_T_114, _T_76) node _T_116 = and(_T_115, _T_89) node _T_117 = and(_T_116, _T_102) node _T_118 = and(_T_117, _T_110) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_118, UInt<1>(0h1), "") : assert_1 node _T_122 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_122 : node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_127 = shr(io.in.a.bits.source, 2) node _T_128 = eq(_T_127, UInt<4>(0h8)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_132 = and(_T_130, _T_131) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_133 = shr(io.in.a.bits.source, 2) node _T_134 = eq(_T_133, UInt<4>(0h9)) node _T_135 = leq(UInt<1>(0h0), uncommonBits_8) node _T_136 = and(_T_134, _T_135) node _T_137 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<4>(0ha)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_9) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<4>(0hb)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_10) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_151 = shr(io.in.a.bits.source, 3) node _T_152 = eq(_T_151, UInt<2>(0h2)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_11) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_157 = shr(io.in.a.bits.source, 3) node _T_158 = eq(_T_157, UInt<1>(0h1)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_12) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_162 = and(_T_160, _T_161) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_163 = shr(io.in.a.bits.source, 3) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_13) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_13, UInt<3>(0h7)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_170 = or(_T_126, _T_132) node _T_171 = or(_T_170, _T_138) node _T_172 = or(_T_171, _T_144) node _T_173 = or(_T_172, _T_150) node _T_174 = or(_T_173, _T_156) node _T_175 = or(_T_174, _T_162) node _T_176 = or(_T_175, _T_168) node _T_177 = or(_T_176, _T_169) node _T_178 = and(_T_125, _T_177) node _T_179 = or(UInt<1>(0h0), _T_178) node _T_180 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_181 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = and(_T_180, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = and(_T_179, _T_187) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_188, UInt<1>(0h1), "") : assert_2 node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_193 = shr(io.in.a.bits.source, 2) node _T_194 = eq(_T_193, UInt<4>(0h8)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_14) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_199 = shr(io.in.a.bits.source, 2) node _T_200 = eq(_T_199, UInt<4>(0h9)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_15) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_204 = and(_T_202, _T_203) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<4>(0ha)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_16) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<4>(0hb)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_17) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_217 = shr(io.in.a.bits.source, 3) node _T_218 = eq(_T_217, UInt<2>(0h2)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_18) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_223 = shr(io.in.a.bits.source, 3) node _T_224 = eq(_T_223, UInt<1>(0h1)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_19) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_229 = shr(io.in.a.bits.source, 3) node _T_230 = eq(_T_229, UInt<1>(0h0)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_20) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_20, UInt<3>(0h7)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_192 connect _WIRE[1], _T_198 connect _WIRE[2], _T_204 connect _WIRE[3], _T_210 connect _WIRE[4], _T_216 connect _WIRE[5], _T_222 connect _WIRE[6], _T_228 connect _WIRE[7], _T_234 connect _WIRE[8], _T_235 node _T_236 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_237 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_238 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_242 = mux(_WIRE[5], _T_236, UInt<1>(0h0)) node _T_243 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_244 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_245 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = or(_T_237, _T_238) node _T_247 = or(_T_246, _T_239) node _T_248 = or(_T_247, _T_240) node _T_249 = or(_T_248, _T_241) node _T_250 = or(_T_249, _T_242) node _T_251 = or(_T_250, _T_243) node _T_252 = or(_T_251, _T_244) node _T_253 = or(_T_252, _T_245) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_253 node _T_254 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_255 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_256 = and(_T_254, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<13>(0h1000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = and(_T_257, _T_262) node _T_264 = or(UInt<1>(0h0), _T_263) node _T_265 = and(_WIRE_1, _T_264) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_265, UInt<1>(0h1), "") : assert_3 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(source_ok, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_272 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_272, UInt<1>(0h1), "") : assert_5 node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(is_aligned, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_279 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_279, UInt<1>(0h1), "") : assert_7 node _T_283 = not(io.in.a.bits.mask) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_284, UInt<1>(0h1), "") : assert_8 node _T_288 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_288, UInt<1>(0h1), "") : assert_9 node _T_292 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_292 : node _T_293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_294 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_297 = shr(io.in.a.bits.source, 2) node _T_298 = eq(_T_297, UInt<4>(0h8)) node _T_299 = leq(UInt<1>(0h0), uncommonBits_21) node _T_300 = and(_T_298, _T_299) node _T_301 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<4>(0h9)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_22) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<4>(0ha)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_23) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<4>(0hb)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_24) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_321 = shr(io.in.a.bits.source, 3) node _T_322 = eq(_T_321, UInt<2>(0h2)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_25) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_326 = and(_T_324, _T_325) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_327 = shr(io.in.a.bits.source, 3) node _T_328 = eq(_T_327, UInt<1>(0h1)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_26) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_333 = shr(io.in.a.bits.source, 3) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_27) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_27, UInt<3>(0h7)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_340 = or(_T_296, _T_302) node _T_341 = or(_T_340, _T_308) node _T_342 = or(_T_341, _T_314) node _T_343 = or(_T_342, _T_320) node _T_344 = or(_T_343, _T_326) node _T_345 = or(_T_344, _T_332) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = and(_T_295, _T_347) node _T_349 = or(UInt<1>(0h0), _T_348) node _T_350 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<13>(0h1000))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = and(_T_350, _T_355) node _T_357 = or(UInt<1>(0h0), _T_356) node _T_358 = and(_T_349, _T_357) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_358, UInt<1>(0h1), "") : assert_10 node _T_362 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_363 = shr(io.in.a.bits.source, 2) node _T_364 = eq(_T_363, UInt<4>(0h8)) node _T_365 = leq(UInt<1>(0h0), uncommonBits_28) node _T_366 = and(_T_364, _T_365) node _T_367 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_369 = shr(io.in.a.bits.source, 2) node _T_370 = eq(_T_369, UInt<4>(0h9)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_29) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_374 = and(_T_372, _T_373) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_375 = shr(io.in.a.bits.source, 2) node _T_376 = eq(_T_375, UInt<4>(0ha)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_30) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_380 = and(_T_378, _T_379) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_381 = shr(io.in.a.bits.source, 2) node _T_382 = eq(_T_381, UInt<4>(0hb)) node _T_383 = leq(UInt<1>(0h0), uncommonBits_31) node _T_384 = and(_T_382, _T_383) node _T_385 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_387 = shr(io.in.a.bits.source, 3) node _T_388 = eq(_T_387, UInt<2>(0h2)) node _T_389 = leq(UInt<1>(0h0), uncommonBits_32) node _T_390 = and(_T_388, _T_389) node _T_391 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_392 = and(_T_390, _T_391) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_393 = shr(io.in.a.bits.source, 3) node _T_394 = eq(_T_393, UInt<1>(0h1)) node _T_395 = leq(UInt<1>(0h0), uncommonBits_33) node _T_396 = and(_T_394, _T_395) node _T_397 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_398 = and(_T_396, _T_397) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_399 = shr(io.in.a.bits.source, 3) node _T_400 = eq(_T_399, UInt<1>(0h0)) node _T_401 = leq(UInt<1>(0h0), uncommonBits_34) node _T_402 = and(_T_400, _T_401) node _T_403 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_404 = and(_T_402, _T_403) node _T_405 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_362 connect _WIRE_2[1], _T_368 connect _WIRE_2[2], _T_374 connect _WIRE_2[3], _T_380 connect _WIRE_2[4], _T_386 connect _WIRE_2[5], _T_392 connect _WIRE_2[6], _T_398 connect _WIRE_2[7], _T_404 connect _WIRE_2[8], _T_405 node _T_406 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_407 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_408 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_410 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_411 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_412 = mux(_WIRE_2[5], _T_406, UInt<1>(0h0)) node _T_413 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_414 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_415 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_416 = or(_T_407, _T_408) node _T_417 = or(_T_416, _T_409) node _T_418 = or(_T_417, _T_410) node _T_419 = or(_T_418, _T_411) node _T_420 = or(_T_419, _T_412) node _T_421 = or(_T_420, _T_413) node _T_422 = or(_T_421, _T_414) node _T_423 = or(_T_422, _T_415) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_423 node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_426 = and(_T_424, _T_425) node _T_427 = or(UInt<1>(0h0), _T_426) node _T_428 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_429 = cvt(_T_428) node _T_430 = and(_T_429, asSInt(UInt<13>(0h1000))) node _T_431 = asSInt(_T_430) node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0))) node _T_433 = and(_T_427, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = and(_WIRE_3, _T_434) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_435, UInt<1>(0h1), "") : assert_11 node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(source_ok, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_442 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_442, UInt<1>(0h1), "") : assert_13 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(is_aligned, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_449 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_449, UInt<1>(0h1), "") : assert_15 node _T_453 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_453, UInt<1>(0h1), "") : assert_16 node _T_457 = not(io.in.a.bits.mask) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_458, UInt<1>(0h1), "") : assert_17 node _T_462 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_462, UInt<1>(0h1), "") : assert_18 node _T_466 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_466 : node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_471 = shr(io.in.a.bits.source, 2) node _T_472 = eq(_T_471, UInt<4>(0h8)) node _T_473 = leq(UInt<1>(0h0), uncommonBits_35) node _T_474 = and(_T_472, _T_473) node _T_475 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_476 = and(_T_474, _T_475) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_477 = shr(io.in.a.bits.source, 2) node _T_478 = eq(_T_477, UInt<4>(0h9)) node _T_479 = leq(UInt<1>(0h0), uncommonBits_36) node _T_480 = and(_T_478, _T_479) node _T_481 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_482 = and(_T_480, _T_481) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_483 = shr(io.in.a.bits.source, 2) node _T_484 = eq(_T_483, UInt<4>(0ha)) node _T_485 = leq(UInt<1>(0h0), uncommonBits_37) node _T_486 = and(_T_484, _T_485) node _T_487 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_489 = shr(io.in.a.bits.source, 2) node _T_490 = eq(_T_489, UInt<4>(0hb)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_38) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_494 = and(_T_492, _T_493) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_495 = shr(io.in.a.bits.source, 3) node _T_496 = eq(_T_495, UInt<2>(0h2)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_39) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_501 = shr(io.in.a.bits.source, 3) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_40) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_507 = shr(io.in.a.bits.source, 3) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_41) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_41, UInt<3>(0h7)) node _T_512 = and(_T_510, _T_511) node _T_513 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_514 = or(_T_470, _T_476) node _T_515 = or(_T_514, _T_482) node _T_516 = or(_T_515, _T_488) node _T_517 = or(_T_516, _T_494) node _T_518 = or(_T_517, _T_500) node _T_519 = or(_T_518, _T_506) node _T_520 = or(_T_519, _T_512) node _T_521 = or(_T_520, _T_513) node _T_522 = and(_T_469, _T_521) node _T_523 = or(UInt<1>(0h0), _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_523, UInt<1>(0h1), "") : assert_19 node _T_527 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_528 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_529 = and(_T_527, _T_528) node _T_530 = or(UInt<1>(0h0), _T_529) node _T_531 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<13>(0h1000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = and(_T_530, _T_535) node _T_537 = or(UInt<1>(0h0), _T_536) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_537, UInt<1>(0h1), "") : assert_20 node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(source_ok, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(is_aligned, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_547 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_548 = asUInt(reset) node _T_549 = eq(_T_548, UInt<1>(0h0)) when _T_549 : node _T_550 = eq(_T_547, UInt<1>(0h0)) when _T_550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_547, UInt<1>(0h1), "") : assert_23 node _T_551 = eq(io.in.a.bits.mask, mask) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_551, UInt<1>(0h1), "") : assert_24 node _T_555 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_555, UInt<1>(0h1), "") : assert_25 node _T_559 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_559 : node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<4>(0h8)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_42) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_570 = shr(io.in.a.bits.source, 2) node _T_571 = eq(_T_570, UInt<4>(0h9)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_43) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<4>(0ha)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_44) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<4>(0hb)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_45) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_588 = shr(io.in.a.bits.source, 3) node _T_589 = eq(_T_588, UInt<2>(0h2)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_46) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_594 = shr(io.in.a.bits.source, 3) node _T_595 = eq(_T_594, UInt<1>(0h1)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_47) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_600 = shr(io.in.a.bits.source, 3) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_48) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_48, UInt<3>(0h7)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_563, _T_569) node _T_608 = or(_T_607, _T_575) node _T_609 = or(_T_608, _T_581) node _T_610 = or(_T_609, _T_587) node _T_611 = or(_T_610, _T_593) node _T_612 = or(_T_611, _T_599) node _T_613 = or(_T_612, _T_605) node _T_614 = or(_T_613, _T_606) node _T_615 = and(_T_562, _T_614) node _T_616 = or(UInt<1>(0h0), _T_615) node _T_617 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_618 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_619 = and(_T_617, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_622 = cvt(_T_621) node _T_623 = and(_T_622, asSInt(UInt<13>(0h1000))) node _T_624 = asSInt(_T_623) node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0))) node _T_626 = and(_T_620, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = and(_T_616, _T_627) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_628, UInt<1>(0h1), "") : assert_26 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(is_aligned, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_638 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_638, UInt<1>(0h1), "") : assert_29 node _T_642 = eq(io.in.a.bits.mask, mask) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_642, UInt<1>(0h1), "") : assert_30 node _T_646 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_646 : node _T_647 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_648 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<4>(0h8)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_49) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_657 = shr(io.in.a.bits.source, 2) node _T_658 = eq(_T_657, UInt<4>(0h9)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_50) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_663 = shr(io.in.a.bits.source, 2) node _T_664 = eq(_T_663, UInt<4>(0ha)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_51) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_668 = and(_T_666, _T_667) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_669 = shr(io.in.a.bits.source, 2) node _T_670 = eq(_T_669, UInt<4>(0hb)) node _T_671 = leq(UInt<1>(0h0), uncommonBits_52) node _T_672 = and(_T_670, _T_671) node _T_673 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_674 = and(_T_672, _T_673) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_675 = shr(io.in.a.bits.source, 3) node _T_676 = eq(_T_675, UInt<2>(0h2)) node _T_677 = leq(UInt<1>(0h0), uncommonBits_53) node _T_678 = and(_T_676, _T_677) node _T_679 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_680 = and(_T_678, _T_679) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_681 = shr(io.in.a.bits.source, 3) node _T_682 = eq(_T_681, UInt<1>(0h1)) node _T_683 = leq(UInt<1>(0h0), uncommonBits_54) node _T_684 = and(_T_682, _T_683) node _T_685 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_686 = and(_T_684, _T_685) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_687 = shr(io.in.a.bits.source, 3) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = leq(UInt<1>(0h0), uncommonBits_55) node _T_690 = and(_T_688, _T_689) node _T_691 = leq(uncommonBits_55, UInt<3>(0h7)) node _T_692 = and(_T_690, _T_691) node _T_693 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_694 = or(_T_650, _T_656) node _T_695 = or(_T_694, _T_662) node _T_696 = or(_T_695, _T_668) node _T_697 = or(_T_696, _T_674) node _T_698 = or(_T_697, _T_680) node _T_699 = or(_T_698, _T_686) node _T_700 = or(_T_699, _T_692) node _T_701 = or(_T_700, _T_693) node _T_702 = and(_T_649, _T_701) node _T_703 = or(UInt<1>(0h0), _T_702) node _T_704 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_705 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_706 = and(_T_704, _T_705) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<13>(0h1000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = and(_T_707, _T_712) node _T_714 = or(UInt<1>(0h0), _T_713) node _T_715 = and(_T_703, _T_714) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_715, UInt<1>(0h1), "") : assert_31 node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(source_ok, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(is_aligned, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_725 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_725, UInt<1>(0h1), "") : assert_34 node _T_729 = not(mask) node _T_730 = and(io.in.a.bits.mask, _T_729) node _T_731 = eq(_T_730, UInt<1>(0h0)) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_731, UInt<1>(0h1), "") : assert_35 node _T_735 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_735 : node _T_736 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_737 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<4>(0h8)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_56) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<4>(0h9)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_57) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<4>(0ha)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_58) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_757 = and(_T_755, _T_756) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<4>(0hb)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_59) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_764 = shr(io.in.a.bits.source, 3) node _T_765 = eq(_T_764, UInt<2>(0h2)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_60) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_770 = shr(io.in.a.bits.source, 3) node _T_771 = eq(_T_770, UInt<1>(0h1)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_61) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_776 = shr(io.in.a.bits.source, 3) node _T_777 = eq(_T_776, UInt<1>(0h0)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_62) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_62, UInt<3>(0h7)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_783 = or(_T_739, _T_745) node _T_784 = or(_T_783, _T_751) node _T_785 = or(_T_784, _T_757) node _T_786 = or(_T_785, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = and(_T_738, _T_790) node _T_792 = or(UInt<1>(0h0), _T_791) node _T_793 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_794 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_795 = cvt(_T_794) node _T_796 = and(_T_795, asSInt(UInt<13>(0h1000))) node _T_797 = asSInt(_T_796) node _T_798 = eq(_T_797, asSInt(UInt<1>(0h0))) node _T_799 = and(_T_793, _T_798) node _T_800 = or(UInt<1>(0h0), _T_799) node _T_801 = and(_T_792, _T_800) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_801, UInt<1>(0h1), "") : assert_36 node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(source_ok, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(is_aligned, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_811 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_811, UInt<1>(0h1), "") : assert_39 node _T_815 = eq(io.in.a.bits.mask, mask) node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(_T_815, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_815, UInt<1>(0h1), "") : assert_40 node _T_819 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_819 : node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_822 = and(_T_820, _T_821) node _T_823 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_824 = shr(io.in.a.bits.source, 2) node _T_825 = eq(_T_824, UInt<4>(0h8)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_63) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_829 = and(_T_827, _T_828) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_830 = shr(io.in.a.bits.source, 2) node _T_831 = eq(_T_830, UInt<4>(0h9)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_64) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_835 = and(_T_833, _T_834) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_836 = shr(io.in.a.bits.source, 2) node _T_837 = eq(_T_836, UInt<4>(0ha)) node _T_838 = leq(UInt<1>(0h0), uncommonBits_65) node _T_839 = and(_T_837, _T_838) node _T_840 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_841 = and(_T_839, _T_840) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<4>(0hb)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_66) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_848 = shr(io.in.a.bits.source, 3) node _T_849 = eq(_T_848, UInt<2>(0h2)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_67) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_854 = shr(io.in.a.bits.source, 3) node _T_855 = eq(_T_854, UInt<1>(0h1)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_68) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_860 = shr(io.in.a.bits.source, 3) node _T_861 = eq(_T_860, UInt<1>(0h0)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_69) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_867 = or(_T_823, _T_829) node _T_868 = or(_T_867, _T_835) node _T_869 = or(_T_868, _T_841) node _T_870 = or(_T_869, _T_847) node _T_871 = or(_T_870, _T_853) node _T_872 = or(_T_871, _T_859) node _T_873 = or(_T_872, _T_865) node _T_874 = or(_T_873, _T_866) node _T_875 = and(_T_822, _T_874) node _T_876 = or(UInt<1>(0h0), _T_875) node _T_877 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_878 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<13>(0h1000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = and(_T_877, _T_882) node _T_884 = or(UInt<1>(0h0), _T_883) node _T_885 = and(_T_876, _T_884) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_885, UInt<1>(0h1), "") : assert_41 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(source_ok, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(is_aligned, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_895 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_895, UInt<1>(0h1), "") : assert_44 node _T_899 = eq(io.in.a.bits.mask, mask) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_899, UInt<1>(0h1), "") : assert_45 node _T_903 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_903 : node _T_904 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_905 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_906 = and(_T_904, _T_905) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_908 = shr(io.in.a.bits.source, 2) node _T_909 = eq(_T_908, UInt<4>(0h8)) node _T_910 = leq(UInt<1>(0h0), uncommonBits_70) node _T_911 = and(_T_909, _T_910) node _T_912 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_913 = and(_T_911, _T_912) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_914 = shr(io.in.a.bits.source, 2) node _T_915 = eq(_T_914, UInt<4>(0h9)) node _T_916 = leq(UInt<1>(0h0), uncommonBits_71) node _T_917 = and(_T_915, _T_916) node _T_918 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_919 = and(_T_917, _T_918) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_920 = shr(io.in.a.bits.source, 2) node _T_921 = eq(_T_920, UInt<4>(0ha)) node _T_922 = leq(UInt<1>(0h0), uncommonBits_72) node _T_923 = and(_T_921, _T_922) node _T_924 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_925 = and(_T_923, _T_924) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_926 = shr(io.in.a.bits.source, 2) node _T_927 = eq(_T_926, UInt<4>(0hb)) node _T_928 = leq(UInt<1>(0h0), uncommonBits_73) node _T_929 = and(_T_927, _T_928) node _T_930 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_931 = and(_T_929, _T_930) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_932 = shr(io.in.a.bits.source, 3) node _T_933 = eq(_T_932, UInt<2>(0h2)) node _T_934 = leq(UInt<1>(0h0), uncommonBits_74) node _T_935 = and(_T_933, _T_934) node _T_936 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_937 = and(_T_935, _T_936) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_938 = shr(io.in.a.bits.source, 3) node _T_939 = eq(_T_938, UInt<1>(0h1)) node _T_940 = leq(UInt<1>(0h0), uncommonBits_75) node _T_941 = and(_T_939, _T_940) node _T_942 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_943 = and(_T_941, _T_942) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_944 = shr(io.in.a.bits.source, 3) node _T_945 = eq(_T_944, UInt<1>(0h0)) node _T_946 = leq(UInt<1>(0h0), uncommonBits_76) node _T_947 = and(_T_945, _T_946) node _T_948 = leq(uncommonBits_76, UInt<3>(0h7)) node _T_949 = and(_T_947, _T_948) node _T_950 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_951 = or(_T_907, _T_913) node _T_952 = or(_T_951, _T_919) node _T_953 = or(_T_952, _T_925) node _T_954 = or(_T_953, _T_931) node _T_955 = or(_T_954, _T_937) node _T_956 = or(_T_955, _T_943) node _T_957 = or(_T_956, _T_949) node _T_958 = or(_T_957, _T_950) node _T_959 = and(_T_906, _T_958) node _T_960 = or(UInt<1>(0h0), _T_959) node _T_961 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_962 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_963 = cvt(_T_962) node _T_964 = and(_T_963, asSInt(UInt<13>(0h1000))) node _T_965 = asSInt(_T_964) node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0))) node _T_967 = and(_T_961, _T_966) node _T_968 = or(UInt<1>(0h0), _T_967) node _T_969 = and(_T_960, _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_969, UInt<1>(0h1), "") : assert_46 node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(source_ok, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(is_aligned, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_979 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(_T_979, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_979, UInt<1>(0h1), "") : assert_49 node _T_983 = eq(io.in.a.bits.mask, mask) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_983, UInt<1>(0h1), "") : assert_50 node _T_987 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_987, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_991 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_991, UInt<1>(0h1), "") : assert_52 node _source_ok_T_51 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<4>(0h8)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<4>(0h9)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 2) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<4>(0ha)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_70 = shr(io.in.d.bits.source, 2) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<4>(0hb)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_76 = shr(io.in.d.bits.source, 3) node _source_ok_T_77 = eq(_source_ok_T_76, UInt<2>(0h2)) node _source_ok_T_78 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_T_80 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_82 = shr(io.in.d.bits.source, 3) node _source_ok_T_83 = eq(_source_ok_T_82, UInt<1>(0h1)) node _source_ok_T_84 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_T_86 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_88 = shr(io.in.d.bits.source, 3) node _source_ok_T_89 = eq(_source_ok_T_88, UInt<1>(0h0)) node _source_ok_T_90 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) node _source_ok_T_92 = leq(source_ok_uncommonBits_13, UInt<3>(0h7)) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_51 connect _source_ok_WIRE_1[1], _source_ok_T_57 connect _source_ok_WIRE_1[2], _source_ok_T_63 connect _source_ok_WIRE_1[3], _source_ok_T_69 connect _source_ok_WIRE_1[4], _source_ok_T_75 connect _source_ok_WIRE_1[5], _source_ok_T_81 connect _source_ok_WIRE_1[6], _source_ok_T_87 connect _source_ok_WIRE_1[7], _source_ok_T_93 connect _source_ok_WIRE_1[8], _source_ok_T_94 node _source_ok_T_95 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[2]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[3]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[4]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[5]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[6]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_101, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_995 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_995 : node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(source_ok_1, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_999 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_999, UInt<1>(0h1), "") : assert_54 node _T_1003 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_55 node _T_1007 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_56 node _T_1011 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_57 node _T_1015 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1015 : node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(source_ok_1, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(sink_ok, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1022 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_60 node _T_1026 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_61 node _T_1030 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_62 node _T_1034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_63 node _T_1038 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1039 = or(UInt<1>(0h0), _T_1038) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_64 node _T_1043 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1043 : node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(source_ok_1, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(sink_ok, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1050 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_67 node _T_1054 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_68 node _T_1058 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_69 node _T_1062 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1063 = or(_T_1062, io.in.d.bits.corrupt) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_70 node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1068 = or(UInt<1>(0h0), _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_71 node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1072 : node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(source_ok_1, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_73 node _T_1080 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_74 node _T_1084 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_75 node _T_1089 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1089 : node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(source_ok_1, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1093 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_77 node _T_1097 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1098 = or(_T_1097, io.in.d.bits.corrupt) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_78 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(UInt<1>(0h0), _T_1102) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_79 node _T_1107 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1107 : node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(source_ok_1, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1111 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_81 node _T_1115 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_82 node _T_1119 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1120 = or(UInt<1>(0h0), _T_1119) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1124 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1128 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1132 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1136 = eq(a_first, UInt<1>(0h0)) node _T_1137 = and(io.in.a.valid, _T_1136) when _T_1137 : node _T_1138 = eq(io.in.a.bits.opcode, opcode) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_87 node _T_1142 = eq(io.in.a.bits.param, param) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_88 node _T_1146 = eq(io.in.a.bits.size, size) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_89 node _T_1150 = eq(io.in.a.bits.source, source) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_90 node _T_1154 = eq(io.in.a.bits.address, address) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_91 node _T_1158 = and(io.in.a.ready, io.in.a.valid) node _T_1159 = and(_T_1158, a_first) when _T_1159 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1160 = eq(d_first, UInt<1>(0h0)) node _T_1161 = and(io.in.d.valid, _T_1160) when _T_1161 : node _T_1162 = eq(io.in.d.bits.opcode, opcode_1) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_92 node _T_1166 = eq(io.in.d.bits.param, param_1) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_93 node _T_1170 = eq(io.in.d.bits.size, size_1) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_94 node _T_1174 = eq(io.in.d.bits.source, source_1) node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(_T_1174, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1174, UInt<1>(0h1), "") : assert_95 node _T_1178 = eq(io.in.d.bits.sink, sink) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_96 node _T_1182 = eq(io.in.d.bits.denied, denied) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_97 node _T_1186 = and(io.in.d.ready, io.in.d.valid) node _T_1187 = and(_T_1186, d_first) when _T_1187 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1188 = and(io.in.a.valid, a_first_1) node _T_1189 = and(_T_1188, UInt<1>(0h1)) when _T_1189 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1190 = and(io.in.a.ready, io.in.a.valid) node _T_1191 = and(_T_1190, a_first_1) node _T_1192 = and(_T_1191, UInt<1>(0h1)) when _T_1192 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1193 = dshr(inflight, io.in.a.bits.source) node _T_1194 = bits(_T_1193, 0, 0) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1203 = and(io.in.d.ready, io.in.d.valid) node _T_1204 = and(_T_1203, d_first_1) node _T_1205 = and(_T_1204, UInt<1>(0h1)) node _T_1206 = eq(d_release_ack, UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1208 = and(io.in.d.valid, d_first_1) node _T_1209 = and(_T_1208, UInt<1>(0h1)) node _T_1210 = eq(d_release_ack, UInt<1>(0h0)) node _T_1211 = and(_T_1209, _T_1210) when _T_1211 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1212 = dshr(inflight, io.in.d.bits.source) node _T_1213 = bits(_T_1212, 0, 0) node _T_1214 = or(_T_1213, same_cycle_resp) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1218 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1219 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1220 = or(_T_1218, _T_1219) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_100 node _T_1224 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_101 else : node _T_1228 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1229 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1230 = or(_T_1228, _T_1229) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_102 node _T_1234 = eq(io.in.d.bits.size, a_size_lookup) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_103 node _T_1238 = and(io.in.d.valid, d_first_1) node _T_1239 = and(_T_1238, a_first_1) node _T_1240 = and(_T_1239, io.in.a.valid) node _T_1241 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1242 = and(_T_1240, _T_1241) node _T_1243 = eq(d_release_ack, UInt<1>(0h0)) node _T_1244 = and(_T_1242, _T_1243) when _T_1244 : node _T_1245 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1246 = or(_T_1245, io.in.a.ready) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_133 node _T_1250 = orr(inflight) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) node _T_1252 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = lt(watchdog, plusarg_reader.out) node _T_1255 = or(_T_1253, _T_1254) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(io.in.d.ready, io.in.d.valid) node _T_1261 = or(_T_1259, _T_1260) when _T_1261 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1262 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1263 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1264 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1265 = and(_T_1263, _T_1264) node _T_1266 = and(_T_1262, _T_1265) when _T_1266 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1267 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1268 = and(_T_1267, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1269 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1270 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = and(_T_1268, _T_1271) when _T_1272 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1273 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1274 = bits(_T_1273, 0, 0) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1279 = and(io.in.d.valid, d_first_2) node _T_1280 = and(_T_1279, UInt<1>(0h1)) node _T_1281 = and(_T_1280, d_release_ack_1) when _T_1281 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1282 = and(io.in.d.ready, io.in.d.valid) node _T_1283 = and(_T_1282, d_first_2) node _T_1284 = and(_T_1283, UInt<1>(0h1)) node _T_1285 = and(_T_1284, d_release_ack_1) when _T_1285 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1286 = and(io.in.d.valid, d_first_2) node _T_1287 = and(_T_1286, UInt<1>(0h1)) node _T_1288 = and(_T_1287, d_release_ack_1) when _T_1288 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1289 = dshr(inflight_1, io.in.d.bits.source) node _T_1290 = bits(_T_1289, 0, 0) node _T_1291 = or(_T_1290, same_cycle_resp_1) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1295 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_108 else : node _T_1299 = eq(io.in.d.bits.size, c_size_lookup) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_109 node _T_1303 = and(io.in.d.valid, d_first_2) node _T_1304 = and(_T_1303, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1305 = and(_T_1304, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1306 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = and(_T_1307, d_release_ack_1) node _T_1309 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1310 = and(_T_1308, _T_1309) when _T_1310 : node _T_1311 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1312 = or(_T_1311, _WIRE_27.ready) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_134 node _T_1316 = orr(inflight_1) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) node _T_1318 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1319 = or(_T_1317, _T_1318) node _T_1320 = lt(watchdog_1, plusarg_reader_1.out) node _T_1321 = or(_T_1319, _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1325 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1326 = and(io.in.d.ready, io.in.d.valid) node _T_1327 = or(_T_1325, _T_1326) when _T_1327 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1259 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1259; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1259; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1327 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1327; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1327; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1327; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1192 = _T_1259 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1192 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1207 = _T_1327 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1207 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1303 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1303 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1285 = _T_1327 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1285 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1285 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1285 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_1 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_1 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_1 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id) when _T_11 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_12 = eq(UInt<2>(0h3), io.in.flit[0].bits.flow.egress_node_id) when _T_12 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_13 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_13 : connect states[0].g, UInt<3>(0h2) connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_14 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_14 : connect states[2].g, UInt<3>(0h2) node _T_15 = and(io.router_req.ready, io.router_req.valid) when _T_15 : node _T_16 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_16, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_20 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_20 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_21 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_21 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_22 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_22 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_23 = and(io.router_req.ready, io.router_req.valid) when _T_23 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_24 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_25 = or(_T_24, vcalloc_vals[2]) when _T_25 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[1] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>[1] node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_12[0], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_12 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1] node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>[1] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_16[0], _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_16 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_18 wire _io_vcalloc_req_bits_WIRE_19 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_20 : UInt<2> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_19.egress_node_id, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_21 : UInt<4> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_19.egress_node, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_22 : UInt<3> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_19.ingress_node_id, _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_23 : UInt<4> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE_19.ingress_node, _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_19.vnet_id, _io_vcalloc_req_bits_WIRE_24 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_19 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].vc_sel.`5`, states[0].vc_sel.`5` connect vcalloc_reqs[0].flow, states[0].flow node _T_26 = bits(vcalloc_sel, 0, 0) node _T_27 = and(vcalloc_vals[0], _T_26) node _T_28 = and(_T_27, io.vcalloc_req.ready) when _T_28 : connect states[0].g, UInt<3>(0h3) node _T_29 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_29 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[0].vc_sel.`5`, io.router_resp.vc_sel.`5` connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`3`[0] invalidate vcalloc_reqs[1].vc_sel.`4`[0] invalidate vcalloc_reqs[1].vc_sel.`5`[0] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_30 = bits(vcalloc_sel, 2, 2) node _T_31 = and(vcalloc_vals[2], _T_30) node _T_32 = and(_T_31, io.vcalloc_req.ready) when _T_32 : connect states[2].g, UInt<3>(0h3) node _T_33 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_33 : connect vcalloc_vals[2], UInt<1>(0h1) connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_34 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_34 : node _T_35 = bits(vcalloc_sel, 0, 0) when _T_35 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_36 = bits(vcalloc_sel, 1, 1) when _T_36 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_37 = bits(vcalloc_sel, 2, 2) when _T_37 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_1 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0]) node credit_available_lo_hi = cat(states[0].vc_sel.`2`[0], _credit_available_T_1) node credit_available_lo = cat(credit_available_lo_hi, _credit_available_T) node credit_available_hi_hi = cat(states[0].vc_sel.`5`[0], states[0].vc_sel.`4`[0]) node credit_available_hi_2 = cat(credit_available_hi_hi, states[0].vc_sel.`3`[0]) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo) node credit_available_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_3 = cat(credit_available_hi_3, io.out_credit_available.`0`[0]) node credit_available_hi_4 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`1`[0]) node credit_available_lo_hi_1 = cat(io.out_credit_available.`2`[0], _credit_available_T_4) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T_3) node credit_available_hi_hi_1 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_5 = cat(credit_available_hi_hi_1, io.out_credit_available.`3`[0]) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_1) node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5) node credit_available = neq(_credit_available_T_6, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`5`[0], states[0].vc_sel.`5`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_38 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_39 = and(_T_38, input_buffer.io.deq[0].bits.tail) when _T_39 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`5`[0] node credit_available_hi_6 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node _credit_available_T_7 = cat(credit_available_hi_6, states[2].vc_sel.`0`[0]) node credit_available_hi_7 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1]) node _credit_available_T_8 = cat(credit_available_hi_7, states[2].vc_sel.`1`[0]) node credit_available_lo_hi_2 = cat(states[2].vc_sel.`2`[0], _credit_available_T_8) node credit_available_lo_2 = cat(credit_available_lo_hi_2, _credit_available_T_7) node credit_available_hi_hi_2 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_8 = cat(credit_available_hi_hi_2, states[2].vc_sel.`3`[0]) node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_2) node credit_available_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_10 = cat(credit_available_hi_9, io.out_credit_available.`0`[0]) node credit_available_hi_10 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_11 = cat(credit_available_hi_10, io.out_credit_available.`1`[0]) node credit_available_lo_hi_3 = cat(io.out_credit_available.`2`[0], _credit_available_T_11) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_10) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_11 = cat(credit_available_hi_hi_3, io.out_credit_available.`3`[0]) node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_3) node _credit_available_T_13 = and(_credit_available_T_9, _credit_available_T_12) node credit_available_1 = neq(_credit_available_T_13, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_40 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_41 = and(_T_40, input_buffer.io.deq[2].bits.tail) when _T_41 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[1] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_10 : UInt<1>[1] node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_42 connect _vc_sel_WIRE_10[0], _vc_sel_WIRE_11 connect vc_sel.`3`, _vc_sel_WIRE_10 wire _vc_sel_WIRE_12 : UInt<1>[1] node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_47 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 connect vc_sel.`4`, _vc_sel_WIRE_12 wire _vc_sel_WIRE_14 : UInt<1>[1] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_52 connect _vc_sel_WIRE_14[0], _vc_sel_WIRE_15 connect vc_sel.`5`, _vc_sel_WIRE_14 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node _virt_channel_T_10 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_11 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_12 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_13 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_14 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_15 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_16 = or(_virt_channel_T_10, _virt_channel_T_11) node _virt_channel_T_17 = or(_virt_channel_T_16, _virt_channel_T_12) node _virt_channel_T_18 = or(_virt_channel_T_17, _virt_channel_T_13) node _virt_channel_T_19 = or(_virt_channel_T_18, _virt_channel_T_14) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_15) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_20 node _T_42 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_42 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[0], UInt<1>(0h0) connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`3`[0] invalidate states[1].vc_sel.`4`[0] invalidate states[1].vc_sel.`5`[0] invalidate states[1].g connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) node _T_43 = asUInt(reset) when _T_43 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)
module InputUnit_1( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_3; // @[MixedVec.scala:116:9] wire _GEN_4; // @[MixedVec.scala:116:9] wire _GEN_5; // @[MixedVec.scala:116:9] wire _GEN_6; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_7 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_8 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLFIFOFixer : input clock : Clock input reset : Reset output auto : { flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.user.amba_prot.fetch invalidate anonIn.a.bits.user.amba_prot.secure invalidate anonIn.a.bits.user.amba_prot.privileged invalidate anonIn.a.bits.user.amba_prot.writealloc invalidate anonIn.a.bits.user.amba_prot.readalloc invalidate anonIn.a.bits.user.amba_prot.modifiable invalidate anonIn.a.bits.user.amba_prot.bufferable invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonIn_1.e.bits.sink invalidate anonIn_1.e.valid invalidate anonIn_1.e.ready invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.c.bits.corrupt invalidate anonIn_1.c.bits.data invalidate anonIn_1.c.bits.address invalidate anonIn_1.c.bits.source invalidate anonIn_1.c.bits.size invalidate anonIn_1.c.bits.param invalidate anonIn_1.c.bits.opcode invalidate anonIn_1.c.valid invalidate anonIn_1.c.ready invalidate anonIn_1.b.bits.corrupt invalidate anonIn_1.b.bits.data invalidate anonIn_1.b.bits.mask invalidate anonIn_1.b.bits.address invalidate anonIn_1.b.bits.source invalidate anonIn_1.b.bits.size invalidate anonIn_1.b.bits.param invalidate anonIn_1.b.bits.opcode invalidate anonIn_1.b.valid invalidate anonIn_1.b.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_2.d.bits.corrupt invalidate anonIn_2.d.bits.data invalidate anonIn_2.d.bits.denied invalidate anonIn_2.d.bits.sink invalidate anonIn_2.d.bits.source invalidate anonIn_2.d.bits.size invalidate anonIn_2.d.bits.param invalidate anonIn_2.d.bits.opcode invalidate anonIn_2.d.valid invalidate anonIn_2.d.ready invalidate anonIn_2.a.bits.corrupt invalidate anonIn_2.a.bits.data invalidate anonIn_2.a.bits.mask invalidate anonIn_2.a.bits.user.amba_prot.fetch invalidate anonIn_2.a.bits.user.amba_prot.secure invalidate anonIn_2.a.bits.user.amba_prot.privileged invalidate anonIn_2.a.bits.user.amba_prot.writealloc invalidate anonIn_2.a.bits.user.amba_prot.readalloc invalidate anonIn_2.a.bits.user.amba_prot.modifiable invalidate anonIn_2.a.bits.user.amba_prot.bufferable invalidate anonIn_2.a.bits.address invalidate anonIn_2.a.bits.source invalidate anonIn_2.a.bits.size invalidate anonIn_2.a.bits.param invalidate anonIn_2.a.bits.opcode invalidate anonIn_2.a.valid invalidate anonIn_2.a.ready inst monitor of TLMonitor_3 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_4 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink connect monitor_1.io.in.e.valid, anonIn_1.e.valid connect monitor_1.io.in.e.ready, anonIn_1.e.ready connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode connect monitor_1.io.in.c.valid, anonIn_1.c.valid connect monitor_1.io.in.c.ready, anonIn_1.c.ready connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode connect monitor_1.io.in.b.valid, anonIn_1.b.valid connect monitor_1.io.in.b.ready, anonIn_1.b.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready inst monitor_2 of TLMonitor_5 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode connect monitor_2.io.in.d.valid, anonIn_2.d.valid connect monitor_2.io.in.d.ready, anonIn_2.d.ready connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask connect monitor_2.io.in.a.bits.user.amba_prot.fetch, anonIn_2.a.bits.user.amba_prot.fetch connect monitor_2.io.in.a.bits.user.amba_prot.secure, anonIn_2.a.bits.user.amba_prot.secure connect monitor_2.io.in.a.bits.user.amba_prot.privileged, anonIn_2.a.bits.user.amba_prot.privileged connect monitor_2.io.in.a.bits.user.amba_prot.writealloc, anonIn_2.a.bits.user.amba_prot.writealloc connect monitor_2.io.in.a.bits.user.amba_prot.readalloc, anonIn_2.a.bits.user.amba_prot.readalloc connect monitor_2.io.in.a.bits.user.amba_prot.modifiable, anonIn_2.a.bits.user.amba_prot.modifiable connect monitor_2.io.in.a.bits.user.amba_prot.bufferable, anonIn_2.a.bits.user.amba_prot.bufferable connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode connect monitor_2.io.in.a.valid, anonIn_2.a.valid connect monitor_2.io.in.a.ready, anonIn_2.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.user.amba_prot.fetch invalidate anonOut.a.bits.user.amba_prot.secure invalidate anonOut.a.bits.user.amba_prot.privileged invalidate anonOut.a.bits.user.amba_prot.writealloc invalidate anonOut.a.bits.user.amba_prot.readalloc invalidate anonOut.a.bits.user.amba_prot.modifiable invalidate anonOut.a.bits.user.amba_prot.bufferable invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_anonOut.e.bits.sink invalidate x1_anonOut.e.valid invalidate x1_anonOut.e.ready invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.c.bits.corrupt invalidate x1_anonOut.c.bits.data invalidate x1_anonOut.c.bits.address invalidate x1_anonOut.c.bits.source invalidate x1_anonOut.c.bits.size invalidate x1_anonOut.c.bits.param invalidate x1_anonOut.c.bits.opcode invalidate x1_anonOut.c.valid invalidate x1_anonOut.c.ready invalidate x1_anonOut.b.bits.corrupt invalidate x1_anonOut.b.bits.data invalidate x1_anonOut.b.bits.mask invalidate x1_anonOut.b.bits.address invalidate x1_anonOut.b.bits.source invalidate x1_anonOut.b.bits.size invalidate x1_anonOut.b.bits.param invalidate x1_anonOut.b.bits.opcode invalidate x1_anonOut.b.valid invalidate x1_anonOut.b.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_1.d.bits.corrupt invalidate x1_anonOut_1.d.bits.data invalidate x1_anonOut_1.d.bits.denied invalidate x1_anonOut_1.d.bits.sink invalidate x1_anonOut_1.d.bits.source invalidate x1_anonOut_1.d.bits.size invalidate x1_anonOut_1.d.bits.param invalidate x1_anonOut_1.d.bits.opcode invalidate x1_anonOut_1.d.valid invalidate x1_anonOut_1.d.ready invalidate x1_anonOut_1.a.bits.corrupt invalidate x1_anonOut_1.a.bits.data invalidate x1_anonOut_1.a.bits.mask invalidate x1_anonOut_1.a.bits.user.amba_prot.fetch invalidate x1_anonOut_1.a.bits.user.amba_prot.secure invalidate x1_anonOut_1.a.bits.user.amba_prot.privileged invalidate x1_anonOut_1.a.bits.user.amba_prot.writealloc invalidate x1_anonOut_1.a.bits.user.amba_prot.readalloc invalidate x1_anonOut_1.a.bits.user.amba_prot.modifiable invalidate x1_anonOut_1.a.bits.user.amba_prot.bufferable invalidate x1_anonOut_1.a.bits.address invalidate x1_anonOut_1.a.bits.source invalidate x1_anonOut_1.a.bits.size invalidate x1_anonOut_1.a.bits.param invalidate x1_anonOut_1.a.bits.opcode invalidate x1_anonOut_1.a.valid invalidate x1_anonOut_1.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect auto.anon_out_2, x1_anonOut_1 connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 connect anonIn_2, auto.anon_in_2 node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_5 = xor(anonIn.a.bits.address, UInt<17>(0h10000)) node _a_notFIFO_T_6 = cvt(_a_notFIFO_T_5) node _a_notFIFO_T_7 = and(_a_notFIFO_T_6, asSInt(UInt<33>(0h9c011000))) node _a_notFIFO_T_8 = asSInt(_a_notFIFO_T_7) node _a_notFIFO_T_9 = eq(_a_notFIFO_T_8, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_10 = xor(anonIn.a.bits.address, UInt<28>(0hc000000)) node _a_notFIFO_T_11 = cvt(_a_notFIFO_T_10) node _a_notFIFO_T_12 = and(_a_notFIFO_T_11, asSInt(UInt<33>(0h9c000000))) node _a_notFIFO_T_13 = asSInt(_a_notFIFO_T_12) node _a_notFIFO_T_14 = eq(_a_notFIFO_T_13, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_15 = xor(anonIn.a.bits.address, UInt<29>(0h10000000)) node _a_notFIFO_T_16 = cvt(_a_notFIFO_T_15) node _a_notFIFO_T_17 = and(_a_notFIFO_T_16, asSInt(UInt<33>(0h9c011000))) node _a_notFIFO_T_18 = asSInt(_a_notFIFO_T_17) node _a_notFIFO_T_19 = eq(_a_notFIFO_T_18, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_20 = or(_a_notFIFO_T_4, _a_notFIFO_T_9) node _a_notFIFO_T_21 = or(_a_notFIFO_T_20, _a_notFIFO_T_14) node _a_notFIFO_T_22 = or(_a_notFIFO_T_21, _a_notFIFO_T_19) node _a_notFIFO_T_23 = xor(anonIn.a.bits.address, UInt<28>(0h8000000)) node _a_notFIFO_T_24 = cvt(_a_notFIFO_T_23) node _a_notFIFO_T_25 = and(_a_notFIFO_T_24, asSInt(UInt<33>(0h9c010000))) node _a_notFIFO_T_26 = asSInt(_a_notFIFO_T_25) node _a_notFIFO_T_27 = eq(_a_notFIFO_T_26, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_28 = xor(anonIn.a.bits.address, UInt<32>(0h80000000)) node _a_notFIFO_T_29 = cvt(_a_notFIFO_T_28) node _a_notFIFO_T_30 = and(_a_notFIFO_T_29, asSInt(UInt<33>(0h90000000))) node _a_notFIFO_T_31 = asSInt(_a_notFIFO_T_30) node _a_notFIFO_T_32 = eq(_a_notFIFO_T_31, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_33 = or(_a_notFIFO_T_27, _a_notFIFO_T_32) node _a_notFIFO_T_34 = mux(_a_notFIFO_T_22, UInt<1>(0h0), UInt<1>(0h0)) node _a_notFIFO_T_35 = mux(_a_notFIFO_T_33, UInt<1>(0h1), UInt<1>(0h0)) node _a_notFIFO_T_36 = or(_a_notFIFO_T_34, _a_notFIFO_T_35) wire a_notFIFO : UInt<1> connect a_notFIFO, _a_notFIFO_T_36 node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) node _a_id_T_1 = cvt(_a_id_T) node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<1>(0h0))) node _a_id_T_3 = asSInt(_a_id_T_2) node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) node a_noDomain = eq(UInt<1>(0h1), UInt<1>(0h0)) node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonIn.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) node d_first = and(d_first_first, _d_first_T_1) wire _flight_WIRE : UInt<1>[17] connect _flight_WIRE[0], UInt<1>(0h0) connect _flight_WIRE[1], UInt<1>(0h0) connect _flight_WIRE[2], UInt<1>(0h0) connect _flight_WIRE[3], UInt<1>(0h0) connect _flight_WIRE[4], UInt<1>(0h0) connect _flight_WIRE[5], UInt<1>(0h0) connect _flight_WIRE[6], UInt<1>(0h0) connect _flight_WIRE[7], UInt<1>(0h0) connect _flight_WIRE[8], UInt<1>(0h0) connect _flight_WIRE[9], UInt<1>(0h0) connect _flight_WIRE[10], UInt<1>(0h0) connect _flight_WIRE[11], UInt<1>(0h0) connect _flight_WIRE[12], UInt<1>(0h0) connect _flight_WIRE[13], UInt<1>(0h0) connect _flight_WIRE[14], UInt<1>(0h0) connect _flight_WIRE[15], UInt<1>(0h0) connect _flight_WIRE[16], UInt<1>(0h0) regreset flight : UInt<1>[17], clock, reset, _flight_WIRE node _T = and(anonIn.a.ready, anonIn.a.valid) node _T_1 = and(a_first, _T) when _T_1 : node _flight_T = eq(a_notFIFO, UInt<1>(0h0)) connect flight[anonIn.a.bits.source], _flight_T node _T_2 = and(anonIn.d.ready, anonIn.d.valid) node _T_3 = and(d_first, _T_2) when _T_3 : connect flight[anonIn.d.bits.source], UInt<1>(0h0) connect anonOut.a, anonIn.a connect anonIn.d, anonOut.d node _anonOut_a_valid_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _anonOut_a_valid_T_1 = or(a_notFIFO, _anonOut_a_valid_T) node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) connect anonOut.a.valid, _anonOut_a_valid_T_2 node _anonIn_a_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(a_notFIFO, _anonIn_a_ready_T) node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) connect anonIn.a.ready, _anonIn_a_ready_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) node _T_4 = and(anonIn.a.valid, UInt<1>(0h0)) regreset SourceIdFIFOed : UInt<17>, clock, reset, UInt<17>(0h0) wire SourceIdSet : UInt<17> connect SourceIdSet, UInt<17>(0h0) wire SourceIdClear : UInt<17> connect SourceIdClear, UInt<17>(0h0) node _T_5 = and(anonIn.a.ready, anonIn.a.valid) node _T_6 = and(a_first, _T_5) node _T_7 = eq(a_notFIFO, UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) connect SourceIdSet, _SourceIdSet_T node _T_9 = and(anonIn.d.ready, anonIn.d.valid) node _T_10 = and(d_first, _T_9) when _T_10 : node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) connect SourceIdClear, _SourceIdClear_T node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) connect SourceIdFIFOed, _SourceIdFIFOed_T node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<17>(0h1ffff), UInt<17>(0h0)) node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T) node _T_11 = or(flight[0], flight[1]) node _T_12 = or(_T_11, flight[2]) node _T_13 = or(_T_12, flight[3]) node _T_14 = or(_T_13, flight[4]) node _T_15 = or(_T_14, flight[5]) node _T_16 = or(_T_15, flight[6]) node _T_17 = or(_T_16, flight[7]) node _T_18 = or(_T_17, flight[8]) node _T_19 = or(_T_18, flight[9]) node _T_20 = or(_T_19, flight[10]) node _T_21 = or(_T_20, flight[11]) node _T_22 = or(_T_21, flight[12]) node _T_23 = or(_T_22, flight[13]) node _T_24 = or(_T_23, flight[14]) node _T_25 = or(_T_24, flight[15]) node _T_26 = or(_T_25, flight[16]) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = gt(SourceIdSet, UInt<1>(0h0)) node _T_29 = gt(SourceIdClear, UInt<1>(0h0)) node _a_notFIFO_T_37 = xor(anonIn_1.a.bits.address, UInt<1>(0h0)) node _a_notFIFO_T_38 = cvt(_a_notFIFO_T_37) node _a_notFIFO_T_39 = and(_a_notFIFO_T_38, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_40 = asSInt(_a_notFIFO_T_39) node _a_notFIFO_T_41 = eq(_a_notFIFO_T_40, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_42 = xor(anonIn_1.a.bits.address, UInt<17>(0h10000)) node _a_notFIFO_T_43 = cvt(_a_notFIFO_T_42) node _a_notFIFO_T_44 = and(_a_notFIFO_T_43, asSInt(UInt<33>(0h9c011000))) node _a_notFIFO_T_45 = asSInt(_a_notFIFO_T_44) node _a_notFIFO_T_46 = eq(_a_notFIFO_T_45, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_47 = xor(anonIn_1.a.bits.address, UInt<28>(0hc000000)) node _a_notFIFO_T_48 = cvt(_a_notFIFO_T_47) node _a_notFIFO_T_49 = and(_a_notFIFO_T_48, asSInt(UInt<33>(0h9c000000))) node _a_notFIFO_T_50 = asSInt(_a_notFIFO_T_49) node _a_notFIFO_T_51 = eq(_a_notFIFO_T_50, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_52 = xor(anonIn_1.a.bits.address, UInt<29>(0h10000000)) node _a_notFIFO_T_53 = cvt(_a_notFIFO_T_52) node _a_notFIFO_T_54 = and(_a_notFIFO_T_53, asSInt(UInt<33>(0h9c011000))) node _a_notFIFO_T_55 = asSInt(_a_notFIFO_T_54) node _a_notFIFO_T_56 = eq(_a_notFIFO_T_55, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_57 = or(_a_notFIFO_T_41, _a_notFIFO_T_46) node _a_notFIFO_T_58 = or(_a_notFIFO_T_57, _a_notFIFO_T_51) node _a_notFIFO_T_59 = or(_a_notFIFO_T_58, _a_notFIFO_T_56) node _a_notFIFO_T_60 = xor(anonIn_1.a.bits.address, UInt<28>(0h8000000)) node _a_notFIFO_T_61 = cvt(_a_notFIFO_T_60) node _a_notFIFO_T_62 = and(_a_notFIFO_T_61, asSInt(UInt<33>(0h9c010000))) node _a_notFIFO_T_63 = asSInt(_a_notFIFO_T_62) node _a_notFIFO_T_64 = eq(_a_notFIFO_T_63, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_65 = xor(anonIn_1.a.bits.address, UInt<32>(0h80000000)) node _a_notFIFO_T_66 = cvt(_a_notFIFO_T_65) node _a_notFIFO_T_67 = and(_a_notFIFO_T_66, asSInt(UInt<33>(0h90000000))) node _a_notFIFO_T_68 = asSInt(_a_notFIFO_T_67) node _a_notFIFO_T_69 = eq(_a_notFIFO_T_68, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_70 = or(_a_notFIFO_T_64, _a_notFIFO_T_69) node _a_notFIFO_T_71 = mux(_a_notFIFO_T_59, UInt<1>(0h0), UInt<1>(0h0)) node _a_notFIFO_T_72 = mux(_a_notFIFO_T_70, UInt<1>(0h1), UInt<1>(0h0)) node _a_notFIFO_T_73 = or(_a_notFIFO_T_71, _a_notFIFO_T_72) wire a_notFIFO_1 : UInt<1> connect a_notFIFO_1, _a_notFIFO_T_73 node _a_id_T_5 = xor(anonIn_1.a.bits.address, UInt<1>(0h0)) node _a_id_T_6 = cvt(_a_id_T_5) node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<1>(0h0))) node _a_id_T_8 = asSInt(_a_id_T_7) node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) node a_noDomain_1 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _a_first_T_1 = and(anonIn_1.a.ready, anonIn_1.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), anonIn_1.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(anonIn_1.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_2 = and(x1_anonOut.d.ready, x1_anonOut.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), x1_anonOut.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(x1_anonOut.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_2) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_2 : node _d_first_counter_T_1 = mux(d_first_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 node _d_first_T_3 = neq(x1_anonOut.d.bits.opcode, UInt<3>(0h6)) node d_first_1 = and(d_first_first_1, _d_first_T_3) wire _flight_WIRE_1 : UInt<1>[3] connect _flight_WIRE_1[0], UInt<1>(0h0) connect _flight_WIRE_1[1], UInt<1>(0h0) connect _flight_WIRE_1[2], UInt<1>(0h0) regreset flight_1 : UInt<1>[3], clock, reset, _flight_WIRE_1 node _T_30 = and(anonIn_1.a.ready, anonIn_1.a.valid) node _T_31 = and(a_first_1, _T_30) when _T_31 : node _flight_T_1 = eq(a_notFIFO_1, UInt<1>(0h0)) connect flight_1[anonIn_1.a.bits.source], _flight_T_1 node _T_32 = and(anonIn_1.d.ready, anonIn_1.d.valid) node _T_33 = and(d_first_1, _T_32) when _T_33 : connect flight_1[anonIn_1.d.bits.source], UInt<1>(0h0) connect x1_anonOut.a, anonIn_1.a connect anonIn_1.d, x1_anonOut.d node _anonOut_a_valid_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _anonOut_a_valid_T_4 = or(a_notFIFO_1, _anonOut_a_valid_T_3) node _anonOut_a_valid_T_5 = and(anonIn_1.a.valid, _anonOut_a_valid_T_4) connect x1_anonOut.a.valid, _anonOut_a_valid_T_5 node _anonIn_a_ready_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _anonIn_a_ready_T_4 = or(a_notFIFO_1, _anonIn_a_ready_T_3) node _anonIn_a_ready_T_5 = and(x1_anonOut.a.ready, _anonIn_a_ready_T_4) connect anonIn_1.a.ready, _anonIn_a_ready_T_5 connect anonIn_1.b, x1_anonOut.b connect x1_anonOut.c, anonIn_1.c connect x1_anonOut.e, anonIn_1.e node _T_34 = and(anonIn_1.a.valid, UInt<1>(0h0)) regreset SourceIdFIFOed_1 : UInt<3>, clock, reset, UInt<3>(0h0) wire SourceIdSet_1 : UInt<3> connect SourceIdSet_1, UInt<3>(0h0) wire SourceIdClear_1 : UInt<3> connect SourceIdClear_1, UInt<3>(0h0) node _T_35 = and(anonIn_1.a.ready, anonIn_1.a.valid) node _T_36 = and(a_first_1, _T_35) node _T_37 = eq(a_notFIFO_1, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) when _T_38 : node _SourceIdSet_T_1 = dshl(UInt<1>(0h1), anonIn_1.a.bits.source) connect SourceIdSet_1, _SourceIdSet_T_1 node _T_39 = and(anonIn_1.d.ready, anonIn_1.d.valid) node _T_40 = and(d_first_1, _T_39) when _T_40 : node _SourceIdClear_T_1 = dshl(UInt<1>(0h1), anonIn_1.d.bits.source) connect SourceIdClear_1, _SourceIdClear_T_1 node _SourceIdFIFOed_T_1 = or(SourceIdFIFOed_1, SourceIdSet_1) connect SourceIdFIFOed_1, _SourceIdFIFOed_T_1 node _allIDs_FIFOed_T_1 = mux(UInt<1>(0h1), UInt<3>(0h7), UInt<3>(0h0)) node allIDs_FIFOed_1 = eq(SourceIdFIFOed_1, _allIDs_FIFOed_T_1) node _T_41 = or(flight_1[0], flight_1[1]) node _T_42 = or(_T_41, flight_1[2]) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = gt(SourceIdSet_1, UInt<1>(0h0)) node _T_45 = gt(SourceIdClear_1, UInt<1>(0h0)) node _a_notFIFO_T_74 = xor(anonIn_2.a.bits.address, UInt<1>(0h0)) node _a_notFIFO_T_75 = cvt(_a_notFIFO_T_74) node _a_notFIFO_T_76 = and(_a_notFIFO_T_75, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_77 = asSInt(_a_notFIFO_T_76) node _a_notFIFO_T_78 = eq(_a_notFIFO_T_77, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_79 = xor(anonIn_2.a.bits.address, UInt<17>(0h10000)) node _a_notFIFO_T_80 = cvt(_a_notFIFO_T_79) node _a_notFIFO_T_81 = and(_a_notFIFO_T_80, asSInt(UInt<33>(0h9c011000))) node _a_notFIFO_T_82 = asSInt(_a_notFIFO_T_81) node _a_notFIFO_T_83 = eq(_a_notFIFO_T_82, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_84 = xor(anonIn_2.a.bits.address, UInt<28>(0hc000000)) node _a_notFIFO_T_85 = cvt(_a_notFIFO_T_84) node _a_notFIFO_T_86 = and(_a_notFIFO_T_85, asSInt(UInt<33>(0h9c000000))) node _a_notFIFO_T_87 = asSInt(_a_notFIFO_T_86) node _a_notFIFO_T_88 = eq(_a_notFIFO_T_87, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_89 = xor(anonIn_2.a.bits.address, UInt<29>(0h10000000)) node _a_notFIFO_T_90 = cvt(_a_notFIFO_T_89) node _a_notFIFO_T_91 = and(_a_notFIFO_T_90, asSInt(UInt<33>(0h9c011000))) node _a_notFIFO_T_92 = asSInt(_a_notFIFO_T_91) node _a_notFIFO_T_93 = eq(_a_notFIFO_T_92, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_94 = or(_a_notFIFO_T_78, _a_notFIFO_T_83) node _a_notFIFO_T_95 = or(_a_notFIFO_T_94, _a_notFIFO_T_88) node _a_notFIFO_T_96 = or(_a_notFIFO_T_95, _a_notFIFO_T_93) node _a_notFIFO_T_97 = xor(anonIn_2.a.bits.address, UInt<28>(0h8000000)) node _a_notFIFO_T_98 = cvt(_a_notFIFO_T_97) node _a_notFIFO_T_99 = and(_a_notFIFO_T_98, asSInt(UInt<33>(0h9c010000))) node _a_notFIFO_T_100 = asSInt(_a_notFIFO_T_99) node _a_notFIFO_T_101 = eq(_a_notFIFO_T_100, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_102 = xor(anonIn_2.a.bits.address, UInt<32>(0h80000000)) node _a_notFIFO_T_103 = cvt(_a_notFIFO_T_102) node _a_notFIFO_T_104 = and(_a_notFIFO_T_103, asSInt(UInt<33>(0h90000000))) node _a_notFIFO_T_105 = asSInt(_a_notFIFO_T_104) node _a_notFIFO_T_106 = eq(_a_notFIFO_T_105, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_107 = or(_a_notFIFO_T_101, _a_notFIFO_T_106) node _a_notFIFO_T_108 = mux(_a_notFIFO_T_96, UInt<1>(0h0), UInt<1>(0h0)) node _a_notFIFO_T_109 = mux(_a_notFIFO_T_107, UInt<1>(0h1), UInt<1>(0h0)) node _a_notFIFO_T_110 = or(_a_notFIFO_T_108, _a_notFIFO_T_109) wire a_notFIFO_2 : UInt<1> connect a_notFIFO_2, _a_notFIFO_T_110 node _a_id_T_10 = xor(anonIn_2.a.bits.address, UInt<1>(0h0)) node _a_id_T_11 = cvt(_a_id_T_10) node _a_id_T_12 = and(_a_id_T_11, asSInt(UInt<1>(0h0))) node _a_id_T_13 = asSInt(_a_id_T_12) node _a_id_T_14 = eq(_a_id_T_13, asSInt(UInt<1>(0h0))) node a_noDomain_2 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _a_first_T_2 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _a_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), anonIn_2.a.bits.size) node _a_first_beats1_decode_T_7 = bits(_a_first_beats1_decode_T_6, 11, 0) node _a_first_beats1_decode_T_8 = not(_a_first_beats1_decode_T_7) node a_first_beats1_decode_2 = shr(_a_first_beats1_decode_T_8, 3) node _a_first_beats1_opdata_T_2 = bits(anonIn_2.a.bits.opcode, 2, 2) node a_first_beats1_opdata_2 = eq(_a_first_beats1_opdata_T_2, UInt<1>(0h0)) node a_first_beats1_2 = mux(a_first_beats1_opdata_2, a_first_beats1_decode_2, UInt<1>(0h0)) regreset a_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_2 = sub(a_first_counter_2, UInt<1>(0h1)) node a_first_counter1_2 = tail(_a_first_counter1_T_2, 1) node a_first_2 = eq(a_first_counter_2, UInt<1>(0h0)) node _a_first_last_T_4 = eq(a_first_counter_2, UInt<1>(0h1)) node _a_first_last_T_5 = eq(a_first_beats1_2, UInt<1>(0h0)) node a_first_last_2 = or(_a_first_last_T_4, _a_first_last_T_5) node a_first_done_2 = and(a_first_last_2, _a_first_T_2) node _a_first_count_T_2 = not(a_first_counter1_2) node a_first_count_2 = and(a_first_beats1_2, _a_first_count_T_2) when _a_first_T_2 : node _a_first_counter_T_2 = mux(a_first_2, a_first_beats1_2, a_first_counter1_2) connect a_first_counter_2, _a_first_counter_T_2 node _d_first_T_4 = and(x1_anonOut_1.d.ready, x1_anonOut_1.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), x1_anonOut_1.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(x1_anonOut_1.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_4) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_4 : node _d_first_counter_T_2 = mux(d_first_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 node _d_first_T_5 = neq(x1_anonOut_1.d.bits.opcode, UInt<3>(0h6)) node d_first_2 = and(d_first_first_2, _d_first_T_5) wire _flight_WIRE_2 : UInt<1>[256] connect _flight_WIRE_2[0], UInt<1>(0h0) connect _flight_WIRE_2[1], UInt<1>(0h0) connect _flight_WIRE_2[2], UInt<1>(0h0) connect _flight_WIRE_2[3], UInt<1>(0h0) connect _flight_WIRE_2[4], UInt<1>(0h0) connect _flight_WIRE_2[5], UInt<1>(0h0) connect _flight_WIRE_2[6], UInt<1>(0h0) connect _flight_WIRE_2[7], UInt<1>(0h0) connect _flight_WIRE_2[8], UInt<1>(0h0) connect _flight_WIRE_2[9], UInt<1>(0h0) connect _flight_WIRE_2[10], UInt<1>(0h0) connect _flight_WIRE_2[11], UInt<1>(0h0) connect _flight_WIRE_2[12], UInt<1>(0h0) connect _flight_WIRE_2[13], UInt<1>(0h0) connect _flight_WIRE_2[14], UInt<1>(0h0) connect _flight_WIRE_2[15], UInt<1>(0h0) connect _flight_WIRE_2[16], UInt<1>(0h0) connect _flight_WIRE_2[17], UInt<1>(0h0) connect _flight_WIRE_2[18], UInt<1>(0h0) connect _flight_WIRE_2[19], UInt<1>(0h0) connect _flight_WIRE_2[20], UInt<1>(0h0) connect _flight_WIRE_2[21], UInt<1>(0h0) connect _flight_WIRE_2[22], UInt<1>(0h0) connect _flight_WIRE_2[23], UInt<1>(0h0) connect _flight_WIRE_2[24], UInt<1>(0h0) connect _flight_WIRE_2[25], UInt<1>(0h0) connect _flight_WIRE_2[26], UInt<1>(0h0) connect _flight_WIRE_2[27], UInt<1>(0h0) connect _flight_WIRE_2[28], UInt<1>(0h0) connect _flight_WIRE_2[29], UInt<1>(0h0) connect _flight_WIRE_2[30], UInt<1>(0h0) connect _flight_WIRE_2[31], UInt<1>(0h0) connect _flight_WIRE_2[32], UInt<1>(0h0) connect _flight_WIRE_2[33], UInt<1>(0h0) connect _flight_WIRE_2[34], UInt<1>(0h0) connect _flight_WIRE_2[35], UInt<1>(0h0) connect _flight_WIRE_2[36], UInt<1>(0h0) connect _flight_WIRE_2[37], UInt<1>(0h0) connect _flight_WIRE_2[38], UInt<1>(0h0) connect _flight_WIRE_2[39], UInt<1>(0h0) connect _flight_WIRE_2[40], UInt<1>(0h0) connect _flight_WIRE_2[41], UInt<1>(0h0) connect _flight_WIRE_2[42], UInt<1>(0h0) connect _flight_WIRE_2[43], UInt<1>(0h0) connect _flight_WIRE_2[44], UInt<1>(0h0) connect _flight_WIRE_2[45], UInt<1>(0h0) connect _flight_WIRE_2[46], UInt<1>(0h0) connect _flight_WIRE_2[47], UInt<1>(0h0) connect _flight_WIRE_2[48], UInt<1>(0h0) connect _flight_WIRE_2[49], UInt<1>(0h0) connect _flight_WIRE_2[50], UInt<1>(0h0) connect _flight_WIRE_2[51], UInt<1>(0h0) connect _flight_WIRE_2[52], UInt<1>(0h0) connect _flight_WIRE_2[53], UInt<1>(0h0) connect _flight_WIRE_2[54], UInt<1>(0h0) connect _flight_WIRE_2[55], UInt<1>(0h0) connect _flight_WIRE_2[56], UInt<1>(0h0) connect _flight_WIRE_2[57], UInt<1>(0h0) connect _flight_WIRE_2[58], UInt<1>(0h0) connect _flight_WIRE_2[59], UInt<1>(0h0) connect _flight_WIRE_2[60], UInt<1>(0h0) connect _flight_WIRE_2[61], UInt<1>(0h0) connect _flight_WIRE_2[62], UInt<1>(0h0) connect _flight_WIRE_2[63], UInt<1>(0h0) connect _flight_WIRE_2[64], UInt<1>(0h0) connect _flight_WIRE_2[65], UInt<1>(0h0) connect _flight_WIRE_2[66], UInt<1>(0h0) connect _flight_WIRE_2[67], UInt<1>(0h0) connect _flight_WIRE_2[68], UInt<1>(0h0) connect _flight_WIRE_2[69], UInt<1>(0h0) connect _flight_WIRE_2[70], UInt<1>(0h0) connect _flight_WIRE_2[71], UInt<1>(0h0) connect _flight_WIRE_2[72], UInt<1>(0h0) connect _flight_WIRE_2[73], UInt<1>(0h0) connect _flight_WIRE_2[74], UInt<1>(0h0) connect _flight_WIRE_2[75], UInt<1>(0h0) connect _flight_WIRE_2[76], UInt<1>(0h0) connect _flight_WIRE_2[77], UInt<1>(0h0) connect _flight_WIRE_2[78], UInt<1>(0h0) connect _flight_WIRE_2[79], UInt<1>(0h0) connect _flight_WIRE_2[80], UInt<1>(0h0) connect _flight_WIRE_2[81], UInt<1>(0h0) connect _flight_WIRE_2[82], UInt<1>(0h0) connect _flight_WIRE_2[83], UInt<1>(0h0) connect _flight_WIRE_2[84], UInt<1>(0h0) connect _flight_WIRE_2[85], UInt<1>(0h0) connect _flight_WIRE_2[86], UInt<1>(0h0) connect _flight_WIRE_2[87], UInt<1>(0h0) connect _flight_WIRE_2[88], UInt<1>(0h0) connect _flight_WIRE_2[89], UInt<1>(0h0) connect _flight_WIRE_2[90], UInt<1>(0h0) connect _flight_WIRE_2[91], UInt<1>(0h0) connect _flight_WIRE_2[92], UInt<1>(0h0) connect _flight_WIRE_2[93], UInt<1>(0h0) connect _flight_WIRE_2[94], UInt<1>(0h0) connect _flight_WIRE_2[95], UInt<1>(0h0) connect _flight_WIRE_2[96], UInt<1>(0h0) connect _flight_WIRE_2[97], UInt<1>(0h0) connect _flight_WIRE_2[98], UInt<1>(0h0) connect _flight_WIRE_2[99], UInt<1>(0h0) connect _flight_WIRE_2[100], UInt<1>(0h0) connect _flight_WIRE_2[101], UInt<1>(0h0) connect _flight_WIRE_2[102], UInt<1>(0h0) connect _flight_WIRE_2[103], UInt<1>(0h0) connect _flight_WIRE_2[104], UInt<1>(0h0) connect _flight_WIRE_2[105], UInt<1>(0h0) connect _flight_WIRE_2[106], UInt<1>(0h0) connect _flight_WIRE_2[107], UInt<1>(0h0) connect _flight_WIRE_2[108], UInt<1>(0h0) connect _flight_WIRE_2[109], UInt<1>(0h0) connect _flight_WIRE_2[110], UInt<1>(0h0) connect _flight_WIRE_2[111], UInt<1>(0h0) connect _flight_WIRE_2[112], UInt<1>(0h0) connect _flight_WIRE_2[113], UInt<1>(0h0) connect _flight_WIRE_2[114], UInt<1>(0h0) connect _flight_WIRE_2[115], UInt<1>(0h0) connect _flight_WIRE_2[116], UInt<1>(0h0) connect _flight_WIRE_2[117], UInt<1>(0h0) connect _flight_WIRE_2[118], UInt<1>(0h0) connect _flight_WIRE_2[119], UInt<1>(0h0) connect _flight_WIRE_2[120], UInt<1>(0h0) connect _flight_WIRE_2[121], UInt<1>(0h0) connect _flight_WIRE_2[122], UInt<1>(0h0) connect _flight_WIRE_2[123], UInt<1>(0h0) connect _flight_WIRE_2[124], UInt<1>(0h0) connect _flight_WIRE_2[125], UInt<1>(0h0) connect _flight_WIRE_2[126], UInt<1>(0h0) connect _flight_WIRE_2[127], UInt<1>(0h0) connect _flight_WIRE_2[128], UInt<1>(0h0) connect _flight_WIRE_2[129], UInt<1>(0h0) connect _flight_WIRE_2[130], UInt<1>(0h0) connect _flight_WIRE_2[131], UInt<1>(0h0) connect _flight_WIRE_2[132], UInt<1>(0h0) connect _flight_WIRE_2[133], UInt<1>(0h0) connect _flight_WIRE_2[134], UInt<1>(0h0) connect _flight_WIRE_2[135], UInt<1>(0h0) connect _flight_WIRE_2[136], UInt<1>(0h0) connect _flight_WIRE_2[137], UInt<1>(0h0) connect _flight_WIRE_2[138], UInt<1>(0h0) connect _flight_WIRE_2[139], UInt<1>(0h0) connect _flight_WIRE_2[140], UInt<1>(0h0) connect _flight_WIRE_2[141], UInt<1>(0h0) connect _flight_WIRE_2[142], UInt<1>(0h0) connect _flight_WIRE_2[143], UInt<1>(0h0) connect _flight_WIRE_2[144], UInt<1>(0h0) connect _flight_WIRE_2[145], UInt<1>(0h0) connect _flight_WIRE_2[146], UInt<1>(0h0) connect _flight_WIRE_2[147], UInt<1>(0h0) connect _flight_WIRE_2[148], UInt<1>(0h0) connect _flight_WIRE_2[149], UInt<1>(0h0) connect _flight_WIRE_2[150], UInt<1>(0h0) connect _flight_WIRE_2[151], UInt<1>(0h0) connect _flight_WIRE_2[152], UInt<1>(0h0) connect _flight_WIRE_2[153], UInt<1>(0h0) connect _flight_WIRE_2[154], UInt<1>(0h0) connect _flight_WIRE_2[155], UInt<1>(0h0) connect _flight_WIRE_2[156], UInt<1>(0h0) connect _flight_WIRE_2[157], UInt<1>(0h0) connect _flight_WIRE_2[158], UInt<1>(0h0) connect _flight_WIRE_2[159], UInt<1>(0h0) connect _flight_WIRE_2[160], UInt<1>(0h0) connect _flight_WIRE_2[161], UInt<1>(0h0) connect _flight_WIRE_2[162], UInt<1>(0h0) connect _flight_WIRE_2[163], UInt<1>(0h0) connect _flight_WIRE_2[164], UInt<1>(0h0) connect _flight_WIRE_2[165], UInt<1>(0h0) connect _flight_WIRE_2[166], UInt<1>(0h0) connect _flight_WIRE_2[167], UInt<1>(0h0) connect _flight_WIRE_2[168], UInt<1>(0h0) connect _flight_WIRE_2[169], UInt<1>(0h0) connect _flight_WIRE_2[170], UInt<1>(0h0) connect _flight_WIRE_2[171], UInt<1>(0h0) connect _flight_WIRE_2[172], UInt<1>(0h0) connect _flight_WIRE_2[173], UInt<1>(0h0) connect _flight_WIRE_2[174], UInt<1>(0h0) connect _flight_WIRE_2[175], UInt<1>(0h0) connect _flight_WIRE_2[176], UInt<1>(0h0) connect _flight_WIRE_2[177], UInt<1>(0h0) connect _flight_WIRE_2[178], UInt<1>(0h0) connect _flight_WIRE_2[179], UInt<1>(0h0) connect _flight_WIRE_2[180], UInt<1>(0h0) connect _flight_WIRE_2[181], UInt<1>(0h0) connect _flight_WIRE_2[182], UInt<1>(0h0) connect _flight_WIRE_2[183], UInt<1>(0h0) connect _flight_WIRE_2[184], UInt<1>(0h0) connect _flight_WIRE_2[185], UInt<1>(0h0) connect _flight_WIRE_2[186], UInt<1>(0h0) connect _flight_WIRE_2[187], UInt<1>(0h0) connect _flight_WIRE_2[188], UInt<1>(0h0) connect _flight_WIRE_2[189], UInt<1>(0h0) connect _flight_WIRE_2[190], UInt<1>(0h0) connect _flight_WIRE_2[191], UInt<1>(0h0) connect _flight_WIRE_2[192], UInt<1>(0h0) connect _flight_WIRE_2[193], UInt<1>(0h0) connect _flight_WIRE_2[194], UInt<1>(0h0) connect _flight_WIRE_2[195], UInt<1>(0h0) connect _flight_WIRE_2[196], UInt<1>(0h0) connect _flight_WIRE_2[197], UInt<1>(0h0) connect _flight_WIRE_2[198], UInt<1>(0h0) connect _flight_WIRE_2[199], UInt<1>(0h0) connect _flight_WIRE_2[200], UInt<1>(0h0) connect _flight_WIRE_2[201], UInt<1>(0h0) connect _flight_WIRE_2[202], UInt<1>(0h0) connect _flight_WIRE_2[203], UInt<1>(0h0) connect _flight_WIRE_2[204], UInt<1>(0h0) connect _flight_WIRE_2[205], UInt<1>(0h0) connect _flight_WIRE_2[206], UInt<1>(0h0) connect _flight_WIRE_2[207], UInt<1>(0h0) connect _flight_WIRE_2[208], UInt<1>(0h0) connect _flight_WIRE_2[209], UInt<1>(0h0) connect _flight_WIRE_2[210], UInt<1>(0h0) connect _flight_WIRE_2[211], UInt<1>(0h0) connect _flight_WIRE_2[212], UInt<1>(0h0) connect _flight_WIRE_2[213], UInt<1>(0h0) connect _flight_WIRE_2[214], UInt<1>(0h0) connect _flight_WIRE_2[215], UInt<1>(0h0) connect _flight_WIRE_2[216], UInt<1>(0h0) connect _flight_WIRE_2[217], UInt<1>(0h0) connect _flight_WIRE_2[218], UInt<1>(0h0) connect _flight_WIRE_2[219], UInt<1>(0h0) connect _flight_WIRE_2[220], UInt<1>(0h0) connect _flight_WIRE_2[221], UInt<1>(0h0) connect _flight_WIRE_2[222], UInt<1>(0h0) connect _flight_WIRE_2[223], UInt<1>(0h0) connect _flight_WIRE_2[224], UInt<1>(0h0) connect _flight_WIRE_2[225], UInt<1>(0h0) connect _flight_WIRE_2[226], UInt<1>(0h0) connect _flight_WIRE_2[227], UInt<1>(0h0) connect _flight_WIRE_2[228], UInt<1>(0h0) connect _flight_WIRE_2[229], UInt<1>(0h0) connect _flight_WIRE_2[230], UInt<1>(0h0) connect _flight_WIRE_2[231], UInt<1>(0h0) connect _flight_WIRE_2[232], UInt<1>(0h0) connect _flight_WIRE_2[233], UInt<1>(0h0) connect _flight_WIRE_2[234], UInt<1>(0h0) connect _flight_WIRE_2[235], UInt<1>(0h0) connect _flight_WIRE_2[236], UInt<1>(0h0) connect _flight_WIRE_2[237], UInt<1>(0h0) connect _flight_WIRE_2[238], UInt<1>(0h0) connect _flight_WIRE_2[239], UInt<1>(0h0) connect _flight_WIRE_2[240], UInt<1>(0h0) connect _flight_WIRE_2[241], UInt<1>(0h0) connect _flight_WIRE_2[242], UInt<1>(0h0) connect _flight_WIRE_2[243], UInt<1>(0h0) connect _flight_WIRE_2[244], UInt<1>(0h0) connect _flight_WIRE_2[245], UInt<1>(0h0) connect _flight_WIRE_2[246], UInt<1>(0h0) connect _flight_WIRE_2[247], UInt<1>(0h0) connect _flight_WIRE_2[248], UInt<1>(0h0) connect _flight_WIRE_2[249], UInt<1>(0h0) connect _flight_WIRE_2[250], UInt<1>(0h0) connect _flight_WIRE_2[251], UInt<1>(0h0) connect _flight_WIRE_2[252], UInt<1>(0h0) connect _flight_WIRE_2[253], UInt<1>(0h0) connect _flight_WIRE_2[254], UInt<1>(0h0) connect _flight_WIRE_2[255], UInt<1>(0h0) regreset flight_2 : UInt<1>[256], clock, reset, _flight_WIRE_2 node _T_46 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _T_47 = and(a_first_2, _T_46) when _T_47 : node _flight_T_2 = eq(a_notFIFO_2, UInt<1>(0h0)) connect flight_2[anonIn_2.a.bits.source], _flight_T_2 node _T_48 = and(anonIn_2.d.ready, anonIn_2.d.valid) node _T_49 = and(d_first_2, _T_48) when _T_49 : connect flight_2[anonIn_2.d.bits.source], UInt<1>(0h0) node _stalls_a_sel_uncommonBits_T = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits = bits(_stalls_a_sel_uncommonBits_T, 4, 0) node _stalls_a_sel_T = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_1 = eq(_stalls_a_sel_T, UInt<1>(0h0)) node _stalls_a_sel_T_2 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits) node _stalls_a_sel_T_3 = and(_stalls_a_sel_T_1, _stalls_a_sel_T_2) node _stalls_a_sel_T_4 = leq(stalls_a_sel_uncommonBits, UInt<5>(0h1f)) node stalls_a_sel = and(_stalls_a_sel_T_3, _stalls_a_sel_T_4) node _stalls_id_T = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_1 = and(_stalls_id_T, stalls_a_sel) node _stalls_id_T_2 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_3 = and(_stalls_id_T_1, _stalls_id_T_2) reg stalls_id : UInt<1>, clock when _stalls_id_T_3 : connect stalls_id, UInt<1>(0h1) node _stalls_T = and(stalls_a_sel, a_first_2) node _stalls_T_1 = or(flight_2[0], flight_2[1]) node _stalls_T_2 = or(_stalls_T_1, flight_2[2]) node _stalls_T_3 = or(_stalls_T_2, flight_2[3]) node _stalls_T_4 = or(_stalls_T_3, flight_2[4]) node _stalls_T_5 = or(_stalls_T_4, flight_2[5]) node _stalls_T_6 = or(_stalls_T_5, flight_2[6]) node _stalls_T_7 = or(_stalls_T_6, flight_2[7]) node _stalls_T_8 = or(_stalls_T_7, flight_2[8]) node _stalls_T_9 = or(_stalls_T_8, flight_2[9]) node _stalls_T_10 = or(_stalls_T_9, flight_2[10]) node _stalls_T_11 = or(_stalls_T_10, flight_2[11]) node _stalls_T_12 = or(_stalls_T_11, flight_2[12]) node _stalls_T_13 = or(_stalls_T_12, flight_2[13]) node _stalls_T_14 = or(_stalls_T_13, flight_2[14]) node _stalls_T_15 = or(_stalls_T_14, flight_2[15]) node _stalls_T_16 = or(_stalls_T_15, flight_2[16]) node _stalls_T_17 = or(_stalls_T_16, flight_2[17]) node _stalls_T_18 = or(_stalls_T_17, flight_2[18]) node _stalls_T_19 = or(_stalls_T_18, flight_2[19]) node _stalls_T_20 = or(_stalls_T_19, flight_2[20]) node _stalls_T_21 = or(_stalls_T_20, flight_2[21]) node _stalls_T_22 = or(_stalls_T_21, flight_2[22]) node _stalls_T_23 = or(_stalls_T_22, flight_2[23]) node _stalls_T_24 = or(_stalls_T_23, flight_2[24]) node _stalls_T_25 = or(_stalls_T_24, flight_2[25]) node _stalls_T_26 = or(_stalls_T_25, flight_2[26]) node _stalls_T_27 = or(_stalls_T_26, flight_2[27]) node _stalls_T_28 = or(_stalls_T_27, flight_2[28]) node _stalls_T_29 = or(_stalls_T_28, flight_2[29]) node _stalls_T_30 = or(_stalls_T_29, flight_2[30]) node _stalls_T_31 = or(_stalls_T_30, flight_2[31]) node _stalls_T_32 = and(_stalls_T, _stalls_T_31) node _stalls_T_33 = neq(stalls_id, UInt<1>(0h1)) node _stalls_T_34 = or(a_noDomain_2, _stalls_T_33) node stalls_0 = and(_stalls_T_32, _stalls_T_34) node _stalls_a_sel_uncommonBits_T_1 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_1 = bits(_stalls_a_sel_uncommonBits_T_1, 4, 0) node _stalls_a_sel_T_5 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_6 = eq(_stalls_a_sel_T_5, UInt<1>(0h1)) node _stalls_a_sel_T_7 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_1) node _stalls_a_sel_T_8 = and(_stalls_a_sel_T_6, _stalls_a_sel_T_7) node _stalls_a_sel_T_9 = leq(stalls_a_sel_uncommonBits_1, UInt<5>(0h1f)) node stalls_a_sel_1 = and(_stalls_a_sel_T_8, _stalls_a_sel_T_9) node _stalls_id_T_4 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_5 = and(_stalls_id_T_4, stalls_a_sel_1) node _stalls_id_T_6 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_7 = and(_stalls_id_T_5, _stalls_id_T_6) reg stalls_id_1 : UInt<1>, clock when _stalls_id_T_7 : connect stalls_id_1, UInt<1>(0h1) node _stalls_T_35 = and(stalls_a_sel_1, a_first_2) node _stalls_T_36 = or(flight_2[32], flight_2[33]) node _stalls_T_37 = or(_stalls_T_36, flight_2[34]) node _stalls_T_38 = or(_stalls_T_37, flight_2[35]) node _stalls_T_39 = or(_stalls_T_38, flight_2[36]) node _stalls_T_40 = or(_stalls_T_39, flight_2[37]) node _stalls_T_41 = or(_stalls_T_40, flight_2[38]) node _stalls_T_42 = or(_stalls_T_41, flight_2[39]) node _stalls_T_43 = or(_stalls_T_42, flight_2[40]) node _stalls_T_44 = or(_stalls_T_43, flight_2[41]) node _stalls_T_45 = or(_stalls_T_44, flight_2[42]) node _stalls_T_46 = or(_stalls_T_45, flight_2[43]) node _stalls_T_47 = or(_stalls_T_46, flight_2[44]) node _stalls_T_48 = or(_stalls_T_47, flight_2[45]) node _stalls_T_49 = or(_stalls_T_48, flight_2[46]) node _stalls_T_50 = or(_stalls_T_49, flight_2[47]) node _stalls_T_51 = or(_stalls_T_50, flight_2[48]) node _stalls_T_52 = or(_stalls_T_51, flight_2[49]) node _stalls_T_53 = or(_stalls_T_52, flight_2[50]) node _stalls_T_54 = or(_stalls_T_53, flight_2[51]) node _stalls_T_55 = or(_stalls_T_54, flight_2[52]) node _stalls_T_56 = or(_stalls_T_55, flight_2[53]) node _stalls_T_57 = or(_stalls_T_56, flight_2[54]) node _stalls_T_58 = or(_stalls_T_57, flight_2[55]) node _stalls_T_59 = or(_stalls_T_58, flight_2[56]) node _stalls_T_60 = or(_stalls_T_59, flight_2[57]) node _stalls_T_61 = or(_stalls_T_60, flight_2[58]) node _stalls_T_62 = or(_stalls_T_61, flight_2[59]) node _stalls_T_63 = or(_stalls_T_62, flight_2[60]) node _stalls_T_64 = or(_stalls_T_63, flight_2[61]) node _stalls_T_65 = or(_stalls_T_64, flight_2[62]) node _stalls_T_66 = or(_stalls_T_65, flight_2[63]) node _stalls_T_67 = and(_stalls_T_35, _stalls_T_66) node _stalls_T_68 = neq(stalls_id_1, UInt<1>(0h1)) node _stalls_T_69 = or(a_noDomain_2, _stalls_T_68) node stalls_1 = and(_stalls_T_67, _stalls_T_69) node _stalls_a_sel_uncommonBits_T_2 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_2 = bits(_stalls_a_sel_uncommonBits_T_2, 4, 0) node _stalls_a_sel_T_10 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_11 = eq(_stalls_a_sel_T_10, UInt<2>(0h2)) node _stalls_a_sel_T_12 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_2) node _stalls_a_sel_T_13 = and(_stalls_a_sel_T_11, _stalls_a_sel_T_12) node _stalls_a_sel_T_14 = leq(stalls_a_sel_uncommonBits_2, UInt<5>(0h1f)) node stalls_a_sel_2 = and(_stalls_a_sel_T_13, _stalls_a_sel_T_14) node _stalls_id_T_8 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_9 = and(_stalls_id_T_8, stalls_a_sel_2) node _stalls_id_T_10 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_11 = and(_stalls_id_T_9, _stalls_id_T_10) reg stalls_id_2 : UInt<1>, clock when _stalls_id_T_11 : connect stalls_id_2, UInt<1>(0h1) node _stalls_T_70 = and(stalls_a_sel_2, a_first_2) node _stalls_T_71 = or(flight_2[64], flight_2[65]) node _stalls_T_72 = or(_stalls_T_71, flight_2[66]) node _stalls_T_73 = or(_stalls_T_72, flight_2[67]) node _stalls_T_74 = or(_stalls_T_73, flight_2[68]) node _stalls_T_75 = or(_stalls_T_74, flight_2[69]) node _stalls_T_76 = or(_stalls_T_75, flight_2[70]) node _stalls_T_77 = or(_stalls_T_76, flight_2[71]) node _stalls_T_78 = or(_stalls_T_77, flight_2[72]) node _stalls_T_79 = or(_stalls_T_78, flight_2[73]) node _stalls_T_80 = or(_stalls_T_79, flight_2[74]) node _stalls_T_81 = or(_stalls_T_80, flight_2[75]) node _stalls_T_82 = or(_stalls_T_81, flight_2[76]) node _stalls_T_83 = or(_stalls_T_82, flight_2[77]) node _stalls_T_84 = or(_stalls_T_83, flight_2[78]) node _stalls_T_85 = or(_stalls_T_84, flight_2[79]) node _stalls_T_86 = or(_stalls_T_85, flight_2[80]) node _stalls_T_87 = or(_stalls_T_86, flight_2[81]) node _stalls_T_88 = or(_stalls_T_87, flight_2[82]) node _stalls_T_89 = or(_stalls_T_88, flight_2[83]) node _stalls_T_90 = or(_stalls_T_89, flight_2[84]) node _stalls_T_91 = or(_stalls_T_90, flight_2[85]) node _stalls_T_92 = or(_stalls_T_91, flight_2[86]) node _stalls_T_93 = or(_stalls_T_92, flight_2[87]) node _stalls_T_94 = or(_stalls_T_93, flight_2[88]) node _stalls_T_95 = or(_stalls_T_94, flight_2[89]) node _stalls_T_96 = or(_stalls_T_95, flight_2[90]) node _stalls_T_97 = or(_stalls_T_96, flight_2[91]) node _stalls_T_98 = or(_stalls_T_97, flight_2[92]) node _stalls_T_99 = or(_stalls_T_98, flight_2[93]) node _stalls_T_100 = or(_stalls_T_99, flight_2[94]) node _stalls_T_101 = or(_stalls_T_100, flight_2[95]) node _stalls_T_102 = and(_stalls_T_70, _stalls_T_101) node _stalls_T_103 = neq(stalls_id_2, UInt<1>(0h1)) node _stalls_T_104 = or(a_noDomain_2, _stalls_T_103) node stalls_2 = and(_stalls_T_102, _stalls_T_104) node _stalls_a_sel_uncommonBits_T_3 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_3 = bits(_stalls_a_sel_uncommonBits_T_3, 4, 0) node _stalls_a_sel_T_15 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_16 = eq(_stalls_a_sel_T_15, UInt<2>(0h3)) node _stalls_a_sel_T_17 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_3) node _stalls_a_sel_T_18 = and(_stalls_a_sel_T_16, _stalls_a_sel_T_17) node _stalls_a_sel_T_19 = leq(stalls_a_sel_uncommonBits_3, UInt<5>(0h1f)) node stalls_a_sel_3 = and(_stalls_a_sel_T_18, _stalls_a_sel_T_19) node _stalls_id_T_12 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_13 = and(_stalls_id_T_12, stalls_a_sel_3) node _stalls_id_T_14 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_15 = and(_stalls_id_T_13, _stalls_id_T_14) reg stalls_id_3 : UInt<1>, clock when _stalls_id_T_15 : connect stalls_id_3, UInt<1>(0h1) node _stalls_T_105 = and(stalls_a_sel_3, a_first_2) node _stalls_T_106 = or(flight_2[96], flight_2[97]) node _stalls_T_107 = or(_stalls_T_106, flight_2[98]) node _stalls_T_108 = or(_stalls_T_107, flight_2[99]) node _stalls_T_109 = or(_stalls_T_108, flight_2[100]) node _stalls_T_110 = or(_stalls_T_109, flight_2[101]) node _stalls_T_111 = or(_stalls_T_110, flight_2[102]) node _stalls_T_112 = or(_stalls_T_111, flight_2[103]) node _stalls_T_113 = or(_stalls_T_112, flight_2[104]) node _stalls_T_114 = or(_stalls_T_113, flight_2[105]) node _stalls_T_115 = or(_stalls_T_114, flight_2[106]) node _stalls_T_116 = or(_stalls_T_115, flight_2[107]) node _stalls_T_117 = or(_stalls_T_116, flight_2[108]) node _stalls_T_118 = or(_stalls_T_117, flight_2[109]) node _stalls_T_119 = or(_stalls_T_118, flight_2[110]) node _stalls_T_120 = or(_stalls_T_119, flight_2[111]) node _stalls_T_121 = or(_stalls_T_120, flight_2[112]) node _stalls_T_122 = or(_stalls_T_121, flight_2[113]) node _stalls_T_123 = or(_stalls_T_122, flight_2[114]) node _stalls_T_124 = or(_stalls_T_123, flight_2[115]) node _stalls_T_125 = or(_stalls_T_124, flight_2[116]) node _stalls_T_126 = or(_stalls_T_125, flight_2[117]) node _stalls_T_127 = or(_stalls_T_126, flight_2[118]) node _stalls_T_128 = or(_stalls_T_127, flight_2[119]) node _stalls_T_129 = or(_stalls_T_128, flight_2[120]) node _stalls_T_130 = or(_stalls_T_129, flight_2[121]) node _stalls_T_131 = or(_stalls_T_130, flight_2[122]) node _stalls_T_132 = or(_stalls_T_131, flight_2[123]) node _stalls_T_133 = or(_stalls_T_132, flight_2[124]) node _stalls_T_134 = or(_stalls_T_133, flight_2[125]) node _stalls_T_135 = or(_stalls_T_134, flight_2[126]) node _stalls_T_136 = or(_stalls_T_135, flight_2[127]) node _stalls_T_137 = and(_stalls_T_105, _stalls_T_136) node _stalls_T_138 = neq(stalls_id_3, UInt<1>(0h1)) node _stalls_T_139 = or(a_noDomain_2, _stalls_T_138) node stalls_3 = and(_stalls_T_137, _stalls_T_139) node _stalls_a_sel_uncommonBits_T_4 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_4 = bits(_stalls_a_sel_uncommonBits_T_4, 4, 0) node _stalls_a_sel_T_20 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_21 = eq(_stalls_a_sel_T_20, UInt<3>(0h4)) node _stalls_a_sel_T_22 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_4) node _stalls_a_sel_T_23 = and(_stalls_a_sel_T_21, _stalls_a_sel_T_22) node _stalls_a_sel_T_24 = leq(stalls_a_sel_uncommonBits_4, UInt<5>(0h1f)) node stalls_a_sel_4 = and(_stalls_a_sel_T_23, _stalls_a_sel_T_24) node _stalls_id_T_16 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_17 = and(_stalls_id_T_16, stalls_a_sel_4) node _stalls_id_T_18 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_19 = and(_stalls_id_T_17, _stalls_id_T_18) reg stalls_id_4 : UInt<1>, clock when _stalls_id_T_19 : connect stalls_id_4, UInt<1>(0h1) node _stalls_T_140 = and(stalls_a_sel_4, a_first_2) node _stalls_T_141 = or(flight_2[128], flight_2[129]) node _stalls_T_142 = or(_stalls_T_141, flight_2[130]) node _stalls_T_143 = or(_stalls_T_142, flight_2[131]) node _stalls_T_144 = or(_stalls_T_143, flight_2[132]) node _stalls_T_145 = or(_stalls_T_144, flight_2[133]) node _stalls_T_146 = or(_stalls_T_145, flight_2[134]) node _stalls_T_147 = or(_stalls_T_146, flight_2[135]) node _stalls_T_148 = or(_stalls_T_147, flight_2[136]) node _stalls_T_149 = or(_stalls_T_148, flight_2[137]) node _stalls_T_150 = or(_stalls_T_149, flight_2[138]) node _stalls_T_151 = or(_stalls_T_150, flight_2[139]) node _stalls_T_152 = or(_stalls_T_151, flight_2[140]) node _stalls_T_153 = or(_stalls_T_152, flight_2[141]) node _stalls_T_154 = or(_stalls_T_153, flight_2[142]) node _stalls_T_155 = or(_stalls_T_154, flight_2[143]) node _stalls_T_156 = or(_stalls_T_155, flight_2[144]) node _stalls_T_157 = or(_stalls_T_156, flight_2[145]) node _stalls_T_158 = or(_stalls_T_157, flight_2[146]) node _stalls_T_159 = or(_stalls_T_158, flight_2[147]) node _stalls_T_160 = or(_stalls_T_159, flight_2[148]) node _stalls_T_161 = or(_stalls_T_160, flight_2[149]) node _stalls_T_162 = or(_stalls_T_161, flight_2[150]) node _stalls_T_163 = or(_stalls_T_162, flight_2[151]) node _stalls_T_164 = or(_stalls_T_163, flight_2[152]) node _stalls_T_165 = or(_stalls_T_164, flight_2[153]) node _stalls_T_166 = or(_stalls_T_165, flight_2[154]) node _stalls_T_167 = or(_stalls_T_166, flight_2[155]) node _stalls_T_168 = or(_stalls_T_167, flight_2[156]) node _stalls_T_169 = or(_stalls_T_168, flight_2[157]) node _stalls_T_170 = or(_stalls_T_169, flight_2[158]) node _stalls_T_171 = or(_stalls_T_170, flight_2[159]) node _stalls_T_172 = and(_stalls_T_140, _stalls_T_171) node _stalls_T_173 = neq(stalls_id_4, UInt<1>(0h1)) node _stalls_T_174 = or(a_noDomain_2, _stalls_T_173) node stalls_4 = and(_stalls_T_172, _stalls_T_174) node _stalls_a_sel_uncommonBits_T_5 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_5 = bits(_stalls_a_sel_uncommonBits_T_5, 4, 0) node _stalls_a_sel_T_25 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_26 = eq(_stalls_a_sel_T_25, UInt<3>(0h5)) node _stalls_a_sel_T_27 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_5) node _stalls_a_sel_T_28 = and(_stalls_a_sel_T_26, _stalls_a_sel_T_27) node _stalls_a_sel_T_29 = leq(stalls_a_sel_uncommonBits_5, UInt<5>(0h1f)) node stalls_a_sel_5 = and(_stalls_a_sel_T_28, _stalls_a_sel_T_29) node _stalls_id_T_20 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_21 = and(_stalls_id_T_20, stalls_a_sel_5) node _stalls_id_T_22 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_23 = and(_stalls_id_T_21, _stalls_id_T_22) reg stalls_id_5 : UInt<1>, clock when _stalls_id_T_23 : connect stalls_id_5, UInt<1>(0h1) node _stalls_T_175 = and(stalls_a_sel_5, a_first_2) node _stalls_T_176 = or(flight_2[160], flight_2[161]) node _stalls_T_177 = or(_stalls_T_176, flight_2[162]) node _stalls_T_178 = or(_stalls_T_177, flight_2[163]) node _stalls_T_179 = or(_stalls_T_178, flight_2[164]) node _stalls_T_180 = or(_stalls_T_179, flight_2[165]) node _stalls_T_181 = or(_stalls_T_180, flight_2[166]) node _stalls_T_182 = or(_stalls_T_181, flight_2[167]) node _stalls_T_183 = or(_stalls_T_182, flight_2[168]) node _stalls_T_184 = or(_stalls_T_183, flight_2[169]) node _stalls_T_185 = or(_stalls_T_184, flight_2[170]) node _stalls_T_186 = or(_stalls_T_185, flight_2[171]) node _stalls_T_187 = or(_stalls_T_186, flight_2[172]) node _stalls_T_188 = or(_stalls_T_187, flight_2[173]) node _stalls_T_189 = or(_stalls_T_188, flight_2[174]) node _stalls_T_190 = or(_stalls_T_189, flight_2[175]) node _stalls_T_191 = or(_stalls_T_190, flight_2[176]) node _stalls_T_192 = or(_stalls_T_191, flight_2[177]) node _stalls_T_193 = or(_stalls_T_192, flight_2[178]) node _stalls_T_194 = or(_stalls_T_193, flight_2[179]) node _stalls_T_195 = or(_stalls_T_194, flight_2[180]) node _stalls_T_196 = or(_stalls_T_195, flight_2[181]) node _stalls_T_197 = or(_stalls_T_196, flight_2[182]) node _stalls_T_198 = or(_stalls_T_197, flight_2[183]) node _stalls_T_199 = or(_stalls_T_198, flight_2[184]) node _stalls_T_200 = or(_stalls_T_199, flight_2[185]) node _stalls_T_201 = or(_stalls_T_200, flight_2[186]) node _stalls_T_202 = or(_stalls_T_201, flight_2[187]) node _stalls_T_203 = or(_stalls_T_202, flight_2[188]) node _stalls_T_204 = or(_stalls_T_203, flight_2[189]) node _stalls_T_205 = or(_stalls_T_204, flight_2[190]) node _stalls_T_206 = or(_stalls_T_205, flight_2[191]) node _stalls_T_207 = and(_stalls_T_175, _stalls_T_206) node _stalls_T_208 = neq(stalls_id_5, UInt<1>(0h1)) node _stalls_T_209 = or(a_noDomain_2, _stalls_T_208) node stalls_5 = and(_stalls_T_207, _stalls_T_209) node _stalls_a_sel_uncommonBits_T_6 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_6 = bits(_stalls_a_sel_uncommonBits_T_6, 4, 0) node _stalls_a_sel_T_30 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_31 = eq(_stalls_a_sel_T_30, UInt<3>(0h6)) node _stalls_a_sel_T_32 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_6) node _stalls_a_sel_T_33 = and(_stalls_a_sel_T_31, _stalls_a_sel_T_32) node _stalls_a_sel_T_34 = leq(stalls_a_sel_uncommonBits_6, UInt<5>(0h1f)) node stalls_a_sel_6 = and(_stalls_a_sel_T_33, _stalls_a_sel_T_34) node _stalls_id_T_24 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_25 = and(_stalls_id_T_24, stalls_a_sel_6) node _stalls_id_T_26 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_27 = and(_stalls_id_T_25, _stalls_id_T_26) reg stalls_id_6 : UInt<1>, clock when _stalls_id_T_27 : connect stalls_id_6, UInt<1>(0h1) node _stalls_T_210 = and(stalls_a_sel_6, a_first_2) node _stalls_T_211 = or(flight_2[192], flight_2[193]) node _stalls_T_212 = or(_stalls_T_211, flight_2[194]) node _stalls_T_213 = or(_stalls_T_212, flight_2[195]) node _stalls_T_214 = or(_stalls_T_213, flight_2[196]) node _stalls_T_215 = or(_stalls_T_214, flight_2[197]) node _stalls_T_216 = or(_stalls_T_215, flight_2[198]) node _stalls_T_217 = or(_stalls_T_216, flight_2[199]) node _stalls_T_218 = or(_stalls_T_217, flight_2[200]) node _stalls_T_219 = or(_stalls_T_218, flight_2[201]) node _stalls_T_220 = or(_stalls_T_219, flight_2[202]) node _stalls_T_221 = or(_stalls_T_220, flight_2[203]) node _stalls_T_222 = or(_stalls_T_221, flight_2[204]) node _stalls_T_223 = or(_stalls_T_222, flight_2[205]) node _stalls_T_224 = or(_stalls_T_223, flight_2[206]) node _stalls_T_225 = or(_stalls_T_224, flight_2[207]) node _stalls_T_226 = or(_stalls_T_225, flight_2[208]) node _stalls_T_227 = or(_stalls_T_226, flight_2[209]) node _stalls_T_228 = or(_stalls_T_227, flight_2[210]) node _stalls_T_229 = or(_stalls_T_228, flight_2[211]) node _stalls_T_230 = or(_stalls_T_229, flight_2[212]) node _stalls_T_231 = or(_stalls_T_230, flight_2[213]) node _stalls_T_232 = or(_stalls_T_231, flight_2[214]) node _stalls_T_233 = or(_stalls_T_232, flight_2[215]) node _stalls_T_234 = or(_stalls_T_233, flight_2[216]) node _stalls_T_235 = or(_stalls_T_234, flight_2[217]) node _stalls_T_236 = or(_stalls_T_235, flight_2[218]) node _stalls_T_237 = or(_stalls_T_236, flight_2[219]) node _stalls_T_238 = or(_stalls_T_237, flight_2[220]) node _stalls_T_239 = or(_stalls_T_238, flight_2[221]) node _stalls_T_240 = or(_stalls_T_239, flight_2[222]) node _stalls_T_241 = or(_stalls_T_240, flight_2[223]) node _stalls_T_242 = and(_stalls_T_210, _stalls_T_241) node _stalls_T_243 = neq(stalls_id_6, UInt<1>(0h1)) node _stalls_T_244 = or(a_noDomain_2, _stalls_T_243) node stalls_6 = and(_stalls_T_242, _stalls_T_244) node _stalls_a_sel_uncommonBits_T_7 = or(anonIn_2.a.bits.source, UInt<5>(0h0)) node stalls_a_sel_uncommonBits_7 = bits(_stalls_a_sel_uncommonBits_T_7, 4, 0) node _stalls_a_sel_T_35 = shr(anonIn_2.a.bits.source, 5) node _stalls_a_sel_T_36 = eq(_stalls_a_sel_T_35, UInt<3>(0h7)) node _stalls_a_sel_T_37 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_7) node _stalls_a_sel_T_38 = and(_stalls_a_sel_T_36, _stalls_a_sel_T_37) node _stalls_a_sel_T_39 = leq(stalls_a_sel_uncommonBits_7, UInt<5>(0h1f)) node stalls_a_sel_7 = and(_stalls_a_sel_T_38, _stalls_a_sel_T_39) node _stalls_id_T_28 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _stalls_id_T_29 = and(_stalls_id_T_28, stalls_a_sel_7) node _stalls_id_T_30 = eq(a_notFIFO_2, UInt<1>(0h0)) node _stalls_id_T_31 = and(_stalls_id_T_29, _stalls_id_T_30) reg stalls_id_7 : UInt<1>, clock when _stalls_id_T_31 : connect stalls_id_7, UInt<1>(0h1) node _stalls_T_245 = and(stalls_a_sel_7, a_first_2) node _stalls_T_246 = or(flight_2[224], flight_2[225]) node _stalls_T_247 = or(_stalls_T_246, flight_2[226]) node _stalls_T_248 = or(_stalls_T_247, flight_2[227]) node _stalls_T_249 = or(_stalls_T_248, flight_2[228]) node _stalls_T_250 = or(_stalls_T_249, flight_2[229]) node _stalls_T_251 = or(_stalls_T_250, flight_2[230]) node _stalls_T_252 = or(_stalls_T_251, flight_2[231]) node _stalls_T_253 = or(_stalls_T_252, flight_2[232]) node _stalls_T_254 = or(_stalls_T_253, flight_2[233]) node _stalls_T_255 = or(_stalls_T_254, flight_2[234]) node _stalls_T_256 = or(_stalls_T_255, flight_2[235]) node _stalls_T_257 = or(_stalls_T_256, flight_2[236]) node _stalls_T_258 = or(_stalls_T_257, flight_2[237]) node _stalls_T_259 = or(_stalls_T_258, flight_2[238]) node _stalls_T_260 = or(_stalls_T_259, flight_2[239]) node _stalls_T_261 = or(_stalls_T_260, flight_2[240]) node _stalls_T_262 = or(_stalls_T_261, flight_2[241]) node _stalls_T_263 = or(_stalls_T_262, flight_2[242]) node _stalls_T_264 = or(_stalls_T_263, flight_2[243]) node _stalls_T_265 = or(_stalls_T_264, flight_2[244]) node _stalls_T_266 = or(_stalls_T_265, flight_2[245]) node _stalls_T_267 = or(_stalls_T_266, flight_2[246]) node _stalls_T_268 = or(_stalls_T_267, flight_2[247]) node _stalls_T_269 = or(_stalls_T_268, flight_2[248]) node _stalls_T_270 = or(_stalls_T_269, flight_2[249]) node _stalls_T_271 = or(_stalls_T_270, flight_2[250]) node _stalls_T_272 = or(_stalls_T_271, flight_2[251]) node _stalls_T_273 = or(_stalls_T_272, flight_2[252]) node _stalls_T_274 = or(_stalls_T_273, flight_2[253]) node _stalls_T_275 = or(_stalls_T_274, flight_2[254]) node _stalls_T_276 = or(_stalls_T_275, flight_2[255]) node _stalls_T_277 = and(_stalls_T_245, _stalls_T_276) node _stalls_T_278 = neq(stalls_id_7, UInt<1>(0h1)) node _stalls_T_279 = or(a_noDomain_2, _stalls_T_278) node stalls_7 = and(_stalls_T_277, _stalls_T_279) node _stall_T = or(UInt<1>(0h0), stalls_0) node _stall_T_1 = or(_stall_T, stalls_1) node _stall_T_2 = or(_stall_T_1, stalls_2) node _stall_T_3 = or(_stall_T_2, stalls_3) node _stall_T_4 = or(_stall_T_3, stalls_4) node _stall_T_5 = or(_stall_T_4, stalls_5) node _stall_T_6 = or(_stall_T_5, stalls_6) node stall = or(_stall_T_6, stalls_7) connect x1_anonOut_1.a, anonIn_2.a connect anonIn_2.d, x1_anonOut_1.d node _anonOut_a_valid_T_6 = eq(stall, UInt<1>(0h0)) node _anonOut_a_valid_T_7 = or(a_notFIFO_2, _anonOut_a_valid_T_6) node _anonOut_a_valid_T_8 = and(anonIn_2.a.valid, _anonOut_a_valid_T_7) connect x1_anonOut_1.a.valid, _anonOut_a_valid_T_8 node _anonIn_a_ready_T_6 = eq(stall, UInt<1>(0h0)) node _anonIn_a_ready_T_7 = or(a_notFIFO_2, _anonIn_a_ready_T_6) node _anonIn_a_ready_T_8 = and(x1_anonOut_1.a.ready, _anonIn_a_ready_T_7) connect anonIn_2.a.ready, _anonIn_a_ready_T_8 wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.mask, UInt<8>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<2>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_16.bits.sink, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready connect _WIRE_17.ready, UInt<1>(0h1) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.mask, UInt<8>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.ready, UInt<1>(0h1) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_22.bits.sink, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.valid, UInt<1>(0h0) node _T_50 = and(anonIn_2.a.valid, stall) regreset SourceIdFIFOed_2 : UInt<256>, clock, reset, UInt<256>(0h0) wire SourceIdSet_2 : UInt<256> connect SourceIdSet_2, UInt<256>(0h0) wire SourceIdClear_2 : UInt<256> connect SourceIdClear_2, UInt<256>(0h0) node _T_51 = and(anonIn_2.a.ready, anonIn_2.a.valid) node _T_52 = and(a_first_2, _T_51) node _T_53 = eq(a_notFIFO_2, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : node _SourceIdSet_T_2 = dshl(UInt<1>(0h1), anonIn_2.a.bits.source) connect SourceIdSet_2, _SourceIdSet_T_2 node _T_55 = and(anonIn_2.d.ready, anonIn_2.d.valid) node _T_56 = and(d_first_2, _T_55) when _T_56 : node _SourceIdClear_T_2 = dshl(UInt<1>(0h1), anonIn_2.d.bits.source) connect SourceIdClear_2, _SourceIdClear_T_2 node _SourceIdFIFOed_T_2 = or(SourceIdFIFOed_2, SourceIdSet_2) connect SourceIdFIFOed_2, _SourceIdFIFOed_T_2 node _allIDs_FIFOed_T_2 = mux(UInt<1>(0h1), UInt<256>(0hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff), UInt<256>(0h0)) node allIDs_FIFOed_2 = eq(SourceIdFIFOed_2, _allIDs_FIFOed_T_2) node _T_57 = or(flight_2[0], flight_2[1]) node _T_58 = or(_T_57, flight_2[2]) node _T_59 = or(_T_58, flight_2[3]) node _T_60 = or(_T_59, flight_2[4]) node _T_61 = or(_T_60, flight_2[5]) node _T_62 = or(_T_61, flight_2[6]) node _T_63 = or(_T_62, flight_2[7]) node _T_64 = or(_T_63, flight_2[8]) node _T_65 = or(_T_64, flight_2[9]) node _T_66 = or(_T_65, flight_2[10]) node _T_67 = or(_T_66, flight_2[11]) node _T_68 = or(_T_67, flight_2[12]) node _T_69 = or(_T_68, flight_2[13]) node _T_70 = or(_T_69, flight_2[14]) node _T_71 = or(_T_70, flight_2[15]) node _T_72 = or(_T_71, flight_2[16]) node _T_73 = or(_T_72, flight_2[17]) node _T_74 = or(_T_73, flight_2[18]) node _T_75 = or(_T_74, flight_2[19]) node _T_76 = or(_T_75, flight_2[20]) node _T_77 = or(_T_76, flight_2[21]) node _T_78 = or(_T_77, flight_2[22]) node _T_79 = or(_T_78, flight_2[23]) node _T_80 = or(_T_79, flight_2[24]) node _T_81 = or(_T_80, flight_2[25]) node _T_82 = or(_T_81, flight_2[26]) node _T_83 = or(_T_82, flight_2[27]) node _T_84 = or(_T_83, flight_2[28]) node _T_85 = or(_T_84, flight_2[29]) node _T_86 = or(_T_85, flight_2[30]) node _T_87 = or(_T_86, flight_2[31]) node _T_88 = or(_T_87, flight_2[32]) node _T_89 = or(_T_88, flight_2[33]) node _T_90 = or(_T_89, flight_2[34]) node _T_91 = or(_T_90, flight_2[35]) node _T_92 = or(_T_91, flight_2[36]) node _T_93 = or(_T_92, flight_2[37]) node _T_94 = or(_T_93, flight_2[38]) node _T_95 = or(_T_94, flight_2[39]) node _T_96 = or(_T_95, flight_2[40]) node _T_97 = or(_T_96, flight_2[41]) node _T_98 = or(_T_97, flight_2[42]) node _T_99 = or(_T_98, flight_2[43]) node _T_100 = or(_T_99, flight_2[44]) node _T_101 = or(_T_100, flight_2[45]) node _T_102 = or(_T_101, flight_2[46]) node _T_103 = or(_T_102, flight_2[47]) node _T_104 = or(_T_103, flight_2[48]) node _T_105 = or(_T_104, flight_2[49]) node _T_106 = or(_T_105, flight_2[50]) node _T_107 = or(_T_106, flight_2[51]) node _T_108 = or(_T_107, flight_2[52]) node _T_109 = or(_T_108, flight_2[53]) node _T_110 = or(_T_109, flight_2[54]) node _T_111 = or(_T_110, flight_2[55]) node _T_112 = or(_T_111, flight_2[56]) node _T_113 = or(_T_112, flight_2[57]) node _T_114 = or(_T_113, flight_2[58]) node _T_115 = or(_T_114, flight_2[59]) node _T_116 = or(_T_115, flight_2[60]) node _T_117 = or(_T_116, flight_2[61]) node _T_118 = or(_T_117, flight_2[62]) node _T_119 = or(_T_118, flight_2[63]) node _T_120 = or(_T_119, flight_2[64]) node _T_121 = or(_T_120, flight_2[65]) node _T_122 = or(_T_121, flight_2[66]) node _T_123 = or(_T_122, flight_2[67]) node _T_124 = or(_T_123, flight_2[68]) node _T_125 = or(_T_124, flight_2[69]) node _T_126 = or(_T_125, flight_2[70]) node _T_127 = or(_T_126, flight_2[71]) node _T_128 = or(_T_127, flight_2[72]) node _T_129 = or(_T_128, flight_2[73]) node _T_130 = or(_T_129, flight_2[74]) node _T_131 = or(_T_130, flight_2[75]) node _T_132 = or(_T_131, flight_2[76]) node _T_133 = or(_T_132, flight_2[77]) node _T_134 = or(_T_133, flight_2[78]) node _T_135 = or(_T_134, flight_2[79]) node _T_136 = or(_T_135, flight_2[80]) node _T_137 = or(_T_136, flight_2[81]) node _T_138 = or(_T_137, flight_2[82]) node _T_139 = or(_T_138, flight_2[83]) node _T_140 = or(_T_139, flight_2[84]) node _T_141 = or(_T_140, flight_2[85]) node _T_142 = or(_T_141, flight_2[86]) node _T_143 = or(_T_142, flight_2[87]) node _T_144 = or(_T_143, flight_2[88]) node _T_145 = or(_T_144, flight_2[89]) node _T_146 = or(_T_145, flight_2[90]) node _T_147 = or(_T_146, flight_2[91]) node _T_148 = or(_T_147, flight_2[92]) node _T_149 = or(_T_148, flight_2[93]) node _T_150 = or(_T_149, flight_2[94]) node _T_151 = or(_T_150, flight_2[95]) node _T_152 = or(_T_151, flight_2[96]) node _T_153 = or(_T_152, flight_2[97]) node _T_154 = or(_T_153, flight_2[98]) node _T_155 = or(_T_154, flight_2[99]) node _T_156 = or(_T_155, flight_2[100]) node _T_157 = or(_T_156, flight_2[101]) node _T_158 = or(_T_157, flight_2[102]) node _T_159 = or(_T_158, flight_2[103]) node _T_160 = or(_T_159, flight_2[104]) node _T_161 = or(_T_160, flight_2[105]) node _T_162 = or(_T_161, flight_2[106]) node _T_163 = or(_T_162, flight_2[107]) node _T_164 = or(_T_163, flight_2[108]) node _T_165 = or(_T_164, flight_2[109]) node _T_166 = or(_T_165, flight_2[110]) node _T_167 = or(_T_166, flight_2[111]) node _T_168 = or(_T_167, flight_2[112]) node _T_169 = or(_T_168, flight_2[113]) node _T_170 = or(_T_169, flight_2[114]) node _T_171 = or(_T_170, flight_2[115]) node _T_172 = or(_T_171, flight_2[116]) node _T_173 = or(_T_172, flight_2[117]) node _T_174 = or(_T_173, flight_2[118]) node _T_175 = or(_T_174, flight_2[119]) node _T_176 = or(_T_175, flight_2[120]) node _T_177 = or(_T_176, flight_2[121]) node _T_178 = or(_T_177, flight_2[122]) node _T_179 = or(_T_178, flight_2[123]) node _T_180 = or(_T_179, flight_2[124]) node _T_181 = or(_T_180, flight_2[125]) node _T_182 = or(_T_181, flight_2[126]) node _T_183 = or(_T_182, flight_2[127]) node _T_184 = or(_T_183, flight_2[128]) node _T_185 = or(_T_184, flight_2[129]) node _T_186 = or(_T_185, flight_2[130]) node _T_187 = or(_T_186, flight_2[131]) node _T_188 = or(_T_187, flight_2[132]) node _T_189 = or(_T_188, flight_2[133]) node _T_190 = or(_T_189, flight_2[134]) node _T_191 = or(_T_190, flight_2[135]) node _T_192 = or(_T_191, flight_2[136]) node _T_193 = or(_T_192, flight_2[137]) node _T_194 = or(_T_193, flight_2[138]) node _T_195 = or(_T_194, flight_2[139]) node _T_196 = or(_T_195, flight_2[140]) node _T_197 = or(_T_196, flight_2[141]) node _T_198 = or(_T_197, flight_2[142]) node _T_199 = or(_T_198, flight_2[143]) node _T_200 = or(_T_199, flight_2[144]) node _T_201 = or(_T_200, flight_2[145]) node _T_202 = or(_T_201, flight_2[146]) node _T_203 = or(_T_202, flight_2[147]) node _T_204 = or(_T_203, flight_2[148]) node _T_205 = or(_T_204, flight_2[149]) node _T_206 = or(_T_205, flight_2[150]) node _T_207 = or(_T_206, flight_2[151]) node _T_208 = or(_T_207, flight_2[152]) node _T_209 = or(_T_208, flight_2[153]) node _T_210 = or(_T_209, flight_2[154]) node _T_211 = or(_T_210, flight_2[155]) node _T_212 = or(_T_211, flight_2[156]) node _T_213 = or(_T_212, flight_2[157]) node _T_214 = or(_T_213, flight_2[158]) node _T_215 = or(_T_214, flight_2[159]) node _T_216 = or(_T_215, flight_2[160]) node _T_217 = or(_T_216, flight_2[161]) node _T_218 = or(_T_217, flight_2[162]) node _T_219 = or(_T_218, flight_2[163]) node _T_220 = or(_T_219, flight_2[164]) node _T_221 = or(_T_220, flight_2[165]) node _T_222 = or(_T_221, flight_2[166]) node _T_223 = or(_T_222, flight_2[167]) node _T_224 = or(_T_223, flight_2[168]) node _T_225 = or(_T_224, flight_2[169]) node _T_226 = or(_T_225, flight_2[170]) node _T_227 = or(_T_226, flight_2[171]) node _T_228 = or(_T_227, flight_2[172]) node _T_229 = or(_T_228, flight_2[173]) node _T_230 = or(_T_229, flight_2[174]) node _T_231 = or(_T_230, flight_2[175]) node _T_232 = or(_T_231, flight_2[176]) node _T_233 = or(_T_232, flight_2[177]) node _T_234 = or(_T_233, flight_2[178]) node _T_235 = or(_T_234, flight_2[179]) node _T_236 = or(_T_235, flight_2[180]) node _T_237 = or(_T_236, flight_2[181]) node _T_238 = or(_T_237, flight_2[182]) node _T_239 = or(_T_238, flight_2[183]) node _T_240 = or(_T_239, flight_2[184]) node _T_241 = or(_T_240, flight_2[185]) node _T_242 = or(_T_241, flight_2[186]) node _T_243 = or(_T_242, flight_2[187]) node _T_244 = or(_T_243, flight_2[188]) node _T_245 = or(_T_244, flight_2[189]) node _T_246 = or(_T_245, flight_2[190]) node _T_247 = or(_T_246, flight_2[191]) node _T_248 = or(_T_247, flight_2[192]) node _T_249 = or(_T_248, flight_2[193]) node _T_250 = or(_T_249, flight_2[194]) node _T_251 = or(_T_250, flight_2[195]) node _T_252 = or(_T_251, flight_2[196]) node _T_253 = or(_T_252, flight_2[197]) node _T_254 = or(_T_253, flight_2[198]) node _T_255 = or(_T_254, flight_2[199]) node _T_256 = or(_T_255, flight_2[200]) node _T_257 = or(_T_256, flight_2[201]) node _T_258 = or(_T_257, flight_2[202]) node _T_259 = or(_T_258, flight_2[203]) node _T_260 = or(_T_259, flight_2[204]) node _T_261 = or(_T_260, flight_2[205]) node _T_262 = or(_T_261, flight_2[206]) node _T_263 = or(_T_262, flight_2[207]) node _T_264 = or(_T_263, flight_2[208]) node _T_265 = or(_T_264, flight_2[209]) node _T_266 = or(_T_265, flight_2[210]) node _T_267 = or(_T_266, flight_2[211]) node _T_268 = or(_T_267, flight_2[212]) node _T_269 = or(_T_268, flight_2[213]) node _T_270 = or(_T_269, flight_2[214]) node _T_271 = or(_T_270, flight_2[215]) node _T_272 = or(_T_271, flight_2[216]) node _T_273 = or(_T_272, flight_2[217]) node _T_274 = or(_T_273, flight_2[218]) node _T_275 = or(_T_274, flight_2[219]) node _T_276 = or(_T_275, flight_2[220]) node _T_277 = or(_T_276, flight_2[221]) node _T_278 = or(_T_277, flight_2[222]) node _T_279 = or(_T_278, flight_2[223]) node _T_280 = or(_T_279, flight_2[224]) node _T_281 = or(_T_280, flight_2[225]) node _T_282 = or(_T_281, flight_2[226]) node _T_283 = or(_T_282, flight_2[227]) node _T_284 = or(_T_283, flight_2[228]) node _T_285 = or(_T_284, flight_2[229]) node _T_286 = or(_T_285, flight_2[230]) node _T_287 = or(_T_286, flight_2[231]) node _T_288 = or(_T_287, flight_2[232]) node _T_289 = or(_T_288, flight_2[233]) node _T_290 = or(_T_289, flight_2[234]) node _T_291 = or(_T_290, flight_2[235]) node _T_292 = or(_T_291, flight_2[236]) node _T_293 = or(_T_292, flight_2[237]) node _T_294 = or(_T_293, flight_2[238]) node _T_295 = or(_T_294, flight_2[239]) node _T_296 = or(_T_295, flight_2[240]) node _T_297 = or(_T_296, flight_2[241]) node _T_298 = or(_T_297, flight_2[242]) node _T_299 = or(_T_298, flight_2[243]) node _T_300 = or(_T_299, flight_2[244]) node _T_301 = or(_T_300, flight_2[245]) node _T_302 = or(_T_301, flight_2[246]) node _T_303 = or(_T_302, flight_2[247]) node _T_304 = or(_T_303, flight_2[248]) node _T_305 = or(_T_304, flight_2[249]) node _T_306 = or(_T_305, flight_2[250]) node _T_307 = or(_T_306, flight_2[251]) node _T_308 = or(_T_307, flight_2[252]) node _T_309 = or(_T_308, flight_2[253]) node _T_310 = or(_T_309, flight_2[254]) node _T_311 = or(_T_310, flight_2[255]) node _T_312 = eq(_T_311, UInt<1>(0h0)) node _T_313 = gt(SourceIdSet_2, UInt<1>(0h0)) node _T_314 = gt(SourceIdClear_2, UInt<1>(0h0))
module TLFIFOFixer( // @[FIFOFixer.scala:50:9] input clock, // @[FIFOFixer.scala:50:9] input reset, // @[FIFOFixer.scala:50:9] output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLMonitor_3 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_anon_out_0_a_ready), .io_in_a_valid (auto_anon_in_0_a_valid), .io_in_a_bits_opcode (auto_anon_in_0_a_bits_opcode), .io_in_a_bits_param (auto_anon_in_0_a_bits_param), .io_in_a_bits_size (auto_anon_in_0_a_bits_size), .io_in_a_bits_source (auto_anon_in_0_a_bits_source), .io_in_a_bits_address (auto_anon_in_0_a_bits_address), .io_in_a_bits_mask (auto_anon_in_0_a_bits_mask), .io_in_a_bits_corrupt (auto_anon_in_0_a_bits_corrupt), .io_in_d_ready (auto_anon_in_0_d_ready), .io_in_d_valid (auto_anon_out_0_d_valid), .io_in_d_bits_opcode (auto_anon_out_0_d_bits_opcode), .io_in_d_bits_param (auto_anon_out_0_d_bits_param), .io_in_d_bits_size (auto_anon_out_0_d_bits_size), .io_in_d_bits_source (auto_anon_out_0_d_bits_source), .io_in_d_bits_sink (auto_anon_out_0_d_bits_sink), .io_in_d_bits_denied (auto_anon_out_0_d_bits_denied), .io_in_d_bits_corrupt (auto_anon_out_0_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_4 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_anon_out_1_a_ready), .io_in_a_valid (auto_anon_in_1_a_valid), .io_in_a_bits_opcode (auto_anon_in_1_a_bits_opcode), .io_in_a_bits_param (auto_anon_in_1_a_bits_param), .io_in_a_bits_size (auto_anon_in_1_a_bits_size), .io_in_a_bits_source (auto_anon_in_1_a_bits_source), .io_in_a_bits_address (auto_anon_in_1_a_bits_address), .io_in_a_bits_mask (auto_anon_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_anon_in_1_a_bits_corrupt), .io_in_b_ready (auto_anon_in_1_b_ready), .io_in_b_valid (auto_anon_out_1_b_valid), .io_in_b_bits_param (auto_anon_out_1_b_bits_param), .io_in_b_bits_address (auto_anon_out_1_b_bits_address), .io_in_c_ready (auto_anon_out_1_c_ready), .io_in_c_valid (auto_anon_in_1_c_valid), .io_in_c_bits_opcode (auto_anon_in_1_c_bits_opcode), .io_in_c_bits_param (auto_anon_in_1_c_bits_param), .io_in_c_bits_size (auto_anon_in_1_c_bits_size), .io_in_c_bits_source (auto_anon_in_1_c_bits_source), .io_in_c_bits_address (auto_anon_in_1_c_bits_address), .io_in_c_bits_corrupt (auto_anon_in_1_c_bits_corrupt), .io_in_d_ready (auto_anon_in_1_d_ready), .io_in_d_valid (auto_anon_out_1_d_valid), .io_in_d_bits_opcode (auto_anon_out_1_d_bits_opcode), .io_in_d_bits_param (auto_anon_out_1_d_bits_param), .io_in_d_bits_size (auto_anon_out_1_d_bits_size), .io_in_d_bits_source (auto_anon_out_1_d_bits_source), .io_in_d_bits_sink (auto_anon_out_1_d_bits_sink), .io_in_d_bits_denied (auto_anon_out_1_d_bits_denied), .io_in_d_bits_corrupt (auto_anon_out_1_d_bits_corrupt), .io_in_e_valid (auto_anon_in_1_e_valid), .io_in_e_bits_sink (auto_anon_in_1_e_bits_sink) ); // @[Nodes.scala:27:25] TLMonitor_5 monitor_2 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_anon_out_2_a_ready), .io_in_a_valid (auto_anon_in_2_a_valid), .io_in_a_bits_opcode (auto_anon_in_2_a_bits_opcode), .io_in_a_bits_param (auto_anon_in_2_a_bits_param), .io_in_a_bits_size (auto_anon_in_2_a_bits_size), .io_in_a_bits_source (auto_anon_in_2_a_bits_source), .io_in_a_bits_address (auto_anon_in_2_a_bits_address), .io_in_a_bits_mask (auto_anon_in_2_a_bits_mask), .io_in_a_bits_corrupt (auto_anon_in_2_a_bits_corrupt), .io_in_d_ready (auto_anon_in_2_d_ready), .io_in_d_valid (auto_anon_out_2_d_valid), .io_in_d_bits_opcode (auto_anon_out_2_d_bits_opcode), .io_in_d_bits_param (auto_anon_out_2_d_bits_param), .io_in_d_bits_size (auto_anon_out_2_d_bits_size), .io_in_d_bits_source (auto_anon_out_2_d_bits_source), .io_in_d_bits_sink (auto_anon_out_2_d_bits_sink), .io_in_d_bits_denied (auto_anon_out_2_d_bits_denied), .io_in_d_bits_corrupt (auto_anon_out_2_d_bits_corrupt) ); // @[Nodes.scala:27:25] assign auto_anon_in_2_a_ready = auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_valid = auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_opcode = auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_param = auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_size = auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_source = auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_sink = auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_denied = auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_data = auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_in_2_d_bits_corrupt = auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_a_ready = auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_valid = auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_bits_param = auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_bits_address = auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_c_ready = auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_valid = auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_opcode = auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_param = auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_size = auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_source = auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_sink = auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_denied = auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_data = auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_a_ready = auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_valid = auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_opcode = auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_param = auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_size = auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_source = auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_sink = auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_denied = auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_data = auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_valid = auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_opcode = auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_param = auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_size = auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_source = auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_address = auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_bufferable = auto_anon_in_2_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_modifiable = auto_anon_in_2_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_readalloc = auto_anon_in_2_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_writealloc = auto_anon_in_2_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_privileged = auto_anon_in_2_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_secure = auto_anon_in_2_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_user_amba_prot_fetch = auto_anon_in_2_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_mask = auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_data = auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_a_bits_corrupt = auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_2_d_ready = auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_valid = auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_param = auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_size = auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_source = auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_address = auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_mask = auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_data = auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_b_ready = auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_valid = auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_param = auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_size = auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_source = auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_address = auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_data = auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_d_ready = auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_e_valid = auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_e_bits_sink = auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_valid = auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_opcode = auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_param = auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_size = auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_source = auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_address = auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_bufferable = auto_anon_in_0_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_modifiable = auto_anon_in_0_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_readalloc = auto_anon_in_0_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_writealloc = auto_anon_in_0_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_privileged = auto_anon_in_0_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_secure = auto_anon_in_0_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_user_amba_prot_fetch = auto_anon_in_0_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_mask = auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_data = auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_d_ready = auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_113 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_369 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_113( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_369 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain : output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_rockettile_reset_vector_in : UInt<32>, flip element_reset_domain_rockettile_hartid_in : UInt<3>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst element_reset_domain of HierarchicalElementResetDomain inst clockNode of FixedClockBroadcast_1_1 inst buffer of TLBuffer_a32d64s2k5z4c_1 connect buffer.clock, childClock connect buffer.reset, childReset inst buffer_1 of TLBuffer_2 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst intsink of IntSyncAsyncCrossingSink_n1x1 connect intsink.clock, childClock connect intsink.reset, childReset inst intsink_1 of IntSyncSyncCrossingSink_n1x2 inst intsink_2 of IntSyncSyncCrossingSink_n1x1 inst intsink_3 of IntSyncSyncCrossingSink_n1x1_1 inst intsink_4 of IntSyncSyncCrossingSink_n1x1_2 inst intsource of IntSyncCrossingSource_n1x1 connect intsource.clock, childClock connect intsource.reset, childReset inst intsink_5 of IntSyncSyncCrossingSink_n1x1_3 inst intsource_1 of IntSyncCrossingSource_n1x1_1 connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsink_6 of IntSyncSyncCrossingSink_n1x1_4 inst intsource_2 of IntSyncCrossingSource_n1x1_2 connect intsource_2.clock, childClock connect intsource_2.reset, childReset wire tapClockNodeOut : { clock : Clock, reset : Reset} invalidate tapClockNodeOut.reset invalidate tapClockNodeOut.clock wire tapClockNodeIn : { clock : Clock, reset : Reset} invalidate tapClockNodeIn.reset invalidate tapClockNodeIn.clock connect tapClockNodeOut, tapClockNodeIn wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}} invalidate tlMasterClockXingOut.e.bits.sink invalidate tlMasterClockXingOut.e.valid invalidate tlMasterClockXingOut.e.ready invalidate tlMasterClockXingOut.d.bits.corrupt invalidate tlMasterClockXingOut.d.bits.data invalidate tlMasterClockXingOut.d.bits.denied invalidate tlMasterClockXingOut.d.bits.sink invalidate tlMasterClockXingOut.d.bits.source invalidate tlMasterClockXingOut.d.bits.size invalidate tlMasterClockXingOut.d.bits.param invalidate tlMasterClockXingOut.d.bits.opcode invalidate tlMasterClockXingOut.d.valid invalidate tlMasterClockXingOut.d.ready invalidate tlMasterClockXingOut.c.bits.corrupt invalidate tlMasterClockXingOut.c.bits.data invalidate tlMasterClockXingOut.c.bits.address invalidate tlMasterClockXingOut.c.bits.source invalidate tlMasterClockXingOut.c.bits.size invalidate tlMasterClockXingOut.c.bits.param invalidate tlMasterClockXingOut.c.bits.opcode invalidate tlMasterClockXingOut.c.valid invalidate tlMasterClockXingOut.c.ready invalidate tlMasterClockXingOut.b.bits.corrupt invalidate tlMasterClockXingOut.b.bits.data invalidate tlMasterClockXingOut.b.bits.mask invalidate tlMasterClockXingOut.b.bits.address invalidate tlMasterClockXingOut.b.bits.source invalidate tlMasterClockXingOut.b.bits.size invalidate tlMasterClockXingOut.b.bits.param invalidate tlMasterClockXingOut.b.bits.opcode invalidate tlMasterClockXingOut.b.valid invalidate tlMasterClockXingOut.b.ready invalidate tlMasterClockXingOut.a.bits.corrupt invalidate tlMasterClockXingOut.a.bits.data invalidate tlMasterClockXingOut.a.bits.mask invalidate tlMasterClockXingOut.a.bits.address invalidate tlMasterClockXingOut.a.bits.source invalidate tlMasterClockXingOut.a.bits.size invalidate tlMasterClockXingOut.a.bits.param invalidate tlMasterClockXingOut.a.bits.opcode invalidate tlMasterClockXingOut.a.valid invalidate tlMasterClockXingOut.a.ready wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}} invalidate tlMasterClockXingIn.e.bits.sink invalidate tlMasterClockXingIn.e.valid invalidate tlMasterClockXingIn.e.ready invalidate tlMasterClockXingIn.d.bits.corrupt invalidate tlMasterClockXingIn.d.bits.data invalidate tlMasterClockXingIn.d.bits.denied invalidate tlMasterClockXingIn.d.bits.sink invalidate tlMasterClockXingIn.d.bits.source invalidate tlMasterClockXingIn.d.bits.size invalidate tlMasterClockXingIn.d.bits.param invalidate tlMasterClockXingIn.d.bits.opcode invalidate tlMasterClockXingIn.d.valid invalidate tlMasterClockXingIn.d.ready invalidate tlMasterClockXingIn.c.bits.corrupt invalidate tlMasterClockXingIn.c.bits.data invalidate tlMasterClockXingIn.c.bits.address invalidate tlMasterClockXingIn.c.bits.source invalidate tlMasterClockXingIn.c.bits.size invalidate tlMasterClockXingIn.c.bits.param invalidate tlMasterClockXingIn.c.bits.opcode invalidate tlMasterClockXingIn.c.valid invalidate tlMasterClockXingIn.c.ready invalidate tlMasterClockXingIn.b.bits.corrupt invalidate tlMasterClockXingIn.b.bits.data invalidate tlMasterClockXingIn.b.bits.mask invalidate tlMasterClockXingIn.b.bits.address invalidate tlMasterClockXingIn.b.bits.source invalidate tlMasterClockXingIn.b.bits.size invalidate tlMasterClockXingIn.b.bits.param invalidate tlMasterClockXingIn.b.bits.opcode invalidate tlMasterClockXingIn.b.valid invalidate tlMasterClockXingIn.b.ready invalidate tlMasterClockXingIn.a.bits.corrupt invalidate tlMasterClockXingIn.a.bits.data invalidate tlMasterClockXingIn.a.bits.mask invalidate tlMasterClockXingIn.a.bits.address invalidate tlMasterClockXingIn.a.bits.source invalidate tlMasterClockXingIn.a.bits.size invalidate tlMasterClockXingIn.a.bits.param invalidate tlMasterClockXingIn.a.bits.opcode invalidate tlMasterClockXingIn.a.valid invalidate tlMasterClockXingIn.a.ready connect tlMasterClockXingOut, tlMasterClockXingIn wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 wire intInClockXingOut_2 : { sync : UInt<1>[1]} invalidate intInClockXingOut_2.sync[0] wire intInClockXingIn_2 : { sync : UInt<1>[1]} invalidate intInClockXingIn_2.sync[0] connect intInClockXingOut_2, intInClockXingIn_2 wire intOutClockXingOut : { sync : UInt<1>[1]} invalidate intOutClockXingOut.sync[0] wire intOutClockXingIn : { sync : UInt<1>[1]} invalidate intOutClockXingIn.sync[0] connect intOutClockXingOut, intOutClockXingIn wire intOutClockXingOut_1 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_1.sync[0] wire intOutClockXingIn_1 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_1.sync[0] connect intOutClockXingOut_1, intOutClockXingIn_1 wire intOutClockXingOut_2 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_2.sync[0] wire intOutClockXingIn_2 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_2.sync[0] connect intOutClockXingOut_2, intOutClockXingIn_2 wire intOutClockXingOut_3 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_3.sync[0] wire intOutClockXingIn_3 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_3.sync[0] connect intOutClockXingOut_3, intOutClockXingIn_3 wire intOutClockXingOut_4 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_4.sync[0] wire intOutClockXingIn_4 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_4.sync[0] connect intOutClockXingOut_4, intOutClockXingIn_4 wire intOutClockXingOut_5 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_5.sync[0] wire intOutClockXingIn_5 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_5.sync[0] connect intOutClockXingOut_5, intOutClockXingIn_5 connect clockNode.auto.anon_in, tapClockNodeOut connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out connect intsource.auto.in[0], element_reset_domain.auto.rockettile_halt_out[0] connect intsource_2.auto.in[0], element_reset_domain.auto.rockettile_cease_out[0] connect intsource_1.auto.in[0], element_reset_domain.auto.rockettile_wfi_out[0] connect buffer.auto.in, element_reset_domain.auto.rockettile_buffer_out connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready connect buffer.auto.out.d, tlMasterClockXingIn.d connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready connect buffer.auto.out.b, tlMasterClockXingIn.b connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready connect element_reset_domain.auto.rockettile_int_local_in_0[0], intsink.auto.out[0] connect element_reset_domain.auto.rockettile_int_local_in_1[0], intsink_1.auto.out[0] connect element_reset_domain.auto.rockettile_int_local_in_1[1], intsink_1.auto.out[1] connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0] connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1] connect element_reset_domain.auto.rockettile_int_local_in_2[0], intsink_2.auto.out[0] connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0] connect element_reset_domain.auto.rockettile_int_local_in_3[0], intsink_3.auto.out[0] connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0] connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0] connect intOutClockXingIn, intOutClockXingOut_1 connect intOutClockXingIn_1, intsource.auto.out connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0] connect intOutClockXingIn_2, intOutClockXingOut_3 connect intOutClockXingIn_3, intsource_1.auto.out connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0] connect intOutClockXingIn_4, intOutClockXingOut_5 connect intOutClockXingIn_5, intsource_2.auto.out connect tapClockNodeIn, auto.tap_clock_in connect auto.tl_master_clock_xing_out, tlMasterClockXingOut connect intInClockXingIn, auto.int_in_clock_xing_in_0 connect intInClockXingIn_1, auto.int_in_clock_xing_in_1 connect intInClockXingIn_2, auto.int_in_clock_xing_in_2 connect element_reset_domain.auto.rockettile_hartid_in, auto.element_reset_domain_rockettile_hartid_in connect element_reset_domain.auto.rockettile_reset_vector_in, auto.element_reset_domain_rockettile_reset_vector_in connect auto.element_reset_domain_rockettile_trace_source_out.time, element_reset_domain.auto.rockettile_trace_source_out.time connect auto.element_reset_domain_rockettile_trace_source_out.insns, element_reset_domain.auto.rockettile_trace_source_out.insns connect auto.element_reset_domain_rockettile_trace_core_source_out.cause, element_reset_domain.auto.rockettile_trace_core_source_out.cause connect auto.element_reset_domain_rockettile_trace_core_source_out.tval, element_reset_domain.auto.rockettile_trace_core_source_out.tval connect auto.element_reset_domain_rockettile_trace_core_source_out.priv, element_reset_domain.auto.rockettile_trace_core_source_out.priv connect auto.element_reset_domain_rockettile_trace_core_source_out.group, element_reset_domain.auto.rockettile_trace_core_source_out.group connect intsink.auto.in.sync[0], auto.intsink_in.sync[0] connect auto.intsink_out_0, intsink_4.auto.out connect auto.intsink_out_1, intsink_5.auto.out connect auto.intsink_out_2, intsink_6.auto.out connect childClock, tapClockNodeIn.clock connect childReset, tapClockNodeIn.reset connect clock, tapClockNodeIn.clock connect reset, tapClockNodeIn.reset extmodule plusarg_reader_153 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_154 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TilePRCIDomain( // @[ClockDomain.scala:14:9] input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25] input [2:0] auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_master_clock_xing_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _intsink_3_auto_out_0; // @[Crossing.scala:109:29] wire _intsink_2_auto_out_0; // @[Crossing.scala:109:29] wire _intsink_1_auto_out_0; // @[Crossing.scala:109:29] wire _intsink_1_auto_out_1; // @[Crossing.scala:109:29] wire _intsink_auto_out_0; // @[Crossing.scala:86:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_b_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_b_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_b_bits_size; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_b_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_auto_in_b_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_in_b_bits_mask; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_c_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_e_ready; // @[Buffer.scala:75:28] wire _element_reset_domain_rockettile_auto_buffer_out_a_valid; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_opcode; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_param; // @[HasTiles.scala:164:59] wire [3:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_size; // @[HasTiles.scala:164:59] wire [1:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_source; // @[HasTiles.scala:164:59] wire [31:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_address; // @[HasTiles.scala:164:59] wire [7:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_mask; // @[HasTiles.scala:164:59] wire [63:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_data; // @[HasTiles.scala:164:59] wire _element_reset_domain_rockettile_auto_buffer_out_b_ready; // @[HasTiles.scala:164:59] wire _element_reset_domain_rockettile_auto_buffer_out_c_valid; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_opcode; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_param; // @[HasTiles.scala:164:59] wire [3:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_size; // @[HasTiles.scala:164:59] wire [1:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_source; // @[HasTiles.scala:164:59] wire [31:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_address; // @[HasTiles.scala:164:59] wire [63:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_data; // @[HasTiles.scala:164:59] wire _element_reset_domain_rockettile_auto_buffer_out_d_ready; // @[HasTiles.scala:164:59] wire _element_reset_domain_rockettile_auto_buffer_out_e_valid; // @[HasTiles.scala:164:59] wire [4:0] _element_reset_domain_rockettile_auto_buffer_out_e_bits_sink; // @[HasTiles.scala:164:59] wire _element_reset_domain_rockettile_auto_wfi_out_0; // @[HasTiles.scala:164:59] RocketTile element_reset_domain_rockettile ( // @[HasTiles.scala:164:59] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_buffer_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_buffer_out_a_valid (_element_reset_domain_rockettile_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_element_reset_domain_rockettile_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_element_reset_domain_rockettile_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_element_reset_domain_rockettile_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_element_reset_domain_rockettile_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_element_reset_domain_rockettile_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_element_reset_domain_rockettile_auto_buffer_out_a_bits_data), .auto_buffer_out_b_ready (_element_reset_domain_rockettile_auto_buffer_out_b_ready), .auto_buffer_out_b_valid (_buffer_auto_in_b_valid), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_opcode (_buffer_auto_in_b_bits_opcode), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_param (_buffer_auto_in_b_bits_param), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_size (_buffer_auto_in_b_bits_size), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_source (_buffer_auto_in_b_bits_source), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_address (_buffer_auto_in_b_bits_address), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_mask (_buffer_auto_in_b_bits_mask), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), // @[Buffer.scala:75:28] .auto_buffer_out_c_ready (_buffer_auto_in_c_ready), // @[Buffer.scala:75:28] .auto_buffer_out_c_valid (_element_reset_domain_rockettile_auto_buffer_out_c_valid), .auto_buffer_out_c_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_c_bits_opcode), .auto_buffer_out_c_bits_param (_element_reset_domain_rockettile_auto_buffer_out_c_bits_param), .auto_buffer_out_c_bits_size (_element_reset_domain_rockettile_auto_buffer_out_c_bits_size), .auto_buffer_out_c_bits_source (_element_reset_domain_rockettile_auto_buffer_out_c_bits_source), .auto_buffer_out_c_bits_address (_element_reset_domain_rockettile_auto_buffer_out_c_bits_address), .auto_buffer_out_c_bits_data (_element_reset_domain_rockettile_auto_buffer_out_c_bits_data), .auto_buffer_out_d_ready (_element_reset_domain_rockettile_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_buffer_out_e_ready (_buffer_auto_in_e_ready), // @[Buffer.scala:75:28] .auto_buffer_out_e_valid (_element_reset_domain_rockettile_auto_buffer_out_e_valid), .auto_buffer_out_e_bits_sink (_element_reset_domain_rockettile_auto_buffer_out_e_bits_sink), .auto_wfi_out_0 (_element_reset_domain_rockettile_auto_wfi_out_0), .auto_int_local_in_3_0 (_intsink_3_auto_out_0), // @[Crossing.scala:109:29] .auto_int_local_in_2_0 (_intsink_2_auto_out_0), // @[Crossing.scala:109:29] .auto_int_local_in_1_0 (_intsink_1_auto_out_0), // @[Crossing.scala:109:29] .auto_int_local_in_1_1 (_intsink_1_auto_out_1), // @[Crossing.scala:109:29] .auto_int_local_in_0_0 (_intsink_auto_out_0), // @[Crossing.scala:86:29] .auto_hartid_in (auto_element_reset_domain_rockettile_hartid_in) ); // @[HasTiles.scala:164:59] TLBuffer_a32d64s2k5z4c_1 buffer ( // @[Buffer.scala:75:28] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_element_reset_domain_rockettile_auto_buffer_out_a_valid), // @[HasTiles.scala:164:59] .auto_in_a_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_a_bits_opcode), // @[HasTiles.scala:164:59] .auto_in_a_bits_param (_element_reset_domain_rockettile_auto_buffer_out_a_bits_param), // @[HasTiles.scala:164:59] .auto_in_a_bits_size (_element_reset_domain_rockettile_auto_buffer_out_a_bits_size), // @[HasTiles.scala:164:59] .auto_in_a_bits_source (_element_reset_domain_rockettile_auto_buffer_out_a_bits_source), // @[HasTiles.scala:164:59] .auto_in_a_bits_address (_element_reset_domain_rockettile_auto_buffer_out_a_bits_address), // @[HasTiles.scala:164:59] .auto_in_a_bits_mask (_element_reset_domain_rockettile_auto_buffer_out_a_bits_mask), // @[HasTiles.scala:164:59] .auto_in_a_bits_data (_element_reset_domain_rockettile_auto_buffer_out_a_bits_data), // @[HasTiles.scala:164:59] .auto_in_b_ready (_element_reset_domain_rockettile_auto_buffer_out_b_ready), // @[HasTiles.scala:164:59] .auto_in_b_valid (_buffer_auto_in_b_valid), .auto_in_b_bits_opcode (_buffer_auto_in_b_bits_opcode), .auto_in_b_bits_param (_buffer_auto_in_b_bits_param), .auto_in_b_bits_size (_buffer_auto_in_b_bits_size), .auto_in_b_bits_source (_buffer_auto_in_b_bits_source), .auto_in_b_bits_address (_buffer_auto_in_b_bits_address), .auto_in_b_bits_mask (_buffer_auto_in_b_bits_mask), .auto_in_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), .auto_in_c_ready (_buffer_auto_in_c_ready), .auto_in_c_valid (_element_reset_domain_rockettile_auto_buffer_out_c_valid), // @[HasTiles.scala:164:59] .auto_in_c_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_c_bits_opcode), // @[HasTiles.scala:164:59] .auto_in_c_bits_param (_element_reset_domain_rockettile_auto_buffer_out_c_bits_param), // @[HasTiles.scala:164:59] .auto_in_c_bits_size (_element_reset_domain_rockettile_auto_buffer_out_c_bits_size), // @[HasTiles.scala:164:59] .auto_in_c_bits_source (_element_reset_domain_rockettile_auto_buffer_out_c_bits_source), // @[HasTiles.scala:164:59] .auto_in_c_bits_address (_element_reset_domain_rockettile_auto_buffer_out_c_bits_address), // @[HasTiles.scala:164:59] .auto_in_c_bits_data (_element_reset_domain_rockettile_auto_buffer_out_c_bits_data), // @[HasTiles.scala:164:59] .auto_in_d_ready (_element_reset_domain_rockettile_auto_buffer_out_d_ready), // @[HasTiles.scala:164:59] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_in_e_ready (_buffer_auto_in_e_ready), .auto_in_e_valid (_element_reset_domain_rockettile_auto_buffer_out_e_valid), // @[HasTiles.scala:164:59] .auto_in_e_bits_sink (_element_reset_domain_rockettile_auto_buffer_out_e_bits_sink), // @[HasTiles.scala:164:59] .auto_out_a_ready (auto_tl_master_clock_xing_out_a_ready), .auto_out_a_valid (auto_tl_master_clock_xing_out_a_valid), .auto_out_a_bits_opcode (auto_tl_master_clock_xing_out_a_bits_opcode), .auto_out_a_bits_param (auto_tl_master_clock_xing_out_a_bits_param), .auto_out_a_bits_size (auto_tl_master_clock_xing_out_a_bits_size), .auto_out_a_bits_source (auto_tl_master_clock_xing_out_a_bits_source), .auto_out_a_bits_address (auto_tl_master_clock_xing_out_a_bits_address), .auto_out_a_bits_mask (auto_tl_master_clock_xing_out_a_bits_mask), .auto_out_a_bits_data (auto_tl_master_clock_xing_out_a_bits_data), .auto_out_a_bits_corrupt (auto_tl_master_clock_xing_out_a_bits_corrupt), .auto_out_b_ready (auto_tl_master_clock_xing_out_b_ready), .auto_out_b_valid (auto_tl_master_clock_xing_out_b_valid), .auto_out_b_bits_opcode (auto_tl_master_clock_xing_out_b_bits_opcode), .auto_out_b_bits_param (auto_tl_master_clock_xing_out_b_bits_param), .auto_out_b_bits_size (auto_tl_master_clock_xing_out_b_bits_size), .auto_out_b_bits_source (auto_tl_master_clock_xing_out_b_bits_source), .auto_out_b_bits_address (auto_tl_master_clock_xing_out_b_bits_address), .auto_out_b_bits_mask (auto_tl_master_clock_xing_out_b_bits_mask), .auto_out_b_bits_data (auto_tl_master_clock_xing_out_b_bits_data), .auto_out_b_bits_corrupt (auto_tl_master_clock_xing_out_b_bits_corrupt), .auto_out_c_ready (auto_tl_master_clock_xing_out_c_ready), .auto_out_c_valid (auto_tl_master_clock_xing_out_c_valid), .auto_out_c_bits_opcode (auto_tl_master_clock_xing_out_c_bits_opcode), .auto_out_c_bits_param (auto_tl_master_clock_xing_out_c_bits_param), .auto_out_c_bits_size (auto_tl_master_clock_xing_out_c_bits_size), .auto_out_c_bits_source (auto_tl_master_clock_xing_out_c_bits_source), .auto_out_c_bits_address (auto_tl_master_clock_xing_out_c_bits_address), .auto_out_c_bits_data (auto_tl_master_clock_xing_out_c_bits_data), .auto_out_c_bits_corrupt (auto_tl_master_clock_xing_out_c_bits_corrupt), .auto_out_d_ready (auto_tl_master_clock_xing_out_d_ready), .auto_out_d_valid (auto_tl_master_clock_xing_out_d_valid), .auto_out_d_bits_opcode (auto_tl_master_clock_xing_out_d_bits_opcode), .auto_out_d_bits_param (auto_tl_master_clock_xing_out_d_bits_param), .auto_out_d_bits_size (auto_tl_master_clock_xing_out_d_bits_size), .auto_out_d_bits_source (auto_tl_master_clock_xing_out_d_bits_source), .auto_out_d_bits_sink (auto_tl_master_clock_xing_out_d_bits_sink), .auto_out_d_bits_denied (auto_tl_master_clock_xing_out_d_bits_denied), .auto_out_d_bits_data (auto_tl_master_clock_xing_out_d_bits_data), .auto_out_d_bits_corrupt (auto_tl_master_clock_xing_out_d_bits_corrupt), .auto_out_e_ready (auto_tl_master_clock_xing_out_e_ready), .auto_out_e_valid (auto_tl_master_clock_xing_out_e_valid), .auto_out_e_bits_sink (auto_tl_master_clock_xing_out_e_bits_sink) ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29] .clock (auto_tap_clock_in_clock), .auto_in_sync_0 (auto_intsink_in_sync_0), .auto_out_0 (_intsink_auto_out_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (auto_int_in_clock_xing_in_0_sync_0), .auto_in_sync_1 (auto_int_in_clock_xing_in_0_sync_1), .auto_out_0 (_intsink_1_auto_out_0), .auto_out_1 (_intsink_1_auto_out_1) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (auto_int_in_clock_xing_in_1_sync_0), .auto_out_0 (_intsink_2_auto_out_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1 intsink_3 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (auto_int_in_clock_xing_in_2_sync_0), .auto_out_0 (_intsink_3_auto_out_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_0 (1'h0), // @[Buffer.scala:75:28] .auto_out_sync_0 (/* unused */) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_0 (_element_reset_domain_rockettile_auto_wfi_out_0), // @[HasTiles.scala:164:59] .auto_out_sync_0 (/* unused */) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1 intsource_2 ( // @[Crossing.scala:29:31] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_0 (1'h0), // @[Buffer.scala:75:28] .auto_out_sync_0 (/* unused */) ); // @[Crossing.scala:29:31] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_60 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_60( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_45 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_45(); // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawIn_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawIn_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawIn_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawIn_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawIn_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawIn_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rawIn_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire rawIn_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire rawIn_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire rawIn_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire rawIn_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire _rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire _rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire _rawIn_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire _rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire _io_exceptionFlags_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire _io_exceptionFlags_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}] wire [4:0] io_exceptionFlags = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54] wire io_detectTininess = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35] wire rawIn_sign = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35] wire _rawIn_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35] wire _rawIn_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35] wire _rawIn_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35] wire _io_exceptionFlags_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] io_in = 33'h180000000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35] wire [32:0] io_out = 33'h180000000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35] wire [32:0] _io_out_T = 33'h180000000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RenameStage_1 : input clock : Clock input reset : Reset output io : { ren_stalls : UInt<1>[3], flip kill : UInt<1>, flip dec_fire : UInt<1>[3], flip dec_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], ren2_mask : UInt<1>[3], ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip dis_fire : UInt<1>[3], flip dis_ready : UInt<1>, flip wakeups : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[2], flip com_valids : UInt<1>[3], flip com_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], flip rbk_valids : UInt<1>[3], flip rollback : UInt<1>, flip debug_rob_empty : UInt<1>, debug : { freelist : UInt<96>, isprlist : UInt<96>, busytable : UInt<96>}} connect io.ren_stalls[0], UInt<1>(0h0) connect io.ren_stalls[1], UInt<1>(0h0) connect io.ren_stalls[2], UInt<1>(0h0) invalidate io.debug.busytable invalidate io.debug.isprlist invalidate io.debug.freelist wire ren1_fire : UInt<1>[3] wire ren1_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3] wire ren2_valids : UInt<1>[3] wire ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3] wire ren2_alloc_reqs : UInt<1>[3] connect ren1_fire[0], io.dec_fire[0] connect ren1_uops[0], io.dec_uops[0] connect ren1_fire[1], io.dec_fire[1] connect ren1_uops[1], io.dec_uops[1] connect ren1_fire[2], io.dec_fire[2] connect ren1_uops[2], io.dec_uops[2] regreset r_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock wire next_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect next_uop, r_uop when io.kill : connect r_valid, UInt<1>(0h0) else : when io.dis_ready : connect r_valid, ren1_fire[0] connect next_uop, ren1_uops[0] else : node _r_valid_T = eq(io.dis_fire[0], UInt<1>(0h0)) node _r_valid_T_1 = and(r_valid, _r_valid_T) connect r_valid, _r_valid_T_1 connect next_uop, r_uop wire r_uop_bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect r_uop_bypassed_uop, next_uop node _r_uop_bypass_hits_rs1_T = eq(ren2_uops[0].ldst, next_uop.lrs1) node r_uop_bypass_hits_rs1_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T) node _r_uop_bypass_hits_rs1_T_1 = eq(ren2_uops[1].ldst, next_uop.lrs1) node r_uop_bypass_hits_rs1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs1_T_1) node _r_uop_bypass_hits_rs1_T_2 = eq(ren2_uops[2].ldst, next_uop.lrs1) node r_uop_bypass_hits_rs1_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs1_T_2) node _r_uop_bypass_hits_rs2_T = eq(ren2_uops[0].ldst, next_uop.lrs2) node r_uop_bypass_hits_rs2_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T) node _r_uop_bypass_hits_rs2_T_1 = eq(ren2_uops[1].ldst, next_uop.lrs2) node r_uop_bypass_hits_rs2_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs2_T_1) node _r_uop_bypass_hits_rs2_T_2 = eq(ren2_uops[2].ldst, next_uop.lrs2) node r_uop_bypass_hits_rs2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs2_T_2) node _r_uop_bypass_hits_rs3_T = eq(ren2_uops[0].ldst, next_uop.lrs3) node r_uop_bypass_hits_rs3_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T) node _r_uop_bypass_hits_rs3_T_1 = eq(ren2_uops[1].ldst, next_uop.lrs3) node r_uop_bypass_hits_rs3_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs3_T_1) node _r_uop_bypass_hits_rs3_T_2 = eq(ren2_uops[2].ldst, next_uop.lrs3) node r_uop_bypass_hits_rs3_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs3_T_2) node _r_uop_bypass_hits_dst_T = eq(ren2_uops[0].ldst, next_uop.ldst) node r_uop_bypass_hits_dst_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T) node _r_uop_bypass_hits_dst_T_1 = eq(ren2_uops[1].ldst, next_uop.ldst) node r_uop_bypass_hits_dst_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_dst_T_1) node _r_uop_bypass_hits_dst_T_2 = eq(ren2_uops[2].ldst, next_uop.ldst) node r_uop_bypass_hits_dst_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_dst_T_2) node _r_uop_bypass_sel_rs1_enc_T = mux(r_uop_bypass_hits_rs1_0, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs1_enc_T_1 = mux(r_uop_bypass_hits_rs1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs1_enc_T) node r_uop_bypass_sel_rs1_enc = mux(r_uop_bypass_hits_rs1_2, UInt<3>(0h1), _r_uop_bypass_sel_rs1_enc_T_1) node r_uop_bypass_sel_rs1_2 = bits(r_uop_bypass_sel_rs1_enc, 0, 0) node r_uop_bypass_sel_rs1_1 = bits(r_uop_bypass_sel_rs1_enc, 1, 1) node r_uop_bypass_sel_rs1_0 = bits(r_uop_bypass_sel_rs1_enc, 2, 2) node _r_uop_bypass_sel_rs2_enc_T = mux(r_uop_bypass_hits_rs2_0, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs2_enc_T_1 = mux(r_uop_bypass_hits_rs2_1, UInt<3>(0h2), _r_uop_bypass_sel_rs2_enc_T) node r_uop_bypass_sel_rs2_enc = mux(r_uop_bypass_hits_rs2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs2_enc_T_1) node r_uop_bypass_sel_rs2_2 = bits(r_uop_bypass_sel_rs2_enc, 0, 0) node r_uop_bypass_sel_rs2_1 = bits(r_uop_bypass_sel_rs2_enc, 1, 1) node r_uop_bypass_sel_rs2_0 = bits(r_uop_bypass_sel_rs2_enc, 2, 2) node _r_uop_bypass_sel_rs3_enc_T = mux(r_uop_bypass_hits_rs3_0, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs3_enc_T_1 = mux(r_uop_bypass_hits_rs3_1, UInt<3>(0h2), _r_uop_bypass_sel_rs3_enc_T) node r_uop_bypass_sel_rs3_enc = mux(r_uop_bypass_hits_rs3_2, UInt<3>(0h1), _r_uop_bypass_sel_rs3_enc_T_1) node r_uop_bypass_sel_rs3_2 = bits(r_uop_bypass_sel_rs3_enc, 0, 0) node r_uop_bypass_sel_rs3_1 = bits(r_uop_bypass_sel_rs3_enc, 1, 1) node r_uop_bypass_sel_rs3_0 = bits(r_uop_bypass_sel_rs3_enc, 2, 2) node _r_uop_bypass_sel_dst_enc_T = mux(r_uop_bypass_hits_dst_0, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_dst_enc_T_1 = mux(r_uop_bypass_hits_dst_1, UInt<3>(0h2), _r_uop_bypass_sel_dst_enc_T) node r_uop_bypass_sel_dst_enc = mux(r_uop_bypass_hits_dst_2, UInt<3>(0h1), _r_uop_bypass_sel_dst_enc_T_1) node r_uop_bypass_sel_dst_2 = bits(r_uop_bypass_sel_dst_enc, 0, 0) node r_uop_bypass_sel_dst_1 = bits(r_uop_bypass_sel_dst_enc, 1, 1) node r_uop_bypass_sel_dst_0 = bits(r_uop_bypass_sel_dst_enc, 2, 2) node _r_uop_do_bypass_rs1_T = or(r_uop_bypass_hits_rs1_0, r_uop_bypass_hits_rs1_1) node r_uop_do_bypass_rs1 = or(_r_uop_do_bypass_rs1_T, r_uop_bypass_hits_rs1_2) node _r_uop_do_bypass_rs2_T = or(r_uop_bypass_hits_rs2_0, r_uop_bypass_hits_rs2_1) node r_uop_do_bypass_rs2 = or(_r_uop_do_bypass_rs2_T, r_uop_bypass_hits_rs2_2) node _r_uop_do_bypass_rs3_T = or(r_uop_bypass_hits_rs3_0, r_uop_bypass_hits_rs3_1) node r_uop_do_bypass_rs3 = or(_r_uop_do_bypass_rs3_T, r_uop_bypass_hits_rs3_2) node _r_uop_do_bypass_dst_T = or(r_uop_bypass_hits_dst_0, r_uop_bypass_hits_dst_1) node r_uop_do_bypass_dst = or(_r_uop_do_bypass_dst_T, r_uop_bypass_hits_dst_2) when r_uop_do_bypass_rs1 : node _r_uop_bypassed_uop_prs1_T = mux(r_uop_bypass_sel_rs1_0, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_1 = mux(r_uop_bypass_sel_rs1_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_2 = mux(r_uop_bypass_sel_rs1_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_3 = or(_r_uop_bypassed_uop_prs1_T, _r_uop_bypassed_uop_prs1_T_1) node _r_uop_bypassed_uop_prs1_T_4 = or(_r_uop_bypassed_uop_prs1_T_3, _r_uop_bypassed_uop_prs1_T_2) wire _r_uop_bypassed_uop_prs1_WIRE : UInt<7> connect _r_uop_bypassed_uop_prs1_WIRE, _r_uop_bypassed_uop_prs1_T_4 connect r_uop_bypassed_uop.prs1, _r_uop_bypassed_uop_prs1_WIRE when r_uop_do_bypass_rs2 : node _r_uop_bypassed_uop_prs2_T = mux(r_uop_bypass_sel_rs2_0, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_1 = mux(r_uop_bypass_sel_rs2_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_2 = mux(r_uop_bypass_sel_rs2_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_3 = or(_r_uop_bypassed_uop_prs2_T, _r_uop_bypassed_uop_prs2_T_1) node _r_uop_bypassed_uop_prs2_T_4 = or(_r_uop_bypassed_uop_prs2_T_3, _r_uop_bypassed_uop_prs2_T_2) wire _r_uop_bypassed_uop_prs2_WIRE : UInt<7> connect _r_uop_bypassed_uop_prs2_WIRE, _r_uop_bypassed_uop_prs2_T_4 connect r_uop_bypassed_uop.prs2, _r_uop_bypassed_uop_prs2_WIRE when r_uop_do_bypass_rs3 : node _r_uop_bypassed_uop_prs3_T = mux(r_uop_bypass_sel_rs3_0, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_1 = mux(r_uop_bypass_sel_rs3_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_2 = mux(r_uop_bypass_sel_rs3_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_3 = or(_r_uop_bypassed_uop_prs3_T, _r_uop_bypassed_uop_prs3_T_1) node _r_uop_bypassed_uop_prs3_T_4 = or(_r_uop_bypassed_uop_prs3_T_3, _r_uop_bypassed_uop_prs3_T_2) wire _r_uop_bypassed_uop_prs3_WIRE : UInt<7> connect _r_uop_bypassed_uop_prs3_WIRE, _r_uop_bypassed_uop_prs3_T_4 connect r_uop_bypassed_uop.prs3, _r_uop_bypassed_uop_prs3_WIRE when r_uop_do_bypass_dst : node _r_uop_bypassed_uop_stale_pdst_T = mux(r_uop_bypass_sel_dst_0, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_1 = mux(r_uop_bypass_sel_dst_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_2 = mux(r_uop_bypass_sel_dst_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_3 = or(_r_uop_bypassed_uop_stale_pdst_T, _r_uop_bypassed_uop_stale_pdst_T_1) node _r_uop_bypassed_uop_stale_pdst_T_4 = or(_r_uop_bypassed_uop_stale_pdst_T_3, _r_uop_bypassed_uop_stale_pdst_T_2) wire _r_uop_bypassed_uop_stale_pdst_WIRE : UInt<7> connect _r_uop_bypassed_uop_stale_pdst_WIRE, _r_uop_bypassed_uop_stale_pdst_T_4 connect r_uop_bypassed_uop.stale_pdst, _r_uop_bypassed_uop_stale_pdst_WIRE node _r_uop_bypassed_uop_prs1_busy_T = or(next_uop.prs1_busy, r_uop_do_bypass_rs1) connect r_uop_bypassed_uop.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T node _r_uop_bypassed_uop_prs2_busy_T = or(next_uop.prs2_busy, r_uop_do_bypass_rs2) connect r_uop_bypassed_uop.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T node _r_uop_bypassed_uop_prs3_busy_T = or(next_uop.prs3_busy, r_uop_do_bypass_rs3) connect r_uop_bypassed_uop.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T wire r_uop_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect r_uop_newuop, r_uop_bypassed_uop node _r_uop_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uop_newuop_br_mask_T_1 = and(r_uop_bypassed_uop.br_mask, _r_uop_newuop_br_mask_T) connect r_uop_newuop.br_mask, _r_uop_newuop_br_mask_T_1 connect r_uop, r_uop_newuop connect ren2_valids[0], r_valid connect ren2_uops[0], r_uop regreset r_valid_1 : UInt<1>, clock, reset, UInt<1>(0h0) reg r_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock wire next_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect next_uop_1, r_uop_1 when io.kill : connect r_valid_1, UInt<1>(0h0) else : when io.dis_ready : connect r_valid_1, ren1_fire[1] connect next_uop_1, ren1_uops[1] else : node _r_valid_T_2 = eq(io.dis_fire[1], UInt<1>(0h0)) node _r_valid_T_3 = and(r_valid_1, _r_valid_T_2) connect r_valid_1, _r_valid_T_3 connect next_uop_1, r_uop_1 wire r_uop_bypassed_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect r_uop_bypassed_uop_1, next_uop_1 node _r_uop_bypass_hits_rs1_T_3 = eq(ren2_uops[0].ldst, next_uop_1.lrs1) node r_uop_bypass_hits_rs1_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T_3) node _r_uop_bypass_hits_rs1_T_4 = eq(ren2_uops[1].ldst, next_uop_1.lrs1) node r_uop_bypass_hits_rs1_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs1_T_4) node _r_uop_bypass_hits_rs1_T_5 = eq(ren2_uops[2].ldst, next_uop_1.lrs1) node r_uop_bypass_hits_rs1_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs1_T_5) node _r_uop_bypass_hits_rs2_T_3 = eq(ren2_uops[0].ldst, next_uop_1.lrs2) node r_uop_bypass_hits_rs2_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T_3) node _r_uop_bypass_hits_rs2_T_4 = eq(ren2_uops[1].ldst, next_uop_1.lrs2) node r_uop_bypass_hits_rs2_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs2_T_4) node _r_uop_bypass_hits_rs2_T_5 = eq(ren2_uops[2].ldst, next_uop_1.lrs2) node r_uop_bypass_hits_rs2_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs2_T_5) node _r_uop_bypass_hits_rs3_T_3 = eq(ren2_uops[0].ldst, next_uop_1.lrs3) node r_uop_bypass_hits_rs3_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T_3) node _r_uop_bypass_hits_rs3_T_4 = eq(ren2_uops[1].ldst, next_uop_1.lrs3) node r_uop_bypass_hits_rs3_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs3_T_4) node _r_uop_bypass_hits_rs3_T_5 = eq(ren2_uops[2].ldst, next_uop_1.lrs3) node r_uop_bypass_hits_rs3_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs3_T_5) node _r_uop_bypass_hits_dst_T_3 = eq(ren2_uops[0].ldst, next_uop_1.ldst) node r_uop_bypass_hits_dst_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T_3) node _r_uop_bypass_hits_dst_T_4 = eq(ren2_uops[1].ldst, next_uop_1.ldst) node r_uop_bypass_hits_dst_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_dst_T_4) node _r_uop_bypass_hits_dst_T_5 = eq(ren2_uops[2].ldst, next_uop_1.ldst) node r_uop_bypass_hits_dst_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_dst_T_5) node _r_uop_bypass_sel_rs1_enc_T_2 = mux(r_uop_bypass_hits_rs1_0_1, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs1_enc_T_3 = mux(r_uop_bypass_hits_rs1_1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs1_enc_T_2) node r_uop_bypass_sel_rs1_enc_1 = mux(r_uop_bypass_hits_rs1_2_1, UInt<3>(0h1), _r_uop_bypass_sel_rs1_enc_T_3) node r_uop_bypass_sel_rs1_2_1 = bits(r_uop_bypass_sel_rs1_enc_1, 0, 0) node r_uop_bypass_sel_rs1_1_1 = bits(r_uop_bypass_sel_rs1_enc_1, 1, 1) node r_uop_bypass_sel_rs1_0_1 = bits(r_uop_bypass_sel_rs1_enc_1, 2, 2) node _r_uop_bypass_sel_rs2_enc_T_2 = mux(r_uop_bypass_hits_rs2_0_1, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs2_enc_T_3 = mux(r_uop_bypass_hits_rs2_1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs2_enc_T_2) node r_uop_bypass_sel_rs2_enc_1 = mux(r_uop_bypass_hits_rs2_2_1, UInt<3>(0h1), _r_uop_bypass_sel_rs2_enc_T_3) node r_uop_bypass_sel_rs2_2_1 = bits(r_uop_bypass_sel_rs2_enc_1, 0, 0) node r_uop_bypass_sel_rs2_1_1 = bits(r_uop_bypass_sel_rs2_enc_1, 1, 1) node r_uop_bypass_sel_rs2_0_1 = bits(r_uop_bypass_sel_rs2_enc_1, 2, 2) node _r_uop_bypass_sel_rs3_enc_T_2 = mux(r_uop_bypass_hits_rs3_0_1, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs3_enc_T_3 = mux(r_uop_bypass_hits_rs3_1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs3_enc_T_2) node r_uop_bypass_sel_rs3_enc_1 = mux(r_uop_bypass_hits_rs3_2_1, UInt<3>(0h1), _r_uop_bypass_sel_rs3_enc_T_3) node r_uop_bypass_sel_rs3_2_1 = bits(r_uop_bypass_sel_rs3_enc_1, 0, 0) node r_uop_bypass_sel_rs3_1_1 = bits(r_uop_bypass_sel_rs3_enc_1, 1, 1) node r_uop_bypass_sel_rs3_0_1 = bits(r_uop_bypass_sel_rs3_enc_1, 2, 2) node _r_uop_bypass_sel_dst_enc_T_2 = mux(r_uop_bypass_hits_dst_0_1, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_dst_enc_T_3 = mux(r_uop_bypass_hits_dst_1_1, UInt<3>(0h2), _r_uop_bypass_sel_dst_enc_T_2) node r_uop_bypass_sel_dst_enc_1 = mux(r_uop_bypass_hits_dst_2_1, UInt<3>(0h1), _r_uop_bypass_sel_dst_enc_T_3) node r_uop_bypass_sel_dst_2_1 = bits(r_uop_bypass_sel_dst_enc_1, 0, 0) node r_uop_bypass_sel_dst_1_1 = bits(r_uop_bypass_sel_dst_enc_1, 1, 1) node r_uop_bypass_sel_dst_0_1 = bits(r_uop_bypass_sel_dst_enc_1, 2, 2) node _r_uop_do_bypass_rs1_T_1 = or(r_uop_bypass_hits_rs1_0_1, r_uop_bypass_hits_rs1_1_1) node r_uop_do_bypass_rs1_1 = or(_r_uop_do_bypass_rs1_T_1, r_uop_bypass_hits_rs1_2_1) node _r_uop_do_bypass_rs2_T_1 = or(r_uop_bypass_hits_rs2_0_1, r_uop_bypass_hits_rs2_1_1) node r_uop_do_bypass_rs2_1 = or(_r_uop_do_bypass_rs2_T_1, r_uop_bypass_hits_rs2_2_1) node _r_uop_do_bypass_rs3_T_1 = or(r_uop_bypass_hits_rs3_0_1, r_uop_bypass_hits_rs3_1_1) node r_uop_do_bypass_rs3_1 = or(_r_uop_do_bypass_rs3_T_1, r_uop_bypass_hits_rs3_2_1) node _r_uop_do_bypass_dst_T_1 = or(r_uop_bypass_hits_dst_0_1, r_uop_bypass_hits_dst_1_1) node r_uop_do_bypass_dst_1 = or(_r_uop_do_bypass_dst_T_1, r_uop_bypass_hits_dst_2_1) when r_uop_do_bypass_rs1_1 : node _r_uop_bypassed_uop_prs1_T_5 = mux(r_uop_bypass_sel_rs1_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_6 = mux(r_uop_bypass_sel_rs1_1_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_7 = mux(r_uop_bypass_sel_rs1_2_1, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_8 = or(_r_uop_bypassed_uop_prs1_T_5, _r_uop_bypassed_uop_prs1_T_6) node _r_uop_bypassed_uop_prs1_T_9 = or(_r_uop_bypassed_uop_prs1_T_8, _r_uop_bypassed_uop_prs1_T_7) wire _r_uop_bypassed_uop_prs1_WIRE_1 : UInt<7> connect _r_uop_bypassed_uop_prs1_WIRE_1, _r_uop_bypassed_uop_prs1_T_9 connect r_uop_bypassed_uop_1.prs1, _r_uop_bypassed_uop_prs1_WIRE_1 when r_uop_do_bypass_rs2_1 : node _r_uop_bypassed_uop_prs2_T_5 = mux(r_uop_bypass_sel_rs2_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_6 = mux(r_uop_bypass_sel_rs2_1_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_7 = mux(r_uop_bypass_sel_rs2_2_1, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_8 = or(_r_uop_bypassed_uop_prs2_T_5, _r_uop_bypassed_uop_prs2_T_6) node _r_uop_bypassed_uop_prs2_T_9 = or(_r_uop_bypassed_uop_prs2_T_8, _r_uop_bypassed_uop_prs2_T_7) wire _r_uop_bypassed_uop_prs2_WIRE_1 : UInt<7> connect _r_uop_bypassed_uop_prs2_WIRE_1, _r_uop_bypassed_uop_prs2_T_9 connect r_uop_bypassed_uop_1.prs2, _r_uop_bypassed_uop_prs2_WIRE_1 when r_uop_do_bypass_rs3_1 : node _r_uop_bypassed_uop_prs3_T_5 = mux(r_uop_bypass_sel_rs3_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_6 = mux(r_uop_bypass_sel_rs3_1_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_7 = mux(r_uop_bypass_sel_rs3_2_1, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_8 = or(_r_uop_bypassed_uop_prs3_T_5, _r_uop_bypassed_uop_prs3_T_6) node _r_uop_bypassed_uop_prs3_T_9 = or(_r_uop_bypassed_uop_prs3_T_8, _r_uop_bypassed_uop_prs3_T_7) wire _r_uop_bypassed_uop_prs3_WIRE_1 : UInt<7> connect _r_uop_bypassed_uop_prs3_WIRE_1, _r_uop_bypassed_uop_prs3_T_9 connect r_uop_bypassed_uop_1.prs3, _r_uop_bypassed_uop_prs3_WIRE_1 when r_uop_do_bypass_dst_1 : node _r_uop_bypassed_uop_stale_pdst_T_5 = mux(r_uop_bypass_sel_dst_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_6 = mux(r_uop_bypass_sel_dst_1_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_7 = mux(r_uop_bypass_sel_dst_2_1, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_8 = or(_r_uop_bypassed_uop_stale_pdst_T_5, _r_uop_bypassed_uop_stale_pdst_T_6) node _r_uop_bypassed_uop_stale_pdst_T_9 = or(_r_uop_bypassed_uop_stale_pdst_T_8, _r_uop_bypassed_uop_stale_pdst_T_7) wire _r_uop_bypassed_uop_stale_pdst_WIRE_1 : UInt<7> connect _r_uop_bypassed_uop_stale_pdst_WIRE_1, _r_uop_bypassed_uop_stale_pdst_T_9 connect r_uop_bypassed_uop_1.stale_pdst, _r_uop_bypassed_uop_stale_pdst_WIRE_1 node _r_uop_bypassed_uop_prs1_busy_T_1 = or(next_uop_1.prs1_busy, r_uop_do_bypass_rs1_1) connect r_uop_bypassed_uop_1.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T_1 node _r_uop_bypassed_uop_prs2_busy_T_1 = or(next_uop_1.prs2_busy, r_uop_do_bypass_rs2_1) connect r_uop_bypassed_uop_1.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T_1 node _r_uop_bypassed_uop_prs3_busy_T_1 = or(next_uop_1.prs3_busy, r_uop_do_bypass_rs3_1) connect r_uop_bypassed_uop_1.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T_1 wire r_uop_newuop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect r_uop_newuop_1, r_uop_bypassed_uop_1 node _r_uop_newuop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _r_uop_newuop_br_mask_T_3 = and(r_uop_bypassed_uop_1.br_mask, _r_uop_newuop_br_mask_T_2) connect r_uop_newuop_1.br_mask, _r_uop_newuop_br_mask_T_3 connect r_uop_1, r_uop_newuop_1 connect ren2_valids[1], r_valid_1 connect ren2_uops[1], r_uop_1 regreset r_valid_2 : UInt<1>, clock, reset, UInt<1>(0h0) reg r_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock wire next_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect next_uop_2, r_uop_2 when io.kill : connect r_valid_2, UInt<1>(0h0) else : when io.dis_ready : connect r_valid_2, ren1_fire[2] connect next_uop_2, ren1_uops[2] else : node _r_valid_T_4 = eq(io.dis_fire[2], UInt<1>(0h0)) node _r_valid_T_5 = and(r_valid_2, _r_valid_T_4) connect r_valid_2, _r_valid_T_5 connect next_uop_2, r_uop_2 wire r_uop_bypassed_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect r_uop_bypassed_uop_2, next_uop_2 node _r_uop_bypass_hits_rs1_T_6 = eq(ren2_uops[0].ldst, next_uop_2.lrs1) node r_uop_bypass_hits_rs1_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T_6) node _r_uop_bypass_hits_rs1_T_7 = eq(ren2_uops[1].ldst, next_uop_2.lrs1) node r_uop_bypass_hits_rs1_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs1_T_7) node _r_uop_bypass_hits_rs1_T_8 = eq(ren2_uops[2].ldst, next_uop_2.lrs1) node r_uop_bypass_hits_rs1_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs1_T_8) node _r_uop_bypass_hits_rs2_T_6 = eq(ren2_uops[0].ldst, next_uop_2.lrs2) node r_uop_bypass_hits_rs2_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T_6) node _r_uop_bypass_hits_rs2_T_7 = eq(ren2_uops[1].ldst, next_uop_2.lrs2) node r_uop_bypass_hits_rs2_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs2_T_7) node _r_uop_bypass_hits_rs2_T_8 = eq(ren2_uops[2].ldst, next_uop_2.lrs2) node r_uop_bypass_hits_rs2_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs2_T_8) node _r_uop_bypass_hits_rs3_T_6 = eq(ren2_uops[0].ldst, next_uop_2.lrs3) node r_uop_bypass_hits_rs3_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T_6) node _r_uop_bypass_hits_rs3_T_7 = eq(ren2_uops[1].ldst, next_uop_2.lrs3) node r_uop_bypass_hits_rs3_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs3_T_7) node _r_uop_bypass_hits_rs3_T_8 = eq(ren2_uops[2].ldst, next_uop_2.lrs3) node r_uop_bypass_hits_rs3_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs3_T_8) node _r_uop_bypass_hits_dst_T_6 = eq(ren2_uops[0].ldst, next_uop_2.ldst) node r_uop_bypass_hits_dst_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T_6) node _r_uop_bypass_hits_dst_T_7 = eq(ren2_uops[1].ldst, next_uop_2.ldst) node r_uop_bypass_hits_dst_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_dst_T_7) node _r_uop_bypass_hits_dst_T_8 = eq(ren2_uops[2].ldst, next_uop_2.ldst) node r_uop_bypass_hits_dst_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_dst_T_8) node _r_uop_bypass_sel_rs1_enc_T_4 = mux(r_uop_bypass_hits_rs1_0_2, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs1_enc_T_5 = mux(r_uop_bypass_hits_rs1_1_2, UInt<3>(0h2), _r_uop_bypass_sel_rs1_enc_T_4) node r_uop_bypass_sel_rs1_enc_2 = mux(r_uop_bypass_hits_rs1_2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs1_enc_T_5) node r_uop_bypass_sel_rs1_2_2 = bits(r_uop_bypass_sel_rs1_enc_2, 0, 0) node r_uop_bypass_sel_rs1_1_2 = bits(r_uop_bypass_sel_rs1_enc_2, 1, 1) node r_uop_bypass_sel_rs1_0_2 = bits(r_uop_bypass_sel_rs1_enc_2, 2, 2) node _r_uop_bypass_sel_rs2_enc_T_4 = mux(r_uop_bypass_hits_rs2_0_2, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs2_enc_T_5 = mux(r_uop_bypass_hits_rs2_1_2, UInt<3>(0h2), _r_uop_bypass_sel_rs2_enc_T_4) node r_uop_bypass_sel_rs2_enc_2 = mux(r_uop_bypass_hits_rs2_2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs2_enc_T_5) node r_uop_bypass_sel_rs2_2_2 = bits(r_uop_bypass_sel_rs2_enc_2, 0, 0) node r_uop_bypass_sel_rs2_1_2 = bits(r_uop_bypass_sel_rs2_enc_2, 1, 1) node r_uop_bypass_sel_rs2_0_2 = bits(r_uop_bypass_sel_rs2_enc_2, 2, 2) node _r_uop_bypass_sel_rs3_enc_T_4 = mux(r_uop_bypass_hits_rs3_0_2, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_rs3_enc_T_5 = mux(r_uop_bypass_hits_rs3_1_2, UInt<3>(0h2), _r_uop_bypass_sel_rs3_enc_T_4) node r_uop_bypass_sel_rs3_enc_2 = mux(r_uop_bypass_hits_rs3_2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs3_enc_T_5) node r_uop_bypass_sel_rs3_2_2 = bits(r_uop_bypass_sel_rs3_enc_2, 0, 0) node r_uop_bypass_sel_rs3_1_2 = bits(r_uop_bypass_sel_rs3_enc_2, 1, 1) node r_uop_bypass_sel_rs3_0_2 = bits(r_uop_bypass_sel_rs3_enc_2, 2, 2) node _r_uop_bypass_sel_dst_enc_T_4 = mux(r_uop_bypass_hits_dst_0_2, UInt<3>(0h4), UInt<3>(0h0)) node _r_uop_bypass_sel_dst_enc_T_5 = mux(r_uop_bypass_hits_dst_1_2, UInt<3>(0h2), _r_uop_bypass_sel_dst_enc_T_4) node r_uop_bypass_sel_dst_enc_2 = mux(r_uop_bypass_hits_dst_2_2, UInt<3>(0h1), _r_uop_bypass_sel_dst_enc_T_5) node r_uop_bypass_sel_dst_2_2 = bits(r_uop_bypass_sel_dst_enc_2, 0, 0) node r_uop_bypass_sel_dst_1_2 = bits(r_uop_bypass_sel_dst_enc_2, 1, 1) node r_uop_bypass_sel_dst_0_2 = bits(r_uop_bypass_sel_dst_enc_2, 2, 2) node _r_uop_do_bypass_rs1_T_2 = or(r_uop_bypass_hits_rs1_0_2, r_uop_bypass_hits_rs1_1_2) node r_uop_do_bypass_rs1_2 = or(_r_uop_do_bypass_rs1_T_2, r_uop_bypass_hits_rs1_2_2) node _r_uop_do_bypass_rs2_T_2 = or(r_uop_bypass_hits_rs2_0_2, r_uop_bypass_hits_rs2_1_2) node r_uop_do_bypass_rs2_2 = or(_r_uop_do_bypass_rs2_T_2, r_uop_bypass_hits_rs2_2_2) node _r_uop_do_bypass_rs3_T_2 = or(r_uop_bypass_hits_rs3_0_2, r_uop_bypass_hits_rs3_1_2) node r_uop_do_bypass_rs3_2 = or(_r_uop_do_bypass_rs3_T_2, r_uop_bypass_hits_rs3_2_2) node _r_uop_do_bypass_dst_T_2 = or(r_uop_bypass_hits_dst_0_2, r_uop_bypass_hits_dst_1_2) node r_uop_do_bypass_dst_2 = or(_r_uop_do_bypass_dst_T_2, r_uop_bypass_hits_dst_2_2) when r_uop_do_bypass_rs1_2 : node _r_uop_bypassed_uop_prs1_T_10 = mux(r_uop_bypass_sel_rs1_0_2, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_11 = mux(r_uop_bypass_sel_rs1_1_2, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_12 = mux(r_uop_bypass_sel_rs1_2_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs1_T_13 = or(_r_uop_bypassed_uop_prs1_T_10, _r_uop_bypassed_uop_prs1_T_11) node _r_uop_bypassed_uop_prs1_T_14 = or(_r_uop_bypassed_uop_prs1_T_13, _r_uop_bypassed_uop_prs1_T_12) wire _r_uop_bypassed_uop_prs1_WIRE_2 : UInt<7> connect _r_uop_bypassed_uop_prs1_WIRE_2, _r_uop_bypassed_uop_prs1_T_14 connect r_uop_bypassed_uop_2.prs1, _r_uop_bypassed_uop_prs1_WIRE_2 when r_uop_do_bypass_rs2_2 : node _r_uop_bypassed_uop_prs2_T_10 = mux(r_uop_bypass_sel_rs2_0_2, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_11 = mux(r_uop_bypass_sel_rs2_1_2, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_12 = mux(r_uop_bypass_sel_rs2_2_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs2_T_13 = or(_r_uop_bypassed_uop_prs2_T_10, _r_uop_bypassed_uop_prs2_T_11) node _r_uop_bypassed_uop_prs2_T_14 = or(_r_uop_bypassed_uop_prs2_T_13, _r_uop_bypassed_uop_prs2_T_12) wire _r_uop_bypassed_uop_prs2_WIRE_2 : UInt<7> connect _r_uop_bypassed_uop_prs2_WIRE_2, _r_uop_bypassed_uop_prs2_T_14 connect r_uop_bypassed_uop_2.prs2, _r_uop_bypassed_uop_prs2_WIRE_2 when r_uop_do_bypass_rs3_2 : node _r_uop_bypassed_uop_prs3_T_10 = mux(r_uop_bypass_sel_rs3_0_2, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_11 = mux(r_uop_bypass_sel_rs3_1_2, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_12 = mux(r_uop_bypass_sel_rs3_2_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_prs3_T_13 = or(_r_uop_bypassed_uop_prs3_T_10, _r_uop_bypassed_uop_prs3_T_11) node _r_uop_bypassed_uop_prs3_T_14 = or(_r_uop_bypassed_uop_prs3_T_13, _r_uop_bypassed_uop_prs3_T_12) wire _r_uop_bypassed_uop_prs3_WIRE_2 : UInt<7> connect _r_uop_bypassed_uop_prs3_WIRE_2, _r_uop_bypassed_uop_prs3_T_14 connect r_uop_bypassed_uop_2.prs3, _r_uop_bypassed_uop_prs3_WIRE_2 when r_uop_do_bypass_dst_2 : node _r_uop_bypassed_uop_stale_pdst_T_10 = mux(r_uop_bypass_sel_dst_0_2, ren2_uops[0].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_11 = mux(r_uop_bypass_sel_dst_1_2, ren2_uops[1].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_12 = mux(r_uop_bypass_sel_dst_2_2, ren2_uops[2].pdst, UInt<1>(0h0)) node _r_uop_bypassed_uop_stale_pdst_T_13 = or(_r_uop_bypassed_uop_stale_pdst_T_10, _r_uop_bypassed_uop_stale_pdst_T_11) node _r_uop_bypassed_uop_stale_pdst_T_14 = or(_r_uop_bypassed_uop_stale_pdst_T_13, _r_uop_bypassed_uop_stale_pdst_T_12) wire _r_uop_bypassed_uop_stale_pdst_WIRE_2 : UInt<7> connect _r_uop_bypassed_uop_stale_pdst_WIRE_2, _r_uop_bypassed_uop_stale_pdst_T_14 connect r_uop_bypassed_uop_2.stale_pdst, _r_uop_bypassed_uop_stale_pdst_WIRE_2 node _r_uop_bypassed_uop_prs1_busy_T_2 = or(next_uop_2.prs1_busy, r_uop_do_bypass_rs1_2) connect r_uop_bypassed_uop_2.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T_2 node _r_uop_bypassed_uop_prs2_busy_T_2 = or(next_uop_2.prs2_busy, r_uop_do_bypass_rs2_2) connect r_uop_bypassed_uop_2.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T_2 node _r_uop_bypassed_uop_prs3_busy_T_2 = or(next_uop_2.prs3_busy, r_uop_do_bypass_rs3_2) connect r_uop_bypassed_uop_2.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T_2 wire r_uop_newuop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect r_uop_newuop_2, r_uop_bypassed_uop_2 node _r_uop_newuop_br_mask_T_4 = not(io.brupdate.b1.resolve_mask) node _r_uop_newuop_br_mask_T_5 = and(r_uop_bypassed_uop_2.br_mask, _r_uop_newuop_br_mask_T_4) connect r_uop_newuop_2.br_mask, _r_uop_newuop_br_mask_T_5 connect r_uop_2, r_uop_newuop_2 connect ren2_valids[2], r_valid_2 connect ren2_uops[2], r_uop_2 connect io.ren2_mask, ren2_valids inst maptable of RenameMapTable_1 connect maptable.clock, clock connect maptable.reset, reset inst freelist of RenameFreeList_1 connect freelist.clock, clock connect freelist.reset, reset inst busytable of RenameBusyTable_1 connect busytable.clock, clock connect busytable.reset, reset wire ren2_br_tags : { valid : UInt<1>, bits : UInt<4>}[3] wire com_valids : UInt<1>[3] wire rbk_valids : UInt<1>[3] node _ren2_alloc_reqs_0_T = eq(ren2_uops[0].dst_rtype, UInt<2>(0h1)) node _ren2_alloc_reqs_0_T_1 = and(ren2_uops[0].ldst_val, _ren2_alloc_reqs_0_T) node _ren2_alloc_reqs_0_T_2 = and(_ren2_alloc_reqs_0_T_1, io.dis_fire[0]) connect ren2_alloc_reqs[0], _ren2_alloc_reqs_0_T_2 node _ren2_br_tags_0_valid_T = eq(ren2_uops[0].is_sfb, UInt<1>(0h0)) node _ren2_br_tags_0_valid_T_1 = and(ren2_uops[0].is_br, _ren2_br_tags_0_valid_T) node _ren2_br_tags_0_valid_T_2 = or(_ren2_br_tags_0_valid_T_1, ren2_uops[0].is_jalr) node _ren2_br_tags_0_valid_T_3 = and(io.dis_fire[0], _ren2_br_tags_0_valid_T_2) connect ren2_br_tags[0].valid, _ren2_br_tags_0_valid_T_3 node _com_valids_0_T = eq(io.com_uops[0].dst_rtype, UInt<2>(0h1)) node _com_valids_0_T_1 = and(io.com_uops[0].ldst_val, _com_valids_0_T) node _com_valids_0_T_2 = and(_com_valids_0_T_1, io.com_valids[0]) connect com_valids[0], _com_valids_0_T_2 node _rbk_valids_0_T = eq(io.com_uops[0].dst_rtype, UInt<2>(0h1)) node _rbk_valids_0_T_1 = and(io.com_uops[0].ldst_val, _rbk_valids_0_T) node _rbk_valids_0_T_2 = and(_rbk_valids_0_T_1, io.rbk_valids[0]) connect rbk_valids[0], _rbk_valids_0_T_2 connect ren2_br_tags[0].bits, ren2_uops[0].br_tag node _ren2_alloc_reqs_1_T = eq(ren2_uops[1].dst_rtype, UInt<2>(0h1)) node _ren2_alloc_reqs_1_T_1 = and(ren2_uops[1].ldst_val, _ren2_alloc_reqs_1_T) node _ren2_alloc_reqs_1_T_2 = and(_ren2_alloc_reqs_1_T_1, io.dis_fire[1]) connect ren2_alloc_reqs[1], _ren2_alloc_reqs_1_T_2 node _ren2_br_tags_1_valid_T = eq(ren2_uops[1].is_sfb, UInt<1>(0h0)) node _ren2_br_tags_1_valid_T_1 = and(ren2_uops[1].is_br, _ren2_br_tags_1_valid_T) node _ren2_br_tags_1_valid_T_2 = or(_ren2_br_tags_1_valid_T_1, ren2_uops[1].is_jalr) node _ren2_br_tags_1_valid_T_3 = and(io.dis_fire[1], _ren2_br_tags_1_valid_T_2) connect ren2_br_tags[1].valid, _ren2_br_tags_1_valid_T_3 node _com_valids_1_T = eq(io.com_uops[1].dst_rtype, UInt<2>(0h1)) node _com_valids_1_T_1 = and(io.com_uops[1].ldst_val, _com_valids_1_T) node _com_valids_1_T_2 = and(_com_valids_1_T_1, io.com_valids[1]) connect com_valids[1], _com_valids_1_T_2 node _rbk_valids_1_T = eq(io.com_uops[1].dst_rtype, UInt<2>(0h1)) node _rbk_valids_1_T_1 = and(io.com_uops[1].ldst_val, _rbk_valids_1_T) node _rbk_valids_1_T_2 = and(_rbk_valids_1_T_1, io.rbk_valids[1]) connect rbk_valids[1], _rbk_valids_1_T_2 connect ren2_br_tags[1].bits, ren2_uops[1].br_tag node _ren2_alloc_reqs_2_T = eq(ren2_uops[2].dst_rtype, UInt<2>(0h1)) node _ren2_alloc_reqs_2_T_1 = and(ren2_uops[2].ldst_val, _ren2_alloc_reqs_2_T) node _ren2_alloc_reqs_2_T_2 = and(_ren2_alloc_reqs_2_T_1, io.dis_fire[2]) connect ren2_alloc_reqs[2], _ren2_alloc_reqs_2_T_2 node _ren2_br_tags_2_valid_T = eq(ren2_uops[2].is_sfb, UInt<1>(0h0)) node _ren2_br_tags_2_valid_T_1 = and(ren2_uops[2].is_br, _ren2_br_tags_2_valid_T) node _ren2_br_tags_2_valid_T_2 = or(_ren2_br_tags_2_valid_T_1, ren2_uops[2].is_jalr) node _ren2_br_tags_2_valid_T_3 = and(io.dis_fire[2], _ren2_br_tags_2_valid_T_2) connect ren2_br_tags[2].valid, _ren2_br_tags_2_valid_T_3 node _com_valids_2_T = eq(io.com_uops[2].dst_rtype, UInt<2>(0h1)) node _com_valids_2_T_1 = and(io.com_uops[2].ldst_val, _com_valids_2_T) node _com_valids_2_T_2 = and(_com_valids_2_T_1, io.com_valids[2]) connect com_valids[2], _com_valids_2_T_2 node _rbk_valids_2_T = eq(io.com_uops[2].dst_rtype, UInt<2>(0h1)) node _rbk_valids_2_T_1 = and(io.com_uops[2].ldst_val, _rbk_valids_2_T) node _rbk_valids_2_T_2 = and(_rbk_valids_2_T_1, io.rbk_valids[2]) connect rbk_valids[2], _rbk_valids_2_T_2 connect ren2_br_tags[2].bits, ren2_uops[2].br_tag wire map_reqs : { lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst : UInt<6>}[3] wire remap_reqs : { ldst : UInt<6>, pdst : UInt<7>, valid : UInt<1>}[3] connect map_reqs[0].lrs1, ren1_uops[0].lrs1 connect map_reqs[0].lrs2, ren1_uops[0].lrs2 connect map_reqs[0].lrs3, ren1_uops[0].lrs3 connect map_reqs[0].ldst, ren1_uops[0].ldst node _remap_reqs_0_ldst_T = mux(io.rollback, io.com_uops[2].ldst, ren2_uops[0].ldst) connect remap_reqs[0].ldst, _remap_reqs_0_ldst_T node _remap_reqs_0_pdst_T = mux(io.rollback, io.com_uops[2].stale_pdst, ren2_uops[0].pdst) connect remap_reqs[0].pdst, _remap_reqs_0_pdst_T connect map_reqs[1].lrs1, ren1_uops[1].lrs1 connect map_reqs[1].lrs2, ren1_uops[1].lrs2 connect map_reqs[1].lrs3, ren1_uops[1].lrs3 connect map_reqs[1].ldst, ren1_uops[1].ldst node _remap_reqs_1_ldst_T = mux(io.rollback, io.com_uops[1].ldst, ren2_uops[1].ldst) connect remap_reqs[1].ldst, _remap_reqs_1_ldst_T node _remap_reqs_1_pdst_T = mux(io.rollback, io.com_uops[1].stale_pdst, ren2_uops[1].pdst) connect remap_reqs[1].pdst, _remap_reqs_1_pdst_T connect map_reqs[2].lrs1, ren1_uops[2].lrs1 connect map_reqs[2].lrs2, ren1_uops[2].lrs2 connect map_reqs[2].lrs3, ren1_uops[2].lrs3 connect map_reqs[2].ldst, ren1_uops[2].ldst node _remap_reqs_2_ldst_T = mux(io.rollback, io.com_uops[0].ldst, ren2_uops[2].ldst) connect remap_reqs[2].ldst, _remap_reqs_2_ldst_T node _remap_reqs_2_pdst_T = mux(io.rollback, io.com_uops[0].stale_pdst, ren2_uops[2].pdst) connect remap_reqs[2].pdst, _remap_reqs_2_pdst_T node _remap_reqs_0_valid_T = or(ren2_alloc_reqs[0], rbk_valids[2]) connect remap_reqs[0].valid, _remap_reqs_0_valid_T node _remap_reqs_1_valid_T = or(ren2_alloc_reqs[1], rbk_valids[1]) connect remap_reqs[1].valid, _remap_reqs_1_valid_T node _remap_reqs_2_valid_T = or(ren2_alloc_reqs[2], rbk_valids[0]) connect remap_reqs[2].valid, _remap_reqs_2_valid_T connect maptable.io.map_reqs[0].ldst, map_reqs[0].ldst connect maptable.io.map_reqs[0].lrs3, map_reqs[0].lrs3 connect maptable.io.map_reqs[0].lrs2, map_reqs[0].lrs2 connect maptable.io.map_reqs[0].lrs1, map_reqs[0].lrs1 connect maptable.io.map_reqs[1].ldst, map_reqs[1].ldst connect maptable.io.map_reqs[1].lrs3, map_reqs[1].lrs3 connect maptable.io.map_reqs[1].lrs2, map_reqs[1].lrs2 connect maptable.io.map_reqs[1].lrs1, map_reqs[1].lrs1 connect maptable.io.map_reqs[2].ldst, map_reqs[2].ldst connect maptable.io.map_reqs[2].lrs3, map_reqs[2].lrs3 connect maptable.io.map_reqs[2].lrs2, map_reqs[2].lrs2 connect maptable.io.map_reqs[2].lrs1, map_reqs[2].lrs1 connect maptable.io.remap_reqs[0].valid, remap_reqs[0].valid connect maptable.io.remap_reqs[0].pdst, remap_reqs[0].pdst connect maptable.io.remap_reqs[0].ldst, remap_reqs[0].ldst connect maptable.io.remap_reqs[1].valid, remap_reqs[1].valid connect maptable.io.remap_reqs[1].pdst, remap_reqs[1].pdst connect maptable.io.remap_reqs[1].ldst, remap_reqs[1].ldst connect maptable.io.remap_reqs[2].valid, remap_reqs[2].valid connect maptable.io.remap_reqs[2].pdst, remap_reqs[2].pdst connect maptable.io.remap_reqs[2].ldst, remap_reqs[2].ldst connect maptable.io.ren_br_tags[0].bits, ren2_br_tags[0].bits connect maptable.io.ren_br_tags[0].valid, ren2_br_tags[0].valid connect maptable.io.ren_br_tags[1].bits, ren2_br_tags[1].bits connect maptable.io.ren_br_tags[1].valid, ren2_br_tags[1].valid connect maptable.io.ren_br_tags[2].bits, ren2_br_tags[2].bits connect maptable.io.ren_br_tags[2].valid, ren2_br_tags[2].valid connect maptable.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect maptable.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect maptable.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect maptable.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect maptable.io.brupdate.b2.taken, io.brupdate.b2.taken connect maptable.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect maptable.io.brupdate.b2.valid, io.brupdate.b2.valid connect maptable.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect maptable.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect maptable.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect maptable.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect maptable.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect maptable.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect maptable.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect maptable.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect maptable.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect maptable.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect maptable.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect maptable.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect maptable.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect maptable.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect maptable.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect maptable.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect maptable.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect maptable.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect maptable.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect maptable.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect maptable.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect maptable.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect maptable.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect maptable.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect maptable.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect maptable.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect maptable.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect maptable.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect maptable.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect maptable.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect maptable.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect maptable.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect maptable.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect maptable.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect maptable.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect maptable.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect maptable.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect maptable.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect maptable.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect maptable.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect maptable.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect maptable.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect maptable.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect maptable.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect maptable.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect maptable.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect maptable.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect maptable.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect maptable.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect maptable.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect maptable.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect maptable.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect maptable.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect maptable.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect maptable.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect maptable.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect maptable.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect maptable.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect maptable.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect maptable.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect maptable.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect maptable.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect maptable.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect maptable.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect maptable.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect maptable.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect maptable.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect maptable.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect maptable.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect maptable.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect maptable.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect maptable.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect maptable.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect maptable.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect maptable.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect maptable.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect maptable.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect maptable.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect maptable.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect maptable.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect maptable.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect maptable.io.rollback, io.rollback connect ren1_uops[0].prs1, maptable.io.map_resps[0].prs1 connect ren1_uops[0].prs2, maptable.io.map_resps[0].prs2 connect ren1_uops[0].prs3, maptable.io.map_resps[0].prs3 connect ren1_uops[0].stale_pdst, maptable.io.map_resps[0].stale_pdst connect ren1_uops[1].prs1, maptable.io.map_resps[1].prs1 connect ren1_uops[1].prs2, maptable.io.map_resps[1].prs2 connect ren1_uops[1].prs3, maptable.io.map_resps[1].prs3 connect ren1_uops[1].stale_pdst, maptable.io.map_resps[1].stale_pdst connect ren1_uops[2].prs1, maptable.io.map_resps[2].prs1 connect ren1_uops[2].prs2, maptable.io.map_resps[2].prs2 connect ren1_uops[2].prs3, maptable.io.map_resps[2].prs3 connect ren1_uops[2].stale_pdst, maptable.io.map_resps[2].stale_pdst connect freelist.io.reqs[0], ren2_alloc_reqs[0] connect freelist.io.reqs[1], ren2_alloc_reqs[1] connect freelist.io.reqs[2], ren2_alloc_reqs[2] node _freelist_io_dealloc_pregs_0_valid_T = or(com_valids[0], rbk_valids[0]) connect freelist.io.dealloc_pregs[0].valid, _freelist_io_dealloc_pregs_0_valid_T node _freelist_io_dealloc_pregs_1_valid_T = or(com_valids[1], rbk_valids[1]) connect freelist.io.dealloc_pregs[1].valid, _freelist_io_dealloc_pregs_1_valid_T node _freelist_io_dealloc_pregs_2_valid_T = or(com_valids[2], rbk_valids[2]) connect freelist.io.dealloc_pregs[2].valid, _freelist_io_dealloc_pregs_2_valid_T node _freelist_io_dealloc_pregs_0_bits_T = mux(io.rollback, io.com_uops[0].pdst, io.com_uops[0].stale_pdst) connect freelist.io.dealloc_pregs[0].bits, _freelist_io_dealloc_pregs_0_bits_T node _freelist_io_dealloc_pregs_1_bits_T = mux(io.rollback, io.com_uops[1].pdst, io.com_uops[1].stale_pdst) connect freelist.io.dealloc_pregs[1].bits, _freelist_io_dealloc_pregs_1_bits_T node _freelist_io_dealloc_pregs_2_bits_T = mux(io.rollback, io.com_uops[2].pdst, io.com_uops[2].stale_pdst) connect freelist.io.dealloc_pregs[2].bits, _freelist_io_dealloc_pregs_2_bits_T connect freelist.io.ren_br_tags[0].bits, ren2_br_tags[0].bits connect freelist.io.ren_br_tags[0].valid, ren2_br_tags[0].valid connect freelist.io.ren_br_tags[1].bits, ren2_br_tags[1].bits connect freelist.io.ren_br_tags[1].valid, ren2_br_tags[1].valid connect freelist.io.ren_br_tags[2].bits, ren2_br_tags[2].bits connect freelist.io.ren_br_tags[2].valid, ren2_br_tags[2].valid connect freelist.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect freelist.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect freelist.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect freelist.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect freelist.io.brupdate.b2.taken, io.brupdate.b2.taken connect freelist.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect freelist.io.brupdate.b2.valid, io.brupdate.b2.valid connect freelist.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect freelist.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect freelist.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect freelist.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect freelist.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect freelist.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect freelist.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect freelist.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect freelist.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect freelist.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect freelist.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect freelist.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect freelist.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect freelist.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect freelist.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect freelist.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect freelist.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect freelist.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect freelist.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect freelist.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect freelist.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect freelist.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect freelist.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect freelist.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect freelist.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect freelist.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect freelist.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect freelist.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect freelist.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect freelist.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect freelist.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect freelist.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect freelist.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect freelist.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect freelist.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect freelist.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect freelist.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect freelist.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect freelist.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect freelist.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect freelist.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect freelist.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect freelist.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect freelist.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect freelist.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect freelist.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect freelist.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect freelist.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect freelist.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect freelist.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect freelist.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect freelist.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect freelist.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect freelist.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect freelist.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect freelist.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect freelist.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect freelist.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect freelist.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect freelist.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect freelist.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect freelist.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect freelist.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect freelist.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect freelist.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect freelist.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect freelist.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect freelist.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect freelist.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect freelist.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect freelist.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect freelist.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect freelist.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect freelist.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect freelist.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect freelist.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect freelist.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect freelist.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect freelist.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect freelist.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect freelist.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect freelist.io.debug.pipeline_empty, io.debug_rob_empty node _T = eq(ren2_alloc_reqs[0], UInt<1>(0h0)) node _T_1 = neq(freelist.io.alloc_pregs[0].bits, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(ren2_alloc_reqs[1], UInt<1>(0h0)) node _T_4 = neq(freelist.io.alloc_pregs[1].bits, UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(ren2_alloc_reqs[2], UInt<1>(0h0)) node _T_7 = neq(freelist.io.alloc_pregs[2].bits, UInt<1>(0h0)) node _T_8 = or(_T_6, _T_7) node _T_9 = and(_T_2, _T_5) node _T_10 = and(_T_9, _T_8) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename-stage] A uop is trying to allocate the zero physical register.\n at rename-stage.scala:300 assert (ren2_alloc_reqs zip freelist.io.alloc_pregs map {case (r,p) => !r || p.bits =/= 0.U} reduce (_&&_),\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _ren2_uops_0_pdst_T = neq(ren2_uops[0].ldst, UInt<1>(0h0)) node _ren2_uops_0_pdst_T_1 = or(_ren2_uops_0_pdst_T, UInt<1>(0h1)) node _ren2_uops_0_pdst_T_2 = mux(_ren2_uops_0_pdst_T_1, freelist.io.alloc_pregs[0].bits, UInt<1>(0h0)) connect ren2_uops[0].pdst, _ren2_uops_0_pdst_T_2 node _ren2_uops_1_pdst_T = neq(ren2_uops[1].ldst, UInt<1>(0h0)) node _ren2_uops_1_pdst_T_1 = or(_ren2_uops_1_pdst_T, UInt<1>(0h1)) node _ren2_uops_1_pdst_T_2 = mux(_ren2_uops_1_pdst_T_1, freelist.io.alloc_pregs[1].bits, UInt<1>(0h0)) connect ren2_uops[1].pdst, _ren2_uops_1_pdst_T_2 node _ren2_uops_2_pdst_T = neq(ren2_uops[2].ldst, UInt<1>(0h0)) node _ren2_uops_2_pdst_T_1 = or(_ren2_uops_2_pdst_T, UInt<1>(0h1)) node _ren2_uops_2_pdst_T_2 = mux(_ren2_uops_2_pdst_T_1, freelist.io.alloc_pregs[2].bits, UInt<1>(0h0)) connect ren2_uops[2].pdst, _ren2_uops_2_pdst_T_2 connect busytable.io.ren_uops[0].debug_tsrc, ren2_uops[0].debug_tsrc connect busytable.io.ren_uops[0].debug_fsrc, ren2_uops[0].debug_fsrc connect busytable.io.ren_uops[0].bp_xcpt_if, ren2_uops[0].bp_xcpt_if connect busytable.io.ren_uops[0].bp_debug_if, ren2_uops[0].bp_debug_if connect busytable.io.ren_uops[0].xcpt_ma_if, ren2_uops[0].xcpt_ma_if connect busytable.io.ren_uops[0].xcpt_ae_if, ren2_uops[0].xcpt_ae_if connect busytable.io.ren_uops[0].xcpt_pf_if, ren2_uops[0].xcpt_pf_if connect busytable.io.ren_uops[0].fp_single, ren2_uops[0].fp_single connect busytable.io.ren_uops[0].fp_val, ren2_uops[0].fp_val connect busytable.io.ren_uops[0].frs3_en, ren2_uops[0].frs3_en connect busytable.io.ren_uops[0].lrs2_rtype, ren2_uops[0].lrs2_rtype connect busytable.io.ren_uops[0].lrs1_rtype, ren2_uops[0].lrs1_rtype connect busytable.io.ren_uops[0].dst_rtype, ren2_uops[0].dst_rtype connect busytable.io.ren_uops[0].ldst_val, ren2_uops[0].ldst_val connect busytable.io.ren_uops[0].lrs3, ren2_uops[0].lrs3 connect busytable.io.ren_uops[0].lrs2, ren2_uops[0].lrs2 connect busytable.io.ren_uops[0].lrs1, ren2_uops[0].lrs1 connect busytable.io.ren_uops[0].ldst, ren2_uops[0].ldst connect busytable.io.ren_uops[0].ldst_is_rs1, ren2_uops[0].ldst_is_rs1 connect busytable.io.ren_uops[0].flush_on_commit, ren2_uops[0].flush_on_commit connect busytable.io.ren_uops[0].is_unique, ren2_uops[0].is_unique connect busytable.io.ren_uops[0].is_sys_pc2epc, ren2_uops[0].is_sys_pc2epc connect busytable.io.ren_uops[0].uses_stq, ren2_uops[0].uses_stq connect busytable.io.ren_uops[0].uses_ldq, ren2_uops[0].uses_ldq connect busytable.io.ren_uops[0].is_amo, ren2_uops[0].is_amo connect busytable.io.ren_uops[0].is_fencei, ren2_uops[0].is_fencei connect busytable.io.ren_uops[0].is_fence, ren2_uops[0].is_fence connect busytable.io.ren_uops[0].mem_signed, ren2_uops[0].mem_signed connect busytable.io.ren_uops[0].mem_size, ren2_uops[0].mem_size connect busytable.io.ren_uops[0].mem_cmd, ren2_uops[0].mem_cmd connect busytable.io.ren_uops[0].bypassable, ren2_uops[0].bypassable connect busytable.io.ren_uops[0].exc_cause, ren2_uops[0].exc_cause connect busytable.io.ren_uops[0].exception, ren2_uops[0].exception connect busytable.io.ren_uops[0].stale_pdst, ren2_uops[0].stale_pdst connect busytable.io.ren_uops[0].ppred_busy, ren2_uops[0].ppred_busy connect busytable.io.ren_uops[0].prs3_busy, ren2_uops[0].prs3_busy connect busytable.io.ren_uops[0].prs2_busy, ren2_uops[0].prs2_busy connect busytable.io.ren_uops[0].prs1_busy, ren2_uops[0].prs1_busy connect busytable.io.ren_uops[0].ppred, ren2_uops[0].ppred connect busytable.io.ren_uops[0].prs3, ren2_uops[0].prs3 connect busytable.io.ren_uops[0].prs2, ren2_uops[0].prs2 connect busytable.io.ren_uops[0].prs1, ren2_uops[0].prs1 connect busytable.io.ren_uops[0].pdst, ren2_uops[0].pdst connect busytable.io.ren_uops[0].rxq_idx, ren2_uops[0].rxq_idx connect busytable.io.ren_uops[0].stq_idx, ren2_uops[0].stq_idx connect busytable.io.ren_uops[0].ldq_idx, ren2_uops[0].ldq_idx connect busytable.io.ren_uops[0].rob_idx, ren2_uops[0].rob_idx connect busytable.io.ren_uops[0].csr_addr, ren2_uops[0].csr_addr connect busytable.io.ren_uops[0].imm_packed, ren2_uops[0].imm_packed connect busytable.io.ren_uops[0].taken, ren2_uops[0].taken connect busytable.io.ren_uops[0].pc_lob, ren2_uops[0].pc_lob connect busytable.io.ren_uops[0].edge_inst, ren2_uops[0].edge_inst connect busytable.io.ren_uops[0].ftq_idx, ren2_uops[0].ftq_idx connect busytable.io.ren_uops[0].br_tag, ren2_uops[0].br_tag connect busytable.io.ren_uops[0].br_mask, ren2_uops[0].br_mask connect busytable.io.ren_uops[0].is_sfb, ren2_uops[0].is_sfb connect busytable.io.ren_uops[0].is_jal, ren2_uops[0].is_jal connect busytable.io.ren_uops[0].is_jalr, ren2_uops[0].is_jalr connect busytable.io.ren_uops[0].is_br, ren2_uops[0].is_br connect busytable.io.ren_uops[0].iw_p2_poisoned, ren2_uops[0].iw_p2_poisoned connect busytable.io.ren_uops[0].iw_p1_poisoned, ren2_uops[0].iw_p1_poisoned connect busytable.io.ren_uops[0].iw_state, ren2_uops[0].iw_state connect busytable.io.ren_uops[0].ctrl.is_std, ren2_uops[0].ctrl.is_std connect busytable.io.ren_uops[0].ctrl.is_sta, ren2_uops[0].ctrl.is_sta connect busytable.io.ren_uops[0].ctrl.is_load, ren2_uops[0].ctrl.is_load connect busytable.io.ren_uops[0].ctrl.csr_cmd, ren2_uops[0].ctrl.csr_cmd connect busytable.io.ren_uops[0].ctrl.fcn_dw, ren2_uops[0].ctrl.fcn_dw connect busytable.io.ren_uops[0].ctrl.op_fcn, ren2_uops[0].ctrl.op_fcn connect busytable.io.ren_uops[0].ctrl.imm_sel, ren2_uops[0].ctrl.imm_sel connect busytable.io.ren_uops[0].ctrl.op2_sel, ren2_uops[0].ctrl.op2_sel connect busytable.io.ren_uops[0].ctrl.op1_sel, ren2_uops[0].ctrl.op1_sel connect busytable.io.ren_uops[0].ctrl.br_type, ren2_uops[0].ctrl.br_type connect busytable.io.ren_uops[0].fu_code, ren2_uops[0].fu_code connect busytable.io.ren_uops[0].iq_type, ren2_uops[0].iq_type connect busytable.io.ren_uops[0].debug_pc, ren2_uops[0].debug_pc connect busytable.io.ren_uops[0].is_rvc, ren2_uops[0].is_rvc connect busytable.io.ren_uops[0].debug_inst, ren2_uops[0].debug_inst connect busytable.io.ren_uops[0].inst, ren2_uops[0].inst connect busytable.io.ren_uops[0].uopc, ren2_uops[0].uopc connect busytable.io.ren_uops[1].debug_tsrc, ren2_uops[1].debug_tsrc connect busytable.io.ren_uops[1].debug_fsrc, ren2_uops[1].debug_fsrc connect busytable.io.ren_uops[1].bp_xcpt_if, ren2_uops[1].bp_xcpt_if connect busytable.io.ren_uops[1].bp_debug_if, ren2_uops[1].bp_debug_if connect busytable.io.ren_uops[1].xcpt_ma_if, ren2_uops[1].xcpt_ma_if connect busytable.io.ren_uops[1].xcpt_ae_if, ren2_uops[1].xcpt_ae_if connect busytable.io.ren_uops[1].xcpt_pf_if, ren2_uops[1].xcpt_pf_if connect busytable.io.ren_uops[1].fp_single, ren2_uops[1].fp_single connect busytable.io.ren_uops[1].fp_val, ren2_uops[1].fp_val connect busytable.io.ren_uops[1].frs3_en, ren2_uops[1].frs3_en connect busytable.io.ren_uops[1].lrs2_rtype, ren2_uops[1].lrs2_rtype connect busytable.io.ren_uops[1].lrs1_rtype, ren2_uops[1].lrs1_rtype connect busytable.io.ren_uops[1].dst_rtype, ren2_uops[1].dst_rtype connect busytable.io.ren_uops[1].ldst_val, ren2_uops[1].ldst_val connect busytable.io.ren_uops[1].lrs3, ren2_uops[1].lrs3 connect busytable.io.ren_uops[1].lrs2, ren2_uops[1].lrs2 connect busytable.io.ren_uops[1].lrs1, ren2_uops[1].lrs1 connect busytable.io.ren_uops[1].ldst, ren2_uops[1].ldst connect busytable.io.ren_uops[1].ldst_is_rs1, ren2_uops[1].ldst_is_rs1 connect busytable.io.ren_uops[1].flush_on_commit, ren2_uops[1].flush_on_commit connect busytable.io.ren_uops[1].is_unique, ren2_uops[1].is_unique connect busytable.io.ren_uops[1].is_sys_pc2epc, ren2_uops[1].is_sys_pc2epc connect busytable.io.ren_uops[1].uses_stq, ren2_uops[1].uses_stq connect busytable.io.ren_uops[1].uses_ldq, ren2_uops[1].uses_ldq connect busytable.io.ren_uops[1].is_amo, ren2_uops[1].is_amo connect busytable.io.ren_uops[1].is_fencei, ren2_uops[1].is_fencei connect busytable.io.ren_uops[1].is_fence, ren2_uops[1].is_fence connect busytable.io.ren_uops[1].mem_signed, ren2_uops[1].mem_signed connect busytable.io.ren_uops[1].mem_size, ren2_uops[1].mem_size connect busytable.io.ren_uops[1].mem_cmd, ren2_uops[1].mem_cmd connect busytable.io.ren_uops[1].bypassable, ren2_uops[1].bypassable connect busytable.io.ren_uops[1].exc_cause, ren2_uops[1].exc_cause connect busytable.io.ren_uops[1].exception, ren2_uops[1].exception connect busytable.io.ren_uops[1].stale_pdst, ren2_uops[1].stale_pdst connect busytable.io.ren_uops[1].ppred_busy, ren2_uops[1].ppred_busy connect busytable.io.ren_uops[1].prs3_busy, ren2_uops[1].prs3_busy connect busytable.io.ren_uops[1].prs2_busy, ren2_uops[1].prs2_busy connect busytable.io.ren_uops[1].prs1_busy, ren2_uops[1].prs1_busy connect busytable.io.ren_uops[1].ppred, ren2_uops[1].ppred connect busytable.io.ren_uops[1].prs3, ren2_uops[1].prs3 connect busytable.io.ren_uops[1].prs2, ren2_uops[1].prs2 connect busytable.io.ren_uops[1].prs1, ren2_uops[1].prs1 connect busytable.io.ren_uops[1].pdst, ren2_uops[1].pdst connect busytable.io.ren_uops[1].rxq_idx, ren2_uops[1].rxq_idx connect busytable.io.ren_uops[1].stq_idx, ren2_uops[1].stq_idx connect busytable.io.ren_uops[1].ldq_idx, ren2_uops[1].ldq_idx connect busytable.io.ren_uops[1].rob_idx, ren2_uops[1].rob_idx connect busytable.io.ren_uops[1].csr_addr, ren2_uops[1].csr_addr connect busytable.io.ren_uops[1].imm_packed, ren2_uops[1].imm_packed connect busytable.io.ren_uops[1].taken, ren2_uops[1].taken connect busytable.io.ren_uops[1].pc_lob, ren2_uops[1].pc_lob connect busytable.io.ren_uops[1].edge_inst, ren2_uops[1].edge_inst connect busytable.io.ren_uops[1].ftq_idx, ren2_uops[1].ftq_idx connect busytable.io.ren_uops[1].br_tag, ren2_uops[1].br_tag connect busytable.io.ren_uops[1].br_mask, ren2_uops[1].br_mask connect busytable.io.ren_uops[1].is_sfb, ren2_uops[1].is_sfb connect busytable.io.ren_uops[1].is_jal, ren2_uops[1].is_jal connect busytable.io.ren_uops[1].is_jalr, ren2_uops[1].is_jalr connect busytable.io.ren_uops[1].is_br, ren2_uops[1].is_br connect busytable.io.ren_uops[1].iw_p2_poisoned, ren2_uops[1].iw_p2_poisoned connect busytable.io.ren_uops[1].iw_p1_poisoned, ren2_uops[1].iw_p1_poisoned connect busytable.io.ren_uops[1].iw_state, ren2_uops[1].iw_state connect busytable.io.ren_uops[1].ctrl.is_std, ren2_uops[1].ctrl.is_std connect busytable.io.ren_uops[1].ctrl.is_sta, ren2_uops[1].ctrl.is_sta connect busytable.io.ren_uops[1].ctrl.is_load, ren2_uops[1].ctrl.is_load connect busytable.io.ren_uops[1].ctrl.csr_cmd, ren2_uops[1].ctrl.csr_cmd connect busytable.io.ren_uops[1].ctrl.fcn_dw, ren2_uops[1].ctrl.fcn_dw connect busytable.io.ren_uops[1].ctrl.op_fcn, ren2_uops[1].ctrl.op_fcn connect busytable.io.ren_uops[1].ctrl.imm_sel, ren2_uops[1].ctrl.imm_sel connect busytable.io.ren_uops[1].ctrl.op2_sel, ren2_uops[1].ctrl.op2_sel connect busytable.io.ren_uops[1].ctrl.op1_sel, ren2_uops[1].ctrl.op1_sel connect busytable.io.ren_uops[1].ctrl.br_type, ren2_uops[1].ctrl.br_type connect busytable.io.ren_uops[1].fu_code, ren2_uops[1].fu_code connect busytable.io.ren_uops[1].iq_type, ren2_uops[1].iq_type connect busytable.io.ren_uops[1].debug_pc, ren2_uops[1].debug_pc connect busytable.io.ren_uops[1].is_rvc, ren2_uops[1].is_rvc connect busytable.io.ren_uops[1].debug_inst, ren2_uops[1].debug_inst connect busytable.io.ren_uops[1].inst, ren2_uops[1].inst connect busytable.io.ren_uops[1].uopc, ren2_uops[1].uopc connect busytable.io.ren_uops[2].debug_tsrc, ren2_uops[2].debug_tsrc connect busytable.io.ren_uops[2].debug_fsrc, ren2_uops[2].debug_fsrc connect busytable.io.ren_uops[2].bp_xcpt_if, ren2_uops[2].bp_xcpt_if connect busytable.io.ren_uops[2].bp_debug_if, ren2_uops[2].bp_debug_if connect busytable.io.ren_uops[2].xcpt_ma_if, ren2_uops[2].xcpt_ma_if connect busytable.io.ren_uops[2].xcpt_ae_if, ren2_uops[2].xcpt_ae_if connect busytable.io.ren_uops[2].xcpt_pf_if, ren2_uops[2].xcpt_pf_if connect busytable.io.ren_uops[2].fp_single, ren2_uops[2].fp_single connect busytable.io.ren_uops[2].fp_val, ren2_uops[2].fp_val connect busytable.io.ren_uops[2].frs3_en, ren2_uops[2].frs3_en connect busytable.io.ren_uops[2].lrs2_rtype, ren2_uops[2].lrs2_rtype connect busytable.io.ren_uops[2].lrs1_rtype, ren2_uops[2].lrs1_rtype connect busytable.io.ren_uops[2].dst_rtype, ren2_uops[2].dst_rtype connect busytable.io.ren_uops[2].ldst_val, ren2_uops[2].ldst_val connect busytable.io.ren_uops[2].lrs3, ren2_uops[2].lrs3 connect busytable.io.ren_uops[2].lrs2, ren2_uops[2].lrs2 connect busytable.io.ren_uops[2].lrs1, ren2_uops[2].lrs1 connect busytable.io.ren_uops[2].ldst, ren2_uops[2].ldst connect busytable.io.ren_uops[2].ldst_is_rs1, ren2_uops[2].ldst_is_rs1 connect busytable.io.ren_uops[2].flush_on_commit, ren2_uops[2].flush_on_commit connect busytable.io.ren_uops[2].is_unique, ren2_uops[2].is_unique connect busytable.io.ren_uops[2].is_sys_pc2epc, ren2_uops[2].is_sys_pc2epc connect busytable.io.ren_uops[2].uses_stq, ren2_uops[2].uses_stq connect busytable.io.ren_uops[2].uses_ldq, ren2_uops[2].uses_ldq connect busytable.io.ren_uops[2].is_amo, ren2_uops[2].is_amo connect busytable.io.ren_uops[2].is_fencei, ren2_uops[2].is_fencei connect busytable.io.ren_uops[2].is_fence, ren2_uops[2].is_fence connect busytable.io.ren_uops[2].mem_signed, ren2_uops[2].mem_signed connect busytable.io.ren_uops[2].mem_size, ren2_uops[2].mem_size connect busytable.io.ren_uops[2].mem_cmd, ren2_uops[2].mem_cmd connect busytable.io.ren_uops[2].bypassable, ren2_uops[2].bypassable connect busytable.io.ren_uops[2].exc_cause, ren2_uops[2].exc_cause connect busytable.io.ren_uops[2].exception, ren2_uops[2].exception connect busytable.io.ren_uops[2].stale_pdst, ren2_uops[2].stale_pdst connect busytable.io.ren_uops[2].ppred_busy, ren2_uops[2].ppred_busy connect busytable.io.ren_uops[2].prs3_busy, ren2_uops[2].prs3_busy connect busytable.io.ren_uops[2].prs2_busy, ren2_uops[2].prs2_busy connect busytable.io.ren_uops[2].prs1_busy, ren2_uops[2].prs1_busy connect busytable.io.ren_uops[2].ppred, ren2_uops[2].ppred connect busytable.io.ren_uops[2].prs3, ren2_uops[2].prs3 connect busytable.io.ren_uops[2].prs2, ren2_uops[2].prs2 connect busytable.io.ren_uops[2].prs1, ren2_uops[2].prs1 connect busytable.io.ren_uops[2].pdst, ren2_uops[2].pdst connect busytable.io.ren_uops[2].rxq_idx, ren2_uops[2].rxq_idx connect busytable.io.ren_uops[2].stq_idx, ren2_uops[2].stq_idx connect busytable.io.ren_uops[2].ldq_idx, ren2_uops[2].ldq_idx connect busytable.io.ren_uops[2].rob_idx, ren2_uops[2].rob_idx connect busytable.io.ren_uops[2].csr_addr, ren2_uops[2].csr_addr connect busytable.io.ren_uops[2].imm_packed, ren2_uops[2].imm_packed connect busytable.io.ren_uops[2].taken, ren2_uops[2].taken connect busytable.io.ren_uops[2].pc_lob, ren2_uops[2].pc_lob connect busytable.io.ren_uops[2].edge_inst, ren2_uops[2].edge_inst connect busytable.io.ren_uops[2].ftq_idx, ren2_uops[2].ftq_idx connect busytable.io.ren_uops[2].br_tag, ren2_uops[2].br_tag connect busytable.io.ren_uops[2].br_mask, ren2_uops[2].br_mask connect busytable.io.ren_uops[2].is_sfb, ren2_uops[2].is_sfb connect busytable.io.ren_uops[2].is_jal, ren2_uops[2].is_jal connect busytable.io.ren_uops[2].is_jalr, ren2_uops[2].is_jalr connect busytable.io.ren_uops[2].is_br, ren2_uops[2].is_br connect busytable.io.ren_uops[2].iw_p2_poisoned, ren2_uops[2].iw_p2_poisoned connect busytable.io.ren_uops[2].iw_p1_poisoned, ren2_uops[2].iw_p1_poisoned connect busytable.io.ren_uops[2].iw_state, ren2_uops[2].iw_state connect busytable.io.ren_uops[2].ctrl.is_std, ren2_uops[2].ctrl.is_std connect busytable.io.ren_uops[2].ctrl.is_sta, ren2_uops[2].ctrl.is_sta connect busytable.io.ren_uops[2].ctrl.is_load, ren2_uops[2].ctrl.is_load connect busytable.io.ren_uops[2].ctrl.csr_cmd, ren2_uops[2].ctrl.csr_cmd connect busytable.io.ren_uops[2].ctrl.fcn_dw, ren2_uops[2].ctrl.fcn_dw connect busytable.io.ren_uops[2].ctrl.op_fcn, ren2_uops[2].ctrl.op_fcn connect busytable.io.ren_uops[2].ctrl.imm_sel, ren2_uops[2].ctrl.imm_sel connect busytable.io.ren_uops[2].ctrl.op2_sel, ren2_uops[2].ctrl.op2_sel connect busytable.io.ren_uops[2].ctrl.op1_sel, ren2_uops[2].ctrl.op1_sel connect busytable.io.ren_uops[2].ctrl.br_type, ren2_uops[2].ctrl.br_type connect busytable.io.ren_uops[2].fu_code, ren2_uops[2].fu_code connect busytable.io.ren_uops[2].iq_type, ren2_uops[2].iq_type connect busytable.io.ren_uops[2].debug_pc, ren2_uops[2].debug_pc connect busytable.io.ren_uops[2].is_rvc, ren2_uops[2].is_rvc connect busytable.io.ren_uops[2].debug_inst, ren2_uops[2].debug_inst connect busytable.io.ren_uops[2].inst, ren2_uops[2].inst connect busytable.io.ren_uops[2].uopc, ren2_uops[2].uopc connect busytable.io.rebusy_reqs[0], ren2_alloc_reqs[0] connect busytable.io.rebusy_reqs[1], ren2_alloc_reqs[1] connect busytable.io.rebusy_reqs[2], ren2_alloc_reqs[2] connect busytable.io.wb_valids[0], io.wakeups[0].valid connect busytable.io.wb_valids[1], io.wakeups[1].valid connect busytable.io.wb_pdsts[0], io.wakeups[0].bits.uop.pdst connect busytable.io.wb_pdsts[1], io.wakeups[1].bits.uop.pdst node _T_14 = neq(io.wakeups[0].bits.uop.dst_rtype, UInt<2>(0h1)) node _T_15 = and(io.wakeups[0].valid, _T_14) node _T_16 = neq(io.wakeups[1].bits.uop.dst_rtype, UInt<2>(0h1)) node _T_17 = and(io.wakeups[1].valid, _T_16) node _T_18 = or(_T_15, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] Wakeup has wrong rtype.\n at rename-stage.scala:317 assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 node _ren2_uops_0_prs1_busy_T = eq(ren2_uops[0].lrs1_rtype, UInt<2>(0h1)) node _ren2_uops_0_prs1_busy_T_1 = and(_ren2_uops_0_prs1_busy_T, busytable.io.busy_resps[0].prs1_busy) connect ren2_uops[0].prs1_busy, _ren2_uops_0_prs1_busy_T_1 node _ren2_uops_0_prs2_busy_T = eq(ren2_uops[0].lrs2_rtype, UInt<2>(0h1)) node _ren2_uops_0_prs2_busy_T_1 = and(_ren2_uops_0_prs2_busy_T, busytable.io.busy_resps[0].prs2_busy) connect ren2_uops[0].prs2_busy, _ren2_uops_0_prs2_busy_T_1 node _ren2_uops_0_prs3_busy_T = and(ren2_uops[0].frs3_en, busytable.io.busy_resps[0].prs3_busy) connect ren2_uops[0].prs3_busy, _ren2_uops_0_prs3_busy_T node _T_23 = and(ren2_valids[0], busytable.io.busy_resps[0].prs1_busy) node _T_24 = eq(UInt<2>(0h1), UInt<2>(0h0)) node _T_25 = and(_T_23, _T_24) node _T_26 = eq(ren2_uops[0].lrs1, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 node _T_32 = and(ren2_valids[0], busytable.io.busy_resps[0].prs2_busy) node _T_33 = eq(UInt<2>(0h1), UInt<2>(0h0)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(ren2_uops[0].lrs2, UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(_T_36, UInt<1>(0h0)) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_3 assert(clock, _T_37, UInt<1>(0h1), "") : assert_3 node _ren2_uops_1_prs1_busy_T = eq(ren2_uops[1].lrs1_rtype, UInt<2>(0h1)) node _ren2_uops_1_prs1_busy_T_1 = and(_ren2_uops_1_prs1_busy_T, busytable.io.busy_resps[1].prs1_busy) connect ren2_uops[1].prs1_busy, _ren2_uops_1_prs1_busy_T_1 node _ren2_uops_1_prs2_busy_T = eq(ren2_uops[1].lrs2_rtype, UInt<2>(0h1)) node _ren2_uops_1_prs2_busy_T_1 = and(_ren2_uops_1_prs2_busy_T, busytable.io.busy_resps[1].prs2_busy) connect ren2_uops[1].prs2_busy, _ren2_uops_1_prs2_busy_T_1 node _ren2_uops_1_prs3_busy_T = and(ren2_uops[1].frs3_en, busytable.io.busy_resps[1].prs3_busy) connect ren2_uops[1].prs3_busy, _ren2_uops_1_prs3_busy_T node _T_41 = and(ren2_valids[1], busytable.io.busy_resps[1].prs1_busy) node _T_42 = eq(UInt<2>(0h1), UInt<2>(0h0)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(ren2_uops[1].lrs1, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(_T_45, UInt<1>(0h0)) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_4 assert(clock, _T_46, UInt<1>(0h1), "") : assert_4 node _T_50 = and(ren2_valids[1], busytable.io.busy_resps[1].prs2_busy) node _T_51 = eq(UInt<2>(0h1), UInt<2>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(ren2_uops[1].lrs2, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(_T_54, UInt<1>(0h0)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_5 assert(clock, _T_55, UInt<1>(0h1), "") : assert_5 node _ren2_uops_2_prs1_busy_T = eq(ren2_uops[2].lrs1_rtype, UInt<2>(0h1)) node _ren2_uops_2_prs1_busy_T_1 = and(_ren2_uops_2_prs1_busy_T, busytable.io.busy_resps[2].prs1_busy) connect ren2_uops[2].prs1_busy, _ren2_uops_2_prs1_busy_T_1 node _ren2_uops_2_prs2_busy_T = eq(ren2_uops[2].lrs2_rtype, UInt<2>(0h1)) node _ren2_uops_2_prs2_busy_T_1 = and(_ren2_uops_2_prs2_busy_T, busytable.io.busy_resps[2].prs2_busy) connect ren2_uops[2].prs2_busy, _ren2_uops_2_prs2_busy_T_1 node _ren2_uops_2_prs3_busy_T = and(ren2_uops[2].frs3_en, busytable.io.busy_resps[2].prs3_busy) connect ren2_uops[2].prs3_busy, _ren2_uops_2_prs3_busy_T node _T_59 = and(ren2_valids[2], busytable.io.busy_resps[2].prs1_busy) node _T_60 = eq(UInt<2>(0h1), UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(ren2_uops[2].lrs1, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_6 assert(clock, _T_64, UInt<1>(0h1), "") : assert_6 node _T_68 = and(ren2_valids[2], busytable.io.busy_resps[2].prs2_busy) node _T_69 = eq(UInt<2>(0h1), UInt<2>(0h0)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(ren2_uops[2].lrs2, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_7 assert(clock, _T_73, UInt<1>(0h1), "") : assert_7 node _io_ren_stalls_0_T = eq(ren2_uops[0].dst_rtype, UInt<2>(0h1)) node _io_ren_stalls_0_T_1 = eq(freelist.io.alloc_pregs[0].valid, UInt<1>(0h0)) node _io_ren_stalls_0_T_2 = and(_io_ren_stalls_0_T, _io_ren_stalls_0_T_1) connect io.ren_stalls[0], _io_ren_stalls_0_T_2 wire bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect bypassed_uop, ren2_uops[0] wire io_ren2_uops_0_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect io_ren2_uops_0_newuop, bypassed_uop node _io_ren2_uops_0_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_ren2_uops_0_newuop_br_mask_T_1 = and(bypassed_uop.br_mask, _io_ren2_uops_0_newuop_br_mask_T) connect io_ren2_uops_0_newuop.br_mask, _io_ren2_uops_0_newuop_br_mask_T_1 connect io.ren2_uops[0], io_ren2_uops_0_newuop node _io_ren_stalls_1_T = eq(ren2_uops[1].dst_rtype, UInt<2>(0h1)) node _io_ren_stalls_1_T_1 = eq(freelist.io.alloc_pregs[1].valid, UInt<1>(0h0)) node _io_ren_stalls_1_T_2 = and(_io_ren_stalls_1_T, _io_ren_stalls_1_T_1) connect io.ren_stalls[1], _io_ren_stalls_1_T_2 wire bypassed_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} wire bypassed_uop_bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect bypassed_uop_bypassed_uop, ren2_uops[1] node _bypassed_uop_bypass_hits_rs1_T = eq(ren2_uops[0].ldst, ren2_uops[1].lrs1) node bypassed_uop_bypass_hits_rs1_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs1_T) node _bypassed_uop_bypass_hits_rs2_T = eq(ren2_uops[0].ldst, ren2_uops[1].lrs2) node bypassed_uop_bypass_hits_rs2_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs2_T) node _bypassed_uop_bypass_hits_rs3_T = eq(ren2_uops[0].ldst, ren2_uops[1].lrs3) node bypassed_uop_bypass_hits_rs3_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs3_T) node _bypassed_uop_bypass_hits_dst_T = eq(ren2_uops[0].ldst, ren2_uops[1].ldst) node bypassed_uop_bypass_hits_dst_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_dst_T) node bypassed_uop_bypass_sel_rs1_enc = mux(bypassed_uop_bypass_hits_rs1_0, UInt<1>(0h1), UInt<1>(0h0)) node bypassed_uop_bypass_sel_rs1_0 = bits(bypassed_uop_bypass_sel_rs1_enc, 0, 0) node bypassed_uop_bypass_sel_rs2_enc = mux(bypassed_uop_bypass_hits_rs2_0, UInt<1>(0h1), UInt<1>(0h0)) node bypassed_uop_bypass_sel_rs2_0 = bits(bypassed_uop_bypass_sel_rs2_enc, 0, 0) node bypassed_uop_bypass_sel_rs3_enc = mux(bypassed_uop_bypass_hits_rs3_0, UInt<1>(0h1), UInt<1>(0h0)) node bypassed_uop_bypass_sel_rs3_0 = bits(bypassed_uop_bypass_sel_rs3_enc, 0, 0) node bypassed_uop_bypass_sel_dst_enc = mux(bypassed_uop_bypass_hits_dst_0, UInt<1>(0h1), UInt<1>(0h0)) node bypassed_uop_bypass_sel_dst_0 = bits(bypassed_uop_bypass_sel_dst_enc, 0, 0) when bypassed_uop_bypass_hits_rs1_0 : connect bypassed_uop_bypassed_uop.prs1, ren2_uops[0].pdst when bypassed_uop_bypass_hits_rs2_0 : connect bypassed_uop_bypassed_uop.prs2, ren2_uops[0].pdst when bypassed_uop_bypass_hits_rs3_0 : connect bypassed_uop_bypassed_uop.prs3, ren2_uops[0].pdst when bypassed_uop_bypass_hits_dst_0 : connect bypassed_uop_bypassed_uop.stale_pdst, ren2_uops[0].pdst node _bypassed_uop_bypassed_uop_prs1_busy_T = or(ren2_uops[1].prs1_busy, bypassed_uop_bypass_hits_rs1_0) connect bypassed_uop_bypassed_uop.prs1_busy, _bypassed_uop_bypassed_uop_prs1_busy_T node _bypassed_uop_bypassed_uop_prs2_busy_T = or(ren2_uops[1].prs2_busy, bypassed_uop_bypass_hits_rs2_0) connect bypassed_uop_bypassed_uop.prs2_busy, _bypassed_uop_bypassed_uop_prs2_busy_T node _bypassed_uop_bypassed_uop_prs3_busy_T = or(ren2_uops[1].prs3_busy, bypassed_uop_bypass_hits_rs3_0) connect bypassed_uop_bypassed_uop.prs3_busy, _bypassed_uop_bypassed_uop_prs3_busy_T connect bypassed_uop_1, bypassed_uop_bypassed_uop wire io_ren2_uops_1_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect io_ren2_uops_1_newuop, bypassed_uop_1 node _io_ren2_uops_1_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_ren2_uops_1_newuop_br_mask_T_1 = and(bypassed_uop_1.br_mask, _io_ren2_uops_1_newuop_br_mask_T) connect io_ren2_uops_1_newuop.br_mask, _io_ren2_uops_1_newuop_br_mask_T_1 connect io.ren2_uops[1], io_ren2_uops_1_newuop node _io_ren_stalls_2_T = eq(ren2_uops[2].dst_rtype, UInt<2>(0h1)) node _io_ren_stalls_2_T_1 = eq(freelist.io.alloc_pregs[2].valid, UInt<1>(0h0)) node _io_ren_stalls_2_T_2 = and(_io_ren_stalls_2_T, _io_ren_stalls_2_T_1) connect io.ren_stalls[2], _io_ren_stalls_2_T_2 wire bypassed_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} wire bypassed_uop_bypassed_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect bypassed_uop_bypassed_uop_1, ren2_uops[2] node _bypassed_uop_bypass_hits_rs1_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].lrs1) node bypassed_uop_bypass_hits_rs1_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs1_T_1) node _bypassed_uop_bypass_hits_rs1_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].lrs1) node bypassed_uop_bypass_hits_rs1_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_rs1_T_2) node _bypassed_uop_bypass_hits_rs2_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].lrs2) node bypassed_uop_bypass_hits_rs2_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs2_T_1) node _bypassed_uop_bypass_hits_rs2_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].lrs2) node bypassed_uop_bypass_hits_rs2_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_rs2_T_2) node _bypassed_uop_bypass_hits_rs3_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].lrs3) node bypassed_uop_bypass_hits_rs3_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs3_T_1) node _bypassed_uop_bypass_hits_rs3_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].lrs3) node bypassed_uop_bypass_hits_rs3_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_rs3_T_2) node _bypassed_uop_bypass_hits_dst_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].ldst) node bypassed_uop_bypass_hits_dst_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_dst_T_1) node _bypassed_uop_bypass_hits_dst_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].ldst) node bypassed_uop_bypass_hits_dst_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_dst_T_2) node _bypassed_uop_bypass_sel_rs1_enc_T = mux(bypassed_uop_bypass_hits_rs1_0_1, UInt<2>(0h2), UInt<2>(0h0)) node bypassed_uop_bypass_sel_rs1_enc_1 = mux(bypassed_uop_bypass_hits_rs1_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_rs1_enc_T) node bypassed_uop_bypass_sel_rs1_1 = bits(bypassed_uop_bypass_sel_rs1_enc_1, 0, 0) node bypassed_uop_bypass_sel_rs1_0_1 = bits(bypassed_uop_bypass_sel_rs1_enc_1, 1, 1) node _bypassed_uop_bypass_sel_rs2_enc_T = mux(bypassed_uop_bypass_hits_rs2_0_1, UInt<2>(0h2), UInt<2>(0h0)) node bypassed_uop_bypass_sel_rs2_enc_1 = mux(bypassed_uop_bypass_hits_rs2_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_rs2_enc_T) node bypassed_uop_bypass_sel_rs2_1 = bits(bypassed_uop_bypass_sel_rs2_enc_1, 0, 0) node bypassed_uop_bypass_sel_rs2_0_1 = bits(bypassed_uop_bypass_sel_rs2_enc_1, 1, 1) node _bypassed_uop_bypass_sel_rs3_enc_T = mux(bypassed_uop_bypass_hits_rs3_0_1, UInt<2>(0h2), UInt<2>(0h0)) node bypassed_uop_bypass_sel_rs3_enc_1 = mux(bypassed_uop_bypass_hits_rs3_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_rs3_enc_T) node bypassed_uop_bypass_sel_rs3_1 = bits(bypassed_uop_bypass_sel_rs3_enc_1, 0, 0) node bypassed_uop_bypass_sel_rs3_0_1 = bits(bypassed_uop_bypass_sel_rs3_enc_1, 1, 1) node _bypassed_uop_bypass_sel_dst_enc_T = mux(bypassed_uop_bypass_hits_dst_0_1, UInt<2>(0h2), UInt<2>(0h0)) node bypassed_uop_bypass_sel_dst_enc_1 = mux(bypassed_uop_bypass_hits_dst_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_dst_enc_T) node bypassed_uop_bypass_sel_dst_1 = bits(bypassed_uop_bypass_sel_dst_enc_1, 0, 0) node bypassed_uop_bypass_sel_dst_0_1 = bits(bypassed_uop_bypass_sel_dst_enc_1, 1, 1) node bypassed_uop_do_bypass_rs1 = or(bypassed_uop_bypass_hits_rs1_0_1, bypassed_uop_bypass_hits_rs1_1) node bypassed_uop_do_bypass_rs2 = or(bypassed_uop_bypass_hits_rs2_0_1, bypassed_uop_bypass_hits_rs2_1) node bypassed_uop_do_bypass_rs3 = or(bypassed_uop_bypass_hits_rs3_0_1, bypassed_uop_bypass_hits_rs3_1) node bypassed_uop_do_bypass_dst = or(bypassed_uop_bypass_hits_dst_0_1, bypassed_uop_bypass_hits_dst_1) when bypassed_uop_do_bypass_rs1 : node _bypassed_uop_bypassed_uop_prs1_T = mux(bypassed_uop_bypass_sel_rs1_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_prs1_T_1 = mux(bypassed_uop_bypass_sel_rs1_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_prs1_T_2 = or(_bypassed_uop_bypassed_uop_prs1_T, _bypassed_uop_bypassed_uop_prs1_T_1) wire _bypassed_uop_bypassed_uop_prs1_WIRE : UInt<7> connect _bypassed_uop_bypassed_uop_prs1_WIRE, _bypassed_uop_bypassed_uop_prs1_T_2 connect bypassed_uop_bypassed_uop_1.prs1, _bypassed_uop_bypassed_uop_prs1_WIRE when bypassed_uop_do_bypass_rs2 : node _bypassed_uop_bypassed_uop_prs2_T = mux(bypassed_uop_bypass_sel_rs2_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_prs2_T_1 = mux(bypassed_uop_bypass_sel_rs2_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_prs2_T_2 = or(_bypassed_uop_bypassed_uop_prs2_T, _bypassed_uop_bypassed_uop_prs2_T_1) wire _bypassed_uop_bypassed_uop_prs2_WIRE : UInt<7> connect _bypassed_uop_bypassed_uop_prs2_WIRE, _bypassed_uop_bypassed_uop_prs2_T_2 connect bypassed_uop_bypassed_uop_1.prs2, _bypassed_uop_bypassed_uop_prs2_WIRE when bypassed_uop_do_bypass_rs3 : node _bypassed_uop_bypassed_uop_prs3_T = mux(bypassed_uop_bypass_sel_rs3_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_prs3_T_1 = mux(bypassed_uop_bypass_sel_rs3_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_prs3_T_2 = or(_bypassed_uop_bypassed_uop_prs3_T, _bypassed_uop_bypassed_uop_prs3_T_1) wire _bypassed_uop_bypassed_uop_prs3_WIRE : UInt<7> connect _bypassed_uop_bypassed_uop_prs3_WIRE, _bypassed_uop_bypassed_uop_prs3_T_2 connect bypassed_uop_bypassed_uop_1.prs3, _bypassed_uop_bypassed_uop_prs3_WIRE when bypassed_uop_do_bypass_dst : node _bypassed_uop_bypassed_uop_stale_pdst_T = mux(bypassed_uop_bypass_sel_dst_0_1, ren2_uops[0].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_stale_pdst_T_1 = mux(bypassed_uop_bypass_sel_dst_1, ren2_uops[1].pdst, UInt<1>(0h0)) node _bypassed_uop_bypassed_uop_stale_pdst_T_2 = or(_bypassed_uop_bypassed_uop_stale_pdst_T, _bypassed_uop_bypassed_uop_stale_pdst_T_1) wire _bypassed_uop_bypassed_uop_stale_pdst_WIRE : UInt<7> connect _bypassed_uop_bypassed_uop_stale_pdst_WIRE, _bypassed_uop_bypassed_uop_stale_pdst_T_2 connect bypassed_uop_bypassed_uop_1.stale_pdst, _bypassed_uop_bypassed_uop_stale_pdst_WIRE node _bypassed_uop_bypassed_uop_prs1_busy_T_1 = or(ren2_uops[2].prs1_busy, bypassed_uop_do_bypass_rs1) connect bypassed_uop_bypassed_uop_1.prs1_busy, _bypassed_uop_bypassed_uop_prs1_busy_T_1 node _bypassed_uop_bypassed_uop_prs2_busy_T_1 = or(ren2_uops[2].prs2_busy, bypassed_uop_do_bypass_rs2) connect bypassed_uop_bypassed_uop_1.prs2_busy, _bypassed_uop_bypassed_uop_prs2_busy_T_1 node _bypassed_uop_bypassed_uop_prs3_busy_T_1 = or(ren2_uops[2].prs3_busy, bypassed_uop_do_bypass_rs3) connect bypassed_uop_bypassed_uop_1.prs3_busy, _bypassed_uop_bypassed_uop_prs3_busy_T_1 connect bypassed_uop_2, bypassed_uop_bypassed_uop_1 wire io_ren2_uops_2_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect io_ren2_uops_2_newuop, bypassed_uop_2 node _io_ren2_uops_2_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_ren2_uops_2_newuop_br_mask_T_1 = and(bypassed_uop_2.br_mask, _io_ren2_uops_2_newuop_br_mask_T) connect io_ren2_uops_2_newuop.br_mask, _io_ren2_uops_2_newuop_br_mask_T_1 connect io.ren2_uops[2], io_ren2_uops_2_newuop connect io.debug.freelist, freelist.io.debug.freelist connect io.debug.isprlist, freelist.io.debug.isprlist connect io.debug.busytable, busytable.io.debug.busytable
module RenameStage_1( // @[rename-stage.scala:160:7] input clock, // @[rename-stage.scala:160:7] input reset, // @[rename-stage.scala:160:7] output io_ren_stalls_0, // @[rename-stage.scala:60:14] output io_ren_stalls_1, // @[rename-stage.scala:60:14] output io_ren_stalls_2, // @[rename-stage.scala:60:14] input io_kill, // @[rename-stage.scala:60:14] input io_dec_fire_0, // @[rename-stage.scala:60:14] input io_dec_fire_1, // @[rename-stage.scala:60:14] input io_dec_fire_2, // @[rename-stage.scala:60:14] input [6:0] io_dec_uops_0_uopc, // @[rename-stage.scala:60:14] input [31:0] io_dec_uops_0_inst, // @[rename-stage.scala:60:14] input [31:0] io_dec_uops_0_debug_inst, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_dec_uops_0_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_dec_uops_0_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_dec_uops_0_fu_code, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_br, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_jalr, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_jal, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_dec_uops_0_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_dec_uops_0_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_dec_uops_0_ftq_idx, // @[rename-stage.scala:60:14] input io_dec_uops_0_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_0_pc_lob, // @[rename-stage.scala:60:14] input io_dec_uops_0_taken, // @[rename-stage.scala:60:14] input [19:0] io_dec_uops_0_imm_packed, // @[rename-stage.scala:60:14] input io_dec_uops_0_exception, // @[rename-stage.scala:60:14] input [63:0] io_dec_uops_0_exc_cause, // @[rename-stage.scala:60:14] input io_dec_uops_0_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_dec_uops_0_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_0_mem_size, // @[rename-stage.scala:60:14] input io_dec_uops_0_mem_signed, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_fence, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_fencei, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_amo, // @[rename-stage.scala:60:14] input io_dec_uops_0_uses_ldq, // @[rename-stage.scala:60:14] input io_dec_uops_0_uses_stq, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_dec_uops_0_is_unique, // @[rename-stage.scala:60:14] input io_dec_uops_0_flush_on_commit, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_0_ldst, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_0_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_0_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_0_lrs3, // @[rename-stage.scala:60:14] input io_dec_uops_0_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_0_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14] input io_dec_uops_0_frs3_en, // @[rename-stage.scala:60:14] input io_dec_uops_0_fp_val, // @[rename-stage.scala:60:14] input io_dec_uops_0_fp_single, // @[rename-stage.scala:60:14] input io_dec_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_dec_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_dec_uops_0_bp_debug_if, // @[rename-stage.scala:60:14] input io_dec_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_0_debug_fsrc, // @[rename-stage.scala:60:14] input [6:0] io_dec_uops_1_uopc, // @[rename-stage.scala:60:14] input [31:0] io_dec_uops_1_inst, // @[rename-stage.scala:60:14] input [31:0] io_dec_uops_1_debug_inst, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_dec_uops_1_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_dec_uops_1_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_dec_uops_1_fu_code, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_br, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_jalr, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_jal, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_dec_uops_1_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_dec_uops_1_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_dec_uops_1_ftq_idx, // @[rename-stage.scala:60:14] input io_dec_uops_1_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_1_pc_lob, // @[rename-stage.scala:60:14] input io_dec_uops_1_taken, // @[rename-stage.scala:60:14] input [19:0] io_dec_uops_1_imm_packed, // @[rename-stage.scala:60:14] input io_dec_uops_1_exception, // @[rename-stage.scala:60:14] input [63:0] io_dec_uops_1_exc_cause, // @[rename-stage.scala:60:14] input io_dec_uops_1_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_dec_uops_1_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_1_mem_size, // @[rename-stage.scala:60:14] input io_dec_uops_1_mem_signed, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_fence, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_fencei, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_amo, // @[rename-stage.scala:60:14] input io_dec_uops_1_uses_ldq, // @[rename-stage.scala:60:14] input io_dec_uops_1_uses_stq, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_dec_uops_1_is_unique, // @[rename-stage.scala:60:14] input io_dec_uops_1_flush_on_commit, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_1_ldst, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_1_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_1_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_1_lrs3, // @[rename-stage.scala:60:14] input io_dec_uops_1_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_1_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_1_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_1_lrs2_rtype, // @[rename-stage.scala:60:14] input io_dec_uops_1_frs3_en, // @[rename-stage.scala:60:14] input io_dec_uops_1_fp_val, // @[rename-stage.scala:60:14] input io_dec_uops_1_fp_single, // @[rename-stage.scala:60:14] input io_dec_uops_1_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_dec_uops_1_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_dec_uops_1_bp_debug_if, // @[rename-stage.scala:60:14] input io_dec_uops_1_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_1_debug_fsrc, // @[rename-stage.scala:60:14] input [6:0] io_dec_uops_2_uopc, // @[rename-stage.scala:60:14] input [31:0] io_dec_uops_2_inst, // @[rename-stage.scala:60:14] input [31:0] io_dec_uops_2_debug_inst, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_dec_uops_2_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_dec_uops_2_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_dec_uops_2_fu_code, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_br, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_jalr, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_jal, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_dec_uops_2_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_dec_uops_2_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_dec_uops_2_ftq_idx, // @[rename-stage.scala:60:14] input io_dec_uops_2_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_2_pc_lob, // @[rename-stage.scala:60:14] input io_dec_uops_2_taken, // @[rename-stage.scala:60:14] input [19:0] io_dec_uops_2_imm_packed, // @[rename-stage.scala:60:14] input io_dec_uops_2_exception, // @[rename-stage.scala:60:14] input [63:0] io_dec_uops_2_exc_cause, // @[rename-stage.scala:60:14] input io_dec_uops_2_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_dec_uops_2_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_2_mem_size, // @[rename-stage.scala:60:14] input io_dec_uops_2_mem_signed, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_fence, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_fencei, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_amo, // @[rename-stage.scala:60:14] input io_dec_uops_2_uses_ldq, // @[rename-stage.scala:60:14] input io_dec_uops_2_uses_stq, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_dec_uops_2_is_unique, // @[rename-stage.scala:60:14] input io_dec_uops_2_flush_on_commit, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_2_ldst, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_2_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_2_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_dec_uops_2_lrs3, // @[rename-stage.scala:60:14] input io_dec_uops_2_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_2_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_2_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_2_lrs2_rtype, // @[rename-stage.scala:60:14] input io_dec_uops_2_frs3_en, // @[rename-stage.scala:60:14] input io_dec_uops_2_fp_val, // @[rename-stage.scala:60:14] input io_dec_uops_2_fp_single, // @[rename-stage.scala:60:14] input io_dec_uops_2_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_dec_uops_2_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_dec_uops_2_bp_debug_if, // @[rename-stage.scala:60:14] input io_dec_uops_2_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_dec_uops_2_debug_fsrc, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_0_pdst, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_0_prs1, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_0_prs2, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_0_prs3, // @[rename-stage.scala:60:14] output io_ren2_uops_0_prs1_busy, // @[rename-stage.scala:60:14] output io_ren2_uops_0_prs2_busy, // @[rename-stage.scala:60:14] output io_ren2_uops_0_prs3_busy, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_0_stale_pdst, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_1_pdst, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_1_prs1, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_1_prs2, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_1_prs3, // @[rename-stage.scala:60:14] output io_ren2_uops_1_prs1_busy, // @[rename-stage.scala:60:14] output io_ren2_uops_1_prs2_busy, // @[rename-stage.scala:60:14] output io_ren2_uops_1_prs3_busy, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_1_stale_pdst, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_2_pdst, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_2_prs1, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_2_prs2, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_2_prs3, // @[rename-stage.scala:60:14] output io_ren2_uops_2_prs1_busy, // @[rename-stage.scala:60:14] output io_ren2_uops_2_prs2_busy, // @[rename-stage.scala:60:14] output io_ren2_uops_2_prs3_busy, // @[rename-stage.scala:60:14] output [6:0] io_ren2_uops_2_stale_pdst, // @[rename-stage.scala:60:14] input [15:0] io_brupdate_b1_resolve_mask, // @[rename-stage.scala:60:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_uopc, // @[rename-stage.scala:60:14] input [31:0] io_brupdate_b2_uop_inst, // @[rename-stage.scala:60:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ctrl_is_load, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_br, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_jalr, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_jal, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_taken, // @[rename-stage.scala:60:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_pdst, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_prs1, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_prs2, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_prs3, // @[rename-stage.scala:60:14] input [4:0] io_brupdate_b2_uop_ppred, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_prs1_busy, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_prs2_busy, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_prs3_busy, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_exception, // @[rename-stage.scala:60:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_mem_signed, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_fence, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_fencei, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_amo, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_uses_ldq, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_uses_stq, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_is_unique, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_flush_on_commit, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_brupdate_b2_uop_ldst, // @[rename-stage.scala:60:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_frs3_en, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_fp_val, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_fp_single, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_bp_debug_if, // @[rename-stage.scala:60:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-stage.scala:60:14] input io_brupdate_b2_valid, // @[rename-stage.scala:60:14] input io_brupdate_b2_mispredict, // @[rename-stage.scala:60:14] input io_brupdate_b2_taken, // @[rename-stage.scala:60:14] input [2:0] io_brupdate_b2_cfi_type, // @[rename-stage.scala:60:14] input [1:0] io_brupdate_b2_pc_sel, // @[rename-stage.scala:60:14] input [39:0] io_brupdate_b2_jalr_target, // @[rename-stage.scala:60:14] input [20:0] io_brupdate_b2_target_offset, // @[rename-stage.scala:60:14] input io_dis_fire_0, // @[rename-stage.scala:60:14] input io_dis_fire_1, // @[rename-stage.scala:60:14] input io_dis_fire_2, // @[rename-stage.scala:60:14] input io_dis_ready, // @[rename-stage.scala:60:14] input io_wakeups_0_valid, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_uopc, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_uop_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_wakeups_0_bits_uop_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_0_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_iw_state, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_br, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_jalr, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_jal, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_wakeups_0_bits_uop_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_taken, // @[rename-stage.scala:60:14] input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_wakeups_0_bits_uop_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_prs1_busy, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_prs2_busy, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_prs3_busy, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_exception, // @[rename-stage.scala:60:14] input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_mem_signed, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_fence, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_fencei, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_amo, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_uses_ldq, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_uses_stq, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_is_unique, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_frs3_en, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_fp_val, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_fp_single, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14] input [63:0] io_wakeups_0_bits_data, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_predicated, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_valid, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_0_bits_fflags_bits_uop_inst, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_br, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_jalr, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_jal, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_wakeups_0_bits_fflags_bits_uop_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_0_bits_fflags_bits_uop_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_taken, // @[rename-stage.scala:60:14] input [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_pdst, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_prs1, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_prs2, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_prs3, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_uop_ppred, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_prs1_busy, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_prs2_busy, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_prs3_busy, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_exception, // @[rename-stage.scala:60:14] input [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_mem_signed, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_fence, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_fencei, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_amo, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_uses_ldq, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_uses_stq, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_is_unique, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_frs3_en, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_fp_val, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_fp_single, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14] input io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_0_bits_fflags_bits_flags, // @[rename-stage.scala:60:14] input io_wakeups_1_valid, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_uopc, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_uop_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_wakeups_1_bits_uop_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_1_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_iw_state, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_br, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_jalr, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_jal, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_wakeups_1_bits_uop_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_taken, // @[rename-stage.scala:60:14] input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_wakeups_1_bits_uop_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_prs1_busy, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_prs2_busy, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_prs3_busy, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_exception, // @[rename-stage.scala:60:14] input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_mem_signed, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_fence, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_fencei, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_amo, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_uses_ldq, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_uses_stq, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_is_unique, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_frs3_en, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_fp_val, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_fp_single, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14] input [63:0] io_wakeups_1_bits_data, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_valid, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_uopc, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_1_bits_fflags_bits_uop_inst, // @[rename-stage.scala:60:14] input [31:0] io_wakeups_1_bits_fflags_bits_uop_debug_inst, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_wakeups_1_bits_fflags_bits_uop_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_fflags_bits_uop_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_wakeups_1_bits_fflags_bits_uop_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_iw_state, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_br, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_jalr, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_jal, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_wakeups_1_bits_fflags_bits_uop_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_wakeups_1_bits_fflags_bits_uop_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_uop_ftq_idx, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_fflags_bits_uop_pc_lob, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_taken, // @[rename-stage.scala:60:14] input [19:0] io_wakeups_1_bits_fflags_bits_uop_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_wakeups_1_bits_fflags_bits_uop_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_uop_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_uop_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_pdst, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_prs1, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_prs2, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_prs3, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_uop_ppred, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_prs1_busy, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_prs2_busy, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_prs3_busy, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_wakeups_1_bits_fflags_bits_uop_stale_pdst, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_exception, // @[rename-stage.scala:60:14] input [63:0] io_wakeups_1_bits_fflags_bits_uop_exc_cause, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_uop_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_mem_size, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_mem_signed, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_fence, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_fencei, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_amo, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_uses_ldq, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_uses_stq, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_is_unique, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_fflags_bits_uop_ldst, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs3, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_frs3_en, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_fp_val, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_fp_single, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14] input io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14] input [4:0] io_wakeups_1_bits_fflags_bits_flags, // @[rename-stage.scala:60:14] input io_com_valids_0, // @[rename-stage.scala:60:14] input io_com_valids_1, // @[rename-stage.scala:60:14] input io_com_valids_2, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_uopc, // @[rename-stage.scala:60:14] input [31:0] io_com_uops_0_inst, // @[rename-stage.scala:60:14] input [31:0] io_com_uops_0_debug_inst, // @[rename-stage.scala:60:14] input io_com_uops_0_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_com_uops_0_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_0_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_com_uops_0_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_com_uops_0_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_0_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_0_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_0_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_com_uops_0_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_0_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_com_uops_0_ctrl_is_load, // @[rename-stage.scala:60:14] input io_com_uops_0_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_com_uops_0_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_iw_state, // @[rename-stage.scala:60:14] input io_com_uops_0_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_com_uops_0_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_com_uops_0_is_br, // @[rename-stage.scala:60:14] input io_com_uops_0_is_jalr, // @[rename-stage.scala:60:14] input io_com_uops_0_is_jal, // @[rename-stage.scala:60:14] input io_com_uops_0_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_com_uops_0_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_com_uops_0_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_0_ftq_idx, // @[rename-stage.scala:60:14] input io_com_uops_0_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_0_pc_lob, // @[rename-stage.scala:60:14] input io_com_uops_0_taken, // @[rename-stage.scala:60:14] input [19:0] io_com_uops_0_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_com_uops_0_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_0_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_0_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_pdst, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_prs1, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_prs2, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_prs3, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_0_ppred, // @[rename-stage.scala:60:14] input io_com_uops_0_prs1_busy, // @[rename-stage.scala:60:14] input io_com_uops_0_prs2_busy, // @[rename-stage.scala:60:14] input io_com_uops_0_prs3_busy, // @[rename-stage.scala:60:14] input io_com_uops_0_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_0_stale_pdst, // @[rename-stage.scala:60:14] input io_com_uops_0_exception, // @[rename-stage.scala:60:14] input [63:0] io_com_uops_0_exc_cause, // @[rename-stage.scala:60:14] input io_com_uops_0_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_0_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_mem_size, // @[rename-stage.scala:60:14] input io_com_uops_0_mem_signed, // @[rename-stage.scala:60:14] input io_com_uops_0_is_fence, // @[rename-stage.scala:60:14] input io_com_uops_0_is_fencei, // @[rename-stage.scala:60:14] input io_com_uops_0_is_amo, // @[rename-stage.scala:60:14] input io_com_uops_0_uses_ldq, // @[rename-stage.scala:60:14] input io_com_uops_0_uses_stq, // @[rename-stage.scala:60:14] input io_com_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_com_uops_0_is_unique, // @[rename-stage.scala:60:14] input io_com_uops_0_flush_on_commit, // @[rename-stage.scala:60:14] input io_com_uops_0_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_0_ldst, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_0_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_0_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_0_lrs3, // @[rename-stage.scala:60:14] input io_com_uops_0_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14] input io_com_uops_0_frs3_en, // @[rename-stage.scala:60:14] input io_com_uops_0_fp_val, // @[rename-stage.scala:60:14] input io_com_uops_0_fp_single, // @[rename-stage.scala:60:14] input io_com_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_com_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_com_uops_0_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_com_uops_0_bp_debug_if, // @[rename-stage.scala:60:14] input io_com_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_0_debug_tsrc, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_uopc, // @[rename-stage.scala:60:14] input [31:0] io_com_uops_1_inst, // @[rename-stage.scala:60:14] input [31:0] io_com_uops_1_debug_inst, // @[rename-stage.scala:60:14] input io_com_uops_1_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_com_uops_1_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_1_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_com_uops_1_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_com_uops_1_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_1_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_1_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_1_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_com_uops_1_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_1_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_com_uops_1_ctrl_is_load, // @[rename-stage.scala:60:14] input io_com_uops_1_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_com_uops_1_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_iw_state, // @[rename-stage.scala:60:14] input io_com_uops_1_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_com_uops_1_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_com_uops_1_is_br, // @[rename-stage.scala:60:14] input io_com_uops_1_is_jalr, // @[rename-stage.scala:60:14] input io_com_uops_1_is_jal, // @[rename-stage.scala:60:14] input io_com_uops_1_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_com_uops_1_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_com_uops_1_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_1_ftq_idx, // @[rename-stage.scala:60:14] input io_com_uops_1_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_1_pc_lob, // @[rename-stage.scala:60:14] input io_com_uops_1_taken, // @[rename-stage.scala:60:14] input [19:0] io_com_uops_1_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_com_uops_1_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_1_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_1_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_pdst, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_prs1, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_prs2, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_prs3, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_1_ppred, // @[rename-stage.scala:60:14] input io_com_uops_1_prs1_busy, // @[rename-stage.scala:60:14] input io_com_uops_1_prs2_busy, // @[rename-stage.scala:60:14] input io_com_uops_1_prs3_busy, // @[rename-stage.scala:60:14] input io_com_uops_1_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_1_stale_pdst, // @[rename-stage.scala:60:14] input io_com_uops_1_exception, // @[rename-stage.scala:60:14] input [63:0] io_com_uops_1_exc_cause, // @[rename-stage.scala:60:14] input io_com_uops_1_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_1_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_mem_size, // @[rename-stage.scala:60:14] input io_com_uops_1_mem_signed, // @[rename-stage.scala:60:14] input io_com_uops_1_is_fence, // @[rename-stage.scala:60:14] input io_com_uops_1_is_fencei, // @[rename-stage.scala:60:14] input io_com_uops_1_is_amo, // @[rename-stage.scala:60:14] input io_com_uops_1_uses_ldq, // @[rename-stage.scala:60:14] input io_com_uops_1_uses_stq, // @[rename-stage.scala:60:14] input io_com_uops_1_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_com_uops_1_is_unique, // @[rename-stage.scala:60:14] input io_com_uops_1_flush_on_commit, // @[rename-stage.scala:60:14] input io_com_uops_1_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_1_ldst, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_1_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_1_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_1_lrs3, // @[rename-stage.scala:60:14] input io_com_uops_1_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_lrs2_rtype, // @[rename-stage.scala:60:14] input io_com_uops_1_frs3_en, // @[rename-stage.scala:60:14] input io_com_uops_1_fp_val, // @[rename-stage.scala:60:14] input io_com_uops_1_fp_single, // @[rename-stage.scala:60:14] input io_com_uops_1_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_com_uops_1_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_com_uops_1_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_com_uops_1_bp_debug_if, // @[rename-stage.scala:60:14] input io_com_uops_1_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_1_debug_tsrc, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_uopc, // @[rename-stage.scala:60:14] input [31:0] io_com_uops_2_inst, // @[rename-stage.scala:60:14] input [31:0] io_com_uops_2_debug_inst, // @[rename-stage.scala:60:14] input io_com_uops_2_is_rvc, // @[rename-stage.scala:60:14] input [39:0] io_com_uops_2_debug_pc, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_2_iq_type, // @[rename-stage.scala:60:14] input [9:0] io_com_uops_2_fu_code, // @[rename-stage.scala:60:14] input [3:0] io_com_uops_2_ctrl_br_type, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_ctrl_op1_sel, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_2_ctrl_op2_sel, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_2_ctrl_imm_sel, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_2_ctrl_op_fcn, // @[rename-stage.scala:60:14] input io_com_uops_2_ctrl_fcn_dw, // @[rename-stage.scala:60:14] input [2:0] io_com_uops_2_ctrl_csr_cmd, // @[rename-stage.scala:60:14] input io_com_uops_2_ctrl_is_load, // @[rename-stage.scala:60:14] input io_com_uops_2_ctrl_is_sta, // @[rename-stage.scala:60:14] input io_com_uops_2_ctrl_is_std, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_iw_state, // @[rename-stage.scala:60:14] input io_com_uops_2_iw_p1_poisoned, // @[rename-stage.scala:60:14] input io_com_uops_2_iw_p2_poisoned, // @[rename-stage.scala:60:14] input io_com_uops_2_is_br, // @[rename-stage.scala:60:14] input io_com_uops_2_is_jalr, // @[rename-stage.scala:60:14] input io_com_uops_2_is_jal, // @[rename-stage.scala:60:14] input io_com_uops_2_is_sfb, // @[rename-stage.scala:60:14] input [15:0] io_com_uops_2_br_mask, // @[rename-stage.scala:60:14] input [3:0] io_com_uops_2_br_tag, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_2_ftq_idx, // @[rename-stage.scala:60:14] input io_com_uops_2_edge_inst, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_2_pc_lob, // @[rename-stage.scala:60:14] input io_com_uops_2_taken, // @[rename-stage.scala:60:14] input [19:0] io_com_uops_2_imm_packed, // @[rename-stage.scala:60:14] input [11:0] io_com_uops_2_csr_addr, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_rob_idx, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_2_ldq_idx, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_2_stq_idx, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_rxq_idx, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_pdst, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_prs1, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_prs2, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_prs3, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_2_ppred, // @[rename-stage.scala:60:14] input io_com_uops_2_prs1_busy, // @[rename-stage.scala:60:14] input io_com_uops_2_prs2_busy, // @[rename-stage.scala:60:14] input io_com_uops_2_prs3_busy, // @[rename-stage.scala:60:14] input io_com_uops_2_ppred_busy, // @[rename-stage.scala:60:14] input [6:0] io_com_uops_2_stale_pdst, // @[rename-stage.scala:60:14] input io_com_uops_2_exception, // @[rename-stage.scala:60:14] input [63:0] io_com_uops_2_exc_cause, // @[rename-stage.scala:60:14] input io_com_uops_2_bypassable, // @[rename-stage.scala:60:14] input [4:0] io_com_uops_2_mem_cmd, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_mem_size, // @[rename-stage.scala:60:14] input io_com_uops_2_mem_signed, // @[rename-stage.scala:60:14] input io_com_uops_2_is_fence, // @[rename-stage.scala:60:14] input io_com_uops_2_is_fencei, // @[rename-stage.scala:60:14] input io_com_uops_2_is_amo, // @[rename-stage.scala:60:14] input io_com_uops_2_uses_ldq, // @[rename-stage.scala:60:14] input io_com_uops_2_uses_stq, // @[rename-stage.scala:60:14] input io_com_uops_2_is_sys_pc2epc, // @[rename-stage.scala:60:14] input io_com_uops_2_is_unique, // @[rename-stage.scala:60:14] input io_com_uops_2_flush_on_commit, // @[rename-stage.scala:60:14] input io_com_uops_2_ldst_is_rs1, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_2_ldst, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_2_lrs1, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_2_lrs2, // @[rename-stage.scala:60:14] input [5:0] io_com_uops_2_lrs3, // @[rename-stage.scala:60:14] input io_com_uops_2_ldst_val, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_dst_rtype, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_lrs1_rtype, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_lrs2_rtype, // @[rename-stage.scala:60:14] input io_com_uops_2_frs3_en, // @[rename-stage.scala:60:14] input io_com_uops_2_fp_val, // @[rename-stage.scala:60:14] input io_com_uops_2_fp_single, // @[rename-stage.scala:60:14] input io_com_uops_2_xcpt_pf_if, // @[rename-stage.scala:60:14] input io_com_uops_2_xcpt_ae_if, // @[rename-stage.scala:60:14] input io_com_uops_2_xcpt_ma_if, // @[rename-stage.scala:60:14] input io_com_uops_2_bp_debug_if, // @[rename-stage.scala:60:14] input io_com_uops_2_bp_xcpt_if, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_debug_fsrc, // @[rename-stage.scala:60:14] input [1:0] io_com_uops_2_debug_tsrc, // @[rename-stage.scala:60:14] input io_rbk_valids_0, // @[rename-stage.scala:60:14] input io_rbk_valids_1, // @[rename-stage.scala:60:14] input io_rbk_valids_2, // @[rename-stage.scala:60:14] input io_rollback, // @[rename-stage.scala:60:14] input io_debug_rob_empty // @[rename-stage.scala:60:14] ); wire [1:0] bypassed_uop_2_debug_tsrc; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_debug_fsrc; // @[rename-stage.scala:341:28] wire bypassed_uop_2_bp_xcpt_if; // @[rename-stage.scala:341:28] wire bypassed_uop_2_bp_debug_if; // @[rename-stage.scala:341:28] wire bypassed_uop_2_xcpt_ma_if; // @[rename-stage.scala:341:28] wire bypassed_uop_2_xcpt_ae_if; // @[rename-stage.scala:341:28] wire bypassed_uop_2_xcpt_pf_if; // @[rename-stage.scala:341:28] wire bypassed_uop_2_fp_single; // @[rename-stage.scala:341:28] wire bypassed_uop_2_fp_val; // @[rename-stage.scala:341:28] wire bypassed_uop_2_frs3_en; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_lrs2_rtype; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_lrs1_rtype; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_dst_rtype; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ldst_val; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_2_lrs3; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_2_lrs2; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_2_lrs1; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_2_ldst; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ldst_is_rs1; // @[rename-stage.scala:341:28] wire bypassed_uop_2_flush_on_commit; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_unique; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_sys_pc2epc; // @[rename-stage.scala:341:28] wire bypassed_uop_2_uses_stq; // @[rename-stage.scala:341:28] wire bypassed_uop_2_uses_ldq; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_amo; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_fencei; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_fence; // @[rename-stage.scala:341:28] wire bypassed_uop_2_mem_signed; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_mem_size; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_2_mem_cmd; // @[rename-stage.scala:341:28] wire bypassed_uop_2_bypassable; // @[rename-stage.scala:341:28] wire [63:0] bypassed_uop_2_exc_cause; // @[rename-stage.scala:341:28] wire bypassed_uop_2_exception; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_stale_pdst; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ppred_busy; // @[rename-stage.scala:341:28] wire bypassed_uop_2_prs3_busy; // @[rename-stage.scala:341:28] wire bypassed_uop_2_prs2_busy; // @[rename-stage.scala:341:28] wire bypassed_uop_2_prs1_busy; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_2_ppred; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_prs3; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_prs2; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_prs1; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_pdst; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_rxq_idx; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_2_stq_idx; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_2_ldq_idx; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_rob_idx; // @[rename-stage.scala:341:28] wire [11:0] bypassed_uop_2_csr_addr; // @[rename-stage.scala:341:28] wire [19:0] bypassed_uop_2_imm_packed; // @[rename-stage.scala:341:28] wire bypassed_uop_2_taken; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_2_pc_lob; // @[rename-stage.scala:341:28] wire bypassed_uop_2_edge_inst; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_2_ftq_idx; // @[rename-stage.scala:341:28] wire [3:0] bypassed_uop_2_br_tag; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_sfb; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_jal; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_jalr; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_br; // @[rename-stage.scala:341:28] wire bypassed_uop_2_iw_p2_poisoned; // @[rename-stage.scala:341:28] wire bypassed_uop_2_iw_p1_poisoned; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_iw_state; // @[rename-stage.scala:341:28] wire [9:0] bypassed_uop_2_fu_code; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_2_iq_type; // @[rename-stage.scala:341:28] wire [39:0] bypassed_uop_2_debug_pc; // @[rename-stage.scala:341:28] wire bypassed_uop_2_is_rvc; // @[rename-stage.scala:341:28] wire [31:0] bypassed_uop_2_debug_inst; // @[rename-stage.scala:341:28] wire [31:0] bypassed_uop_2_inst; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_2_uopc; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ctrl_is_std; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ctrl_is_sta; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ctrl_is_load; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:341:28] wire bypassed_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_2_ctrl_op_fcn; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_2_ctrl_imm_sel; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_2_ctrl_op2_sel; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_2_ctrl_op1_sel; // @[rename-stage.scala:341:28] wire [3:0] bypassed_uop_2_ctrl_br_type; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_debug_tsrc; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_debug_fsrc; // @[rename-stage.scala:341:28] wire bypassed_uop_1_bp_xcpt_if; // @[rename-stage.scala:341:28] wire bypassed_uop_1_bp_debug_if; // @[rename-stage.scala:341:28] wire bypassed_uop_1_xcpt_ma_if; // @[rename-stage.scala:341:28] wire bypassed_uop_1_xcpt_ae_if; // @[rename-stage.scala:341:28] wire bypassed_uop_1_xcpt_pf_if; // @[rename-stage.scala:341:28] wire bypassed_uop_1_fp_single; // @[rename-stage.scala:341:28] wire bypassed_uop_1_fp_val; // @[rename-stage.scala:341:28] wire bypassed_uop_1_frs3_en; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_lrs2_rtype; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_lrs1_rtype; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_dst_rtype; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ldst_val; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_1_lrs3; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_1_lrs2; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_1_lrs1; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_1_ldst; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ldst_is_rs1; // @[rename-stage.scala:341:28] wire bypassed_uop_1_flush_on_commit; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_unique; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_sys_pc2epc; // @[rename-stage.scala:341:28] wire bypassed_uop_1_uses_stq; // @[rename-stage.scala:341:28] wire bypassed_uop_1_uses_ldq; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_amo; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_fencei; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_fence; // @[rename-stage.scala:341:28] wire bypassed_uop_1_mem_signed; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_mem_size; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_1_mem_cmd; // @[rename-stage.scala:341:28] wire bypassed_uop_1_bypassable; // @[rename-stage.scala:341:28] wire [63:0] bypassed_uop_1_exc_cause; // @[rename-stage.scala:341:28] wire bypassed_uop_1_exception; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_stale_pdst; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ppred_busy; // @[rename-stage.scala:341:28] wire bypassed_uop_1_prs3_busy; // @[rename-stage.scala:341:28] wire bypassed_uop_1_prs2_busy; // @[rename-stage.scala:341:28] wire bypassed_uop_1_prs1_busy; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_1_ppred; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_prs3; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_prs2; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_prs1; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_pdst; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_rxq_idx; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_1_stq_idx; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_1_ldq_idx; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_rob_idx; // @[rename-stage.scala:341:28] wire [11:0] bypassed_uop_1_csr_addr; // @[rename-stage.scala:341:28] wire [19:0] bypassed_uop_1_imm_packed; // @[rename-stage.scala:341:28] wire bypassed_uop_1_taken; // @[rename-stage.scala:341:28] wire [5:0] bypassed_uop_1_pc_lob; // @[rename-stage.scala:341:28] wire bypassed_uop_1_edge_inst; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_1_ftq_idx; // @[rename-stage.scala:341:28] wire [3:0] bypassed_uop_1_br_tag; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_sfb; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_jal; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_jalr; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_br; // @[rename-stage.scala:341:28] wire bypassed_uop_1_iw_p2_poisoned; // @[rename-stage.scala:341:28] wire bypassed_uop_1_iw_p1_poisoned; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_iw_state; // @[rename-stage.scala:341:28] wire [9:0] bypassed_uop_1_fu_code; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_1_iq_type; // @[rename-stage.scala:341:28] wire [39:0] bypassed_uop_1_debug_pc; // @[rename-stage.scala:341:28] wire bypassed_uop_1_is_rvc; // @[rename-stage.scala:341:28] wire [31:0] bypassed_uop_1_debug_inst; // @[rename-stage.scala:341:28] wire [31:0] bypassed_uop_1_inst; // @[rename-stage.scala:341:28] wire [6:0] bypassed_uop_1_uopc; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ctrl_is_std; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ctrl_is_sta; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ctrl_is_load; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:341:28] wire bypassed_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:341:28] wire [4:0] bypassed_uop_1_ctrl_op_fcn; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_1_ctrl_imm_sel; // @[rename-stage.scala:341:28] wire [2:0] bypassed_uop_1_ctrl_op2_sel; // @[rename-stage.scala:341:28] wire [1:0] bypassed_uop_1_ctrl_op1_sel; // @[rename-stage.scala:341:28] wire [3:0] bypassed_uop_1_ctrl_br_type; // @[rename-stage.scala:341:28] wire [6:0] r_uop_bypassed_uop_2_stale_pdst; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_2_prs3_busy; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_2_prs2_busy; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_2_prs1_busy; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_2_prs3; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_2_prs2; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_2_prs1; // @[rename-stage.scala:174:28] wire [1:0] next_uop_2_debug_tsrc; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_debug_fsrc; // @[rename-stage.scala:123:24] wire next_uop_2_bp_xcpt_if; // @[rename-stage.scala:123:24] wire next_uop_2_bp_debug_if; // @[rename-stage.scala:123:24] wire next_uop_2_xcpt_ma_if; // @[rename-stage.scala:123:24] wire next_uop_2_xcpt_ae_if; // @[rename-stage.scala:123:24] wire next_uop_2_xcpt_pf_if; // @[rename-stage.scala:123:24] wire next_uop_2_fp_single; // @[rename-stage.scala:123:24] wire next_uop_2_fp_val; // @[rename-stage.scala:123:24] wire next_uop_2_frs3_en; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_lrs2_rtype; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_lrs1_rtype; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_dst_rtype; // @[rename-stage.scala:123:24] wire next_uop_2_ldst_val; // @[rename-stage.scala:123:24] wire [5:0] next_uop_2_lrs3; // @[rename-stage.scala:123:24] wire [5:0] next_uop_2_lrs2; // @[rename-stage.scala:123:24] wire [5:0] next_uop_2_lrs1; // @[rename-stage.scala:123:24] wire [5:0] next_uop_2_ldst; // @[rename-stage.scala:123:24] wire next_uop_2_ldst_is_rs1; // @[rename-stage.scala:123:24] wire next_uop_2_flush_on_commit; // @[rename-stage.scala:123:24] wire next_uop_2_is_unique; // @[rename-stage.scala:123:24] wire next_uop_2_is_sys_pc2epc; // @[rename-stage.scala:123:24] wire next_uop_2_uses_stq; // @[rename-stage.scala:123:24] wire next_uop_2_uses_ldq; // @[rename-stage.scala:123:24] wire next_uop_2_is_amo; // @[rename-stage.scala:123:24] wire next_uop_2_is_fencei; // @[rename-stage.scala:123:24] wire next_uop_2_is_fence; // @[rename-stage.scala:123:24] wire next_uop_2_mem_signed; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_mem_size; // @[rename-stage.scala:123:24] wire [4:0] next_uop_2_mem_cmd; // @[rename-stage.scala:123:24] wire next_uop_2_bypassable; // @[rename-stage.scala:123:24] wire [63:0] next_uop_2_exc_cause; // @[rename-stage.scala:123:24] wire next_uop_2_exception; // @[rename-stage.scala:123:24] wire next_uop_2_ppred_busy; // @[rename-stage.scala:123:24] wire [4:0] next_uop_2_ppred; // @[rename-stage.scala:123:24] wire [6:0] next_uop_2_pdst; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_rxq_idx; // @[rename-stage.scala:123:24] wire [4:0] next_uop_2_stq_idx; // @[rename-stage.scala:123:24] wire [4:0] next_uop_2_ldq_idx; // @[rename-stage.scala:123:24] wire [6:0] next_uop_2_rob_idx; // @[rename-stage.scala:123:24] wire [11:0] next_uop_2_csr_addr; // @[rename-stage.scala:123:24] wire [19:0] next_uop_2_imm_packed; // @[rename-stage.scala:123:24] wire next_uop_2_taken; // @[rename-stage.scala:123:24] wire [5:0] next_uop_2_pc_lob; // @[rename-stage.scala:123:24] wire next_uop_2_edge_inst; // @[rename-stage.scala:123:24] wire [4:0] next_uop_2_ftq_idx; // @[rename-stage.scala:123:24] wire [3:0] next_uop_2_br_tag; // @[rename-stage.scala:123:24] wire [15:0] next_uop_2_br_mask; // @[rename-stage.scala:123:24] wire next_uop_2_is_sfb; // @[rename-stage.scala:123:24] wire next_uop_2_is_jal; // @[rename-stage.scala:123:24] wire next_uop_2_is_jalr; // @[rename-stage.scala:123:24] wire next_uop_2_is_br; // @[rename-stage.scala:123:24] wire next_uop_2_iw_p2_poisoned; // @[rename-stage.scala:123:24] wire next_uop_2_iw_p1_poisoned; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_iw_state; // @[rename-stage.scala:123:24] wire [9:0] next_uop_2_fu_code; // @[rename-stage.scala:123:24] wire [2:0] next_uop_2_iq_type; // @[rename-stage.scala:123:24] wire [39:0] next_uop_2_debug_pc; // @[rename-stage.scala:123:24] wire next_uop_2_is_rvc; // @[rename-stage.scala:123:24] wire [31:0] next_uop_2_debug_inst; // @[rename-stage.scala:123:24] wire [31:0] next_uop_2_inst; // @[rename-stage.scala:123:24] wire [6:0] next_uop_2_uopc; // @[rename-stage.scala:123:24] wire next_uop_2_ctrl_is_std; // @[rename-stage.scala:123:24] wire next_uop_2_ctrl_is_sta; // @[rename-stage.scala:123:24] wire next_uop_2_ctrl_is_load; // @[rename-stage.scala:123:24] wire [2:0] next_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:123:24] wire next_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:123:24] wire [4:0] next_uop_2_ctrl_op_fcn; // @[rename-stage.scala:123:24] wire [2:0] next_uop_2_ctrl_imm_sel; // @[rename-stage.scala:123:24] wire [2:0] next_uop_2_ctrl_op2_sel; // @[rename-stage.scala:123:24] wire [1:0] next_uop_2_ctrl_op1_sel; // @[rename-stage.scala:123:24] wire [3:0] next_uop_2_ctrl_br_type; // @[rename-stage.scala:123:24] wire [6:0] r_uop_bypassed_uop_1_stale_pdst; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_1_prs3_busy; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_1_prs2_busy; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_1_prs1_busy; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_1_prs3; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_1_prs2; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_1_prs1; // @[rename-stage.scala:174:28] wire [1:0] next_uop_1_debug_tsrc; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_debug_fsrc; // @[rename-stage.scala:123:24] wire next_uop_1_bp_xcpt_if; // @[rename-stage.scala:123:24] wire next_uop_1_bp_debug_if; // @[rename-stage.scala:123:24] wire next_uop_1_xcpt_ma_if; // @[rename-stage.scala:123:24] wire next_uop_1_xcpt_ae_if; // @[rename-stage.scala:123:24] wire next_uop_1_xcpt_pf_if; // @[rename-stage.scala:123:24] wire next_uop_1_fp_single; // @[rename-stage.scala:123:24] wire next_uop_1_fp_val; // @[rename-stage.scala:123:24] wire next_uop_1_frs3_en; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_lrs2_rtype; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_lrs1_rtype; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_dst_rtype; // @[rename-stage.scala:123:24] wire next_uop_1_ldst_val; // @[rename-stage.scala:123:24] wire [5:0] next_uop_1_lrs3; // @[rename-stage.scala:123:24] wire [5:0] next_uop_1_lrs2; // @[rename-stage.scala:123:24] wire [5:0] next_uop_1_lrs1; // @[rename-stage.scala:123:24] wire [5:0] next_uop_1_ldst; // @[rename-stage.scala:123:24] wire next_uop_1_ldst_is_rs1; // @[rename-stage.scala:123:24] wire next_uop_1_flush_on_commit; // @[rename-stage.scala:123:24] wire next_uop_1_is_unique; // @[rename-stage.scala:123:24] wire next_uop_1_is_sys_pc2epc; // @[rename-stage.scala:123:24] wire next_uop_1_uses_stq; // @[rename-stage.scala:123:24] wire next_uop_1_uses_ldq; // @[rename-stage.scala:123:24] wire next_uop_1_is_amo; // @[rename-stage.scala:123:24] wire next_uop_1_is_fencei; // @[rename-stage.scala:123:24] wire next_uop_1_is_fence; // @[rename-stage.scala:123:24] wire next_uop_1_mem_signed; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_mem_size; // @[rename-stage.scala:123:24] wire [4:0] next_uop_1_mem_cmd; // @[rename-stage.scala:123:24] wire next_uop_1_bypassable; // @[rename-stage.scala:123:24] wire [63:0] next_uop_1_exc_cause; // @[rename-stage.scala:123:24] wire next_uop_1_exception; // @[rename-stage.scala:123:24] wire next_uop_1_ppred_busy; // @[rename-stage.scala:123:24] wire [4:0] next_uop_1_ppred; // @[rename-stage.scala:123:24] wire [6:0] next_uop_1_pdst; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_rxq_idx; // @[rename-stage.scala:123:24] wire [4:0] next_uop_1_stq_idx; // @[rename-stage.scala:123:24] wire [4:0] next_uop_1_ldq_idx; // @[rename-stage.scala:123:24] wire [6:0] next_uop_1_rob_idx; // @[rename-stage.scala:123:24] wire [11:0] next_uop_1_csr_addr; // @[rename-stage.scala:123:24] wire [19:0] next_uop_1_imm_packed; // @[rename-stage.scala:123:24] wire next_uop_1_taken; // @[rename-stage.scala:123:24] wire [5:0] next_uop_1_pc_lob; // @[rename-stage.scala:123:24] wire next_uop_1_edge_inst; // @[rename-stage.scala:123:24] wire [4:0] next_uop_1_ftq_idx; // @[rename-stage.scala:123:24] wire [3:0] next_uop_1_br_tag; // @[rename-stage.scala:123:24] wire [15:0] next_uop_1_br_mask; // @[rename-stage.scala:123:24] wire next_uop_1_is_sfb; // @[rename-stage.scala:123:24] wire next_uop_1_is_jal; // @[rename-stage.scala:123:24] wire next_uop_1_is_jalr; // @[rename-stage.scala:123:24] wire next_uop_1_is_br; // @[rename-stage.scala:123:24] wire next_uop_1_iw_p2_poisoned; // @[rename-stage.scala:123:24] wire next_uop_1_iw_p1_poisoned; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_iw_state; // @[rename-stage.scala:123:24] wire [9:0] next_uop_1_fu_code; // @[rename-stage.scala:123:24] wire [2:0] next_uop_1_iq_type; // @[rename-stage.scala:123:24] wire [39:0] next_uop_1_debug_pc; // @[rename-stage.scala:123:24] wire next_uop_1_is_rvc; // @[rename-stage.scala:123:24] wire [31:0] next_uop_1_debug_inst; // @[rename-stage.scala:123:24] wire [31:0] next_uop_1_inst; // @[rename-stage.scala:123:24] wire [6:0] next_uop_1_uopc; // @[rename-stage.scala:123:24] wire next_uop_1_ctrl_is_std; // @[rename-stage.scala:123:24] wire next_uop_1_ctrl_is_sta; // @[rename-stage.scala:123:24] wire next_uop_1_ctrl_is_load; // @[rename-stage.scala:123:24] wire [2:0] next_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:123:24] wire next_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:123:24] wire [4:0] next_uop_1_ctrl_op_fcn; // @[rename-stage.scala:123:24] wire [2:0] next_uop_1_ctrl_imm_sel; // @[rename-stage.scala:123:24] wire [2:0] next_uop_1_ctrl_op2_sel; // @[rename-stage.scala:123:24] wire [1:0] next_uop_1_ctrl_op1_sel; // @[rename-stage.scala:123:24] wire [3:0] next_uop_1_ctrl_br_type; // @[rename-stage.scala:123:24] wire [6:0] r_uop_bypassed_uop_stale_pdst; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_prs3_busy; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_prs2_busy; // @[rename-stage.scala:174:28] wire r_uop_bypassed_uop_prs1_busy; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_prs3; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_prs2; // @[rename-stage.scala:174:28] wire [6:0] r_uop_bypassed_uop_prs1; // @[rename-stage.scala:174:28] wire [1:0] next_uop_debug_tsrc; // @[rename-stage.scala:123:24] wire [1:0] next_uop_debug_fsrc; // @[rename-stage.scala:123:24] wire next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24] wire next_uop_bp_debug_if; // @[rename-stage.scala:123:24] wire next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24] wire next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24] wire next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24] wire next_uop_fp_single; // @[rename-stage.scala:123:24] wire next_uop_fp_val; // @[rename-stage.scala:123:24] wire next_uop_frs3_en; // @[rename-stage.scala:123:24] wire [1:0] next_uop_lrs2_rtype; // @[rename-stage.scala:123:24] wire [1:0] next_uop_lrs1_rtype; // @[rename-stage.scala:123:24] wire [1:0] next_uop_dst_rtype; // @[rename-stage.scala:123:24] wire next_uop_ldst_val; // @[rename-stage.scala:123:24] wire [5:0] next_uop_lrs3; // @[rename-stage.scala:123:24] wire [5:0] next_uop_lrs2; // @[rename-stage.scala:123:24] wire [5:0] next_uop_lrs1; // @[rename-stage.scala:123:24] wire [5:0] next_uop_ldst; // @[rename-stage.scala:123:24] wire next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24] wire next_uop_flush_on_commit; // @[rename-stage.scala:123:24] wire next_uop_is_unique; // @[rename-stage.scala:123:24] wire next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24] wire next_uop_uses_stq; // @[rename-stage.scala:123:24] wire next_uop_uses_ldq; // @[rename-stage.scala:123:24] wire next_uop_is_amo; // @[rename-stage.scala:123:24] wire next_uop_is_fencei; // @[rename-stage.scala:123:24] wire next_uop_is_fence; // @[rename-stage.scala:123:24] wire next_uop_mem_signed; // @[rename-stage.scala:123:24] wire [1:0] next_uop_mem_size; // @[rename-stage.scala:123:24] wire [4:0] next_uop_mem_cmd; // @[rename-stage.scala:123:24] wire next_uop_bypassable; // @[rename-stage.scala:123:24] wire [63:0] next_uop_exc_cause; // @[rename-stage.scala:123:24] wire next_uop_exception; // @[rename-stage.scala:123:24] wire next_uop_ppred_busy; // @[rename-stage.scala:123:24] wire [4:0] next_uop_ppred; // @[rename-stage.scala:123:24] wire [6:0] next_uop_pdst; // @[rename-stage.scala:123:24] wire [1:0] next_uop_rxq_idx; // @[rename-stage.scala:123:24] wire [4:0] next_uop_stq_idx; // @[rename-stage.scala:123:24] wire [4:0] next_uop_ldq_idx; // @[rename-stage.scala:123:24] wire [6:0] next_uop_rob_idx; // @[rename-stage.scala:123:24] wire [11:0] next_uop_csr_addr; // @[rename-stage.scala:123:24] wire [19:0] next_uop_imm_packed; // @[rename-stage.scala:123:24] wire next_uop_taken; // @[rename-stage.scala:123:24] wire [5:0] next_uop_pc_lob; // @[rename-stage.scala:123:24] wire next_uop_edge_inst; // @[rename-stage.scala:123:24] wire [4:0] next_uop_ftq_idx; // @[rename-stage.scala:123:24] wire [3:0] next_uop_br_tag; // @[rename-stage.scala:123:24] wire [15:0] next_uop_br_mask; // @[rename-stage.scala:123:24] wire next_uop_is_sfb; // @[rename-stage.scala:123:24] wire next_uop_is_jal; // @[rename-stage.scala:123:24] wire next_uop_is_jalr; // @[rename-stage.scala:123:24] wire next_uop_is_br; // @[rename-stage.scala:123:24] wire next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24] wire next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24] wire [1:0] next_uop_iw_state; // @[rename-stage.scala:123:24] wire [9:0] next_uop_fu_code; // @[rename-stage.scala:123:24] wire [2:0] next_uop_iq_type; // @[rename-stage.scala:123:24] wire [39:0] next_uop_debug_pc; // @[rename-stage.scala:123:24] wire next_uop_is_rvc; // @[rename-stage.scala:123:24] wire [31:0] next_uop_debug_inst; // @[rename-stage.scala:123:24] wire [31:0] next_uop_inst; // @[rename-stage.scala:123:24] wire [6:0] next_uop_uopc; // @[rename-stage.scala:123:24] wire next_uop_ctrl_is_std; // @[rename-stage.scala:123:24] wire next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24] wire next_uop_ctrl_is_load; // @[rename-stage.scala:123:24] wire [2:0] next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24] wire next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24] wire [4:0] next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24] wire [2:0] next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24] wire [2:0] next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24] wire [1:0] next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24] wire [3:0] next_uop_ctrl_br_type; // @[rename-stage.scala:123:24] wire [1:0] ren2_uops_2_debug_tsrc; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_debug_fsrc; // @[rename-stage.scala:108:29] wire ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:108:29] wire ren2_uops_2_bp_debug_if; // @[rename-stage.scala:108:29] wire ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:108:29] wire ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:108:29] wire ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:108:29] wire ren2_uops_2_fp_single; // @[rename-stage.scala:108:29] wire ren2_uops_2_fp_val; // @[rename-stage.scala:108:29] wire ren2_uops_2_frs3_en; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_dst_rtype; // @[rename-stage.scala:108:29] wire ren2_uops_2_ldst_val; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_2_lrs3; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_2_lrs2; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_2_lrs1; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_2_ldst; // @[rename-stage.scala:108:29] wire ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:108:29] wire ren2_uops_2_flush_on_commit; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_unique; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:108:29] wire ren2_uops_2_uses_stq; // @[rename-stage.scala:108:29] wire ren2_uops_2_uses_ldq; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_amo; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_fencei; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_fence; // @[rename-stage.scala:108:29] wire ren2_uops_2_mem_signed; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_mem_size; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_2_mem_cmd; // @[rename-stage.scala:108:29] wire ren2_uops_2_bypassable; // @[rename-stage.scala:108:29] wire [63:0] ren2_uops_2_exc_cause; // @[rename-stage.scala:108:29] wire ren2_uops_2_exception; // @[rename-stage.scala:108:29] wire ren2_uops_2_ppred_busy; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_2_ppred; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_pdst; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_rxq_idx; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_2_stq_idx; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_2_ldq_idx; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_rob_idx; // @[rename-stage.scala:108:29] wire [11:0] ren2_uops_2_csr_addr; // @[rename-stage.scala:108:29] wire [19:0] ren2_uops_2_imm_packed; // @[rename-stage.scala:108:29] wire ren2_uops_2_taken; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_2_pc_lob; // @[rename-stage.scala:108:29] wire ren2_uops_2_edge_inst; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_2_ftq_idx; // @[rename-stage.scala:108:29] wire [3:0] ren2_uops_2_br_tag; // @[rename-stage.scala:108:29] wire [15:0] ren2_uops_2_br_mask; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_sfb; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_jal; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_jalr; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_br; // @[rename-stage.scala:108:29] wire ren2_uops_2_iw_p2_poisoned; // @[rename-stage.scala:108:29] wire ren2_uops_2_iw_p1_poisoned; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_iw_state; // @[rename-stage.scala:108:29] wire [9:0] ren2_uops_2_fu_code; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_2_iq_type; // @[rename-stage.scala:108:29] wire [39:0] ren2_uops_2_debug_pc; // @[rename-stage.scala:108:29] wire ren2_uops_2_is_rvc; // @[rename-stage.scala:108:29] wire [31:0] ren2_uops_2_debug_inst; // @[rename-stage.scala:108:29] wire [31:0] ren2_uops_2_inst; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_uopc; // @[rename-stage.scala:108:29] wire ren2_uops_2_ctrl_is_std; // @[rename-stage.scala:108:29] wire ren2_uops_2_ctrl_is_sta; // @[rename-stage.scala:108:29] wire ren2_uops_2_ctrl_is_load; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:108:29] wire ren2_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_2_ctrl_op_fcn; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_2_ctrl_imm_sel; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_2_ctrl_op2_sel; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_2_ctrl_op1_sel; // @[rename-stage.scala:108:29] wire [3:0] ren2_uops_2_ctrl_br_type; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_debug_tsrc; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_debug_fsrc; // @[rename-stage.scala:108:29] wire ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:108:29] wire ren2_uops_1_bp_debug_if; // @[rename-stage.scala:108:29] wire ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:108:29] wire ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:108:29] wire ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:108:29] wire ren2_uops_1_fp_single; // @[rename-stage.scala:108:29] wire ren2_uops_1_fp_val; // @[rename-stage.scala:108:29] wire ren2_uops_1_frs3_en; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_dst_rtype; // @[rename-stage.scala:108:29] wire ren2_uops_1_ldst_val; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_1_lrs3; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_1_lrs2; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_1_lrs1; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_1_ldst; // @[rename-stage.scala:108:29] wire ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:108:29] wire ren2_uops_1_flush_on_commit; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_unique; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:108:29] wire ren2_uops_1_uses_stq; // @[rename-stage.scala:108:29] wire ren2_uops_1_uses_ldq; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_amo; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_fencei; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_fence; // @[rename-stage.scala:108:29] wire ren2_uops_1_mem_signed; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_mem_size; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_1_mem_cmd; // @[rename-stage.scala:108:29] wire ren2_uops_1_bypassable; // @[rename-stage.scala:108:29] wire [63:0] ren2_uops_1_exc_cause; // @[rename-stage.scala:108:29] wire ren2_uops_1_exception; // @[rename-stage.scala:108:29] wire ren2_uops_1_ppred_busy; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_1_ppred; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_1_pdst; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_rxq_idx; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_1_stq_idx; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_1_ldq_idx; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_1_rob_idx; // @[rename-stage.scala:108:29] wire [11:0] ren2_uops_1_csr_addr; // @[rename-stage.scala:108:29] wire [19:0] ren2_uops_1_imm_packed; // @[rename-stage.scala:108:29] wire ren2_uops_1_taken; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_1_pc_lob; // @[rename-stage.scala:108:29] wire ren2_uops_1_edge_inst; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_1_ftq_idx; // @[rename-stage.scala:108:29] wire [3:0] ren2_uops_1_br_tag; // @[rename-stage.scala:108:29] wire [15:0] ren2_uops_1_br_mask; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_sfb; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_jal; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_jalr; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_br; // @[rename-stage.scala:108:29] wire ren2_uops_1_iw_p2_poisoned; // @[rename-stage.scala:108:29] wire ren2_uops_1_iw_p1_poisoned; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_iw_state; // @[rename-stage.scala:108:29] wire [9:0] ren2_uops_1_fu_code; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_1_iq_type; // @[rename-stage.scala:108:29] wire [39:0] ren2_uops_1_debug_pc; // @[rename-stage.scala:108:29] wire ren2_uops_1_is_rvc; // @[rename-stage.scala:108:29] wire [31:0] ren2_uops_1_debug_inst; // @[rename-stage.scala:108:29] wire [31:0] ren2_uops_1_inst; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_1_uopc; // @[rename-stage.scala:108:29] wire ren2_uops_1_ctrl_is_std; // @[rename-stage.scala:108:29] wire ren2_uops_1_ctrl_is_sta; // @[rename-stage.scala:108:29] wire ren2_uops_1_ctrl_is_load; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:108:29] wire ren2_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_1_ctrl_op_fcn; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_1_ctrl_imm_sel; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_1_ctrl_op2_sel; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_1_ctrl_op1_sel; // @[rename-stage.scala:108:29] wire [3:0] ren2_uops_1_ctrl_br_type; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29] wire ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29] wire ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29] wire ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29] wire ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29] wire ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29] wire ren2_uops_0_fp_single; // @[rename-stage.scala:108:29] wire ren2_uops_0_fp_val; // @[rename-stage.scala:108:29] wire ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29] wire ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_0_lrs3; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_0_lrs2; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_0_lrs1; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_0_ldst; // @[rename-stage.scala:108:29] wire ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29] wire ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_unique; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29] wire ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29] wire ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_amo; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_fence; // @[rename-stage.scala:108:29] wire ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_mem_size; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29] wire ren2_uops_0_bypassable; // @[rename-stage.scala:108:29] wire [63:0] ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29] wire ren2_uops_0_exception; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29] wire ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29] wire ren2_uops_0_prs3_busy; // @[rename-stage.scala:108:29] wire ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29] wire ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_0_ppred; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_prs3; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_prs2; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_prs1; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_pdst; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29] wire [11:0] ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29] wire [19:0] ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29] wire ren2_uops_0_taken; // @[rename-stage.scala:108:29] wire [5:0] ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29] wire ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29] wire [3:0] ren2_uops_0_br_tag; // @[rename-stage.scala:108:29] wire [15:0] ren2_uops_0_br_mask; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_jal; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_br; // @[rename-stage.scala:108:29] wire ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29] wire ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_iw_state; // @[rename-stage.scala:108:29] wire [9:0] ren2_uops_0_fu_code; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_0_iq_type; // @[rename-stage.scala:108:29] wire [39:0] ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29] wire ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29] wire [31:0] ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29] wire [31:0] ren2_uops_0_inst; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_0_uopc; // @[rename-stage.scala:108:29] wire ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29] wire ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29] wire ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29] wire ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29] wire [4:0] ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29] wire [2:0] ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29] wire [1:0] ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29] wire [3:0] ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29] wire _busytable_io_busy_resps_0_prs1_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_0_prs2_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_0_prs3_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_1_prs1_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_1_prs2_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_1_prs3_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_2_prs1_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_2_prs2_busy; // @[rename-stage.scala:224:25] wire _busytable_io_busy_resps_2_prs3_busy; // @[rename-stage.scala:224:25] wire _freelist_io_alloc_pregs_0_valid; // @[rename-stage.scala:220:24] wire [6:0] _freelist_io_alloc_pregs_0_bits; // @[rename-stage.scala:220:24] wire _freelist_io_alloc_pregs_1_valid; // @[rename-stage.scala:220:24] wire [6:0] _freelist_io_alloc_pregs_1_bits; // @[rename-stage.scala:220:24] wire _freelist_io_alloc_pregs_2_valid; // @[rename-stage.scala:220:24] wire [6:0] _freelist_io_alloc_pregs_2_bits; // @[rename-stage.scala:220:24] wire io_kill_0 = io_kill; // @[rename-stage.scala:160:7] wire io_dec_fire_0_0 = io_dec_fire_0; // @[rename-stage.scala:160:7] wire io_dec_fire_1_0 = io_dec_fire_1; // @[rename-stage.scala:160:7] wire io_dec_fire_2_0 = io_dec_fire_2; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_0_uopc_0 = io_dec_uops_0_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_dec_uops_0_inst_0 = io_dec_uops_0_inst; // @[rename-stage.scala:160:7] wire [31:0] io_dec_uops_0_debug_inst_0 = io_dec_uops_0_debug_inst; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_rvc_0 = io_dec_uops_0_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_dec_uops_0_debug_pc_0 = io_dec_uops_0_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_0_iq_type_0 = io_dec_uops_0_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_dec_uops_0_fu_code_0 = io_dec_uops_0_fu_code; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_br_0 = io_dec_uops_0_is_br; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_jalr_0 = io_dec_uops_0_is_jalr; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_jal_0 = io_dec_uops_0_is_jal; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_sfb_0 = io_dec_uops_0_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_dec_uops_0_br_mask_0 = io_dec_uops_0_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_dec_uops_0_br_tag_0 = io_dec_uops_0_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_0_ftq_idx_0 = io_dec_uops_0_ftq_idx; // @[rename-stage.scala:160:7] wire io_dec_uops_0_edge_inst_0 = io_dec_uops_0_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_0_pc_lob_0 = io_dec_uops_0_pc_lob; // @[rename-stage.scala:160:7] wire io_dec_uops_0_taken_0 = io_dec_uops_0_taken; // @[rename-stage.scala:160:7] wire [19:0] io_dec_uops_0_imm_packed_0 = io_dec_uops_0_imm_packed; // @[rename-stage.scala:160:7] wire io_dec_uops_0_exception_0 = io_dec_uops_0_exception; // @[rename-stage.scala:160:7] wire [63:0] io_dec_uops_0_exc_cause_0 = io_dec_uops_0_exc_cause; // @[rename-stage.scala:160:7] wire io_dec_uops_0_bypassable_0 = io_dec_uops_0_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_0_mem_cmd_0 = io_dec_uops_0_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_mem_size_0 = io_dec_uops_0_mem_size; // @[rename-stage.scala:160:7] wire io_dec_uops_0_mem_signed_0 = io_dec_uops_0_mem_signed; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_fence_0 = io_dec_uops_0_is_fence; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_fencei_0 = io_dec_uops_0_is_fencei; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_amo_0 = io_dec_uops_0_is_amo; // @[rename-stage.scala:160:7] wire io_dec_uops_0_uses_ldq_0 = io_dec_uops_0_uses_ldq; // @[rename-stage.scala:160:7] wire io_dec_uops_0_uses_stq_0 = io_dec_uops_0_uses_stq; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_sys_pc2epc_0 = io_dec_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_dec_uops_0_is_unique_0 = io_dec_uops_0_is_unique; // @[rename-stage.scala:160:7] wire io_dec_uops_0_flush_on_commit_0 = io_dec_uops_0_flush_on_commit; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_0_ldst_0 = io_dec_uops_0_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_0_lrs1_0 = io_dec_uops_0_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_0_lrs2_0 = io_dec_uops_0_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_0_lrs3_0 = io_dec_uops_0_lrs3; // @[rename-stage.scala:160:7] wire io_dec_uops_0_ldst_val_0 = io_dec_uops_0_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_dst_rtype_0 = io_dec_uops_0_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_lrs1_rtype_0 = io_dec_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_lrs2_rtype_0 = io_dec_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_dec_uops_0_frs3_en_0 = io_dec_uops_0_frs3_en; // @[rename-stage.scala:160:7] wire io_dec_uops_0_fp_val_0 = io_dec_uops_0_fp_val; // @[rename-stage.scala:160:7] wire io_dec_uops_0_fp_single_0 = io_dec_uops_0_fp_single; // @[rename-stage.scala:160:7] wire io_dec_uops_0_xcpt_pf_if_0 = io_dec_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_dec_uops_0_xcpt_ae_if_0 = io_dec_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_dec_uops_0_bp_debug_if_0 = io_dec_uops_0_bp_debug_if; // @[rename-stage.scala:160:7] wire io_dec_uops_0_bp_xcpt_if_0 = io_dec_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_debug_fsrc_0 = io_dec_uops_0_debug_fsrc; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_uopc_0 = io_dec_uops_1_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_dec_uops_1_inst_0 = io_dec_uops_1_inst; // @[rename-stage.scala:160:7] wire [31:0] io_dec_uops_1_debug_inst_0 = io_dec_uops_1_debug_inst; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_rvc_0 = io_dec_uops_1_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_dec_uops_1_debug_pc_0 = io_dec_uops_1_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_1_iq_type_0 = io_dec_uops_1_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_dec_uops_1_fu_code_0 = io_dec_uops_1_fu_code; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_br_0 = io_dec_uops_1_is_br; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_jalr_0 = io_dec_uops_1_is_jalr; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_jal_0 = io_dec_uops_1_is_jal; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_sfb_0 = io_dec_uops_1_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_dec_uops_1_br_mask_0 = io_dec_uops_1_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_dec_uops_1_br_tag_0 = io_dec_uops_1_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_1_ftq_idx_0 = io_dec_uops_1_ftq_idx; // @[rename-stage.scala:160:7] wire io_dec_uops_1_edge_inst_0 = io_dec_uops_1_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_1_pc_lob_0 = io_dec_uops_1_pc_lob; // @[rename-stage.scala:160:7] wire io_dec_uops_1_taken_0 = io_dec_uops_1_taken; // @[rename-stage.scala:160:7] wire [19:0] io_dec_uops_1_imm_packed_0 = io_dec_uops_1_imm_packed; // @[rename-stage.scala:160:7] wire io_dec_uops_1_exception_0 = io_dec_uops_1_exception; // @[rename-stage.scala:160:7] wire [63:0] io_dec_uops_1_exc_cause_0 = io_dec_uops_1_exc_cause; // @[rename-stage.scala:160:7] wire io_dec_uops_1_bypassable_0 = io_dec_uops_1_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_1_mem_cmd_0 = io_dec_uops_1_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_mem_size_0 = io_dec_uops_1_mem_size; // @[rename-stage.scala:160:7] wire io_dec_uops_1_mem_signed_0 = io_dec_uops_1_mem_signed; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_fence_0 = io_dec_uops_1_is_fence; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_fencei_0 = io_dec_uops_1_is_fencei; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_amo_0 = io_dec_uops_1_is_amo; // @[rename-stage.scala:160:7] wire io_dec_uops_1_uses_ldq_0 = io_dec_uops_1_uses_ldq; // @[rename-stage.scala:160:7] wire io_dec_uops_1_uses_stq_0 = io_dec_uops_1_uses_stq; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_sys_pc2epc_0 = io_dec_uops_1_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_dec_uops_1_is_unique_0 = io_dec_uops_1_is_unique; // @[rename-stage.scala:160:7] wire io_dec_uops_1_flush_on_commit_0 = io_dec_uops_1_flush_on_commit; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_1_ldst_0 = io_dec_uops_1_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_1_lrs1_0 = io_dec_uops_1_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_1_lrs2_0 = io_dec_uops_1_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_1_lrs3_0 = io_dec_uops_1_lrs3; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ldst_val_0 = io_dec_uops_1_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_dst_rtype_0 = io_dec_uops_1_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_lrs1_rtype_0 = io_dec_uops_1_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_lrs2_rtype_0 = io_dec_uops_1_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_dec_uops_1_frs3_en_0 = io_dec_uops_1_frs3_en; // @[rename-stage.scala:160:7] wire io_dec_uops_1_fp_val_0 = io_dec_uops_1_fp_val; // @[rename-stage.scala:160:7] wire io_dec_uops_1_fp_single_0 = io_dec_uops_1_fp_single; // @[rename-stage.scala:160:7] wire io_dec_uops_1_xcpt_pf_if_0 = io_dec_uops_1_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_dec_uops_1_xcpt_ae_if_0 = io_dec_uops_1_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_dec_uops_1_bp_debug_if_0 = io_dec_uops_1_bp_debug_if; // @[rename-stage.scala:160:7] wire io_dec_uops_1_bp_xcpt_if_0 = io_dec_uops_1_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_debug_fsrc_0 = io_dec_uops_1_debug_fsrc; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_uopc_0 = io_dec_uops_2_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_dec_uops_2_inst_0 = io_dec_uops_2_inst; // @[rename-stage.scala:160:7] wire [31:0] io_dec_uops_2_debug_inst_0 = io_dec_uops_2_debug_inst; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_rvc_0 = io_dec_uops_2_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_dec_uops_2_debug_pc_0 = io_dec_uops_2_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_2_iq_type_0 = io_dec_uops_2_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_dec_uops_2_fu_code_0 = io_dec_uops_2_fu_code; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_br_0 = io_dec_uops_2_is_br; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_jalr_0 = io_dec_uops_2_is_jalr; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_jal_0 = io_dec_uops_2_is_jal; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_sfb_0 = io_dec_uops_2_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_dec_uops_2_br_mask_0 = io_dec_uops_2_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_dec_uops_2_br_tag_0 = io_dec_uops_2_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_2_ftq_idx_0 = io_dec_uops_2_ftq_idx; // @[rename-stage.scala:160:7] wire io_dec_uops_2_edge_inst_0 = io_dec_uops_2_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_2_pc_lob_0 = io_dec_uops_2_pc_lob; // @[rename-stage.scala:160:7] wire io_dec_uops_2_taken_0 = io_dec_uops_2_taken; // @[rename-stage.scala:160:7] wire [19:0] io_dec_uops_2_imm_packed_0 = io_dec_uops_2_imm_packed; // @[rename-stage.scala:160:7] wire io_dec_uops_2_exception_0 = io_dec_uops_2_exception; // @[rename-stage.scala:160:7] wire [63:0] io_dec_uops_2_exc_cause_0 = io_dec_uops_2_exc_cause; // @[rename-stage.scala:160:7] wire io_dec_uops_2_bypassable_0 = io_dec_uops_2_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_2_mem_cmd_0 = io_dec_uops_2_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_mem_size_0 = io_dec_uops_2_mem_size; // @[rename-stage.scala:160:7] wire io_dec_uops_2_mem_signed_0 = io_dec_uops_2_mem_signed; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_fence_0 = io_dec_uops_2_is_fence; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_fencei_0 = io_dec_uops_2_is_fencei; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_amo_0 = io_dec_uops_2_is_amo; // @[rename-stage.scala:160:7] wire io_dec_uops_2_uses_ldq_0 = io_dec_uops_2_uses_ldq; // @[rename-stage.scala:160:7] wire io_dec_uops_2_uses_stq_0 = io_dec_uops_2_uses_stq; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_sys_pc2epc_0 = io_dec_uops_2_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_dec_uops_2_is_unique_0 = io_dec_uops_2_is_unique; // @[rename-stage.scala:160:7] wire io_dec_uops_2_flush_on_commit_0 = io_dec_uops_2_flush_on_commit; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_2_ldst_0 = io_dec_uops_2_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_2_lrs1_0 = io_dec_uops_2_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_2_lrs2_0 = io_dec_uops_2_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_dec_uops_2_lrs3_0 = io_dec_uops_2_lrs3; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ldst_val_0 = io_dec_uops_2_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_dst_rtype_0 = io_dec_uops_2_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_lrs1_rtype_0 = io_dec_uops_2_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_lrs2_rtype_0 = io_dec_uops_2_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_dec_uops_2_frs3_en_0 = io_dec_uops_2_frs3_en; // @[rename-stage.scala:160:7] wire io_dec_uops_2_fp_val_0 = io_dec_uops_2_fp_val; // @[rename-stage.scala:160:7] wire io_dec_uops_2_fp_single_0 = io_dec_uops_2_fp_single; // @[rename-stage.scala:160:7] wire io_dec_uops_2_xcpt_pf_if_0 = io_dec_uops_2_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_dec_uops_2_xcpt_ae_if_0 = io_dec_uops_2_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_dec_uops_2_bp_debug_if_0 = io_dec_uops_2_bp_debug_if; // @[rename-stage.scala:160:7] wire io_dec_uops_2_bp_xcpt_if_0 = io_dec_uops_2_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_debug_fsrc_0 = io_dec_uops_2_debug_fsrc; // @[rename-stage.scala:160:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-stage.scala:160:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-stage.scala:160:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-stage.scala:160:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-stage.scala:160:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-stage.scala:160:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-stage.scala:160:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rename-stage.scala:160:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-stage.scala:160:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-stage.scala:160:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-stage.scala:160:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-stage.scala:160:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-stage.scala:160:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-stage.scala:160:7] wire io_dis_fire_0_0 = io_dis_fire_0; // @[rename-stage.scala:160:7] wire io_dis_fire_1_0 = io_dis_fire_1; // @[rename-stage.scala:160:7] wire io_dis_fire_2_0 = io_dis_fire_2; // @[rename-stage.scala:160:7] wire io_dis_ready_0 = io_dis_ready; // @[rename-stage.scala:160:7] wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_uopc_0 = io_wakeups_0_bits_uop_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_uop_iq_type_0 = io_wakeups_0_bits_uop_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_wakeups_0_bits_uop_fu_code_0 = io_wakeups_0_bits_uop_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_0_bits_uop_ctrl_br_type_0 = io_wakeups_0_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel_0 = io_wakeups_0_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel_0 = io_wakeups_0_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel_0 = io_wakeups_0_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn_0 = io_wakeups_0_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ctrl_fcn_dw_0 = io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd_0 = io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ctrl_is_load_0 = io_wakeups_0_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ctrl_is_sta_0 = io_wakeups_0_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ctrl_is_std_0 = io_wakeups_0_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_iw_state_0 = io_wakeups_0_bits_uop_iw_state; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_iw_p1_poisoned_0 = io_wakeups_0_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_iw_p2_poisoned_0 = io_wakeups_0_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_br_0 = io_wakeups_0_bits_uop_is_br; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_jalr_0 = io_wakeups_0_bits_uop_is_jalr; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_jal_0 = io_wakeups_0_bits_uop_is_jal; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-stage.scala:160:7] wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_wakeups_0_bits_uop_csr_addr_0 = io_wakeups_0_bits_uop_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-stage.scala:160:7] wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_bypassable_0 = io_wakeups_0_bits_uop_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_ldst_val_0 = io_wakeups_0_bits_uop_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_fp_single_0 = io_wakeups_0_bits_uop_fp_single; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7] wire [63:0] io_wakeups_0_bits_data_0 = io_wakeups_0_bits_data; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_predicated_0 = io_wakeups_0_bits_predicated; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_valid_0 = io_wakeups_0_bits_fflags_valid; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc_0 = io_wakeups_0_bits_fflags_bits_uop_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_0_bits_fflags_bits_uop_inst_0 = io_wakeups_0_bits_fflags_bits_uop_inst; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst_0 = io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_rvc_0 = io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type_0 = io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code_0 = io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state_0 = io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_br_0 = io_wakeups_0_bits_fflags_bits_uop_is_br; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_jalr_0 = io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_jal_0 = io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_sfb_0 = io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_wakeups_0_bits_fflags_bits_uop_br_mask_0 = io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_0_bits_fflags_bits_uop_br_tag_0 = io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_edge_inst_0 = io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob_0 = io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_taken_0 = io_wakeups_0_bits_fflags_bits_uop_taken; // @[rename-stage.scala:160:7] wire [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed_0 = io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr_0 = io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx_0 = io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_pdst_0 = io_wakeups_0_bits_fflags_bits_uop_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_prs1_0 = io_wakeups_0_bits_fflags_bits_uop_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_prs2_0 = io_wakeups_0_bits_fflags_bits_uop_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_prs3_0 = io_wakeups_0_bits_fflags_bits_uop_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ppred_0 = io_wakeups_0_bits_fflags_bits_uop_ppred; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_prs1_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_prs2_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_prs3_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ppred_busy_0 = io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst_0 = io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_exception_0 = io_wakeups_0_bits_fflags_bits_uop_exception; // @[rename-stage.scala:160:7] wire [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause_0 = io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_bypassable_0 = io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd_0 = io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size_0 = io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_mem_signed_0 = io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_fence_0 = io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_fencei_0 = io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_amo_0 = io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_uses_ldq_0 = io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_uses_stq_0 = io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_is_unique_0 = io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst_0 = io_wakeups_0_bits_fflags_bits_uop_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_0 = io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_0 = io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3_0 = io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_ldst_val_0 = io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_frs3_en_0 = io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_fp_val_0 = io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_fp_single_0 = io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7] wire io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_0_bits_fflags_bits_flags_0 = io_wakeups_0_bits_fflags_bits_flags; // @[rename-stage.scala:160:7] wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_uopc_0 = io_wakeups_1_bits_uop_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_uop_iq_type_0 = io_wakeups_1_bits_uop_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_wakeups_1_bits_uop_fu_code_0 = io_wakeups_1_bits_uop_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_1_bits_uop_ctrl_br_type_0 = io_wakeups_1_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_ctrl_op1_sel_0 = io_wakeups_1_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_uop_ctrl_op2_sel_0 = io_wakeups_1_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_uop_ctrl_imm_sel_0 = io_wakeups_1_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_uop_ctrl_op_fcn_0 = io_wakeups_1_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ctrl_fcn_dw_0 = io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_uop_ctrl_csr_cmd_0 = io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ctrl_is_load_0 = io_wakeups_1_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ctrl_is_sta_0 = io_wakeups_1_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ctrl_is_std_0 = io_wakeups_1_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_iw_state_0 = io_wakeups_1_bits_uop_iw_state; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_iw_p1_poisoned_0 = io_wakeups_1_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_iw_p2_poisoned_0 = io_wakeups_1_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_br_0 = io_wakeups_1_bits_uop_is_br; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_jalr_0 = io_wakeups_1_bits_uop_is_jalr; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_jal_0 = io_wakeups_1_bits_uop_is_jal; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-stage.scala:160:7] wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_wakeups_1_bits_uop_csr_addr_0 = io_wakeups_1_bits_uop_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-stage.scala:160:7] wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_bypassable_0 = io_wakeups_1_bits_uop_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_ldst_val_0 = io_wakeups_1_bits_uop_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_fp_single_0 = io_wakeups_1_bits_uop_fp_single; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7] wire [63:0] io_wakeups_1_bits_data_0 = io_wakeups_1_bits_data; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_valid_0 = io_wakeups_1_bits_fflags_valid; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_uopc_0 = io_wakeups_1_bits_fflags_bits_uop_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_1_bits_fflags_bits_uop_inst_0 = io_wakeups_1_bits_fflags_bits_uop_inst; // @[rename-stage.scala:160:7] wire [31:0] io_wakeups_1_bits_fflags_bits_uop_debug_inst_0 = io_wakeups_1_bits_fflags_bits_uop_debug_inst; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_rvc_0 = io_wakeups_1_bits_fflags_bits_uop_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_wakeups_1_bits_fflags_bits_uop_debug_pc_0 = io_wakeups_1_bits_fflags_bits_uop_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_fflags_bits_uop_iq_type_0 = io_wakeups_1_bits_fflags_bits_uop_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_wakeups_1_bits_fflags_bits_uop_fu_code_0 = io_wakeups_1_bits_fflags_bits_uop_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_iw_state_0 = io_wakeups_1_bits_fflags_bits_uop_iw_state; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_br_0 = io_wakeups_1_bits_fflags_bits_uop_is_br; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_jalr_0 = io_wakeups_1_bits_fflags_bits_uop_is_jalr; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_jal_0 = io_wakeups_1_bits_fflags_bits_uop_is_jal; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_sfb_0 = io_wakeups_1_bits_fflags_bits_uop_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_wakeups_1_bits_fflags_bits_uop_br_mask_0 = io_wakeups_1_bits_fflags_bits_uop_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_wakeups_1_bits_fflags_bits_uop_br_tag_0 = io_wakeups_1_bits_fflags_bits_uop_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ftq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_ftq_idx; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_edge_inst_0 = io_wakeups_1_bits_fflags_bits_uop_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_fflags_bits_uop_pc_lob_0 = io_wakeups_1_bits_fflags_bits_uop_pc_lob; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_taken_0 = io_wakeups_1_bits_fflags_bits_uop_taken; // @[rename-stage.scala:160:7] wire [19:0] io_wakeups_1_bits_fflags_bits_uop_imm_packed_0 = io_wakeups_1_bits_fflags_bits_uop_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_wakeups_1_bits_fflags_bits_uop_csr_addr_0 = io_wakeups_1_bits_fflags_bits_uop_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_rob_idx_0 = io_wakeups_1_bits_fflags_bits_uop_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ldq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_uop_stq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_rxq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_pdst_0 = io_wakeups_1_bits_fflags_bits_uop_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_prs1_0 = io_wakeups_1_bits_fflags_bits_uop_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_prs2_0 = io_wakeups_1_bits_fflags_bits_uop_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_prs3_0 = io_wakeups_1_bits_fflags_bits_uop_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ppred_0 = io_wakeups_1_bits_fflags_bits_uop_ppred; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_prs1_busy_0 = io_wakeups_1_bits_fflags_bits_uop_prs1_busy; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_prs2_busy_0 = io_wakeups_1_bits_fflags_bits_uop_prs2_busy; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_prs3_busy_0 = io_wakeups_1_bits_fflags_bits_uop_prs3_busy; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ppred_busy_0 = io_wakeups_1_bits_fflags_bits_uop_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_wakeups_1_bits_fflags_bits_uop_stale_pdst_0 = io_wakeups_1_bits_fflags_bits_uop_stale_pdst; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_exception_0 = io_wakeups_1_bits_fflags_bits_uop_exception; // @[rename-stage.scala:160:7] wire [63:0] io_wakeups_1_bits_fflags_bits_uop_exc_cause_0 = io_wakeups_1_bits_fflags_bits_uop_exc_cause; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_bypassable_0 = io_wakeups_1_bits_fflags_bits_uop_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_uop_mem_cmd_0 = io_wakeups_1_bits_fflags_bits_uop_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_mem_size_0 = io_wakeups_1_bits_fflags_bits_uop_mem_size; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_mem_signed_0 = io_wakeups_1_bits_fflags_bits_uop_mem_signed; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_fence_0 = io_wakeups_1_bits_fflags_bits_uop_is_fence; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_fencei_0 = io_wakeups_1_bits_fflags_bits_uop_is_fencei; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_amo_0 = io_wakeups_1_bits_fflags_bits_uop_is_amo; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_uses_ldq_0 = io_wakeups_1_bits_fflags_bits_uop_uses_ldq; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_uses_stq_0 = io_wakeups_1_bits_fflags_bits_uop_uses_stq; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_is_unique_0 = io_wakeups_1_bits_fflags_bits_uop_is_unique; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_fflags_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_fflags_bits_uop_ldst_0 = io_wakeups_1_bits_fflags_bits_uop_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_0 = io_wakeups_1_bits_fflags_bits_uop_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_0 = io_wakeups_1_bits_fflags_bits_uop_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs3_0 = io_wakeups_1_bits_fflags_bits_uop_lrs3; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_ldst_val_0 = io_wakeups_1_bits_fflags_bits_uop_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_dst_rtype_0 = io_wakeups_1_bits_fflags_bits_uop_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_frs3_en_0 = io_wakeups_1_bits_fflags_bits_uop_frs3_en; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_fp_val_0 = io_wakeups_1_bits_fflags_bits_uop_fp_val; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_fp_single_0 = io_wakeups_1_bits_fflags_bits_uop_fp_single; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_fflags_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_fflags_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_fflags_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7] wire [4:0] io_wakeups_1_bits_fflags_bits_flags_0 = io_wakeups_1_bits_fflags_bits_flags; // @[rename-stage.scala:160:7] wire io_com_valids_0_0 = io_com_valids_0; // @[rename-stage.scala:160:7] wire io_com_valids_1_0 = io_com_valids_1; // @[rename-stage.scala:160:7] wire io_com_valids_2_0 = io_com_valids_2; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_uopc_0 = io_com_uops_0_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_com_uops_0_inst_0 = io_com_uops_0_inst; // @[rename-stage.scala:160:7] wire [31:0] io_com_uops_0_debug_inst_0 = io_com_uops_0_debug_inst; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_rvc_0 = io_com_uops_0_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_com_uops_0_debug_pc_0 = io_com_uops_0_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_0_iq_type_0 = io_com_uops_0_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_com_uops_0_fu_code_0 = io_com_uops_0_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_com_uops_0_ctrl_br_type_0 = io_com_uops_0_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_ctrl_op1_sel_0 = io_com_uops_0_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_0_ctrl_op2_sel_0 = io_com_uops_0_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_0_ctrl_imm_sel_0 = io_com_uops_0_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_0_ctrl_op_fcn_0 = io_com_uops_0_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_com_uops_0_ctrl_fcn_dw_0 = io_com_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_0_ctrl_csr_cmd_0 = io_com_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_com_uops_0_ctrl_is_load_0 = io_com_uops_0_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_com_uops_0_ctrl_is_sta_0 = io_com_uops_0_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_com_uops_0_ctrl_is_std_0 = io_com_uops_0_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_iw_state_0 = io_com_uops_0_iw_state; // @[rename-stage.scala:160:7] wire io_com_uops_0_iw_p1_poisoned_0 = io_com_uops_0_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_com_uops_0_iw_p2_poisoned_0 = io_com_uops_0_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_br_0 = io_com_uops_0_is_br; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_jalr_0 = io_com_uops_0_is_jalr; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_jal_0 = io_com_uops_0_is_jal; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_sfb_0 = io_com_uops_0_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_com_uops_0_br_mask_0 = io_com_uops_0_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_com_uops_0_br_tag_0 = io_com_uops_0_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_0_ftq_idx_0 = io_com_uops_0_ftq_idx; // @[rename-stage.scala:160:7] wire io_com_uops_0_edge_inst_0 = io_com_uops_0_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_0_pc_lob_0 = io_com_uops_0_pc_lob; // @[rename-stage.scala:160:7] wire io_com_uops_0_taken_0 = io_com_uops_0_taken; // @[rename-stage.scala:160:7] wire [19:0] io_com_uops_0_imm_packed_0 = io_com_uops_0_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_com_uops_0_csr_addr_0 = io_com_uops_0_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_rob_idx_0 = io_com_uops_0_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_0_ldq_idx_0 = io_com_uops_0_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_0_stq_idx_0 = io_com_uops_0_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_rxq_idx_0 = io_com_uops_0_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_pdst_0 = io_com_uops_0_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_prs1_0 = io_com_uops_0_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_prs2_0 = io_com_uops_0_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_prs3_0 = io_com_uops_0_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_0_ppred_0 = io_com_uops_0_ppred; // @[rename-stage.scala:160:7] wire io_com_uops_0_prs1_busy_0 = io_com_uops_0_prs1_busy; // @[rename-stage.scala:160:7] wire io_com_uops_0_prs2_busy_0 = io_com_uops_0_prs2_busy; // @[rename-stage.scala:160:7] wire io_com_uops_0_prs3_busy_0 = io_com_uops_0_prs3_busy; // @[rename-stage.scala:160:7] wire io_com_uops_0_ppred_busy_0 = io_com_uops_0_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_0_stale_pdst_0 = io_com_uops_0_stale_pdst; // @[rename-stage.scala:160:7] wire io_com_uops_0_exception_0 = io_com_uops_0_exception; // @[rename-stage.scala:160:7] wire [63:0] io_com_uops_0_exc_cause_0 = io_com_uops_0_exc_cause; // @[rename-stage.scala:160:7] wire io_com_uops_0_bypassable_0 = io_com_uops_0_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_0_mem_cmd_0 = io_com_uops_0_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_mem_size_0 = io_com_uops_0_mem_size; // @[rename-stage.scala:160:7] wire io_com_uops_0_mem_signed_0 = io_com_uops_0_mem_signed; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_fence_0 = io_com_uops_0_is_fence; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_fencei_0 = io_com_uops_0_is_fencei; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_amo_0 = io_com_uops_0_is_amo; // @[rename-stage.scala:160:7] wire io_com_uops_0_uses_ldq_0 = io_com_uops_0_uses_ldq; // @[rename-stage.scala:160:7] wire io_com_uops_0_uses_stq_0 = io_com_uops_0_uses_stq; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_sys_pc2epc_0 = io_com_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_com_uops_0_is_unique_0 = io_com_uops_0_is_unique; // @[rename-stage.scala:160:7] wire io_com_uops_0_flush_on_commit_0 = io_com_uops_0_flush_on_commit; // @[rename-stage.scala:160:7] wire io_com_uops_0_ldst_is_rs1_0 = io_com_uops_0_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_0_ldst_0 = io_com_uops_0_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_0_lrs1_0 = io_com_uops_0_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_0_lrs2_0 = io_com_uops_0_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_0_lrs3_0 = io_com_uops_0_lrs3; // @[rename-stage.scala:160:7] wire io_com_uops_0_ldst_val_0 = io_com_uops_0_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_dst_rtype_0 = io_com_uops_0_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_lrs1_rtype_0 = io_com_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_lrs2_rtype_0 = io_com_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_com_uops_0_frs3_en_0 = io_com_uops_0_frs3_en; // @[rename-stage.scala:160:7] wire io_com_uops_0_fp_val_0 = io_com_uops_0_fp_val; // @[rename-stage.scala:160:7] wire io_com_uops_0_fp_single_0 = io_com_uops_0_fp_single; // @[rename-stage.scala:160:7] wire io_com_uops_0_xcpt_pf_if_0 = io_com_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_com_uops_0_xcpt_ae_if_0 = io_com_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_com_uops_0_xcpt_ma_if_0 = io_com_uops_0_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_com_uops_0_bp_debug_if_0 = io_com_uops_0_bp_debug_if; // @[rename-stage.scala:160:7] wire io_com_uops_0_bp_xcpt_if_0 = io_com_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_debug_fsrc_0 = io_com_uops_0_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_0_debug_tsrc_0 = io_com_uops_0_debug_tsrc; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_uopc_0 = io_com_uops_1_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_com_uops_1_inst_0 = io_com_uops_1_inst; // @[rename-stage.scala:160:7] wire [31:0] io_com_uops_1_debug_inst_0 = io_com_uops_1_debug_inst; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_rvc_0 = io_com_uops_1_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_com_uops_1_debug_pc_0 = io_com_uops_1_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_1_iq_type_0 = io_com_uops_1_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_com_uops_1_fu_code_0 = io_com_uops_1_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_com_uops_1_ctrl_br_type_0 = io_com_uops_1_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_ctrl_op1_sel_0 = io_com_uops_1_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_1_ctrl_op2_sel_0 = io_com_uops_1_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_1_ctrl_imm_sel_0 = io_com_uops_1_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_1_ctrl_op_fcn_0 = io_com_uops_1_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_com_uops_1_ctrl_fcn_dw_0 = io_com_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_1_ctrl_csr_cmd_0 = io_com_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_com_uops_1_ctrl_is_load_0 = io_com_uops_1_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_com_uops_1_ctrl_is_sta_0 = io_com_uops_1_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_com_uops_1_ctrl_is_std_0 = io_com_uops_1_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_iw_state_0 = io_com_uops_1_iw_state; // @[rename-stage.scala:160:7] wire io_com_uops_1_iw_p1_poisoned_0 = io_com_uops_1_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_com_uops_1_iw_p2_poisoned_0 = io_com_uops_1_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_br_0 = io_com_uops_1_is_br; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_jalr_0 = io_com_uops_1_is_jalr; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_jal_0 = io_com_uops_1_is_jal; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_sfb_0 = io_com_uops_1_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_com_uops_1_br_mask_0 = io_com_uops_1_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_com_uops_1_br_tag_0 = io_com_uops_1_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_1_ftq_idx_0 = io_com_uops_1_ftq_idx; // @[rename-stage.scala:160:7] wire io_com_uops_1_edge_inst_0 = io_com_uops_1_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_1_pc_lob_0 = io_com_uops_1_pc_lob; // @[rename-stage.scala:160:7] wire io_com_uops_1_taken_0 = io_com_uops_1_taken; // @[rename-stage.scala:160:7] wire [19:0] io_com_uops_1_imm_packed_0 = io_com_uops_1_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_com_uops_1_csr_addr_0 = io_com_uops_1_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_rob_idx_0 = io_com_uops_1_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_1_ldq_idx_0 = io_com_uops_1_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_1_stq_idx_0 = io_com_uops_1_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_rxq_idx_0 = io_com_uops_1_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_pdst_0 = io_com_uops_1_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_prs1_0 = io_com_uops_1_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_prs2_0 = io_com_uops_1_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_prs3_0 = io_com_uops_1_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_1_ppred_0 = io_com_uops_1_ppred; // @[rename-stage.scala:160:7] wire io_com_uops_1_prs1_busy_0 = io_com_uops_1_prs1_busy; // @[rename-stage.scala:160:7] wire io_com_uops_1_prs2_busy_0 = io_com_uops_1_prs2_busy; // @[rename-stage.scala:160:7] wire io_com_uops_1_prs3_busy_0 = io_com_uops_1_prs3_busy; // @[rename-stage.scala:160:7] wire io_com_uops_1_ppred_busy_0 = io_com_uops_1_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_1_stale_pdst_0 = io_com_uops_1_stale_pdst; // @[rename-stage.scala:160:7] wire io_com_uops_1_exception_0 = io_com_uops_1_exception; // @[rename-stage.scala:160:7] wire [63:0] io_com_uops_1_exc_cause_0 = io_com_uops_1_exc_cause; // @[rename-stage.scala:160:7] wire io_com_uops_1_bypassable_0 = io_com_uops_1_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_1_mem_cmd_0 = io_com_uops_1_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_mem_size_0 = io_com_uops_1_mem_size; // @[rename-stage.scala:160:7] wire io_com_uops_1_mem_signed_0 = io_com_uops_1_mem_signed; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_fence_0 = io_com_uops_1_is_fence; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_fencei_0 = io_com_uops_1_is_fencei; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_amo_0 = io_com_uops_1_is_amo; // @[rename-stage.scala:160:7] wire io_com_uops_1_uses_ldq_0 = io_com_uops_1_uses_ldq; // @[rename-stage.scala:160:7] wire io_com_uops_1_uses_stq_0 = io_com_uops_1_uses_stq; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_sys_pc2epc_0 = io_com_uops_1_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_com_uops_1_is_unique_0 = io_com_uops_1_is_unique; // @[rename-stage.scala:160:7] wire io_com_uops_1_flush_on_commit_0 = io_com_uops_1_flush_on_commit; // @[rename-stage.scala:160:7] wire io_com_uops_1_ldst_is_rs1_0 = io_com_uops_1_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_1_ldst_0 = io_com_uops_1_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_1_lrs1_0 = io_com_uops_1_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_1_lrs2_0 = io_com_uops_1_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_1_lrs3_0 = io_com_uops_1_lrs3; // @[rename-stage.scala:160:7] wire io_com_uops_1_ldst_val_0 = io_com_uops_1_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_dst_rtype_0 = io_com_uops_1_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_lrs1_rtype_0 = io_com_uops_1_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_lrs2_rtype_0 = io_com_uops_1_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_com_uops_1_frs3_en_0 = io_com_uops_1_frs3_en; // @[rename-stage.scala:160:7] wire io_com_uops_1_fp_val_0 = io_com_uops_1_fp_val; // @[rename-stage.scala:160:7] wire io_com_uops_1_fp_single_0 = io_com_uops_1_fp_single; // @[rename-stage.scala:160:7] wire io_com_uops_1_xcpt_pf_if_0 = io_com_uops_1_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_com_uops_1_xcpt_ae_if_0 = io_com_uops_1_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_com_uops_1_xcpt_ma_if_0 = io_com_uops_1_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_com_uops_1_bp_debug_if_0 = io_com_uops_1_bp_debug_if; // @[rename-stage.scala:160:7] wire io_com_uops_1_bp_xcpt_if_0 = io_com_uops_1_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_debug_fsrc_0 = io_com_uops_1_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_1_debug_tsrc_0 = io_com_uops_1_debug_tsrc; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_uopc_0 = io_com_uops_2_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_com_uops_2_inst_0 = io_com_uops_2_inst; // @[rename-stage.scala:160:7] wire [31:0] io_com_uops_2_debug_inst_0 = io_com_uops_2_debug_inst; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_rvc_0 = io_com_uops_2_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_com_uops_2_debug_pc_0 = io_com_uops_2_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_2_iq_type_0 = io_com_uops_2_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_com_uops_2_fu_code_0 = io_com_uops_2_fu_code; // @[rename-stage.scala:160:7] wire [3:0] io_com_uops_2_ctrl_br_type_0 = io_com_uops_2_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_ctrl_op1_sel_0 = io_com_uops_2_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_2_ctrl_op2_sel_0 = io_com_uops_2_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_2_ctrl_imm_sel_0 = io_com_uops_2_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_2_ctrl_op_fcn_0 = io_com_uops_2_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_com_uops_2_ctrl_fcn_dw_0 = io_com_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_com_uops_2_ctrl_csr_cmd_0 = io_com_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_com_uops_2_ctrl_is_load_0 = io_com_uops_2_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_com_uops_2_ctrl_is_sta_0 = io_com_uops_2_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_com_uops_2_ctrl_is_std_0 = io_com_uops_2_ctrl_is_std; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_iw_state_0 = io_com_uops_2_iw_state; // @[rename-stage.scala:160:7] wire io_com_uops_2_iw_p1_poisoned_0 = io_com_uops_2_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_com_uops_2_iw_p2_poisoned_0 = io_com_uops_2_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_br_0 = io_com_uops_2_is_br; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_jalr_0 = io_com_uops_2_is_jalr; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_jal_0 = io_com_uops_2_is_jal; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_sfb_0 = io_com_uops_2_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_com_uops_2_br_mask_0 = io_com_uops_2_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_com_uops_2_br_tag_0 = io_com_uops_2_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_2_ftq_idx_0 = io_com_uops_2_ftq_idx; // @[rename-stage.scala:160:7] wire io_com_uops_2_edge_inst_0 = io_com_uops_2_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_2_pc_lob_0 = io_com_uops_2_pc_lob; // @[rename-stage.scala:160:7] wire io_com_uops_2_taken_0 = io_com_uops_2_taken; // @[rename-stage.scala:160:7] wire [19:0] io_com_uops_2_imm_packed_0 = io_com_uops_2_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_com_uops_2_csr_addr_0 = io_com_uops_2_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_rob_idx_0 = io_com_uops_2_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_2_ldq_idx_0 = io_com_uops_2_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_2_stq_idx_0 = io_com_uops_2_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_rxq_idx_0 = io_com_uops_2_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_pdst_0 = io_com_uops_2_pdst; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_prs1_0 = io_com_uops_2_prs1; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_prs2_0 = io_com_uops_2_prs2; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_prs3_0 = io_com_uops_2_prs3; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_2_ppred_0 = io_com_uops_2_ppred; // @[rename-stage.scala:160:7] wire io_com_uops_2_prs1_busy_0 = io_com_uops_2_prs1_busy; // @[rename-stage.scala:160:7] wire io_com_uops_2_prs2_busy_0 = io_com_uops_2_prs2_busy; // @[rename-stage.scala:160:7] wire io_com_uops_2_prs3_busy_0 = io_com_uops_2_prs3_busy; // @[rename-stage.scala:160:7] wire io_com_uops_2_ppred_busy_0 = io_com_uops_2_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_com_uops_2_stale_pdst_0 = io_com_uops_2_stale_pdst; // @[rename-stage.scala:160:7] wire io_com_uops_2_exception_0 = io_com_uops_2_exception; // @[rename-stage.scala:160:7] wire [63:0] io_com_uops_2_exc_cause_0 = io_com_uops_2_exc_cause; // @[rename-stage.scala:160:7] wire io_com_uops_2_bypassable_0 = io_com_uops_2_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_com_uops_2_mem_cmd_0 = io_com_uops_2_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_mem_size_0 = io_com_uops_2_mem_size; // @[rename-stage.scala:160:7] wire io_com_uops_2_mem_signed_0 = io_com_uops_2_mem_signed; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_fence_0 = io_com_uops_2_is_fence; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_fencei_0 = io_com_uops_2_is_fencei; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_amo_0 = io_com_uops_2_is_amo; // @[rename-stage.scala:160:7] wire io_com_uops_2_uses_ldq_0 = io_com_uops_2_uses_ldq; // @[rename-stage.scala:160:7] wire io_com_uops_2_uses_stq_0 = io_com_uops_2_uses_stq; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_sys_pc2epc_0 = io_com_uops_2_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_com_uops_2_is_unique_0 = io_com_uops_2_is_unique; // @[rename-stage.scala:160:7] wire io_com_uops_2_flush_on_commit_0 = io_com_uops_2_flush_on_commit; // @[rename-stage.scala:160:7] wire io_com_uops_2_ldst_is_rs1_0 = io_com_uops_2_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_2_ldst_0 = io_com_uops_2_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_2_lrs1_0 = io_com_uops_2_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_2_lrs2_0 = io_com_uops_2_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_com_uops_2_lrs3_0 = io_com_uops_2_lrs3; // @[rename-stage.scala:160:7] wire io_com_uops_2_ldst_val_0 = io_com_uops_2_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_dst_rtype_0 = io_com_uops_2_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_lrs1_rtype_0 = io_com_uops_2_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_lrs2_rtype_0 = io_com_uops_2_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_com_uops_2_frs3_en_0 = io_com_uops_2_frs3_en; // @[rename-stage.scala:160:7] wire io_com_uops_2_fp_val_0 = io_com_uops_2_fp_val; // @[rename-stage.scala:160:7] wire io_com_uops_2_fp_single_0 = io_com_uops_2_fp_single; // @[rename-stage.scala:160:7] wire io_com_uops_2_xcpt_pf_if_0 = io_com_uops_2_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_com_uops_2_xcpt_ae_if_0 = io_com_uops_2_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_com_uops_2_xcpt_ma_if_0 = io_com_uops_2_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_com_uops_2_bp_debug_if_0 = io_com_uops_2_bp_debug_if; // @[rename-stage.scala:160:7] wire io_com_uops_2_bp_xcpt_if_0 = io_com_uops_2_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_debug_fsrc_0 = io_com_uops_2_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_com_uops_2_debug_tsrc_0 = io_com_uops_2_debug_tsrc; // @[rename-stage.scala:160:7] wire io_rbk_valids_0_0 = io_rbk_valids_0; // @[rename-stage.scala:160:7] wire io_rbk_valids_1_0 = io_rbk_valids_1; // @[rename-stage.scala:160:7] wire io_rbk_valids_2_0 = io_rbk_valids_2; // @[rename-stage.scala:160:7] wire io_rollback_0 = io_rollback; // @[rename-stage.scala:160:7] wire io_debug_rob_empty_0 = io_debug_rob_empty; // @[rename-stage.scala:160:7] wire [3:0] io_dec_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7] wire [3:0] io_dec_uops_1_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7] wire [3:0] io_dec_uops_2_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7] wire [3:0] ren1_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29] wire [3:0] ren1_uops_1_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29] wire [3:0] ren1_uops_2_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29] wire [1:0] io_dec_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_iw_state = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_iw_state = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_rxq_idx = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_1_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_iw_state = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_rxq_idx = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] io_dec_uops_2_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7] wire [1:0] ren1_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_0_iw_state = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_1_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_1_iw_state = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_1_rxq_idx = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_1_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_2_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_2_iw_state = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_2_rxq_idx = 2'h0; // @[rename-stage.scala:101:29] wire [1:0] ren1_uops_2_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29] wire [2:0] io_dec_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_1_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_1_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_1_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_2_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_2_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] io_dec_uops_2_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7] wire [2:0] ren1_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_1_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_1_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_1_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_2_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_2_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29] wire [2:0] ren1_uops_2_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29] wire [4:0] io_dec_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_0_ldq_idx = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_0_stq_idx = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_0_ppred = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_1_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_1_ldq_idx = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_1_stq_idx = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_1_ppred = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_2_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_2_ldq_idx = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_2_stq_idx = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] io_dec_uops_2_ppred = 5'h0; // @[rename-stage.scala:160:7] wire [4:0] ren1_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_0_ldq_idx = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_0_stq_idx = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_0_ppred = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_1_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_1_ldq_idx = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_1_stq_idx = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_1_ppred = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_2_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_2_ldq_idx = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_2_stq_idx = 5'h0; // @[rename-stage.scala:101:29] wire [4:0] ren1_uops_2_ppred = 5'h0; // @[rename-stage.scala:101:29] wire io_dec_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_prs1_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_prs2_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ppred_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_1_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_prs1_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_prs2_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ppred_busy = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7] wire io_dec_uops_2_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7] wire io_wakeups_1_bits_predicated = 1'h0; // @[rename-stage.scala:160:7] wire ren1_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_prs1_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_prs2_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_ppred_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_1_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_prs1_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_prs2_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_ppred_busy = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29] wire ren1_uops_2_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29] wire [11:0] io_dec_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:160:7] wire [11:0] io_dec_uops_1_csr_addr = 12'h0; // @[rename-stage.scala:160:7] wire [11:0] io_dec_uops_2_csr_addr = 12'h0; // @[rename-stage.scala:160:7] wire [11:0] ren1_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:101:29] wire [11:0] ren1_uops_1_csr_addr = 12'h0; // @[rename-stage.scala:101:29] wire [11:0] ren1_uops_2_csr_addr = 12'h0; // @[rename-stage.scala:101:29] wire [6:0] io_dec_uops_0_rob_idx = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_0_pdst = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_0_prs1 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_0_prs2 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_0_prs3 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_0_stale_pdst = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_rob_idx = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_pdst = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_prs1 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_prs2 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_prs3 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_1_stale_pdst = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_rob_idx = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_pdst = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_prs1 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_prs2 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_prs3 = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] io_dec_uops_2_stale_pdst = 7'h0; // @[rename-stage.scala:160:7] wire [6:0] ren1_uops_0_rob_idx = 7'h0; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_0_pdst = 7'h0; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_1_rob_idx = 7'h0; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_1_pdst = 7'h0; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_2_rob_idx = 7'h0; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_2_pdst = 7'h0; // @[rename-stage.scala:101:29] wire [95:0] io_debug_isprlist = 96'h0; // @[rename-stage.scala:160:7] wire _ren2_uops_0_pdst_T_1 = 1'h1; // @[rename-stage.scala:306:38] wire _ren2_uops_1_pdst_T_1 = 1'h1; // @[rename-stage.scala:306:38] wire _ren2_uops_2_pdst_T_1 = 1'h1; // @[rename-stage.scala:306:38] wire _io_ren_stalls_0_T_2; // @[rename-stage.scala:339:60] wire _io_ren_stalls_1_T_2; // @[rename-stage.scala:339:60] wire _io_ren_stalls_2_T_2; // @[rename-stage.scala:339:60] wire ren1_fire_0 = io_dec_fire_0_0; // @[rename-stage.scala:100:29, :160:7] wire ren1_fire_1 = io_dec_fire_1_0; // @[rename-stage.scala:100:29, :160:7] wire ren1_fire_2 = io_dec_fire_2_0; // @[rename-stage.scala:100:29, :160:7] wire [6:0] ren1_uops_0_uopc = io_dec_uops_0_uopc_0; // @[rename-stage.scala:101:29, :160:7] wire [31:0] ren1_uops_0_inst = io_dec_uops_0_inst_0; // @[rename-stage.scala:101:29, :160:7] wire [31:0] ren1_uops_0_debug_inst = io_dec_uops_0_debug_inst_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_rvc = io_dec_uops_0_is_rvc_0; // @[rename-stage.scala:101:29, :160:7] wire [39:0] ren1_uops_0_debug_pc = io_dec_uops_0_debug_pc_0; // @[rename-stage.scala:101:29, :160:7] wire [2:0] ren1_uops_0_iq_type = io_dec_uops_0_iq_type_0; // @[rename-stage.scala:101:29, :160:7] wire [9:0] ren1_uops_0_fu_code = io_dec_uops_0_fu_code_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_br = io_dec_uops_0_is_br_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_jalr = io_dec_uops_0_is_jalr_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_jal = io_dec_uops_0_is_jal_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_sfb = io_dec_uops_0_is_sfb_0; // @[rename-stage.scala:101:29, :160:7] wire [15:0] ren1_uops_0_br_mask = io_dec_uops_0_br_mask_0; // @[rename-stage.scala:101:29, :160:7] wire [3:0] ren1_uops_0_br_tag = io_dec_uops_0_br_tag_0; // @[rename-stage.scala:101:29, :160:7] wire [4:0] ren1_uops_0_ftq_idx = io_dec_uops_0_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_edge_inst = io_dec_uops_0_edge_inst_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_0_pc_lob = io_dec_uops_0_pc_lob_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_taken = io_dec_uops_0_taken_0; // @[rename-stage.scala:101:29, :160:7] wire [19:0] ren1_uops_0_imm_packed = io_dec_uops_0_imm_packed_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_exception = io_dec_uops_0_exception_0; // @[rename-stage.scala:101:29, :160:7] wire [63:0] ren1_uops_0_exc_cause = io_dec_uops_0_exc_cause_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_bypassable = io_dec_uops_0_bypassable_0; // @[rename-stage.scala:101:29, :160:7] wire [4:0] ren1_uops_0_mem_cmd = io_dec_uops_0_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_0_mem_size = io_dec_uops_0_mem_size_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_mem_signed = io_dec_uops_0_mem_signed_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_fence = io_dec_uops_0_is_fence_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_fencei = io_dec_uops_0_is_fencei_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_amo = io_dec_uops_0_is_amo_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_uses_ldq = io_dec_uops_0_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_uses_stq = io_dec_uops_0_uses_stq_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_sys_pc2epc = io_dec_uops_0_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_is_unique = io_dec_uops_0_is_unique_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_flush_on_commit = io_dec_uops_0_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_0_ldst = io_dec_uops_0_ldst_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_0_lrs1 = io_dec_uops_0_lrs1_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_0_lrs2 = io_dec_uops_0_lrs2_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_0_lrs3 = io_dec_uops_0_lrs3_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_ldst_val = io_dec_uops_0_ldst_val_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_0_dst_rtype = io_dec_uops_0_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_0_lrs1_rtype = io_dec_uops_0_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_0_lrs2_rtype = io_dec_uops_0_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_frs3_en = io_dec_uops_0_frs3_en_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_fp_val = io_dec_uops_0_fp_val_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_fp_single = io_dec_uops_0_fp_single_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_xcpt_pf_if = io_dec_uops_0_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_xcpt_ae_if = io_dec_uops_0_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_bp_debug_if = io_dec_uops_0_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_0_bp_xcpt_if = io_dec_uops_0_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_0_debug_fsrc = io_dec_uops_0_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7] wire [6:0] ren1_uops_1_uopc = io_dec_uops_1_uopc_0; // @[rename-stage.scala:101:29, :160:7] wire [31:0] ren1_uops_1_inst = io_dec_uops_1_inst_0; // @[rename-stage.scala:101:29, :160:7] wire [31:0] ren1_uops_1_debug_inst = io_dec_uops_1_debug_inst_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_rvc = io_dec_uops_1_is_rvc_0; // @[rename-stage.scala:101:29, :160:7] wire [39:0] ren1_uops_1_debug_pc = io_dec_uops_1_debug_pc_0; // @[rename-stage.scala:101:29, :160:7] wire [2:0] ren1_uops_1_iq_type = io_dec_uops_1_iq_type_0; // @[rename-stage.scala:101:29, :160:7] wire [9:0] ren1_uops_1_fu_code = io_dec_uops_1_fu_code_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_br = io_dec_uops_1_is_br_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_jalr = io_dec_uops_1_is_jalr_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_jal = io_dec_uops_1_is_jal_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_sfb = io_dec_uops_1_is_sfb_0; // @[rename-stage.scala:101:29, :160:7] wire [15:0] ren1_uops_1_br_mask = io_dec_uops_1_br_mask_0; // @[rename-stage.scala:101:29, :160:7] wire [3:0] ren1_uops_1_br_tag = io_dec_uops_1_br_tag_0; // @[rename-stage.scala:101:29, :160:7] wire [4:0] ren1_uops_1_ftq_idx = io_dec_uops_1_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_edge_inst = io_dec_uops_1_edge_inst_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_1_pc_lob = io_dec_uops_1_pc_lob_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_taken = io_dec_uops_1_taken_0; // @[rename-stage.scala:101:29, :160:7] wire [19:0] ren1_uops_1_imm_packed = io_dec_uops_1_imm_packed_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_exception = io_dec_uops_1_exception_0; // @[rename-stage.scala:101:29, :160:7] wire [63:0] ren1_uops_1_exc_cause = io_dec_uops_1_exc_cause_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_bypassable = io_dec_uops_1_bypassable_0; // @[rename-stage.scala:101:29, :160:7] wire [4:0] ren1_uops_1_mem_cmd = io_dec_uops_1_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_1_mem_size = io_dec_uops_1_mem_size_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_mem_signed = io_dec_uops_1_mem_signed_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_fence = io_dec_uops_1_is_fence_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_fencei = io_dec_uops_1_is_fencei_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_amo = io_dec_uops_1_is_amo_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_uses_ldq = io_dec_uops_1_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_uses_stq = io_dec_uops_1_uses_stq_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_sys_pc2epc = io_dec_uops_1_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_is_unique = io_dec_uops_1_is_unique_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_flush_on_commit = io_dec_uops_1_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_1_ldst = io_dec_uops_1_ldst_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_1_lrs1 = io_dec_uops_1_lrs1_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_1_lrs2 = io_dec_uops_1_lrs2_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_1_lrs3 = io_dec_uops_1_lrs3_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_ldst_val = io_dec_uops_1_ldst_val_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_1_dst_rtype = io_dec_uops_1_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_1_lrs1_rtype = io_dec_uops_1_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_1_lrs2_rtype = io_dec_uops_1_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_frs3_en = io_dec_uops_1_frs3_en_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_fp_val = io_dec_uops_1_fp_val_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_fp_single = io_dec_uops_1_fp_single_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_xcpt_pf_if = io_dec_uops_1_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_xcpt_ae_if = io_dec_uops_1_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_bp_debug_if = io_dec_uops_1_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_1_bp_xcpt_if = io_dec_uops_1_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_1_debug_fsrc = io_dec_uops_1_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7] wire [6:0] ren1_uops_2_uopc = io_dec_uops_2_uopc_0; // @[rename-stage.scala:101:29, :160:7] wire [31:0] ren1_uops_2_inst = io_dec_uops_2_inst_0; // @[rename-stage.scala:101:29, :160:7] wire [31:0] ren1_uops_2_debug_inst = io_dec_uops_2_debug_inst_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_rvc = io_dec_uops_2_is_rvc_0; // @[rename-stage.scala:101:29, :160:7] wire [39:0] ren1_uops_2_debug_pc = io_dec_uops_2_debug_pc_0; // @[rename-stage.scala:101:29, :160:7] wire [2:0] ren1_uops_2_iq_type = io_dec_uops_2_iq_type_0; // @[rename-stage.scala:101:29, :160:7] wire [9:0] ren1_uops_2_fu_code = io_dec_uops_2_fu_code_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_br = io_dec_uops_2_is_br_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_jalr = io_dec_uops_2_is_jalr_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_jal = io_dec_uops_2_is_jal_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_sfb = io_dec_uops_2_is_sfb_0; // @[rename-stage.scala:101:29, :160:7] wire [15:0] ren1_uops_2_br_mask = io_dec_uops_2_br_mask_0; // @[rename-stage.scala:101:29, :160:7] wire [3:0] ren1_uops_2_br_tag = io_dec_uops_2_br_tag_0; // @[rename-stage.scala:101:29, :160:7] wire [4:0] ren1_uops_2_ftq_idx = io_dec_uops_2_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_edge_inst = io_dec_uops_2_edge_inst_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_2_pc_lob = io_dec_uops_2_pc_lob_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_taken = io_dec_uops_2_taken_0; // @[rename-stage.scala:101:29, :160:7] wire [19:0] ren1_uops_2_imm_packed = io_dec_uops_2_imm_packed_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_exception = io_dec_uops_2_exception_0; // @[rename-stage.scala:101:29, :160:7] wire [63:0] ren1_uops_2_exc_cause = io_dec_uops_2_exc_cause_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_bypassable = io_dec_uops_2_bypassable_0; // @[rename-stage.scala:101:29, :160:7] wire [4:0] ren1_uops_2_mem_cmd = io_dec_uops_2_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_2_mem_size = io_dec_uops_2_mem_size_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_mem_signed = io_dec_uops_2_mem_signed_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_fence = io_dec_uops_2_is_fence_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_fencei = io_dec_uops_2_is_fencei_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_amo = io_dec_uops_2_is_amo_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_uses_ldq = io_dec_uops_2_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_uses_stq = io_dec_uops_2_uses_stq_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_sys_pc2epc = io_dec_uops_2_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_is_unique = io_dec_uops_2_is_unique_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_flush_on_commit = io_dec_uops_2_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_2_ldst = io_dec_uops_2_ldst_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_2_lrs1 = io_dec_uops_2_lrs1_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_2_lrs2 = io_dec_uops_2_lrs2_0; // @[rename-stage.scala:101:29, :160:7] wire [5:0] ren1_uops_2_lrs3 = io_dec_uops_2_lrs3_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_ldst_val = io_dec_uops_2_ldst_val_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_2_dst_rtype = io_dec_uops_2_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_2_lrs1_rtype = io_dec_uops_2_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_2_lrs2_rtype = io_dec_uops_2_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_frs3_en = io_dec_uops_2_frs3_en_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_fp_val = io_dec_uops_2_fp_val_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_fp_single = io_dec_uops_2_fp_single_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_xcpt_pf_if = io_dec_uops_2_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_xcpt_ae_if = io_dec_uops_2_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_bp_debug_if = io_dec_uops_2_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7] wire ren1_uops_2_bp_xcpt_if = io_dec_uops_2_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7] wire [1:0] ren1_uops_2_debug_fsrc = io_dec_uops_2_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7] wire ren2_valids_0; // @[rename-stage.scala:107:29] wire ren2_valids_1; // @[rename-stage.scala:107:29] wire ren2_valids_2; // @[rename-stage.scala:107:29] wire [6:0] io_ren2_uops_0_newuop_uopc; // @[util.scala:73:26] wire [31:0] io_ren2_uops_0_newuop_inst; // @[util.scala:73:26] wire [31:0] io_ren2_uops_0_newuop_debug_inst; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_rvc; // @[util.scala:73:26] wire [39:0] io_ren2_uops_0_newuop_debug_pc; // @[util.scala:73:26] wire [2:0] io_ren2_uops_0_newuop_iq_type; // @[util.scala:73:26] wire [9:0] io_ren2_uops_0_newuop_fu_code; // @[util.scala:73:26] wire [3:0] io_ren2_uops_0_newuop_ctrl_br_type; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] io_ren2_uops_0_newuop_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] io_ren2_uops_0_newuop_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] io_ren2_uops_0_newuop_ctrl_op_fcn; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] io_ren2_uops_0_newuop_ctrl_csr_cmd; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ctrl_is_load; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ctrl_is_sta; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ctrl_is_std; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_iw_state; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_iw_p1_poisoned; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_iw_p2_poisoned; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_br; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_jalr; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_jal; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_sfb; // @[util.scala:73:26] wire [15:0] io_ren2_uops_0_newuop_br_mask; // @[util.scala:73:26] wire [3:0] io_ren2_uops_0_newuop_br_tag; // @[util.scala:73:26] wire [4:0] io_ren2_uops_0_newuop_ftq_idx; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_edge_inst; // @[util.scala:73:26] wire [5:0] io_ren2_uops_0_newuop_pc_lob; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_taken; // @[util.scala:73:26] wire [19:0] io_ren2_uops_0_newuop_imm_packed; // @[util.scala:73:26] wire [11:0] io_ren2_uops_0_newuop_csr_addr; // @[util.scala:73:26] wire [6:0] io_ren2_uops_0_newuop_rob_idx; // @[util.scala:73:26] wire [4:0] io_ren2_uops_0_newuop_ldq_idx; // @[util.scala:73:26] wire [4:0] io_ren2_uops_0_newuop_stq_idx; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_rxq_idx; // @[util.scala:73:26] wire [6:0] io_ren2_uops_0_newuop_pdst; // @[util.scala:73:26] wire [6:0] io_ren2_uops_0_newuop_prs1; // @[util.scala:73:26] wire [6:0] io_ren2_uops_0_newuop_prs2; // @[util.scala:73:26] wire [6:0] io_ren2_uops_0_newuop_prs3; // @[util.scala:73:26] wire [4:0] io_ren2_uops_0_newuop_ppred; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_prs1_busy; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_prs2_busy; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_prs3_busy; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ppred_busy; // @[util.scala:73:26] wire [6:0] io_ren2_uops_0_newuop_stale_pdst; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_exception; // @[util.scala:73:26] wire [63:0] io_ren2_uops_0_newuop_exc_cause; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_bypassable; // @[util.scala:73:26] wire [4:0] io_ren2_uops_0_newuop_mem_cmd; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_mem_size; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_mem_signed; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_fence; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_fencei; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_amo; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_uses_ldq; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_uses_stq; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_sys_pc2epc; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_is_unique; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_flush_on_commit; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] io_ren2_uops_0_newuop_ldst; // @[util.scala:73:26] wire [5:0] io_ren2_uops_0_newuop_lrs1; // @[util.scala:73:26] wire [5:0] io_ren2_uops_0_newuop_lrs2; // @[util.scala:73:26] wire [5:0] io_ren2_uops_0_newuop_lrs3; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_ldst_val; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_dst_rtype; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_lrs1_rtype; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_lrs2_rtype; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_frs3_en; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_fp_val; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_fp_single; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_xcpt_pf_if; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_xcpt_ae_if; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_xcpt_ma_if; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_bp_debug_if; // @[util.scala:73:26] wire io_ren2_uops_0_newuop_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_debug_fsrc; // @[util.scala:73:26] wire [1:0] io_ren2_uops_0_newuop_debug_tsrc; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_uopc; // @[util.scala:73:26] wire [31:0] io_ren2_uops_1_newuop_inst; // @[util.scala:73:26] wire [31:0] io_ren2_uops_1_newuop_debug_inst; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_rvc; // @[util.scala:73:26] wire [39:0] io_ren2_uops_1_newuop_debug_pc; // @[util.scala:73:26] wire [2:0] io_ren2_uops_1_newuop_iq_type; // @[util.scala:73:26] wire [9:0] io_ren2_uops_1_newuop_fu_code; // @[util.scala:73:26] wire [3:0] io_ren2_uops_1_newuop_ctrl_br_type; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] io_ren2_uops_1_newuop_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] io_ren2_uops_1_newuop_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] io_ren2_uops_1_newuop_ctrl_op_fcn; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] io_ren2_uops_1_newuop_ctrl_csr_cmd; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ctrl_is_load; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ctrl_is_sta; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ctrl_is_std; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_iw_state; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_iw_p1_poisoned; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_iw_p2_poisoned; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_br; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_jalr; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_jal; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_sfb; // @[util.scala:73:26] wire [15:0] io_ren2_uops_1_newuop_br_mask; // @[util.scala:73:26] wire [3:0] io_ren2_uops_1_newuop_br_tag; // @[util.scala:73:26] wire [4:0] io_ren2_uops_1_newuop_ftq_idx; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_edge_inst; // @[util.scala:73:26] wire [5:0] io_ren2_uops_1_newuop_pc_lob; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_taken; // @[util.scala:73:26] wire [19:0] io_ren2_uops_1_newuop_imm_packed; // @[util.scala:73:26] wire [11:0] io_ren2_uops_1_newuop_csr_addr; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_rob_idx; // @[util.scala:73:26] wire [4:0] io_ren2_uops_1_newuop_ldq_idx; // @[util.scala:73:26] wire [4:0] io_ren2_uops_1_newuop_stq_idx; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_rxq_idx; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_pdst; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_prs1; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_prs2; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_prs3; // @[util.scala:73:26] wire [4:0] io_ren2_uops_1_newuop_ppred; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_prs1_busy; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_prs2_busy; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_prs3_busy; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ppred_busy; // @[util.scala:73:26] wire [6:0] io_ren2_uops_1_newuop_stale_pdst; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_exception; // @[util.scala:73:26] wire [63:0] io_ren2_uops_1_newuop_exc_cause; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_bypassable; // @[util.scala:73:26] wire [4:0] io_ren2_uops_1_newuop_mem_cmd; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_mem_size; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_mem_signed; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_fence; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_fencei; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_amo; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_uses_ldq; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_uses_stq; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_sys_pc2epc; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_is_unique; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_flush_on_commit; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] io_ren2_uops_1_newuop_ldst; // @[util.scala:73:26] wire [5:0] io_ren2_uops_1_newuop_lrs1; // @[util.scala:73:26] wire [5:0] io_ren2_uops_1_newuop_lrs2; // @[util.scala:73:26] wire [5:0] io_ren2_uops_1_newuop_lrs3; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_ldst_val; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_dst_rtype; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_lrs1_rtype; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_lrs2_rtype; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_frs3_en; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_fp_val; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_fp_single; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_xcpt_pf_if; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_xcpt_ae_if; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_xcpt_ma_if; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_bp_debug_if; // @[util.scala:73:26] wire io_ren2_uops_1_newuop_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_debug_fsrc; // @[util.scala:73:26] wire [1:0] io_ren2_uops_1_newuop_debug_tsrc; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_uopc; // @[util.scala:73:26] wire [31:0] io_ren2_uops_2_newuop_inst; // @[util.scala:73:26] wire [31:0] io_ren2_uops_2_newuop_debug_inst; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_rvc; // @[util.scala:73:26] wire [39:0] io_ren2_uops_2_newuop_debug_pc; // @[util.scala:73:26] wire [2:0] io_ren2_uops_2_newuop_iq_type; // @[util.scala:73:26] wire [9:0] io_ren2_uops_2_newuop_fu_code; // @[util.scala:73:26] wire [3:0] io_ren2_uops_2_newuop_ctrl_br_type; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] io_ren2_uops_2_newuop_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] io_ren2_uops_2_newuop_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] io_ren2_uops_2_newuop_ctrl_op_fcn; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] io_ren2_uops_2_newuop_ctrl_csr_cmd; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ctrl_is_load; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ctrl_is_sta; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ctrl_is_std; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_iw_state; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_iw_p1_poisoned; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_iw_p2_poisoned; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_br; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_jalr; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_jal; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_sfb; // @[util.scala:73:26] wire [15:0] io_ren2_uops_2_newuop_br_mask; // @[util.scala:73:26] wire [3:0] io_ren2_uops_2_newuop_br_tag; // @[util.scala:73:26] wire [4:0] io_ren2_uops_2_newuop_ftq_idx; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_edge_inst; // @[util.scala:73:26] wire [5:0] io_ren2_uops_2_newuop_pc_lob; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_taken; // @[util.scala:73:26] wire [19:0] io_ren2_uops_2_newuop_imm_packed; // @[util.scala:73:26] wire [11:0] io_ren2_uops_2_newuop_csr_addr; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_rob_idx; // @[util.scala:73:26] wire [4:0] io_ren2_uops_2_newuop_ldq_idx; // @[util.scala:73:26] wire [4:0] io_ren2_uops_2_newuop_stq_idx; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_rxq_idx; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_pdst; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_prs1; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_prs2; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_prs3; // @[util.scala:73:26] wire [4:0] io_ren2_uops_2_newuop_ppred; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_prs1_busy; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_prs2_busy; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_prs3_busy; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ppred_busy; // @[util.scala:73:26] wire [6:0] io_ren2_uops_2_newuop_stale_pdst; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_exception; // @[util.scala:73:26] wire [63:0] io_ren2_uops_2_newuop_exc_cause; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_bypassable; // @[util.scala:73:26] wire [4:0] io_ren2_uops_2_newuop_mem_cmd; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_mem_size; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_mem_signed; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_fence; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_fencei; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_amo; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_uses_ldq; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_uses_stq; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_sys_pc2epc; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_is_unique; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_flush_on_commit; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] io_ren2_uops_2_newuop_ldst; // @[util.scala:73:26] wire [5:0] io_ren2_uops_2_newuop_lrs1; // @[util.scala:73:26] wire [5:0] io_ren2_uops_2_newuop_lrs2; // @[util.scala:73:26] wire [5:0] io_ren2_uops_2_newuop_lrs3; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_ldst_val; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_dst_rtype; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_lrs1_rtype; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_lrs2_rtype; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_frs3_en; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_fp_val; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_fp_single; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_xcpt_pf_if; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_xcpt_ae_if; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_xcpt_ma_if; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_bp_debug_if; // @[util.scala:73:26] wire io_ren2_uops_2_newuop_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_debug_fsrc; // @[util.scala:73:26] wire [1:0] io_ren2_uops_2_newuop_debug_tsrc; // @[util.scala:73:26] wire io_ren_stalls_0_0; // @[rename-stage.scala:160:7] wire io_ren_stalls_1_0; // @[rename-stage.scala:160:7] wire io_ren_stalls_2_0; // @[rename-stage.scala:160:7] wire io_ren2_mask_0; // @[rename-stage.scala:160:7] wire io_ren2_mask_1; // @[rename-stage.scala:160:7] wire io_ren2_mask_2; // @[rename-stage.scala:160:7] wire [3:0] io_ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_ren2_uops_0_inst; // @[rename-stage.scala:160:7] wire [31:0] io_ren2_uops_0_debug_inst; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_ren2_uops_0_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_0_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_ren2_uops_0_fu_code; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_iw_state; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_br; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_jalr; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_jal; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_ren2_uops_0_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_ren2_uops_0_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_0_ftq_idx; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_0_pc_lob; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_taken; // @[rename-stage.scala:160:7] wire [19:0] io_ren2_uops_0_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_ren2_uops_0_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_0_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_0_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_pdst_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_prs1_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_prs2_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_prs3_0; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_0_ppred; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_prs1_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_prs2_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_prs3_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_0_stale_pdst_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_exception; // @[rename-stage.scala:160:7] wire [63:0] io_ren2_uops_0_exc_cause; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_0_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_mem_size; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_mem_signed; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_fence; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_fencei; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_amo; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_uses_ldq; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_uses_stq; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_is_unique; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_flush_on_commit; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_0_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_0_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_0_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_0_lrs3; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_frs3_en; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_fp_val; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_fp_single; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_bp_debug_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_0_debug_tsrc; // @[rename-stage.scala:160:7] wire [3:0] io_ren2_uops_1_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_1_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_1_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_1_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ctrl_is_std; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_ren2_uops_1_inst; // @[rename-stage.scala:160:7] wire [31:0] io_ren2_uops_1_debug_inst; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_ren2_uops_1_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_1_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_ren2_uops_1_fu_code; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_iw_state; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_br; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_jalr; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_jal; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_ren2_uops_1_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_ren2_uops_1_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_1_ftq_idx; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_1_pc_lob; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_taken; // @[rename-stage.scala:160:7] wire [19:0] io_ren2_uops_1_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_ren2_uops_1_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_1_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_1_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_pdst_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_prs1_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_prs2_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_prs3_0; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_1_ppred; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_prs1_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_prs2_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_prs3_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_1_stale_pdst_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_exception; // @[rename-stage.scala:160:7] wire [63:0] io_ren2_uops_1_exc_cause; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_1_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_mem_size; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_mem_signed; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_fence; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_fencei; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_amo; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_uses_ldq; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_uses_stq; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_is_unique; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_flush_on_commit; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_1_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_1_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_1_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_1_lrs3; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_frs3_en; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_fp_val; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_fp_single; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_bp_debug_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_1_debug_tsrc; // @[rename-stage.scala:160:7] wire [3:0] io_ren2_uops_2_ctrl_br_type; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_ctrl_op1_sel; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_2_ctrl_op2_sel; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_2_ctrl_imm_sel; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_2_ctrl_op_fcn; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ctrl_is_load; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ctrl_is_sta; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ctrl_is_std; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_uopc; // @[rename-stage.scala:160:7] wire [31:0] io_ren2_uops_2_inst; // @[rename-stage.scala:160:7] wire [31:0] io_ren2_uops_2_debug_inst; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_rvc; // @[rename-stage.scala:160:7] wire [39:0] io_ren2_uops_2_debug_pc; // @[rename-stage.scala:160:7] wire [2:0] io_ren2_uops_2_iq_type; // @[rename-stage.scala:160:7] wire [9:0] io_ren2_uops_2_fu_code; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_iw_state; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_iw_p1_poisoned; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_iw_p2_poisoned; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_br; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_jalr; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_jal; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_sfb; // @[rename-stage.scala:160:7] wire [15:0] io_ren2_uops_2_br_mask; // @[rename-stage.scala:160:7] wire [3:0] io_ren2_uops_2_br_tag; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_2_ftq_idx; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_edge_inst; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_2_pc_lob; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_taken; // @[rename-stage.scala:160:7] wire [19:0] io_ren2_uops_2_imm_packed; // @[rename-stage.scala:160:7] wire [11:0] io_ren2_uops_2_csr_addr; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_rob_idx; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_2_ldq_idx; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_2_stq_idx; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_rxq_idx; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_pdst_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_prs1_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_prs2_0; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_prs3_0; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_2_ppred; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_prs1_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_prs2_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_prs3_busy_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ppred_busy; // @[rename-stage.scala:160:7] wire [6:0] io_ren2_uops_2_stale_pdst_0; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_exception; // @[rename-stage.scala:160:7] wire [63:0] io_ren2_uops_2_exc_cause; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_bypassable; // @[rename-stage.scala:160:7] wire [4:0] io_ren2_uops_2_mem_cmd; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_mem_size; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_mem_signed; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_fence; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_fencei; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_amo; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_uses_ldq; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_uses_stq; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_is_unique; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_flush_on_commit; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_2_ldst; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_2_lrs1; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_2_lrs2; // @[rename-stage.scala:160:7] wire [5:0] io_ren2_uops_2_lrs3; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_ldst_val; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_dst_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_frs3_en; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_fp_val; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_fp_single; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_bp_debug_if; // @[rename-stage.scala:160:7] wire io_ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_debug_fsrc; // @[rename-stage.scala:160:7] wire [1:0] io_ren2_uops_2_debug_tsrc; // @[rename-stage.scala:160:7] wire [95:0] io_debug_freelist; // @[rename-stage.scala:160:7] wire [95:0] io_debug_busytable; // @[rename-stage.scala:160:7] wire [5:0] map_reqs_0_ldst = ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_0_lrs1 = ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_0_lrs2 = ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_0_lrs3 = ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_1_ldst = ren1_uops_1_ldst; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_1_lrs1 = ren1_uops_1_lrs1; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_1_lrs2 = ren1_uops_1_lrs2; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_1_lrs3 = ren1_uops_1_lrs3; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_2_ldst = ren1_uops_2_ldst; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_2_lrs1 = ren1_uops_2_lrs1; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_2_lrs2 = ren1_uops_2_lrs2; // @[rename-stage.scala:101:29, :252:24] wire [5:0] map_reqs_2_lrs3 = ren1_uops_2_lrs3; // @[rename-stage.scala:101:29, :252:24] wire [6:0] ren1_uops_0_prs1; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_0_prs2; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_0_prs3; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_0_stale_pdst; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_1_prs1; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_1_prs2; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_1_prs3; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_1_stale_pdst; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_2_prs1; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_2_prs2; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_2_prs3; // @[rename-stage.scala:101:29] wire [6:0] ren1_uops_2_stale_pdst; // @[rename-stage.scala:101:29] assign io_ren2_mask_0 = ren2_valids_0; // @[rename-stage.scala:107:29, :160:7] assign io_ren2_mask_1 = ren2_valids_1; // @[rename-stage.scala:107:29, :160:7] assign io_ren2_mask_2 = ren2_valids_2; // @[rename-stage.scala:107:29, :160:7] wire [6:0] bypassed_uop_uopc = ren2_uops_0_uopc; // @[rename-stage.scala:108:29, :341:28] wire [31:0] bypassed_uop_inst = ren2_uops_0_inst; // @[rename-stage.scala:108:29, :341:28] wire [31:0] bypassed_uop_debug_inst = ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_rvc = ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29, :341:28] wire [39:0] bypassed_uop_debug_pc = ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29, :341:28] wire [2:0] bypassed_uop_iq_type = ren2_uops_0_iq_type; // @[rename-stage.scala:108:29, :341:28] wire [9:0] bypassed_uop_fu_code = ren2_uops_0_fu_code; // @[rename-stage.scala:108:29, :341:28] wire [3:0] bypassed_uop_ctrl_br_type = ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_ctrl_op1_sel = ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29, :341:28] wire [2:0] bypassed_uop_ctrl_op2_sel = ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29, :341:28] wire [2:0] bypassed_uop_ctrl_imm_sel = ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29, :341:28] wire [4:0] bypassed_uop_ctrl_op_fcn = ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ctrl_fcn_dw = ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :341:28] wire [2:0] bypassed_uop_ctrl_csr_cmd = ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ctrl_is_load = ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ctrl_is_sta = ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ctrl_is_std = ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_iw_state = ren2_uops_0_iw_state; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_iw_p1_poisoned = ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_iw_p2_poisoned = ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_br = ren2_uops_0_is_br; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_jalr = ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_jal = ren2_uops_0_is_jal; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_sfb = ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29, :341:28] wire [15:0] bypassed_uop_br_mask = ren2_uops_0_br_mask; // @[rename-stage.scala:108:29, :341:28] wire [3:0] ren2_br_tags_0_bits = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :233:29] wire [3:0] bypassed_uop_br_tag = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :341:28] wire [4:0] bypassed_uop_ftq_idx = ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_edge_inst = ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29, :341:28] wire [5:0] bypassed_uop_pc_lob = ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_taken = ren2_uops_0_taken; // @[rename-stage.scala:108:29, :341:28] wire [19:0] bypassed_uop_imm_packed = ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29, :341:28] wire [11:0] bypassed_uop_csr_addr = ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_rob_idx = ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29, :341:28] wire [4:0] bypassed_uop_ldq_idx = ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29, :341:28] wire [4:0] bypassed_uop_stq_idx = ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29, :341:28] wire [6:0] _ren2_uops_0_pdst_T_2; // @[rename-stage.scala:306:20] wire [1:0] bypassed_uop_rxq_idx = ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_pdst = ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_prs1 = ren2_uops_0_prs1; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_prs2 = ren2_uops_0_prs2; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_prs3 = ren2_uops_0_prs3; // @[rename-stage.scala:108:29, :341:28] wire _ren2_uops_0_prs1_busy_T_1; // @[rename-stage.scala:323:47] wire [4:0] bypassed_uop_ppred = ren2_uops_0_ppred; // @[rename-stage.scala:108:29, :341:28] wire _ren2_uops_0_prs2_busy_T_1; // @[rename-stage.scala:324:47] wire bypassed_uop_prs1_busy = ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29, :341:28] wire _ren2_uops_0_prs3_busy_T; // @[rename-stage.scala:325:34] wire bypassed_uop_prs2_busy = ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_prs3_busy = ren2_uops_0_prs3_busy; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ppred_busy = ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_stale_pdst = ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_exception = ren2_uops_0_exception; // @[rename-stage.scala:108:29, :341:28] wire [63:0] bypassed_uop_exc_cause = ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_bypassable = ren2_uops_0_bypassable; // @[rename-stage.scala:108:29, :341:28] wire [4:0] bypassed_uop_mem_cmd = ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_mem_size = ren2_uops_0_mem_size; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_mem_signed = ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_fence = ren2_uops_0_is_fence; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_fencei = ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_amo = ren2_uops_0_is_amo; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_uses_ldq = ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_uses_stq = ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_sys_pc2epc = ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_is_unique = ren2_uops_0_is_unique; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_flush_on_commit = ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ldst_is_rs1 = ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29, :341:28] wire [5:0] bypassed_uop_ldst = ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :341:28] wire [5:0] bypassed_uop_lrs1 = ren2_uops_0_lrs1; // @[rename-stage.scala:108:29, :341:28] wire [5:0] bypassed_uop_lrs2 = ren2_uops_0_lrs2; // @[rename-stage.scala:108:29, :341:28] wire [5:0] bypassed_uop_lrs3 = ren2_uops_0_lrs3; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_ldst_val = ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_dst_rtype = ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_lrs1_rtype = ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_lrs2_rtype = ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_frs3_en = ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_fp_val = ren2_uops_0_fp_val; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_fp_single = ren2_uops_0_fp_single; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_xcpt_pf_if = ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_xcpt_ae_if = ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_xcpt_ma_if = ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_bp_debug_if = ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29, :341:28] wire bypassed_uop_bp_xcpt_if = ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_debug_fsrc = ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29, :341:28] wire [1:0] bypassed_uop_debug_tsrc = ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29, :341:28] wire [6:0] bypassed_uop_bypassed_uop_uopc = ren2_uops_1_uopc; // @[rename-stage.scala:108:29, :174:28] wire [31:0] bypassed_uop_bypassed_uop_inst = ren2_uops_1_inst; // @[rename-stage.scala:108:29, :174:28] wire [31:0] bypassed_uop_bypassed_uop_debug_inst = ren2_uops_1_debug_inst; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_rvc = ren2_uops_1_is_rvc; // @[rename-stage.scala:108:29, :174:28] wire [39:0] bypassed_uop_bypassed_uop_debug_pc = ren2_uops_1_debug_pc; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_iq_type = ren2_uops_1_iq_type; // @[rename-stage.scala:108:29, :174:28] wire [9:0] bypassed_uop_bypassed_uop_fu_code = ren2_uops_1_fu_code; // @[rename-stage.scala:108:29, :174:28] wire [3:0] bypassed_uop_bypassed_uop_ctrl_br_type = ren2_uops_1_ctrl_br_type; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_ctrl_op1_sel = ren2_uops_1_ctrl_op1_sel; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_ctrl_op2_sel = ren2_uops_1_ctrl_op2_sel; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_ctrl_imm_sel = ren2_uops_1_ctrl_imm_sel; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_ctrl_op_fcn = ren2_uops_1_ctrl_op_fcn; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_ctrl_fcn_dw = ren2_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_ctrl_csr_cmd = ren2_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_ctrl_is_load = ren2_uops_1_ctrl_is_load; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_ctrl_is_sta = ren2_uops_1_ctrl_is_sta; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_ctrl_is_std = ren2_uops_1_ctrl_is_std; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_iw_state = ren2_uops_1_iw_state; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_iw_p1_poisoned = ren2_uops_1_iw_p1_poisoned; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_iw_p2_poisoned = ren2_uops_1_iw_p2_poisoned; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_br = ren2_uops_1_is_br; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_jalr = ren2_uops_1_is_jalr; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_jal = ren2_uops_1_is_jal; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_sfb = ren2_uops_1_is_sfb; // @[rename-stage.scala:108:29, :174:28] wire [15:0] bypassed_uop_bypassed_uop_br_mask = ren2_uops_1_br_mask; // @[rename-stage.scala:108:29, :174:28] wire [3:0] ren2_br_tags_1_bits = ren2_uops_1_br_tag; // @[rename-stage.scala:108:29, :233:29] wire [3:0] bypassed_uop_bypassed_uop_br_tag = ren2_uops_1_br_tag; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_ftq_idx = ren2_uops_1_ftq_idx; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_edge_inst = ren2_uops_1_edge_inst; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_pc_lob = ren2_uops_1_pc_lob; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_taken = ren2_uops_1_taken; // @[rename-stage.scala:108:29, :174:28] wire [19:0] bypassed_uop_bypassed_uop_imm_packed = ren2_uops_1_imm_packed; // @[rename-stage.scala:108:29, :174:28] wire [11:0] bypassed_uop_bypassed_uop_csr_addr = ren2_uops_1_csr_addr; // @[rename-stage.scala:108:29, :174:28] wire [6:0] bypassed_uop_bypassed_uop_rob_idx = ren2_uops_1_rob_idx; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_ldq_idx = ren2_uops_1_ldq_idx; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_stq_idx = ren2_uops_1_stq_idx; // @[rename-stage.scala:108:29, :174:28] wire [6:0] _ren2_uops_1_pdst_T_2; // @[rename-stage.scala:306:20] wire [1:0] bypassed_uop_bypassed_uop_rxq_idx = ren2_uops_1_rxq_idx; // @[rename-stage.scala:108:29, :174:28] wire [6:0] bypassed_uop_bypassed_uop_pdst = ren2_uops_1_pdst; // @[rename-stage.scala:108:29, :174:28] wire _ren2_uops_1_prs1_busy_T_1; // @[rename-stage.scala:323:47] wire [4:0] bypassed_uop_bypassed_uop_ppred = ren2_uops_1_ppred; // @[rename-stage.scala:108:29, :174:28] wire _ren2_uops_1_prs2_busy_T_1; // @[rename-stage.scala:324:47] wire _ren2_uops_1_prs3_busy_T; // @[rename-stage.scala:325:34] wire bypassed_uop_bypassed_uop_ppred_busy = ren2_uops_1_ppred_busy; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_exception = ren2_uops_1_exception; // @[rename-stage.scala:108:29, :174:28] wire [63:0] bypassed_uop_bypassed_uop_exc_cause = ren2_uops_1_exc_cause; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_bypassable = ren2_uops_1_bypassable; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_mem_cmd = ren2_uops_1_mem_cmd; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_mem_size = ren2_uops_1_mem_size; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_mem_signed = ren2_uops_1_mem_signed; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_fence = ren2_uops_1_is_fence; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_fencei = ren2_uops_1_is_fencei; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_amo = ren2_uops_1_is_amo; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_uses_ldq = ren2_uops_1_uses_ldq; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_uses_stq = ren2_uops_1_uses_stq; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_sys_pc2epc = ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_is_unique = ren2_uops_1_is_unique; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_flush_on_commit = ren2_uops_1_flush_on_commit; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_ldst_is_rs1 = ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_ldst = ren2_uops_1_ldst; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_lrs1 = ren2_uops_1_lrs1; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_lrs2 = ren2_uops_1_lrs2; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_lrs3 = ren2_uops_1_lrs3; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_ldst_val = ren2_uops_1_ldst_val; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_dst_rtype = ren2_uops_1_dst_rtype; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_lrs1_rtype = ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_lrs2_rtype = ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_frs3_en = ren2_uops_1_frs3_en; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_fp_val = ren2_uops_1_fp_val; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_fp_single = ren2_uops_1_fp_single; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_xcpt_pf_if = ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_xcpt_ae_if = ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_xcpt_ma_if = ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_bp_debug_if = ren2_uops_1_bp_debug_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_bp_xcpt_if = ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_debug_fsrc = ren2_uops_1_debug_fsrc; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_debug_tsrc = ren2_uops_1_debug_tsrc; // @[rename-stage.scala:108:29, :174:28] wire [6:0] bypassed_uop_bypassed_uop_1_uopc = ren2_uops_2_uopc; // @[rename-stage.scala:108:29, :174:28] wire [31:0] bypassed_uop_bypassed_uop_1_inst = ren2_uops_2_inst; // @[rename-stage.scala:108:29, :174:28] wire [31:0] bypassed_uop_bypassed_uop_1_debug_inst = ren2_uops_2_debug_inst; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_rvc = ren2_uops_2_is_rvc; // @[rename-stage.scala:108:29, :174:28] wire [39:0] bypassed_uop_bypassed_uop_1_debug_pc = ren2_uops_2_debug_pc; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_1_iq_type = ren2_uops_2_iq_type; // @[rename-stage.scala:108:29, :174:28] wire [9:0] bypassed_uop_bypassed_uop_1_fu_code = ren2_uops_2_fu_code; // @[rename-stage.scala:108:29, :174:28] wire [3:0] bypassed_uop_bypassed_uop_1_ctrl_br_type = ren2_uops_2_ctrl_br_type; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_ctrl_op1_sel = ren2_uops_2_ctrl_op1_sel; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_1_ctrl_op2_sel = ren2_uops_2_ctrl_op2_sel; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_1_ctrl_imm_sel = ren2_uops_2_ctrl_imm_sel; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_1_ctrl_op_fcn = ren2_uops_2_ctrl_op_fcn; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_ctrl_fcn_dw = ren2_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :174:28] wire [2:0] bypassed_uop_bypassed_uop_1_ctrl_csr_cmd = ren2_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_ctrl_is_load = ren2_uops_2_ctrl_is_load; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_ctrl_is_sta = ren2_uops_2_ctrl_is_sta; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_ctrl_is_std = ren2_uops_2_ctrl_is_std; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_iw_state = ren2_uops_2_iw_state; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_iw_p1_poisoned = ren2_uops_2_iw_p1_poisoned; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_iw_p2_poisoned = ren2_uops_2_iw_p2_poisoned; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_br = ren2_uops_2_is_br; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_jalr = ren2_uops_2_is_jalr; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_jal = ren2_uops_2_is_jal; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_sfb = ren2_uops_2_is_sfb; // @[rename-stage.scala:108:29, :174:28] wire [15:0] bypassed_uop_bypassed_uop_1_br_mask = ren2_uops_2_br_mask; // @[rename-stage.scala:108:29, :174:28] wire [3:0] ren2_br_tags_2_bits = ren2_uops_2_br_tag; // @[rename-stage.scala:108:29, :233:29] wire [3:0] bypassed_uop_bypassed_uop_1_br_tag = ren2_uops_2_br_tag; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_1_ftq_idx = ren2_uops_2_ftq_idx; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_edge_inst = ren2_uops_2_edge_inst; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_1_pc_lob = ren2_uops_2_pc_lob; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_taken = ren2_uops_2_taken; // @[rename-stage.scala:108:29, :174:28] wire [19:0] bypassed_uop_bypassed_uop_1_imm_packed = ren2_uops_2_imm_packed; // @[rename-stage.scala:108:29, :174:28] wire [11:0] bypassed_uop_bypassed_uop_1_csr_addr = ren2_uops_2_csr_addr; // @[rename-stage.scala:108:29, :174:28] wire [6:0] bypassed_uop_bypassed_uop_1_rob_idx = ren2_uops_2_rob_idx; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_1_ldq_idx = ren2_uops_2_ldq_idx; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_1_stq_idx = ren2_uops_2_stq_idx; // @[rename-stage.scala:108:29, :174:28] wire [6:0] _ren2_uops_2_pdst_T_2; // @[rename-stage.scala:306:20] wire [1:0] bypassed_uop_bypassed_uop_1_rxq_idx = ren2_uops_2_rxq_idx; // @[rename-stage.scala:108:29, :174:28] wire [6:0] bypassed_uop_bypassed_uop_1_pdst = ren2_uops_2_pdst; // @[rename-stage.scala:108:29, :174:28] wire _ren2_uops_2_prs1_busy_T_1; // @[rename-stage.scala:323:47] wire [4:0] bypassed_uop_bypassed_uop_1_ppred = ren2_uops_2_ppred; // @[rename-stage.scala:108:29, :174:28] wire _ren2_uops_2_prs2_busy_T_1; // @[rename-stage.scala:324:47] wire _ren2_uops_2_prs3_busy_T; // @[rename-stage.scala:325:34] wire bypassed_uop_bypassed_uop_1_ppred_busy = ren2_uops_2_ppred_busy; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_exception = ren2_uops_2_exception; // @[rename-stage.scala:108:29, :174:28] wire [63:0] bypassed_uop_bypassed_uop_1_exc_cause = ren2_uops_2_exc_cause; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_bypassable = ren2_uops_2_bypassable; // @[rename-stage.scala:108:29, :174:28] wire [4:0] bypassed_uop_bypassed_uop_1_mem_cmd = ren2_uops_2_mem_cmd; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_mem_size = ren2_uops_2_mem_size; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_mem_signed = ren2_uops_2_mem_signed; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_fence = ren2_uops_2_is_fence; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_fencei = ren2_uops_2_is_fencei; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_amo = ren2_uops_2_is_amo; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_uses_ldq = ren2_uops_2_uses_ldq; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_uses_stq = ren2_uops_2_uses_stq; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_sys_pc2epc = ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_is_unique = ren2_uops_2_is_unique; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_flush_on_commit = ren2_uops_2_flush_on_commit; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_ldst_is_rs1 = ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_1_ldst = ren2_uops_2_ldst; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_1_lrs1 = ren2_uops_2_lrs1; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_1_lrs2 = ren2_uops_2_lrs2; // @[rename-stage.scala:108:29, :174:28] wire [5:0] bypassed_uop_bypassed_uop_1_lrs3 = ren2_uops_2_lrs3; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_ldst_val = ren2_uops_2_ldst_val; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_dst_rtype = ren2_uops_2_dst_rtype; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_lrs1_rtype = ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_lrs2_rtype = ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_frs3_en = ren2_uops_2_frs3_en; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_fp_val = ren2_uops_2_fp_val; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_fp_single = ren2_uops_2_fp_single; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_xcpt_pf_if = ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_xcpt_ae_if = ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_xcpt_ma_if = ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_bp_debug_if = ren2_uops_2_bp_debug_if; // @[rename-stage.scala:108:29, :174:28] wire bypassed_uop_bypassed_uop_1_bp_xcpt_if = ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_debug_fsrc = ren2_uops_2_debug_fsrc; // @[rename-stage.scala:108:29, :174:28] wire [1:0] bypassed_uop_bypassed_uop_1_debug_tsrc = ren2_uops_2_debug_tsrc; // @[rename-stage.scala:108:29, :174:28] wire [6:0] ren2_uops_1_prs1; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_1_prs2; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_1_prs3; // @[rename-stage.scala:108:29] wire ren2_uops_1_prs1_busy; // @[rename-stage.scala:108:29] wire ren2_uops_1_prs2_busy; // @[rename-stage.scala:108:29] wire ren2_uops_1_prs3_busy; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_1_stale_pdst; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_prs1; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_prs2; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_prs3; // @[rename-stage.scala:108:29] wire ren2_uops_2_prs1_busy; // @[rename-stage.scala:108:29] wire ren2_uops_2_prs2_busy; // @[rename-stage.scala:108:29] wire ren2_uops_2_prs3_busy; // @[rename-stage.scala:108:29] wire [6:0] ren2_uops_2_stale_pdst; // @[rename-stage.scala:108:29] wire _ren2_alloc_reqs_0_T_2; // @[rename-stage.scala:240:88] wire _ren2_alloc_reqs_1_T_2; // @[rename-stage.scala:240:88] wire _ren2_alloc_reqs_2_T_2; // @[rename-stage.scala:240:88] wire ren2_alloc_reqs_0; // @[rename-stage.scala:109:29] wire ren2_alloc_reqs_1; // @[rename-stage.scala:109:29] wire ren2_alloc_reqs_2; // @[rename-stage.scala:109:29] reg r_valid; // @[rename-stage.scala:121:27] assign ren2_valids_0 = r_valid; // @[rename-stage.scala:107:29, :121:27] reg [6:0] r_uop_uopc; // @[rename-stage.scala:122:23] assign ren2_uops_0_uopc = r_uop_uopc; // @[rename-stage.scala:108:29, :122:23] reg [31:0] r_uop_inst; // @[rename-stage.scala:122:23] assign ren2_uops_0_inst = r_uop_inst; // @[rename-stage.scala:108:29, :122:23] reg [31:0] r_uop_debug_inst; // @[rename-stage.scala:122:23] assign ren2_uops_0_debug_inst = r_uop_debug_inst; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_rvc; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_rvc = r_uop_is_rvc; // @[rename-stage.scala:108:29, :122:23] reg [39:0] r_uop_debug_pc; // @[rename-stage.scala:122:23] assign ren2_uops_0_debug_pc = r_uop_debug_pc; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_iq_type; // @[rename-stage.scala:122:23] assign ren2_uops_0_iq_type = r_uop_iq_type; // @[rename-stage.scala:108:29, :122:23] reg [9:0] r_uop_fu_code; // @[rename-stage.scala:122:23] assign ren2_uops_0_fu_code = r_uop_fu_code; // @[rename-stage.scala:108:29, :122:23] reg [3:0] r_uop_ctrl_br_type; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_br_type = r_uop_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_ctrl_op1_sel; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_op1_sel = r_uop_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_ctrl_op2_sel; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_op2_sel = r_uop_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_ctrl_imm_sel; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_imm_sel = r_uop_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_ctrl_op_fcn; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_op_fcn = r_uop_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23] reg r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_fcn_dw = r_uop_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_ctrl_csr_cmd; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_csr_cmd = r_uop_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23] reg r_uop_ctrl_is_load; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_is_load = r_uop_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23] reg r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_is_sta = r_uop_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23] reg r_uop_ctrl_is_std; // @[rename-stage.scala:122:23] assign ren2_uops_0_ctrl_is_std = r_uop_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_iw_state; // @[rename-stage.scala:122:23] assign ren2_uops_0_iw_state = r_uop_iw_state; // @[rename-stage.scala:108:29, :122:23] reg r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23] assign ren2_uops_0_iw_p1_poisoned = r_uop_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23] reg r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23] assign ren2_uops_0_iw_p2_poisoned = r_uop_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_br; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_br = r_uop_is_br; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_jalr; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_jalr = r_uop_is_jalr; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_jal; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_jal = r_uop_is_jal; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_sfb; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_sfb = r_uop_is_sfb; // @[rename-stage.scala:108:29, :122:23] reg [15:0] r_uop_br_mask; // @[rename-stage.scala:122:23] assign ren2_uops_0_br_mask = r_uop_br_mask; // @[rename-stage.scala:108:29, :122:23] reg [3:0] r_uop_br_tag; // @[rename-stage.scala:122:23] assign ren2_uops_0_br_tag = r_uop_br_tag; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_ftq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_0_ftq_idx = r_uop_ftq_idx; // @[rename-stage.scala:108:29, :122:23] reg r_uop_edge_inst; // @[rename-stage.scala:122:23] assign ren2_uops_0_edge_inst = r_uop_edge_inst; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_pc_lob; // @[rename-stage.scala:122:23] assign ren2_uops_0_pc_lob = r_uop_pc_lob; // @[rename-stage.scala:108:29, :122:23] reg r_uop_taken; // @[rename-stage.scala:122:23] assign ren2_uops_0_taken = r_uop_taken; // @[rename-stage.scala:108:29, :122:23] reg [19:0] r_uop_imm_packed; // @[rename-stage.scala:122:23] assign ren2_uops_0_imm_packed = r_uop_imm_packed; // @[rename-stage.scala:108:29, :122:23] reg [11:0] r_uop_csr_addr; // @[rename-stage.scala:122:23] assign ren2_uops_0_csr_addr = r_uop_csr_addr; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_rob_idx; // @[rename-stage.scala:122:23] assign ren2_uops_0_rob_idx = r_uop_rob_idx; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_ldq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_0_ldq_idx = r_uop_ldq_idx; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_stq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_0_stq_idx = r_uop_stq_idx; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_rxq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_0_rxq_idx = r_uop_rxq_idx; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_pdst; // @[rename-stage.scala:122:23] reg [6:0] r_uop_prs1; // @[rename-stage.scala:122:23] assign ren2_uops_0_prs1 = r_uop_prs1; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_prs2; // @[rename-stage.scala:122:23] assign ren2_uops_0_prs2 = r_uop_prs2; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_prs3; // @[rename-stage.scala:122:23] assign ren2_uops_0_prs3 = r_uop_prs3; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_ppred; // @[rename-stage.scala:122:23] assign ren2_uops_0_ppred = r_uop_ppred; // @[rename-stage.scala:108:29, :122:23] reg r_uop_prs1_busy; // @[rename-stage.scala:122:23] reg r_uop_prs2_busy; // @[rename-stage.scala:122:23] reg r_uop_prs3_busy; // @[rename-stage.scala:122:23] reg r_uop_ppred_busy; // @[rename-stage.scala:122:23] assign ren2_uops_0_ppred_busy = r_uop_ppred_busy; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_stale_pdst; // @[rename-stage.scala:122:23] assign ren2_uops_0_stale_pdst = r_uop_stale_pdst; // @[rename-stage.scala:108:29, :122:23] reg r_uop_exception; // @[rename-stage.scala:122:23] assign ren2_uops_0_exception = r_uop_exception; // @[rename-stage.scala:108:29, :122:23] reg [63:0] r_uop_exc_cause; // @[rename-stage.scala:122:23] assign ren2_uops_0_exc_cause = r_uop_exc_cause; // @[rename-stage.scala:108:29, :122:23] reg r_uop_bypassable; // @[rename-stage.scala:122:23] assign ren2_uops_0_bypassable = r_uop_bypassable; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_mem_cmd; // @[rename-stage.scala:122:23] assign ren2_uops_0_mem_cmd = r_uop_mem_cmd; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_mem_size; // @[rename-stage.scala:122:23] assign ren2_uops_0_mem_size = r_uop_mem_size; // @[rename-stage.scala:108:29, :122:23] reg r_uop_mem_signed; // @[rename-stage.scala:122:23] assign ren2_uops_0_mem_signed = r_uop_mem_signed; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_fence; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_fence = r_uop_is_fence; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_fencei; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_fencei = r_uop_is_fencei; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_amo; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_amo = r_uop_is_amo; // @[rename-stage.scala:108:29, :122:23] reg r_uop_uses_ldq; // @[rename-stage.scala:122:23] assign ren2_uops_0_uses_ldq = r_uop_uses_ldq; // @[rename-stage.scala:108:29, :122:23] reg r_uop_uses_stq; // @[rename-stage.scala:122:23] assign ren2_uops_0_uses_stq = r_uop_uses_stq; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_sys_pc2epc; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_sys_pc2epc = r_uop_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23] reg r_uop_is_unique; // @[rename-stage.scala:122:23] assign ren2_uops_0_is_unique = r_uop_is_unique; // @[rename-stage.scala:108:29, :122:23] reg r_uop_flush_on_commit; // @[rename-stage.scala:122:23] assign ren2_uops_0_flush_on_commit = r_uop_flush_on_commit; // @[rename-stage.scala:108:29, :122:23] reg r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23] assign ren2_uops_0_ldst_is_rs1 = r_uop_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_ldst; // @[rename-stage.scala:122:23] assign ren2_uops_0_ldst = r_uop_ldst; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_lrs1; // @[rename-stage.scala:122:23] assign ren2_uops_0_lrs1 = r_uop_lrs1; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_lrs2; // @[rename-stage.scala:122:23] assign ren2_uops_0_lrs2 = r_uop_lrs2; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_lrs3; // @[rename-stage.scala:122:23] assign ren2_uops_0_lrs3 = r_uop_lrs3; // @[rename-stage.scala:108:29, :122:23] reg r_uop_ldst_val; // @[rename-stage.scala:122:23] assign ren2_uops_0_ldst_val = r_uop_ldst_val; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_dst_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_0_dst_rtype = r_uop_dst_rtype; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_lrs1_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_0_lrs1_rtype = r_uop_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_lrs2_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_0_lrs2_rtype = r_uop_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23] reg r_uop_frs3_en; // @[rename-stage.scala:122:23] assign ren2_uops_0_frs3_en = r_uop_frs3_en; // @[rename-stage.scala:108:29, :122:23] reg r_uop_fp_val; // @[rename-stage.scala:122:23] assign ren2_uops_0_fp_val = r_uop_fp_val; // @[rename-stage.scala:108:29, :122:23] reg r_uop_fp_single; // @[rename-stage.scala:122:23] assign ren2_uops_0_fp_single = r_uop_fp_single; // @[rename-stage.scala:108:29, :122:23] reg r_uop_xcpt_pf_if; // @[rename-stage.scala:122:23] assign ren2_uops_0_xcpt_pf_if = r_uop_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_xcpt_ae_if; // @[rename-stage.scala:122:23] assign ren2_uops_0_xcpt_ae_if = r_uop_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23] assign ren2_uops_0_xcpt_ma_if = r_uop_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_bp_debug_if; // @[rename-stage.scala:122:23] assign ren2_uops_0_bp_debug_if = r_uop_bp_debug_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_bp_xcpt_if; // @[rename-stage.scala:122:23] assign ren2_uops_0_bp_xcpt_if = r_uop_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_debug_fsrc; // @[rename-stage.scala:122:23] assign ren2_uops_0_debug_fsrc = r_uop_debug_fsrc; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_debug_tsrc; // @[rename-stage.scala:122:23] assign ren2_uops_0_debug_tsrc = r_uop_debug_tsrc; // @[rename-stage.scala:108:29, :122:23] wire [6:0] r_uop_bypassed_uop_uopc = next_uop_uopc; // @[rename-stage.scala:123:24, :174:28] wire [31:0] r_uop_bypassed_uop_inst = next_uop_inst; // @[rename-stage.scala:123:24, :174:28] wire [31:0] r_uop_bypassed_uop_debug_inst = next_uop_debug_inst; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_rvc = next_uop_is_rvc; // @[rename-stage.scala:123:24, :174:28] wire [39:0] r_uop_bypassed_uop_debug_pc = next_uop_debug_pc; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_iq_type = next_uop_iq_type; // @[rename-stage.scala:123:24, :174:28] wire [9:0] r_uop_bypassed_uop_fu_code = next_uop_fu_code; // @[rename-stage.scala:123:24, :174:28] wire [3:0] r_uop_bypassed_uop_ctrl_br_type = next_uop_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_ctrl_op1_sel = next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_ctrl_op2_sel = next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_ctrl_imm_sel = next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_ctrl_op_fcn = next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ctrl_fcn_dw = next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_ctrl_csr_cmd = next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ctrl_is_load = next_uop_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ctrl_is_sta = next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ctrl_is_std = next_uop_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_iw_state = next_uop_iw_state; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_iw_p1_poisoned = next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_iw_p2_poisoned = next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_br = next_uop_is_br; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_jalr = next_uop_is_jalr; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_jal = next_uop_is_jal; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_sfb = next_uop_is_sfb; // @[rename-stage.scala:123:24, :174:28] wire [15:0] r_uop_bypassed_uop_br_mask = next_uop_br_mask; // @[rename-stage.scala:123:24, :174:28] wire [3:0] r_uop_bypassed_uop_br_tag = next_uop_br_tag; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_ftq_idx = next_uop_ftq_idx; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_edge_inst = next_uop_edge_inst; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_pc_lob = next_uop_pc_lob; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_taken = next_uop_taken; // @[rename-stage.scala:123:24, :174:28] wire [19:0] r_uop_bypassed_uop_imm_packed = next_uop_imm_packed; // @[rename-stage.scala:123:24, :174:28] wire [11:0] r_uop_bypassed_uop_csr_addr = next_uop_csr_addr; // @[rename-stage.scala:123:24, :174:28] wire [6:0] r_uop_bypassed_uop_rob_idx = next_uop_rob_idx; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_ldq_idx = next_uop_ldq_idx; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_stq_idx = next_uop_stq_idx; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_rxq_idx = next_uop_rxq_idx; // @[rename-stage.scala:123:24, :174:28] wire [6:0] r_uop_bypassed_uop_pdst = next_uop_pdst; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_ppred = next_uop_ppred; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ppred_busy = next_uop_ppred_busy; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_exception = next_uop_exception; // @[rename-stage.scala:123:24, :174:28] wire [63:0] r_uop_bypassed_uop_exc_cause = next_uop_exc_cause; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_bypassable = next_uop_bypassable; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_mem_cmd = next_uop_mem_cmd; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_mem_size = next_uop_mem_size; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_mem_signed = next_uop_mem_signed; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_fence = next_uop_is_fence; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_fencei = next_uop_is_fencei; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_amo = next_uop_is_amo; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_uses_ldq = next_uop_uses_ldq; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_uses_stq = next_uop_uses_stq; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_sys_pc2epc = next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_is_unique = next_uop_is_unique; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_flush_on_commit = next_uop_flush_on_commit; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ldst_is_rs1 = next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_ldst = next_uop_ldst; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_lrs1 = next_uop_lrs1; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_lrs2 = next_uop_lrs2; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_lrs3 = next_uop_lrs3; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_ldst_val = next_uop_ldst_val; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_dst_rtype = next_uop_dst_rtype; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_lrs1_rtype = next_uop_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_lrs2_rtype = next_uop_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_frs3_en = next_uop_frs3_en; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_fp_val = next_uop_fp_val; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_fp_single = next_uop_fp_single; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_xcpt_pf_if = next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_xcpt_ae_if = next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_xcpt_ma_if = next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_bp_debug_if = next_uop_bp_debug_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_bp_xcpt_if = next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_debug_fsrc = next_uop_debug_fsrc; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_debug_tsrc = next_uop_debug_tsrc; // @[rename-stage.scala:123:24, :174:28] wire [6:0] next_uop_prs1; // @[rename-stage.scala:123:24] wire [6:0] next_uop_prs2; // @[rename-stage.scala:123:24] wire [6:0] next_uop_prs3; // @[rename-stage.scala:123:24] wire next_uop_prs1_busy; // @[rename-stage.scala:123:24] wire next_uop_prs2_busy; // @[rename-stage.scala:123:24] wire next_uop_prs3_busy; // @[rename-stage.scala:123:24] wire [6:0] next_uop_stale_pdst; // @[rename-stage.scala:123:24] wire _r_valid_T = ~io_dis_fire_0_0; // @[rename-stage.scala:133:29, :160:7] wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-stage.scala:121:27, :133:{26,29}] wire _GEN = io_kill_0 | ~io_dis_ready_0; // @[rename-stage.scala:125:14, :127:20, :129:30, :160:7] assign next_uop_uopc = _GEN ? r_uop_uopc : ren1_uops_0_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_inst = _GEN ? r_uop_inst : ren1_uops_0_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_debug_inst = _GEN ? r_uop_debug_inst : ren1_uops_0_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_rvc = _GEN ? r_uop_is_rvc : ren1_uops_0_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_debug_pc = _GEN ? r_uop_debug_pc : ren1_uops_0_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_iq_type = _GEN ? r_uop_iq_type : ren1_uops_0_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_fu_code = _GEN ? r_uop_fu_code : ren1_uops_0_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_br_type = _GEN ? r_uop_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_op1_sel = _GEN ? r_uop_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_op2_sel = _GEN ? r_uop_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_imm_sel = _GEN ? r_uop_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_op_fcn = _GEN ? r_uop_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_fcn_dw = _GEN & r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_csr_cmd = _GEN ? r_uop_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_is_load = _GEN & r_uop_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_is_sta = _GEN & r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ctrl_is_std = _GEN & r_uop_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_iw_state = _GEN ? r_uop_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_iw_p1_poisoned = _GEN & r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_iw_p2_poisoned = _GEN & r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_br = _GEN ? r_uop_is_br : ren1_uops_0_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_jalr = _GEN ? r_uop_is_jalr : ren1_uops_0_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_jal = _GEN ? r_uop_is_jal : ren1_uops_0_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_sfb = _GEN ? r_uop_is_sfb : ren1_uops_0_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_br_mask = _GEN ? r_uop_br_mask : ren1_uops_0_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_br_tag = _GEN ? r_uop_br_tag : ren1_uops_0_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ftq_idx = _GEN ? r_uop_ftq_idx : ren1_uops_0_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_edge_inst = _GEN ? r_uop_edge_inst : ren1_uops_0_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_pc_lob = _GEN ? r_uop_pc_lob : ren1_uops_0_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_taken = _GEN ? r_uop_taken : ren1_uops_0_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_imm_packed = _GEN ? r_uop_imm_packed : ren1_uops_0_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_csr_addr = _GEN ? r_uop_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_rob_idx = _GEN ? r_uop_rob_idx : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ldq_idx = _GEN ? r_uop_ldq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_stq_idx = _GEN ? r_uop_stq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_rxq_idx = _GEN ? r_uop_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_pdst = _GEN ? r_uop_pdst : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_prs1 = _GEN ? r_uop_prs1 : ren1_uops_0_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_prs2 = _GEN ? r_uop_prs2 : ren1_uops_0_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_prs3 = _GEN ? r_uop_prs3 : ren1_uops_0_prs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ppred = _GEN ? r_uop_ppred : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_prs1_busy = _GEN & r_uop_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_prs2_busy = _GEN & r_uop_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_prs3_busy = _GEN & r_uop_prs3_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ppred_busy = _GEN & r_uop_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_stale_pdst = _GEN ? r_uop_stale_pdst : ren1_uops_0_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_exception = _GEN ? r_uop_exception : ren1_uops_0_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_exc_cause = _GEN ? r_uop_exc_cause : ren1_uops_0_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_bypassable = _GEN ? r_uop_bypassable : ren1_uops_0_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_mem_cmd = _GEN ? r_uop_mem_cmd : ren1_uops_0_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_mem_size = _GEN ? r_uop_mem_size : ren1_uops_0_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_mem_signed = _GEN ? r_uop_mem_signed : ren1_uops_0_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_fence = _GEN ? r_uop_is_fence : ren1_uops_0_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_fencei = _GEN ? r_uop_is_fencei : ren1_uops_0_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_amo = _GEN ? r_uop_is_amo : ren1_uops_0_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_uses_ldq = _GEN ? r_uop_uses_ldq : ren1_uops_0_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_uses_stq = _GEN ? r_uop_uses_stq : ren1_uops_0_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_sys_pc2epc = _GEN ? r_uop_is_sys_pc2epc : ren1_uops_0_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_is_unique = _GEN ? r_uop_is_unique : ren1_uops_0_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_flush_on_commit = _GEN ? r_uop_flush_on_commit : ren1_uops_0_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ldst_is_rs1 = _GEN & r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ldst = _GEN ? r_uop_ldst : ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_lrs1 = _GEN ? r_uop_lrs1 : ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_lrs2 = _GEN ? r_uop_lrs2 : ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_lrs3 = _GEN ? r_uop_lrs3 : ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_ldst_val = _GEN ? r_uop_ldst_val : ren1_uops_0_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_dst_rtype = _GEN ? r_uop_dst_rtype : ren1_uops_0_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_lrs1_rtype = _GEN ? r_uop_lrs1_rtype : ren1_uops_0_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_lrs2_rtype = _GEN ? r_uop_lrs2_rtype : ren1_uops_0_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_frs3_en = _GEN ? r_uop_frs3_en : ren1_uops_0_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_fp_val = _GEN ? r_uop_fp_val : ren1_uops_0_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_fp_single = _GEN ? r_uop_fp_single : ren1_uops_0_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_xcpt_pf_if = _GEN ? r_uop_xcpt_pf_if : ren1_uops_0_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_xcpt_ae_if = _GEN ? r_uop_xcpt_ae_if : ren1_uops_0_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_xcpt_ma_if = _GEN & r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_bp_debug_if = _GEN ? r_uop_bp_debug_if : ren1_uops_0_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_bp_xcpt_if = _GEN ? r_uop_bp_xcpt_if : ren1_uops_0_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_debug_fsrc = _GEN ? r_uop_debug_fsrc : ren1_uops_0_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_debug_tsrc = _GEN ? r_uop_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] wire [6:0] r_uop_newuop_uopc = r_uop_bypassed_uop_uopc; // @[util.scala:73:26] wire [31:0] r_uop_newuop_inst = r_uop_bypassed_uop_inst; // @[util.scala:73:26] wire [31:0] r_uop_newuop_debug_inst = r_uop_bypassed_uop_debug_inst; // @[util.scala:73:26] wire r_uop_newuop_is_rvc = r_uop_bypassed_uop_is_rvc; // @[util.scala:73:26] wire [39:0] r_uop_newuop_debug_pc = r_uop_bypassed_uop_debug_pc; // @[util.scala:73:26] wire [2:0] r_uop_newuop_iq_type = r_uop_bypassed_uop_iq_type; // @[util.scala:73:26] wire [9:0] r_uop_newuop_fu_code = r_uop_bypassed_uop_fu_code; // @[util.scala:73:26] wire [3:0] r_uop_newuop_ctrl_br_type = r_uop_bypassed_uop_ctrl_br_type; // @[util.scala:73:26] wire [1:0] r_uop_newuop_ctrl_op1_sel = r_uop_bypassed_uop_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] r_uop_newuop_ctrl_op2_sel = r_uop_bypassed_uop_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] r_uop_newuop_ctrl_imm_sel = r_uop_bypassed_uop_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] r_uop_newuop_ctrl_op_fcn = r_uop_bypassed_uop_ctrl_op_fcn; // @[util.scala:73:26] wire r_uop_newuop_ctrl_fcn_dw = r_uop_bypassed_uop_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] r_uop_newuop_ctrl_csr_cmd = r_uop_bypassed_uop_ctrl_csr_cmd; // @[util.scala:73:26] wire r_uop_newuop_ctrl_is_load = r_uop_bypassed_uop_ctrl_is_load; // @[util.scala:73:26] wire r_uop_newuop_ctrl_is_sta = r_uop_bypassed_uop_ctrl_is_sta; // @[util.scala:73:26] wire r_uop_newuop_ctrl_is_std = r_uop_bypassed_uop_ctrl_is_std; // @[util.scala:73:26] wire [1:0] r_uop_newuop_iw_state = r_uop_bypassed_uop_iw_state; // @[util.scala:73:26] wire r_uop_newuop_iw_p1_poisoned = r_uop_bypassed_uop_iw_p1_poisoned; // @[util.scala:73:26] wire r_uop_newuop_iw_p2_poisoned = r_uop_bypassed_uop_iw_p2_poisoned; // @[util.scala:73:26] wire r_uop_newuop_is_br = r_uop_bypassed_uop_is_br; // @[util.scala:73:26] wire r_uop_newuop_is_jalr = r_uop_bypassed_uop_is_jalr; // @[util.scala:73:26] wire r_uop_newuop_is_jal = r_uop_bypassed_uop_is_jal; // @[util.scala:73:26] wire r_uop_newuop_is_sfb = r_uop_bypassed_uop_is_sfb; // @[util.scala:73:26] wire [3:0] r_uop_newuop_br_tag = r_uop_bypassed_uop_br_tag; // @[util.scala:73:26] wire [4:0] r_uop_newuop_ftq_idx = r_uop_bypassed_uop_ftq_idx; // @[util.scala:73:26] wire r_uop_newuop_edge_inst = r_uop_bypassed_uop_edge_inst; // @[util.scala:73:26] wire [5:0] r_uop_newuop_pc_lob = r_uop_bypassed_uop_pc_lob; // @[util.scala:73:26] wire r_uop_newuop_taken = r_uop_bypassed_uop_taken; // @[util.scala:73:26] wire [19:0] r_uop_newuop_imm_packed = r_uop_bypassed_uop_imm_packed; // @[util.scala:73:26] wire [11:0] r_uop_newuop_csr_addr = r_uop_bypassed_uop_csr_addr; // @[util.scala:73:26] wire [6:0] r_uop_newuop_rob_idx = r_uop_bypassed_uop_rob_idx; // @[util.scala:73:26] wire [4:0] r_uop_newuop_ldq_idx = r_uop_bypassed_uop_ldq_idx; // @[util.scala:73:26] wire [4:0] r_uop_newuop_stq_idx = r_uop_bypassed_uop_stq_idx; // @[util.scala:73:26] wire [1:0] r_uop_newuop_rxq_idx = r_uop_bypassed_uop_rxq_idx; // @[util.scala:73:26] wire [6:0] r_uop_newuop_pdst = r_uop_bypassed_uop_pdst; // @[util.scala:73:26] wire [6:0] r_uop_newuop_prs1 = r_uop_bypassed_uop_prs1; // @[util.scala:73:26] wire [6:0] r_uop_newuop_prs2 = r_uop_bypassed_uop_prs2; // @[util.scala:73:26] wire [6:0] r_uop_newuop_prs3 = r_uop_bypassed_uop_prs3; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs1_busy_T; // @[rename-stage.scala:199:45] wire [4:0] r_uop_newuop_ppred = r_uop_bypassed_uop_ppred; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs2_busy_T; // @[rename-stage.scala:200:45] wire r_uop_newuop_prs1_busy = r_uop_bypassed_uop_prs1_busy; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs3_busy_T; // @[rename-stage.scala:201:45] wire r_uop_newuop_prs2_busy = r_uop_bypassed_uop_prs2_busy; // @[util.scala:73:26] wire r_uop_newuop_prs3_busy = r_uop_bypassed_uop_prs3_busy; // @[util.scala:73:26] wire r_uop_newuop_ppred_busy = r_uop_bypassed_uop_ppred_busy; // @[util.scala:73:26] wire [6:0] r_uop_newuop_stale_pdst = r_uop_bypassed_uop_stale_pdst; // @[util.scala:73:26] wire r_uop_newuop_exception = r_uop_bypassed_uop_exception; // @[util.scala:73:26] wire [63:0] r_uop_newuop_exc_cause = r_uop_bypassed_uop_exc_cause; // @[util.scala:73:26] wire r_uop_newuop_bypassable = r_uop_bypassed_uop_bypassable; // @[util.scala:73:26] wire [4:0] r_uop_newuop_mem_cmd = r_uop_bypassed_uop_mem_cmd; // @[util.scala:73:26] wire [1:0] r_uop_newuop_mem_size = r_uop_bypassed_uop_mem_size; // @[util.scala:73:26] wire r_uop_newuop_mem_signed = r_uop_bypassed_uop_mem_signed; // @[util.scala:73:26] wire r_uop_newuop_is_fence = r_uop_bypassed_uop_is_fence; // @[util.scala:73:26] wire r_uop_newuop_is_fencei = r_uop_bypassed_uop_is_fencei; // @[util.scala:73:26] wire r_uop_newuop_is_amo = r_uop_bypassed_uop_is_amo; // @[util.scala:73:26] wire r_uop_newuop_uses_ldq = r_uop_bypassed_uop_uses_ldq; // @[util.scala:73:26] wire r_uop_newuop_uses_stq = r_uop_bypassed_uop_uses_stq; // @[util.scala:73:26] wire r_uop_newuop_is_sys_pc2epc = r_uop_bypassed_uop_is_sys_pc2epc; // @[util.scala:73:26] wire r_uop_newuop_is_unique = r_uop_bypassed_uop_is_unique; // @[util.scala:73:26] wire r_uop_newuop_flush_on_commit = r_uop_bypassed_uop_flush_on_commit; // @[util.scala:73:26] wire r_uop_newuop_ldst_is_rs1 = r_uop_bypassed_uop_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] r_uop_newuop_ldst = r_uop_bypassed_uop_ldst; // @[util.scala:73:26] wire [5:0] r_uop_newuop_lrs1 = r_uop_bypassed_uop_lrs1; // @[util.scala:73:26] wire [5:0] r_uop_newuop_lrs2 = r_uop_bypassed_uop_lrs2; // @[util.scala:73:26] wire [5:0] r_uop_newuop_lrs3 = r_uop_bypassed_uop_lrs3; // @[util.scala:73:26] wire r_uop_newuop_ldst_val = r_uop_bypassed_uop_ldst_val; // @[util.scala:73:26] wire [1:0] r_uop_newuop_dst_rtype = r_uop_bypassed_uop_dst_rtype; // @[util.scala:73:26] wire [1:0] r_uop_newuop_lrs1_rtype = r_uop_bypassed_uop_lrs1_rtype; // @[util.scala:73:26] wire [1:0] r_uop_newuop_lrs2_rtype = r_uop_bypassed_uop_lrs2_rtype; // @[util.scala:73:26] wire r_uop_newuop_frs3_en = r_uop_bypassed_uop_frs3_en; // @[util.scala:73:26] wire r_uop_newuop_fp_val = r_uop_bypassed_uop_fp_val; // @[util.scala:73:26] wire r_uop_newuop_fp_single = r_uop_bypassed_uop_fp_single; // @[util.scala:73:26] wire r_uop_newuop_xcpt_pf_if = r_uop_bypassed_uop_xcpt_pf_if; // @[util.scala:73:26] wire r_uop_newuop_xcpt_ae_if = r_uop_bypassed_uop_xcpt_ae_if; // @[util.scala:73:26] wire r_uop_newuop_xcpt_ma_if = r_uop_bypassed_uop_xcpt_ma_if; // @[util.scala:73:26] wire r_uop_newuop_bp_debug_if = r_uop_bypassed_uop_bp_debug_if; // @[util.scala:73:26] wire r_uop_newuop_bp_xcpt_if = r_uop_bypassed_uop_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] r_uop_newuop_debug_fsrc = r_uop_bypassed_uop_debug_fsrc; // @[util.scala:73:26] wire [1:0] r_uop_newuop_debug_tsrc = r_uop_bypassed_uop_debug_tsrc; // @[util.scala:73:26] wire _r_uop_bypass_hits_rs1_T = ren2_uops_0_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs1_T_1 = ren2_uops_1_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs1_T_1; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs1_T_2 = ren2_uops_2_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs1_T_2; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs2_T = ren2_uops_0_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs2_T_1 = ren2_uops_1_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs2_T_1; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs2_T_2 = ren2_uops_2_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs2_T_2; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs3_T = ren2_uops_0_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_rs3_T_1 = ren2_uops_1_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs3_T_1; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_rs3_T_2 = ren2_uops_2_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs3_T_2; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_dst_T = ren2_uops_0_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T; // @[rename-stage.scala:109:29, :180:{77,87}] wire _r_uop_bypass_hits_dst_T_1 = ren2_uops_1_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_dst_T_1; // @[rename-stage.scala:109:29, :180:{77,87}] wire _r_uop_bypass_hits_dst_T_2 = ren2_uops_2_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_dst_T_2; // @[rename-stage.scala:109:29, :180:{77,87}] wire [2:0] _r_uop_bypass_sel_rs1_enc_T = {r_uop_bypass_hits_rs1_0, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs1_enc_T_1 = r_uop_bypass_hits_rs1_1 ? 3'h2 : _r_uop_bypass_sel_rs1_enc_T; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs1_enc = r_uop_bypass_hits_rs1_2 ? 3'h1 : _r_uop_bypass_sel_rs1_enc_T_1; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs1_2 = r_uop_bypass_sel_rs1_enc[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs1_1 = r_uop_bypass_sel_rs1_enc[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs1_0 = r_uop_bypass_sel_rs1_enc[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_rs2_enc_T = {r_uop_bypass_hits_rs2_0, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs2_enc_T_1 = r_uop_bypass_hits_rs2_1 ? 3'h2 : _r_uop_bypass_sel_rs2_enc_T; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs2_enc = r_uop_bypass_hits_rs2_2 ? 3'h1 : _r_uop_bypass_sel_rs2_enc_T_1; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs2_2 = r_uop_bypass_sel_rs2_enc[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs2_1 = r_uop_bypass_sel_rs2_enc[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs2_0 = r_uop_bypass_sel_rs2_enc[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_rs3_enc_T = {r_uop_bypass_hits_rs3_0, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs3_enc_T_1 = r_uop_bypass_hits_rs3_1 ? 3'h2 : _r_uop_bypass_sel_rs3_enc_T; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs3_enc = r_uop_bypass_hits_rs3_2 ? 3'h1 : _r_uop_bypass_sel_rs3_enc_T_1; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs3_2 = r_uop_bypass_sel_rs3_enc[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs3_1 = r_uop_bypass_sel_rs3_enc[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs3_0 = r_uop_bypass_sel_rs3_enc[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_dst_enc_T = {r_uop_bypass_hits_dst_0, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_dst_enc_T_1 = r_uop_bypass_hits_dst_1 ? 3'h2 : _r_uop_bypass_sel_dst_enc_T; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_dst_enc = r_uop_bypass_hits_dst_2 ? 3'h1 : _r_uop_bypass_sel_dst_enc_T_1; // @[Mux.scala:50:70] wire r_uop_bypass_sel_dst_2 = r_uop_bypass_sel_dst_enc[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_dst_1 = r_uop_bypass_sel_dst_enc[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_dst_0 = r_uop_bypass_sel_dst_enc[2]; // @[OneHot.scala:83:30] wire _r_uop_do_bypass_rs1_T = r_uop_bypass_hits_rs1_0 | r_uop_bypass_hits_rs1_1; // @[rename-stage.scala:177:77, :187:49] wire r_uop_do_bypass_rs1 = _r_uop_do_bypass_rs1_T | r_uop_bypass_hits_rs1_2; // @[rename-stage.scala:177:77, :187:49] wire _r_uop_do_bypass_rs2_T = r_uop_bypass_hits_rs2_0 | r_uop_bypass_hits_rs2_1; // @[rename-stage.scala:178:77, :188:49] wire r_uop_do_bypass_rs2 = _r_uop_do_bypass_rs2_T | r_uop_bypass_hits_rs2_2; // @[rename-stage.scala:178:77, :188:49] wire _r_uop_do_bypass_rs3_T = r_uop_bypass_hits_rs3_0 | r_uop_bypass_hits_rs3_1; // @[rename-stage.scala:179:77, :189:49] wire r_uop_do_bypass_rs3 = _r_uop_do_bypass_rs3_T | r_uop_bypass_hits_rs3_2; // @[rename-stage.scala:179:77, :189:49] wire _r_uop_do_bypass_dst_T = r_uop_bypass_hits_dst_0 | r_uop_bypass_hits_dst_1; // @[rename-stage.scala:180:77, :190:49] wire r_uop_do_bypass_dst = _r_uop_do_bypass_dst_T | r_uop_bypass_hits_dst_2; // @[rename-stage.scala:180:77, :190:49] wire [6:0] _r_uop_bypassed_uop_prs1_T = r_uop_bypass_sel_rs1_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_1 = r_uop_bypass_sel_rs1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_2 = r_uop_bypass_sel_rs1_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_3 = _r_uop_bypassed_uop_prs1_T | _r_uop_bypassed_uop_prs1_T_1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs1_T_4 = _r_uop_bypassed_uop_prs1_T_3 | _r_uop_bypassed_uop_prs1_T_2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs1_WIRE = _r_uop_bypassed_uop_prs1_T_4; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_prs1 = r_uop_do_bypass_rs1 ? _r_uop_bypassed_uop_prs1_WIRE : next_uop_prs1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_T = r_uop_bypass_sel_rs2_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_1 = r_uop_bypass_sel_rs2_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_2 = r_uop_bypass_sel_rs2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_3 = _r_uop_bypassed_uop_prs2_T | _r_uop_bypassed_uop_prs2_T_1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_T_4 = _r_uop_bypassed_uop_prs2_T_3 | _r_uop_bypassed_uop_prs2_T_2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_WIRE = _r_uop_bypassed_uop_prs2_T_4; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_prs2 = r_uop_do_bypass_rs2 ? _r_uop_bypassed_uop_prs2_WIRE : next_uop_prs2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_T = r_uop_bypass_sel_rs3_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_1 = r_uop_bypass_sel_rs3_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_2 = r_uop_bypass_sel_rs3_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_3 = _r_uop_bypassed_uop_prs3_T | _r_uop_bypassed_uop_prs3_T_1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_T_4 = _r_uop_bypassed_uop_prs3_T_3 | _r_uop_bypassed_uop_prs3_T_2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_WIRE = _r_uop_bypassed_uop_prs3_T_4; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_prs3 = r_uop_do_bypass_rs3 ? _r_uop_bypassed_uop_prs3_WIRE : next_uop_prs3; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T = r_uop_bypass_sel_dst_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_1 = r_uop_bypass_sel_dst_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_2 = r_uop_bypass_sel_dst_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_3 = _r_uop_bypassed_uop_stale_pdst_T | _r_uop_bypassed_uop_stale_pdst_T_1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_4 = _r_uop_bypassed_uop_stale_pdst_T_3 | _r_uop_bypassed_uop_stale_pdst_T_2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_WIRE = _r_uop_bypassed_uop_stale_pdst_T_4; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_stale_pdst = r_uop_do_bypass_dst ? _r_uop_bypassed_uop_stale_pdst_WIRE : next_uop_stale_pdst; // @[Mux.scala:30:73] assign _r_uop_bypassed_uop_prs1_busy_T = next_uop_prs1_busy | r_uop_do_bypass_rs1; // @[rename-stage.scala:123:24, :187:49, :199:45] assign r_uop_bypassed_uop_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T; // @[rename-stage.scala:174:28, :199:45] assign _r_uop_bypassed_uop_prs2_busy_T = next_uop_prs2_busy | r_uop_do_bypass_rs2; // @[rename-stage.scala:123:24, :188:49, :200:45] assign r_uop_bypassed_uop_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T; // @[rename-stage.scala:174:28, :200:45] assign _r_uop_bypassed_uop_prs3_busy_T = next_uop_prs3_busy | r_uop_do_bypass_rs3; // @[rename-stage.scala:123:24, :189:49, :201:45] assign r_uop_bypassed_uop_prs3_busy = _r_uop_bypassed_uop_prs3_busy_T; // @[rename-stage.scala:174:28, :201:45] wire [15:0] _r_uop_newuop_br_mask_T_1; // @[util.scala:74:35] wire [15:0] r_uop_newuop_br_mask; // @[util.scala:73:26] wire [15:0] _r_uop_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37] assign _r_uop_newuop_br_mask_T_1 = r_uop_bypassed_uop_br_mask & _r_uop_newuop_br_mask_T; // @[util.scala:74:{35,37}] assign r_uop_newuop_br_mask = _r_uop_newuop_br_mask_T_1; // @[util.scala:73:26, :74:35] reg r_valid_1; // @[rename-stage.scala:121:27] assign ren2_valids_1 = r_valid_1; // @[rename-stage.scala:107:29, :121:27] reg [6:0] r_uop_1_uopc; // @[rename-stage.scala:122:23] assign ren2_uops_1_uopc = r_uop_1_uopc; // @[rename-stage.scala:108:29, :122:23] reg [31:0] r_uop_1_inst; // @[rename-stage.scala:122:23] assign ren2_uops_1_inst = r_uop_1_inst; // @[rename-stage.scala:108:29, :122:23] reg [31:0] r_uop_1_debug_inst; // @[rename-stage.scala:122:23] assign ren2_uops_1_debug_inst = r_uop_1_debug_inst; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_rvc; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_rvc = r_uop_1_is_rvc; // @[rename-stage.scala:108:29, :122:23] reg [39:0] r_uop_1_debug_pc; // @[rename-stage.scala:122:23] assign ren2_uops_1_debug_pc = r_uop_1_debug_pc; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_1_iq_type; // @[rename-stage.scala:122:23] assign ren2_uops_1_iq_type = r_uop_1_iq_type; // @[rename-stage.scala:108:29, :122:23] reg [9:0] r_uop_1_fu_code; // @[rename-stage.scala:122:23] assign ren2_uops_1_fu_code = r_uop_1_fu_code; // @[rename-stage.scala:108:29, :122:23] reg [3:0] r_uop_1_ctrl_br_type; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_br_type = r_uop_1_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_ctrl_op1_sel; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_op1_sel = r_uop_1_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_1_ctrl_op2_sel; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_op2_sel = r_uop_1_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_1_ctrl_imm_sel; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_imm_sel = r_uop_1_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_1_ctrl_op_fcn; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_op_fcn = r_uop_1_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_fcn_dw = r_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_csr_cmd = r_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_ctrl_is_load; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_is_load = r_uop_1_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_ctrl_is_sta; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_is_sta = r_uop_1_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_ctrl_is_std; // @[rename-stage.scala:122:23] assign ren2_uops_1_ctrl_is_std = r_uop_1_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_iw_state; // @[rename-stage.scala:122:23] assign ren2_uops_1_iw_state = r_uop_1_iw_state; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_iw_p1_poisoned; // @[rename-stage.scala:122:23] assign ren2_uops_1_iw_p1_poisoned = r_uop_1_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_iw_p2_poisoned; // @[rename-stage.scala:122:23] assign ren2_uops_1_iw_p2_poisoned = r_uop_1_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_br; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_br = r_uop_1_is_br; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_jalr; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_jalr = r_uop_1_is_jalr; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_jal; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_jal = r_uop_1_is_jal; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_sfb; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_sfb = r_uop_1_is_sfb; // @[rename-stage.scala:108:29, :122:23] reg [15:0] r_uop_1_br_mask; // @[rename-stage.scala:122:23] assign ren2_uops_1_br_mask = r_uop_1_br_mask; // @[rename-stage.scala:108:29, :122:23] reg [3:0] r_uop_1_br_tag; // @[rename-stage.scala:122:23] assign ren2_uops_1_br_tag = r_uop_1_br_tag; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_1_ftq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_1_ftq_idx = r_uop_1_ftq_idx; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_edge_inst; // @[rename-stage.scala:122:23] assign ren2_uops_1_edge_inst = r_uop_1_edge_inst; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_1_pc_lob; // @[rename-stage.scala:122:23] assign ren2_uops_1_pc_lob = r_uop_1_pc_lob; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_taken; // @[rename-stage.scala:122:23] assign ren2_uops_1_taken = r_uop_1_taken; // @[rename-stage.scala:108:29, :122:23] reg [19:0] r_uop_1_imm_packed; // @[rename-stage.scala:122:23] assign ren2_uops_1_imm_packed = r_uop_1_imm_packed; // @[rename-stage.scala:108:29, :122:23] reg [11:0] r_uop_1_csr_addr; // @[rename-stage.scala:122:23] assign ren2_uops_1_csr_addr = r_uop_1_csr_addr; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_1_rob_idx; // @[rename-stage.scala:122:23] assign ren2_uops_1_rob_idx = r_uop_1_rob_idx; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_1_ldq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_1_ldq_idx = r_uop_1_ldq_idx; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_1_stq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_1_stq_idx = r_uop_1_stq_idx; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_rxq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_1_rxq_idx = r_uop_1_rxq_idx; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_1_pdst; // @[rename-stage.scala:122:23] reg [6:0] r_uop_1_prs1; // @[rename-stage.scala:122:23] assign ren2_uops_1_prs1 = r_uop_1_prs1; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_1_prs2; // @[rename-stage.scala:122:23] assign ren2_uops_1_prs2 = r_uop_1_prs2; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_1_prs3; // @[rename-stage.scala:122:23] assign ren2_uops_1_prs3 = r_uop_1_prs3; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_1_ppred; // @[rename-stage.scala:122:23] assign ren2_uops_1_ppred = r_uop_1_ppred; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_prs1_busy; // @[rename-stage.scala:122:23] reg r_uop_1_prs2_busy; // @[rename-stage.scala:122:23] reg r_uop_1_prs3_busy; // @[rename-stage.scala:122:23] reg r_uop_1_ppred_busy; // @[rename-stage.scala:122:23] assign ren2_uops_1_ppred_busy = r_uop_1_ppred_busy; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_1_stale_pdst; // @[rename-stage.scala:122:23] assign ren2_uops_1_stale_pdst = r_uop_1_stale_pdst; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_exception; // @[rename-stage.scala:122:23] assign ren2_uops_1_exception = r_uop_1_exception; // @[rename-stage.scala:108:29, :122:23] reg [63:0] r_uop_1_exc_cause; // @[rename-stage.scala:122:23] assign ren2_uops_1_exc_cause = r_uop_1_exc_cause; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_bypassable; // @[rename-stage.scala:122:23] assign ren2_uops_1_bypassable = r_uop_1_bypassable; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_1_mem_cmd; // @[rename-stage.scala:122:23] assign ren2_uops_1_mem_cmd = r_uop_1_mem_cmd; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_mem_size; // @[rename-stage.scala:122:23] assign ren2_uops_1_mem_size = r_uop_1_mem_size; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_mem_signed; // @[rename-stage.scala:122:23] assign ren2_uops_1_mem_signed = r_uop_1_mem_signed; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_fence; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_fence = r_uop_1_is_fence; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_fencei; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_fencei = r_uop_1_is_fencei; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_amo; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_amo = r_uop_1_is_amo; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_uses_ldq; // @[rename-stage.scala:122:23] assign ren2_uops_1_uses_ldq = r_uop_1_uses_ldq; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_uses_stq; // @[rename-stage.scala:122:23] assign ren2_uops_1_uses_stq = r_uop_1_uses_stq; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_sys_pc2epc; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_sys_pc2epc = r_uop_1_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_is_unique; // @[rename-stage.scala:122:23] assign ren2_uops_1_is_unique = r_uop_1_is_unique; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_flush_on_commit; // @[rename-stage.scala:122:23] assign ren2_uops_1_flush_on_commit = r_uop_1_flush_on_commit; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_ldst_is_rs1; // @[rename-stage.scala:122:23] assign ren2_uops_1_ldst_is_rs1 = r_uop_1_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_1_ldst; // @[rename-stage.scala:122:23] assign ren2_uops_1_ldst = r_uop_1_ldst; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_1_lrs1; // @[rename-stage.scala:122:23] assign ren2_uops_1_lrs1 = r_uop_1_lrs1; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_1_lrs2; // @[rename-stage.scala:122:23] assign ren2_uops_1_lrs2 = r_uop_1_lrs2; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_1_lrs3; // @[rename-stage.scala:122:23] assign ren2_uops_1_lrs3 = r_uop_1_lrs3; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_ldst_val; // @[rename-stage.scala:122:23] assign ren2_uops_1_ldst_val = r_uop_1_ldst_val; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_dst_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_1_dst_rtype = r_uop_1_dst_rtype; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_lrs1_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_1_lrs1_rtype = r_uop_1_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_lrs2_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_1_lrs2_rtype = r_uop_1_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_frs3_en; // @[rename-stage.scala:122:23] assign ren2_uops_1_frs3_en = r_uop_1_frs3_en; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_fp_val; // @[rename-stage.scala:122:23] assign ren2_uops_1_fp_val = r_uop_1_fp_val; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_fp_single; // @[rename-stage.scala:122:23] assign ren2_uops_1_fp_single = r_uop_1_fp_single; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_xcpt_pf_if; // @[rename-stage.scala:122:23] assign ren2_uops_1_xcpt_pf_if = r_uop_1_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_xcpt_ae_if; // @[rename-stage.scala:122:23] assign ren2_uops_1_xcpt_ae_if = r_uop_1_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_xcpt_ma_if; // @[rename-stage.scala:122:23] assign ren2_uops_1_xcpt_ma_if = r_uop_1_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_bp_debug_if; // @[rename-stage.scala:122:23] assign ren2_uops_1_bp_debug_if = r_uop_1_bp_debug_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_1_bp_xcpt_if; // @[rename-stage.scala:122:23] assign ren2_uops_1_bp_xcpt_if = r_uop_1_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_debug_fsrc; // @[rename-stage.scala:122:23] assign ren2_uops_1_debug_fsrc = r_uop_1_debug_fsrc; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_1_debug_tsrc; // @[rename-stage.scala:122:23] assign ren2_uops_1_debug_tsrc = r_uop_1_debug_tsrc; // @[rename-stage.scala:108:29, :122:23] wire [6:0] r_uop_bypassed_uop_1_uopc = next_uop_1_uopc; // @[rename-stage.scala:123:24, :174:28] wire [31:0] r_uop_bypassed_uop_1_inst = next_uop_1_inst; // @[rename-stage.scala:123:24, :174:28] wire [31:0] r_uop_bypassed_uop_1_debug_inst = next_uop_1_debug_inst; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_rvc = next_uop_1_is_rvc; // @[rename-stage.scala:123:24, :174:28] wire [39:0] r_uop_bypassed_uop_1_debug_pc = next_uop_1_debug_pc; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_1_iq_type = next_uop_1_iq_type; // @[rename-stage.scala:123:24, :174:28] wire [9:0] r_uop_bypassed_uop_1_fu_code = next_uop_1_fu_code; // @[rename-stage.scala:123:24, :174:28] wire [3:0] r_uop_bypassed_uop_1_ctrl_br_type = next_uop_1_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_ctrl_op1_sel = next_uop_1_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_1_ctrl_op2_sel = next_uop_1_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_1_ctrl_imm_sel = next_uop_1_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_1_ctrl_op_fcn = next_uop_1_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ctrl_fcn_dw = next_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_1_ctrl_csr_cmd = next_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ctrl_is_load = next_uop_1_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ctrl_is_sta = next_uop_1_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ctrl_is_std = next_uop_1_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_iw_state = next_uop_1_iw_state; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_iw_p1_poisoned = next_uop_1_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_iw_p2_poisoned = next_uop_1_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_br = next_uop_1_is_br; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_jalr = next_uop_1_is_jalr; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_jal = next_uop_1_is_jal; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_sfb = next_uop_1_is_sfb; // @[rename-stage.scala:123:24, :174:28] wire [15:0] r_uop_bypassed_uop_1_br_mask = next_uop_1_br_mask; // @[rename-stage.scala:123:24, :174:28] wire [3:0] r_uop_bypassed_uop_1_br_tag = next_uop_1_br_tag; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_1_ftq_idx = next_uop_1_ftq_idx; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_edge_inst = next_uop_1_edge_inst; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_1_pc_lob = next_uop_1_pc_lob; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_taken = next_uop_1_taken; // @[rename-stage.scala:123:24, :174:28] wire [19:0] r_uop_bypassed_uop_1_imm_packed = next_uop_1_imm_packed; // @[rename-stage.scala:123:24, :174:28] wire [11:0] r_uop_bypassed_uop_1_csr_addr = next_uop_1_csr_addr; // @[rename-stage.scala:123:24, :174:28] wire [6:0] r_uop_bypassed_uop_1_rob_idx = next_uop_1_rob_idx; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_1_ldq_idx = next_uop_1_ldq_idx; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_1_stq_idx = next_uop_1_stq_idx; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_rxq_idx = next_uop_1_rxq_idx; // @[rename-stage.scala:123:24, :174:28] wire [6:0] r_uop_bypassed_uop_1_pdst = next_uop_1_pdst; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_1_ppred = next_uop_1_ppred; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ppred_busy = next_uop_1_ppred_busy; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_exception = next_uop_1_exception; // @[rename-stage.scala:123:24, :174:28] wire [63:0] r_uop_bypassed_uop_1_exc_cause = next_uop_1_exc_cause; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_bypassable = next_uop_1_bypassable; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_1_mem_cmd = next_uop_1_mem_cmd; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_mem_size = next_uop_1_mem_size; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_mem_signed = next_uop_1_mem_signed; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_fence = next_uop_1_is_fence; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_fencei = next_uop_1_is_fencei; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_amo = next_uop_1_is_amo; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_uses_ldq = next_uop_1_uses_ldq; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_uses_stq = next_uop_1_uses_stq; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_sys_pc2epc = next_uop_1_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_is_unique = next_uop_1_is_unique; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_flush_on_commit = next_uop_1_flush_on_commit; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ldst_is_rs1 = next_uop_1_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_1_ldst = next_uop_1_ldst; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_1_lrs1 = next_uop_1_lrs1; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_1_lrs2 = next_uop_1_lrs2; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_1_lrs3 = next_uop_1_lrs3; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_ldst_val = next_uop_1_ldst_val; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_dst_rtype = next_uop_1_dst_rtype; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_lrs1_rtype = next_uop_1_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_lrs2_rtype = next_uop_1_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_frs3_en = next_uop_1_frs3_en; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_fp_val = next_uop_1_fp_val; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_fp_single = next_uop_1_fp_single; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_xcpt_pf_if = next_uop_1_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_xcpt_ae_if = next_uop_1_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_xcpt_ma_if = next_uop_1_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_bp_debug_if = next_uop_1_bp_debug_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_1_bp_xcpt_if = next_uop_1_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_debug_fsrc = next_uop_1_debug_fsrc; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_1_debug_tsrc = next_uop_1_debug_tsrc; // @[rename-stage.scala:123:24, :174:28] wire [6:0] next_uop_1_prs1; // @[rename-stage.scala:123:24] wire [6:0] next_uop_1_prs2; // @[rename-stage.scala:123:24] wire [6:0] next_uop_1_prs3; // @[rename-stage.scala:123:24] wire next_uop_1_prs1_busy; // @[rename-stage.scala:123:24] wire next_uop_1_prs2_busy; // @[rename-stage.scala:123:24] wire next_uop_1_prs3_busy; // @[rename-stage.scala:123:24] wire [6:0] next_uop_1_stale_pdst; // @[rename-stage.scala:123:24] wire _r_valid_T_2 = ~io_dis_fire_1_0; // @[rename-stage.scala:133:29, :160:7] wire _r_valid_T_3 = r_valid_1 & _r_valid_T_2; // @[rename-stage.scala:121:27, :133:{26,29}] assign next_uop_1_uopc = _GEN ? r_uop_1_uopc : ren1_uops_1_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_inst = _GEN ? r_uop_1_inst : ren1_uops_1_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_debug_inst = _GEN ? r_uop_1_debug_inst : ren1_uops_1_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_rvc = _GEN ? r_uop_1_is_rvc : ren1_uops_1_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_debug_pc = _GEN ? r_uop_1_debug_pc : ren1_uops_1_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_iq_type = _GEN ? r_uop_1_iq_type : ren1_uops_1_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_fu_code = _GEN ? r_uop_1_fu_code : ren1_uops_1_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_br_type = _GEN ? r_uop_1_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_op1_sel = _GEN ? r_uop_1_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_op2_sel = _GEN ? r_uop_1_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_imm_sel = _GEN ? r_uop_1_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_op_fcn = _GEN ? r_uop_1_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_fcn_dw = _GEN & r_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_csr_cmd = _GEN ? r_uop_1_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_is_load = _GEN & r_uop_1_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_is_sta = _GEN & r_uop_1_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ctrl_is_std = _GEN & r_uop_1_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_iw_state = _GEN ? r_uop_1_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_iw_p1_poisoned = _GEN & r_uop_1_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_iw_p2_poisoned = _GEN & r_uop_1_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_br = _GEN ? r_uop_1_is_br : ren1_uops_1_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_jalr = _GEN ? r_uop_1_is_jalr : ren1_uops_1_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_jal = _GEN ? r_uop_1_is_jal : ren1_uops_1_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_sfb = _GEN ? r_uop_1_is_sfb : ren1_uops_1_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_br_mask = _GEN ? r_uop_1_br_mask : ren1_uops_1_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_br_tag = _GEN ? r_uop_1_br_tag : ren1_uops_1_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ftq_idx = _GEN ? r_uop_1_ftq_idx : ren1_uops_1_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_edge_inst = _GEN ? r_uop_1_edge_inst : ren1_uops_1_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_pc_lob = _GEN ? r_uop_1_pc_lob : ren1_uops_1_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_taken = _GEN ? r_uop_1_taken : ren1_uops_1_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_imm_packed = _GEN ? r_uop_1_imm_packed : ren1_uops_1_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_csr_addr = _GEN ? r_uop_1_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_rob_idx = _GEN ? r_uop_1_rob_idx : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ldq_idx = _GEN ? r_uop_1_ldq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_stq_idx = _GEN ? r_uop_1_stq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_rxq_idx = _GEN ? r_uop_1_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_pdst = _GEN ? r_uop_1_pdst : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_prs1 = _GEN ? r_uop_1_prs1 : ren1_uops_1_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_prs2 = _GEN ? r_uop_1_prs2 : ren1_uops_1_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_prs3 = _GEN ? r_uop_1_prs3 : ren1_uops_1_prs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ppred = _GEN ? r_uop_1_ppred : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_prs1_busy = _GEN & r_uop_1_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_prs2_busy = _GEN & r_uop_1_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_prs3_busy = _GEN & r_uop_1_prs3_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ppred_busy = _GEN & r_uop_1_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_stale_pdst = _GEN ? r_uop_1_stale_pdst : ren1_uops_1_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_exception = _GEN ? r_uop_1_exception : ren1_uops_1_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_exc_cause = _GEN ? r_uop_1_exc_cause : ren1_uops_1_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_bypassable = _GEN ? r_uop_1_bypassable : ren1_uops_1_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_mem_cmd = _GEN ? r_uop_1_mem_cmd : ren1_uops_1_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_mem_size = _GEN ? r_uop_1_mem_size : ren1_uops_1_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_mem_signed = _GEN ? r_uop_1_mem_signed : ren1_uops_1_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_fence = _GEN ? r_uop_1_is_fence : ren1_uops_1_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_fencei = _GEN ? r_uop_1_is_fencei : ren1_uops_1_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_amo = _GEN ? r_uop_1_is_amo : ren1_uops_1_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_uses_ldq = _GEN ? r_uop_1_uses_ldq : ren1_uops_1_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_uses_stq = _GEN ? r_uop_1_uses_stq : ren1_uops_1_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_sys_pc2epc = _GEN ? r_uop_1_is_sys_pc2epc : ren1_uops_1_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_is_unique = _GEN ? r_uop_1_is_unique : ren1_uops_1_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_flush_on_commit = _GEN ? r_uop_1_flush_on_commit : ren1_uops_1_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ldst_is_rs1 = _GEN & r_uop_1_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ldst = _GEN ? r_uop_1_ldst : ren1_uops_1_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_lrs1 = _GEN ? r_uop_1_lrs1 : ren1_uops_1_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_lrs2 = _GEN ? r_uop_1_lrs2 : ren1_uops_1_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_lrs3 = _GEN ? r_uop_1_lrs3 : ren1_uops_1_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_ldst_val = _GEN ? r_uop_1_ldst_val : ren1_uops_1_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_dst_rtype = _GEN ? r_uop_1_dst_rtype : ren1_uops_1_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_lrs1_rtype = _GEN ? r_uop_1_lrs1_rtype : ren1_uops_1_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_lrs2_rtype = _GEN ? r_uop_1_lrs2_rtype : ren1_uops_1_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_frs3_en = _GEN ? r_uop_1_frs3_en : ren1_uops_1_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_fp_val = _GEN ? r_uop_1_fp_val : ren1_uops_1_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_fp_single = _GEN ? r_uop_1_fp_single : ren1_uops_1_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_xcpt_pf_if = _GEN ? r_uop_1_xcpt_pf_if : ren1_uops_1_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_xcpt_ae_if = _GEN ? r_uop_1_xcpt_ae_if : ren1_uops_1_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_xcpt_ma_if = _GEN & r_uop_1_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_bp_debug_if = _GEN ? r_uop_1_bp_debug_if : ren1_uops_1_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_bp_xcpt_if = _GEN ? r_uop_1_bp_xcpt_if : ren1_uops_1_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_debug_fsrc = _GEN ? r_uop_1_debug_fsrc : ren1_uops_1_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_1_debug_tsrc = _GEN ? r_uop_1_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] wire [6:0] r_uop_newuop_1_uopc = r_uop_bypassed_uop_1_uopc; // @[util.scala:73:26] wire [31:0] r_uop_newuop_1_inst = r_uop_bypassed_uop_1_inst; // @[util.scala:73:26] wire [31:0] r_uop_newuop_1_debug_inst = r_uop_bypassed_uop_1_debug_inst; // @[util.scala:73:26] wire r_uop_newuop_1_is_rvc = r_uop_bypassed_uop_1_is_rvc; // @[util.scala:73:26] wire [39:0] r_uop_newuop_1_debug_pc = r_uop_bypassed_uop_1_debug_pc; // @[util.scala:73:26] wire [2:0] r_uop_newuop_1_iq_type = r_uop_bypassed_uop_1_iq_type; // @[util.scala:73:26] wire [9:0] r_uop_newuop_1_fu_code = r_uop_bypassed_uop_1_fu_code; // @[util.scala:73:26] wire [3:0] r_uop_newuop_1_ctrl_br_type = r_uop_bypassed_uop_1_ctrl_br_type; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_ctrl_op1_sel = r_uop_bypassed_uop_1_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] r_uop_newuop_1_ctrl_op2_sel = r_uop_bypassed_uop_1_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] r_uop_newuop_1_ctrl_imm_sel = r_uop_bypassed_uop_1_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] r_uop_newuop_1_ctrl_op_fcn = r_uop_bypassed_uop_1_ctrl_op_fcn; // @[util.scala:73:26] wire r_uop_newuop_1_ctrl_fcn_dw = r_uop_bypassed_uop_1_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] r_uop_newuop_1_ctrl_csr_cmd = r_uop_bypassed_uop_1_ctrl_csr_cmd; // @[util.scala:73:26] wire r_uop_newuop_1_ctrl_is_load = r_uop_bypassed_uop_1_ctrl_is_load; // @[util.scala:73:26] wire r_uop_newuop_1_ctrl_is_sta = r_uop_bypassed_uop_1_ctrl_is_sta; // @[util.scala:73:26] wire r_uop_newuop_1_ctrl_is_std = r_uop_bypassed_uop_1_ctrl_is_std; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_iw_state = r_uop_bypassed_uop_1_iw_state; // @[util.scala:73:26] wire r_uop_newuop_1_iw_p1_poisoned = r_uop_bypassed_uop_1_iw_p1_poisoned; // @[util.scala:73:26] wire r_uop_newuop_1_iw_p2_poisoned = r_uop_bypassed_uop_1_iw_p2_poisoned; // @[util.scala:73:26] wire r_uop_newuop_1_is_br = r_uop_bypassed_uop_1_is_br; // @[util.scala:73:26] wire r_uop_newuop_1_is_jalr = r_uop_bypassed_uop_1_is_jalr; // @[util.scala:73:26] wire r_uop_newuop_1_is_jal = r_uop_bypassed_uop_1_is_jal; // @[util.scala:73:26] wire r_uop_newuop_1_is_sfb = r_uop_bypassed_uop_1_is_sfb; // @[util.scala:73:26] wire [3:0] r_uop_newuop_1_br_tag = r_uop_bypassed_uop_1_br_tag; // @[util.scala:73:26] wire [4:0] r_uop_newuop_1_ftq_idx = r_uop_bypassed_uop_1_ftq_idx; // @[util.scala:73:26] wire r_uop_newuop_1_edge_inst = r_uop_bypassed_uop_1_edge_inst; // @[util.scala:73:26] wire [5:0] r_uop_newuop_1_pc_lob = r_uop_bypassed_uop_1_pc_lob; // @[util.scala:73:26] wire r_uop_newuop_1_taken = r_uop_bypassed_uop_1_taken; // @[util.scala:73:26] wire [19:0] r_uop_newuop_1_imm_packed = r_uop_bypassed_uop_1_imm_packed; // @[util.scala:73:26] wire [11:0] r_uop_newuop_1_csr_addr = r_uop_bypassed_uop_1_csr_addr; // @[util.scala:73:26] wire [6:0] r_uop_newuop_1_rob_idx = r_uop_bypassed_uop_1_rob_idx; // @[util.scala:73:26] wire [4:0] r_uop_newuop_1_ldq_idx = r_uop_bypassed_uop_1_ldq_idx; // @[util.scala:73:26] wire [4:0] r_uop_newuop_1_stq_idx = r_uop_bypassed_uop_1_stq_idx; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_rxq_idx = r_uop_bypassed_uop_1_rxq_idx; // @[util.scala:73:26] wire [6:0] r_uop_newuop_1_pdst = r_uop_bypassed_uop_1_pdst; // @[util.scala:73:26] wire [6:0] r_uop_newuop_1_prs1 = r_uop_bypassed_uop_1_prs1; // @[util.scala:73:26] wire [6:0] r_uop_newuop_1_prs2 = r_uop_bypassed_uop_1_prs2; // @[util.scala:73:26] wire [6:0] r_uop_newuop_1_prs3 = r_uop_bypassed_uop_1_prs3; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs1_busy_T_1; // @[rename-stage.scala:199:45] wire [4:0] r_uop_newuop_1_ppred = r_uop_bypassed_uop_1_ppred; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs2_busy_T_1; // @[rename-stage.scala:200:45] wire r_uop_newuop_1_prs1_busy = r_uop_bypassed_uop_1_prs1_busy; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs3_busy_T_1; // @[rename-stage.scala:201:45] wire r_uop_newuop_1_prs2_busy = r_uop_bypassed_uop_1_prs2_busy; // @[util.scala:73:26] wire r_uop_newuop_1_prs3_busy = r_uop_bypassed_uop_1_prs3_busy; // @[util.scala:73:26] wire r_uop_newuop_1_ppred_busy = r_uop_bypassed_uop_1_ppred_busy; // @[util.scala:73:26] wire [6:0] r_uop_newuop_1_stale_pdst = r_uop_bypassed_uop_1_stale_pdst; // @[util.scala:73:26] wire r_uop_newuop_1_exception = r_uop_bypassed_uop_1_exception; // @[util.scala:73:26] wire [63:0] r_uop_newuop_1_exc_cause = r_uop_bypassed_uop_1_exc_cause; // @[util.scala:73:26] wire r_uop_newuop_1_bypassable = r_uop_bypassed_uop_1_bypassable; // @[util.scala:73:26] wire [4:0] r_uop_newuop_1_mem_cmd = r_uop_bypassed_uop_1_mem_cmd; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_mem_size = r_uop_bypassed_uop_1_mem_size; // @[util.scala:73:26] wire r_uop_newuop_1_mem_signed = r_uop_bypassed_uop_1_mem_signed; // @[util.scala:73:26] wire r_uop_newuop_1_is_fence = r_uop_bypassed_uop_1_is_fence; // @[util.scala:73:26] wire r_uop_newuop_1_is_fencei = r_uop_bypassed_uop_1_is_fencei; // @[util.scala:73:26] wire r_uop_newuop_1_is_amo = r_uop_bypassed_uop_1_is_amo; // @[util.scala:73:26] wire r_uop_newuop_1_uses_ldq = r_uop_bypassed_uop_1_uses_ldq; // @[util.scala:73:26] wire r_uop_newuop_1_uses_stq = r_uop_bypassed_uop_1_uses_stq; // @[util.scala:73:26] wire r_uop_newuop_1_is_sys_pc2epc = r_uop_bypassed_uop_1_is_sys_pc2epc; // @[util.scala:73:26] wire r_uop_newuop_1_is_unique = r_uop_bypassed_uop_1_is_unique; // @[util.scala:73:26] wire r_uop_newuop_1_flush_on_commit = r_uop_bypassed_uop_1_flush_on_commit; // @[util.scala:73:26] wire r_uop_newuop_1_ldst_is_rs1 = r_uop_bypassed_uop_1_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] r_uop_newuop_1_ldst = r_uop_bypassed_uop_1_ldst; // @[util.scala:73:26] wire [5:0] r_uop_newuop_1_lrs1 = r_uop_bypassed_uop_1_lrs1; // @[util.scala:73:26] wire [5:0] r_uop_newuop_1_lrs2 = r_uop_bypassed_uop_1_lrs2; // @[util.scala:73:26] wire [5:0] r_uop_newuop_1_lrs3 = r_uop_bypassed_uop_1_lrs3; // @[util.scala:73:26] wire r_uop_newuop_1_ldst_val = r_uop_bypassed_uop_1_ldst_val; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_dst_rtype = r_uop_bypassed_uop_1_dst_rtype; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_lrs1_rtype = r_uop_bypassed_uop_1_lrs1_rtype; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_lrs2_rtype = r_uop_bypassed_uop_1_lrs2_rtype; // @[util.scala:73:26] wire r_uop_newuop_1_frs3_en = r_uop_bypassed_uop_1_frs3_en; // @[util.scala:73:26] wire r_uop_newuop_1_fp_val = r_uop_bypassed_uop_1_fp_val; // @[util.scala:73:26] wire r_uop_newuop_1_fp_single = r_uop_bypassed_uop_1_fp_single; // @[util.scala:73:26] wire r_uop_newuop_1_xcpt_pf_if = r_uop_bypassed_uop_1_xcpt_pf_if; // @[util.scala:73:26] wire r_uop_newuop_1_xcpt_ae_if = r_uop_bypassed_uop_1_xcpt_ae_if; // @[util.scala:73:26] wire r_uop_newuop_1_xcpt_ma_if = r_uop_bypassed_uop_1_xcpt_ma_if; // @[util.scala:73:26] wire r_uop_newuop_1_bp_debug_if = r_uop_bypassed_uop_1_bp_debug_if; // @[util.scala:73:26] wire r_uop_newuop_1_bp_xcpt_if = r_uop_bypassed_uop_1_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_debug_fsrc = r_uop_bypassed_uop_1_debug_fsrc; // @[util.scala:73:26] wire [1:0] r_uop_newuop_1_debug_tsrc = r_uop_bypassed_uop_1_debug_tsrc; // @[util.scala:73:26] wire _r_uop_bypass_hits_rs1_T_3 = ren2_uops_0_ldst == next_uop_1_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T_3; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs1_T_4 = ren2_uops_1_ldst == next_uop_1_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs1_T_4; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs1_T_5 = ren2_uops_2_ldst == next_uop_1_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs1_T_5; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs2_T_3 = ren2_uops_0_ldst == next_uop_1_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T_3; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs2_T_4 = ren2_uops_1_ldst == next_uop_1_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs2_T_4; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs2_T_5 = ren2_uops_2_ldst == next_uop_1_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs2_T_5; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs3_T_3 = ren2_uops_0_ldst == next_uop_1_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T_3; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_rs3_T_4 = ren2_uops_1_ldst == next_uop_1_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs3_T_4; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_rs3_T_5 = ren2_uops_2_ldst == next_uop_1_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs3_T_5; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_dst_T_3 = ren2_uops_0_ldst == next_uop_1_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T_3; // @[rename-stage.scala:109:29, :180:{77,87}] wire _r_uop_bypass_hits_dst_T_4 = ren2_uops_1_ldst == next_uop_1_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_dst_T_4; // @[rename-stage.scala:109:29, :180:{77,87}] wire _r_uop_bypass_hits_dst_T_5 = ren2_uops_2_ldst == next_uop_1_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_dst_T_5; // @[rename-stage.scala:109:29, :180:{77,87}] wire [2:0] _r_uop_bypass_sel_rs1_enc_T_2 = {r_uop_bypass_hits_rs1_0_1, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs1_enc_T_3 = r_uop_bypass_hits_rs1_1_1 ? 3'h2 : _r_uop_bypass_sel_rs1_enc_T_2; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs1_enc_1 = r_uop_bypass_hits_rs1_2_1 ? 3'h1 : _r_uop_bypass_sel_rs1_enc_T_3; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs1_2_1 = r_uop_bypass_sel_rs1_enc_1[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs1_1_1 = r_uop_bypass_sel_rs1_enc_1[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs1_0_1 = r_uop_bypass_sel_rs1_enc_1[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_rs2_enc_T_2 = {r_uop_bypass_hits_rs2_0_1, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs2_enc_T_3 = r_uop_bypass_hits_rs2_1_1 ? 3'h2 : _r_uop_bypass_sel_rs2_enc_T_2; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs2_enc_1 = r_uop_bypass_hits_rs2_2_1 ? 3'h1 : _r_uop_bypass_sel_rs2_enc_T_3; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs2_2_1 = r_uop_bypass_sel_rs2_enc_1[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs2_1_1 = r_uop_bypass_sel_rs2_enc_1[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs2_0_1 = r_uop_bypass_sel_rs2_enc_1[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_rs3_enc_T_2 = {r_uop_bypass_hits_rs3_0_1, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs3_enc_T_3 = r_uop_bypass_hits_rs3_1_1 ? 3'h2 : _r_uop_bypass_sel_rs3_enc_T_2; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs3_enc_1 = r_uop_bypass_hits_rs3_2_1 ? 3'h1 : _r_uop_bypass_sel_rs3_enc_T_3; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs3_2_1 = r_uop_bypass_sel_rs3_enc_1[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs3_1_1 = r_uop_bypass_sel_rs3_enc_1[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs3_0_1 = r_uop_bypass_sel_rs3_enc_1[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_dst_enc_T_2 = {r_uop_bypass_hits_dst_0_1, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_dst_enc_T_3 = r_uop_bypass_hits_dst_1_1 ? 3'h2 : _r_uop_bypass_sel_dst_enc_T_2; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_dst_enc_1 = r_uop_bypass_hits_dst_2_1 ? 3'h1 : _r_uop_bypass_sel_dst_enc_T_3; // @[Mux.scala:50:70] wire r_uop_bypass_sel_dst_2_1 = r_uop_bypass_sel_dst_enc_1[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_dst_1_1 = r_uop_bypass_sel_dst_enc_1[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_dst_0_1 = r_uop_bypass_sel_dst_enc_1[2]; // @[OneHot.scala:83:30] wire _r_uop_do_bypass_rs1_T_1 = r_uop_bypass_hits_rs1_0_1 | r_uop_bypass_hits_rs1_1_1; // @[rename-stage.scala:177:77, :187:49] wire r_uop_do_bypass_rs1_1 = _r_uop_do_bypass_rs1_T_1 | r_uop_bypass_hits_rs1_2_1; // @[rename-stage.scala:177:77, :187:49] wire _r_uop_do_bypass_rs2_T_1 = r_uop_bypass_hits_rs2_0_1 | r_uop_bypass_hits_rs2_1_1; // @[rename-stage.scala:178:77, :188:49] wire r_uop_do_bypass_rs2_1 = _r_uop_do_bypass_rs2_T_1 | r_uop_bypass_hits_rs2_2_1; // @[rename-stage.scala:178:77, :188:49] wire _r_uop_do_bypass_rs3_T_1 = r_uop_bypass_hits_rs3_0_1 | r_uop_bypass_hits_rs3_1_1; // @[rename-stage.scala:179:77, :189:49] wire r_uop_do_bypass_rs3_1 = _r_uop_do_bypass_rs3_T_1 | r_uop_bypass_hits_rs3_2_1; // @[rename-stage.scala:179:77, :189:49] wire _r_uop_do_bypass_dst_T_1 = r_uop_bypass_hits_dst_0_1 | r_uop_bypass_hits_dst_1_1; // @[rename-stage.scala:180:77, :190:49] wire r_uop_do_bypass_dst_1 = _r_uop_do_bypass_dst_T_1 | r_uop_bypass_hits_dst_2_1; // @[rename-stage.scala:180:77, :190:49] wire [6:0] _r_uop_bypassed_uop_prs1_T_5 = r_uop_bypass_sel_rs1_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_6 = r_uop_bypass_sel_rs1_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_7 = r_uop_bypass_sel_rs1_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_8 = _r_uop_bypassed_uop_prs1_T_5 | _r_uop_bypassed_uop_prs1_T_6; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs1_T_9 = _r_uop_bypassed_uop_prs1_T_8 | _r_uop_bypassed_uop_prs1_T_7; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs1_WIRE_1 = _r_uop_bypassed_uop_prs1_T_9; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_1_prs1 = r_uop_do_bypass_rs1_1 ? _r_uop_bypassed_uop_prs1_WIRE_1 : next_uop_1_prs1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_T_5 = r_uop_bypass_sel_rs2_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_6 = r_uop_bypass_sel_rs2_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_7 = r_uop_bypass_sel_rs2_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_8 = _r_uop_bypassed_uop_prs2_T_5 | _r_uop_bypassed_uop_prs2_T_6; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_T_9 = _r_uop_bypassed_uop_prs2_T_8 | _r_uop_bypassed_uop_prs2_T_7; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_WIRE_1 = _r_uop_bypassed_uop_prs2_T_9; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_1_prs2 = r_uop_do_bypass_rs2_1 ? _r_uop_bypassed_uop_prs2_WIRE_1 : next_uop_1_prs2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_T_5 = r_uop_bypass_sel_rs3_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_6 = r_uop_bypass_sel_rs3_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_7 = r_uop_bypass_sel_rs3_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_8 = _r_uop_bypassed_uop_prs3_T_5 | _r_uop_bypassed_uop_prs3_T_6; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_T_9 = _r_uop_bypassed_uop_prs3_T_8 | _r_uop_bypassed_uop_prs3_T_7; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_WIRE_1 = _r_uop_bypassed_uop_prs3_T_9; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_1_prs3 = r_uop_do_bypass_rs3_1 ? _r_uop_bypassed_uop_prs3_WIRE_1 : next_uop_1_prs3; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_5 = r_uop_bypass_sel_dst_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_6 = r_uop_bypass_sel_dst_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_7 = r_uop_bypass_sel_dst_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_8 = _r_uop_bypassed_uop_stale_pdst_T_5 | _r_uop_bypassed_uop_stale_pdst_T_6; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_9 = _r_uop_bypassed_uop_stale_pdst_T_8 | _r_uop_bypassed_uop_stale_pdst_T_7; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_WIRE_1 = _r_uop_bypassed_uop_stale_pdst_T_9; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_1_stale_pdst = r_uop_do_bypass_dst_1 ? _r_uop_bypassed_uop_stale_pdst_WIRE_1 : next_uop_1_stale_pdst; // @[Mux.scala:30:73] assign _r_uop_bypassed_uop_prs1_busy_T_1 = next_uop_1_prs1_busy | r_uop_do_bypass_rs1_1; // @[rename-stage.scala:123:24, :187:49, :199:45] assign r_uop_bypassed_uop_1_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T_1; // @[rename-stage.scala:174:28, :199:45] assign _r_uop_bypassed_uop_prs2_busy_T_1 = next_uop_1_prs2_busy | r_uop_do_bypass_rs2_1; // @[rename-stage.scala:123:24, :188:49, :200:45] assign r_uop_bypassed_uop_1_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T_1; // @[rename-stage.scala:174:28, :200:45] assign _r_uop_bypassed_uop_prs3_busy_T_1 = next_uop_1_prs3_busy | r_uop_do_bypass_rs3_1; // @[rename-stage.scala:123:24, :189:49, :201:45] assign r_uop_bypassed_uop_1_prs3_busy = _r_uop_bypassed_uop_prs3_busy_T_1; // @[rename-stage.scala:174:28, :201:45] wire [15:0] _r_uop_newuop_br_mask_T_3; // @[util.scala:74:35] wire [15:0] r_uop_newuop_1_br_mask; // @[util.scala:73:26] wire [15:0] _r_uop_newuop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37] assign _r_uop_newuop_br_mask_T_3 = r_uop_bypassed_uop_1_br_mask & _r_uop_newuop_br_mask_T_2; // @[util.scala:74:{35,37}] assign r_uop_newuop_1_br_mask = _r_uop_newuop_br_mask_T_3; // @[util.scala:73:26, :74:35] reg r_valid_2; // @[rename-stage.scala:121:27] assign ren2_valids_2 = r_valid_2; // @[rename-stage.scala:107:29, :121:27] reg [6:0] r_uop_2_uopc; // @[rename-stage.scala:122:23] assign ren2_uops_2_uopc = r_uop_2_uopc; // @[rename-stage.scala:108:29, :122:23] reg [31:0] r_uop_2_inst; // @[rename-stage.scala:122:23] assign ren2_uops_2_inst = r_uop_2_inst; // @[rename-stage.scala:108:29, :122:23] reg [31:0] r_uop_2_debug_inst; // @[rename-stage.scala:122:23] assign ren2_uops_2_debug_inst = r_uop_2_debug_inst; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_rvc; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_rvc = r_uop_2_is_rvc; // @[rename-stage.scala:108:29, :122:23] reg [39:0] r_uop_2_debug_pc; // @[rename-stage.scala:122:23] assign ren2_uops_2_debug_pc = r_uop_2_debug_pc; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_2_iq_type; // @[rename-stage.scala:122:23] assign ren2_uops_2_iq_type = r_uop_2_iq_type; // @[rename-stage.scala:108:29, :122:23] reg [9:0] r_uop_2_fu_code; // @[rename-stage.scala:122:23] assign ren2_uops_2_fu_code = r_uop_2_fu_code; // @[rename-stage.scala:108:29, :122:23] reg [3:0] r_uop_2_ctrl_br_type; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_br_type = r_uop_2_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_ctrl_op1_sel; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_op1_sel = r_uop_2_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_2_ctrl_op2_sel; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_op2_sel = r_uop_2_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_2_ctrl_imm_sel; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_imm_sel = r_uop_2_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_2_ctrl_op_fcn; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_op_fcn = r_uop_2_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_fcn_dw = r_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23] reg [2:0] r_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_csr_cmd = r_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_ctrl_is_load; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_is_load = r_uop_2_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_ctrl_is_sta; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_is_sta = r_uop_2_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_ctrl_is_std; // @[rename-stage.scala:122:23] assign ren2_uops_2_ctrl_is_std = r_uop_2_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_iw_state; // @[rename-stage.scala:122:23] assign ren2_uops_2_iw_state = r_uop_2_iw_state; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_iw_p1_poisoned; // @[rename-stage.scala:122:23] assign ren2_uops_2_iw_p1_poisoned = r_uop_2_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_iw_p2_poisoned; // @[rename-stage.scala:122:23] assign ren2_uops_2_iw_p2_poisoned = r_uop_2_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_br; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_br = r_uop_2_is_br; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_jalr; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_jalr = r_uop_2_is_jalr; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_jal; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_jal = r_uop_2_is_jal; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_sfb; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_sfb = r_uop_2_is_sfb; // @[rename-stage.scala:108:29, :122:23] reg [15:0] r_uop_2_br_mask; // @[rename-stage.scala:122:23] assign ren2_uops_2_br_mask = r_uop_2_br_mask; // @[rename-stage.scala:108:29, :122:23] reg [3:0] r_uop_2_br_tag; // @[rename-stage.scala:122:23] assign ren2_uops_2_br_tag = r_uop_2_br_tag; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_2_ftq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_2_ftq_idx = r_uop_2_ftq_idx; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_edge_inst; // @[rename-stage.scala:122:23] assign ren2_uops_2_edge_inst = r_uop_2_edge_inst; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_2_pc_lob; // @[rename-stage.scala:122:23] assign ren2_uops_2_pc_lob = r_uop_2_pc_lob; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_taken; // @[rename-stage.scala:122:23] assign ren2_uops_2_taken = r_uop_2_taken; // @[rename-stage.scala:108:29, :122:23] reg [19:0] r_uop_2_imm_packed; // @[rename-stage.scala:122:23] assign ren2_uops_2_imm_packed = r_uop_2_imm_packed; // @[rename-stage.scala:108:29, :122:23] reg [11:0] r_uop_2_csr_addr; // @[rename-stage.scala:122:23] assign ren2_uops_2_csr_addr = r_uop_2_csr_addr; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_2_rob_idx; // @[rename-stage.scala:122:23] assign ren2_uops_2_rob_idx = r_uop_2_rob_idx; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_2_ldq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_2_ldq_idx = r_uop_2_ldq_idx; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_2_stq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_2_stq_idx = r_uop_2_stq_idx; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_rxq_idx; // @[rename-stage.scala:122:23] assign ren2_uops_2_rxq_idx = r_uop_2_rxq_idx; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_2_pdst; // @[rename-stage.scala:122:23] reg [6:0] r_uop_2_prs1; // @[rename-stage.scala:122:23] assign ren2_uops_2_prs1 = r_uop_2_prs1; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_2_prs2; // @[rename-stage.scala:122:23] assign ren2_uops_2_prs2 = r_uop_2_prs2; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_2_prs3; // @[rename-stage.scala:122:23] assign ren2_uops_2_prs3 = r_uop_2_prs3; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_2_ppred; // @[rename-stage.scala:122:23] assign ren2_uops_2_ppred = r_uop_2_ppred; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_prs1_busy; // @[rename-stage.scala:122:23] reg r_uop_2_prs2_busy; // @[rename-stage.scala:122:23] reg r_uop_2_prs3_busy; // @[rename-stage.scala:122:23] reg r_uop_2_ppred_busy; // @[rename-stage.scala:122:23] assign ren2_uops_2_ppred_busy = r_uop_2_ppred_busy; // @[rename-stage.scala:108:29, :122:23] reg [6:0] r_uop_2_stale_pdst; // @[rename-stage.scala:122:23] assign ren2_uops_2_stale_pdst = r_uop_2_stale_pdst; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_exception; // @[rename-stage.scala:122:23] assign ren2_uops_2_exception = r_uop_2_exception; // @[rename-stage.scala:108:29, :122:23] reg [63:0] r_uop_2_exc_cause; // @[rename-stage.scala:122:23] assign ren2_uops_2_exc_cause = r_uop_2_exc_cause; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_bypassable; // @[rename-stage.scala:122:23] assign ren2_uops_2_bypassable = r_uop_2_bypassable; // @[rename-stage.scala:108:29, :122:23] reg [4:0] r_uop_2_mem_cmd; // @[rename-stage.scala:122:23] assign ren2_uops_2_mem_cmd = r_uop_2_mem_cmd; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_mem_size; // @[rename-stage.scala:122:23] assign ren2_uops_2_mem_size = r_uop_2_mem_size; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_mem_signed; // @[rename-stage.scala:122:23] assign ren2_uops_2_mem_signed = r_uop_2_mem_signed; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_fence; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_fence = r_uop_2_is_fence; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_fencei; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_fencei = r_uop_2_is_fencei; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_amo; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_amo = r_uop_2_is_amo; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_uses_ldq; // @[rename-stage.scala:122:23] assign ren2_uops_2_uses_ldq = r_uop_2_uses_ldq; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_uses_stq; // @[rename-stage.scala:122:23] assign ren2_uops_2_uses_stq = r_uop_2_uses_stq; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_sys_pc2epc; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_sys_pc2epc = r_uop_2_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_is_unique; // @[rename-stage.scala:122:23] assign ren2_uops_2_is_unique = r_uop_2_is_unique; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_flush_on_commit; // @[rename-stage.scala:122:23] assign ren2_uops_2_flush_on_commit = r_uop_2_flush_on_commit; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_ldst_is_rs1; // @[rename-stage.scala:122:23] assign ren2_uops_2_ldst_is_rs1 = r_uop_2_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_2_ldst; // @[rename-stage.scala:122:23] assign ren2_uops_2_ldst = r_uop_2_ldst; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_2_lrs1; // @[rename-stage.scala:122:23] assign ren2_uops_2_lrs1 = r_uop_2_lrs1; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_2_lrs2; // @[rename-stage.scala:122:23] assign ren2_uops_2_lrs2 = r_uop_2_lrs2; // @[rename-stage.scala:108:29, :122:23] reg [5:0] r_uop_2_lrs3; // @[rename-stage.scala:122:23] assign ren2_uops_2_lrs3 = r_uop_2_lrs3; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_ldst_val; // @[rename-stage.scala:122:23] assign ren2_uops_2_ldst_val = r_uop_2_ldst_val; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_dst_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_2_dst_rtype = r_uop_2_dst_rtype; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_lrs1_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_2_lrs1_rtype = r_uop_2_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_lrs2_rtype; // @[rename-stage.scala:122:23] assign ren2_uops_2_lrs2_rtype = r_uop_2_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_frs3_en; // @[rename-stage.scala:122:23] assign ren2_uops_2_frs3_en = r_uop_2_frs3_en; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_fp_val; // @[rename-stage.scala:122:23] assign ren2_uops_2_fp_val = r_uop_2_fp_val; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_fp_single; // @[rename-stage.scala:122:23] assign ren2_uops_2_fp_single = r_uop_2_fp_single; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_xcpt_pf_if; // @[rename-stage.scala:122:23] assign ren2_uops_2_xcpt_pf_if = r_uop_2_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_xcpt_ae_if; // @[rename-stage.scala:122:23] assign ren2_uops_2_xcpt_ae_if = r_uop_2_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_xcpt_ma_if; // @[rename-stage.scala:122:23] assign ren2_uops_2_xcpt_ma_if = r_uop_2_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_bp_debug_if; // @[rename-stage.scala:122:23] assign ren2_uops_2_bp_debug_if = r_uop_2_bp_debug_if; // @[rename-stage.scala:108:29, :122:23] reg r_uop_2_bp_xcpt_if; // @[rename-stage.scala:122:23] assign ren2_uops_2_bp_xcpt_if = r_uop_2_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_debug_fsrc; // @[rename-stage.scala:122:23] assign ren2_uops_2_debug_fsrc = r_uop_2_debug_fsrc; // @[rename-stage.scala:108:29, :122:23] reg [1:0] r_uop_2_debug_tsrc; // @[rename-stage.scala:122:23] assign ren2_uops_2_debug_tsrc = r_uop_2_debug_tsrc; // @[rename-stage.scala:108:29, :122:23] wire [6:0] r_uop_bypassed_uop_2_uopc = next_uop_2_uopc; // @[rename-stage.scala:123:24, :174:28] wire [31:0] r_uop_bypassed_uop_2_inst = next_uop_2_inst; // @[rename-stage.scala:123:24, :174:28] wire [31:0] r_uop_bypassed_uop_2_debug_inst = next_uop_2_debug_inst; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_rvc = next_uop_2_is_rvc; // @[rename-stage.scala:123:24, :174:28] wire [39:0] r_uop_bypassed_uop_2_debug_pc = next_uop_2_debug_pc; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_2_iq_type = next_uop_2_iq_type; // @[rename-stage.scala:123:24, :174:28] wire [9:0] r_uop_bypassed_uop_2_fu_code = next_uop_2_fu_code; // @[rename-stage.scala:123:24, :174:28] wire [3:0] r_uop_bypassed_uop_2_ctrl_br_type = next_uop_2_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_ctrl_op1_sel = next_uop_2_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_2_ctrl_op2_sel = next_uop_2_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_2_ctrl_imm_sel = next_uop_2_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_2_ctrl_op_fcn = next_uop_2_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ctrl_fcn_dw = next_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28] wire [2:0] r_uop_bypassed_uop_2_ctrl_csr_cmd = next_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ctrl_is_load = next_uop_2_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ctrl_is_sta = next_uop_2_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ctrl_is_std = next_uop_2_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_iw_state = next_uop_2_iw_state; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_iw_p1_poisoned = next_uop_2_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_iw_p2_poisoned = next_uop_2_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_br = next_uop_2_is_br; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_jalr = next_uop_2_is_jalr; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_jal = next_uop_2_is_jal; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_sfb = next_uop_2_is_sfb; // @[rename-stage.scala:123:24, :174:28] wire [15:0] r_uop_bypassed_uop_2_br_mask = next_uop_2_br_mask; // @[rename-stage.scala:123:24, :174:28] wire [3:0] r_uop_bypassed_uop_2_br_tag = next_uop_2_br_tag; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_2_ftq_idx = next_uop_2_ftq_idx; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_edge_inst = next_uop_2_edge_inst; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_2_pc_lob = next_uop_2_pc_lob; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_taken = next_uop_2_taken; // @[rename-stage.scala:123:24, :174:28] wire [19:0] r_uop_bypassed_uop_2_imm_packed = next_uop_2_imm_packed; // @[rename-stage.scala:123:24, :174:28] wire [11:0] r_uop_bypassed_uop_2_csr_addr = next_uop_2_csr_addr; // @[rename-stage.scala:123:24, :174:28] wire [6:0] r_uop_bypassed_uop_2_rob_idx = next_uop_2_rob_idx; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_2_ldq_idx = next_uop_2_ldq_idx; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_2_stq_idx = next_uop_2_stq_idx; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_rxq_idx = next_uop_2_rxq_idx; // @[rename-stage.scala:123:24, :174:28] wire [6:0] r_uop_bypassed_uop_2_pdst = next_uop_2_pdst; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_2_ppred = next_uop_2_ppred; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ppred_busy = next_uop_2_ppred_busy; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_exception = next_uop_2_exception; // @[rename-stage.scala:123:24, :174:28] wire [63:0] r_uop_bypassed_uop_2_exc_cause = next_uop_2_exc_cause; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_bypassable = next_uop_2_bypassable; // @[rename-stage.scala:123:24, :174:28] wire [4:0] r_uop_bypassed_uop_2_mem_cmd = next_uop_2_mem_cmd; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_mem_size = next_uop_2_mem_size; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_mem_signed = next_uop_2_mem_signed; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_fence = next_uop_2_is_fence; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_fencei = next_uop_2_is_fencei; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_amo = next_uop_2_is_amo; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_uses_ldq = next_uop_2_uses_ldq; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_uses_stq = next_uop_2_uses_stq; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_sys_pc2epc = next_uop_2_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_is_unique = next_uop_2_is_unique; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_flush_on_commit = next_uop_2_flush_on_commit; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ldst_is_rs1 = next_uop_2_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_2_ldst = next_uop_2_ldst; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_2_lrs1 = next_uop_2_lrs1; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_2_lrs2 = next_uop_2_lrs2; // @[rename-stage.scala:123:24, :174:28] wire [5:0] r_uop_bypassed_uop_2_lrs3 = next_uop_2_lrs3; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_ldst_val = next_uop_2_ldst_val; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_dst_rtype = next_uop_2_dst_rtype; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_lrs1_rtype = next_uop_2_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_lrs2_rtype = next_uop_2_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_frs3_en = next_uop_2_frs3_en; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_fp_val = next_uop_2_fp_val; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_fp_single = next_uop_2_fp_single; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_xcpt_pf_if = next_uop_2_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_xcpt_ae_if = next_uop_2_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_xcpt_ma_if = next_uop_2_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_bp_debug_if = next_uop_2_bp_debug_if; // @[rename-stage.scala:123:24, :174:28] wire r_uop_bypassed_uop_2_bp_xcpt_if = next_uop_2_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_debug_fsrc = next_uop_2_debug_fsrc; // @[rename-stage.scala:123:24, :174:28] wire [1:0] r_uop_bypassed_uop_2_debug_tsrc = next_uop_2_debug_tsrc; // @[rename-stage.scala:123:24, :174:28] wire [6:0] next_uop_2_prs1; // @[rename-stage.scala:123:24] wire [6:0] next_uop_2_prs2; // @[rename-stage.scala:123:24] wire [6:0] next_uop_2_prs3; // @[rename-stage.scala:123:24] wire next_uop_2_prs1_busy; // @[rename-stage.scala:123:24] wire next_uop_2_prs2_busy; // @[rename-stage.scala:123:24] wire next_uop_2_prs3_busy; // @[rename-stage.scala:123:24] wire [6:0] next_uop_2_stale_pdst; // @[rename-stage.scala:123:24] wire _r_valid_T_4 = ~io_dis_fire_2_0; // @[rename-stage.scala:133:29, :160:7] wire _r_valid_T_5 = r_valid_2 & _r_valid_T_4; // @[rename-stage.scala:121:27, :133:{26,29}] assign next_uop_2_uopc = _GEN ? r_uop_2_uopc : ren1_uops_2_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_inst = _GEN ? r_uop_2_inst : ren1_uops_2_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_debug_inst = _GEN ? r_uop_2_debug_inst : ren1_uops_2_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_rvc = _GEN ? r_uop_2_is_rvc : ren1_uops_2_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_debug_pc = _GEN ? r_uop_2_debug_pc : ren1_uops_2_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_iq_type = _GEN ? r_uop_2_iq_type : ren1_uops_2_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_fu_code = _GEN ? r_uop_2_fu_code : ren1_uops_2_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_br_type = _GEN ? r_uop_2_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_op1_sel = _GEN ? r_uop_2_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_op2_sel = _GEN ? r_uop_2_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_imm_sel = _GEN ? r_uop_2_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_op_fcn = _GEN ? r_uop_2_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_fcn_dw = _GEN & r_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_csr_cmd = _GEN ? r_uop_2_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_is_load = _GEN & r_uop_2_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_is_sta = _GEN & r_uop_2_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ctrl_is_std = _GEN & r_uop_2_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_iw_state = _GEN ? r_uop_2_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_iw_p1_poisoned = _GEN & r_uop_2_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_iw_p2_poisoned = _GEN & r_uop_2_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_br = _GEN ? r_uop_2_is_br : ren1_uops_2_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_jalr = _GEN ? r_uop_2_is_jalr : ren1_uops_2_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_jal = _GEN ? r_uop_2_is_jal : ren1_uops_2_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_sfb = _GEN ? r_uop_2_is_sfb : ren1_uops_2_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_br_mask = _GEN ? r_uop_2_br_mask : ren1_uops_2_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_br_tag = _GEN ? r_uop_2_br_tag : ren1_uops_2_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ftq_idx = _GEN ? r_uop_2_ftq_idx : ren1_uops_2_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_edge_inst = _GEN ? r_uop_2_edge_inst : ren1_uops_2_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_pc_lob = _GEN ? r_uop_2_pc_lob : ren1_uops_2_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_taken = _GEN ? r_uop_2_taken : ren1_uops_2_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_imm_packed = _GEN ? r_uop_2_imm_packed : ren1_uops_2_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_csr_addr = _GEN ? r_uop_2_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_rob_idx = _GEN ? r_uop_2_rob_idx : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ldq_idx = _GEN ? r_uop_2_ldq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_stq_idx = _GEN ? r_uop_2_stq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_rxq_idx = _GEN ? r_uop_2_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_pdst = _GEN ? r_uop_2_pdst : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_prs1 = _GEN ? r_uop_2_prs1 : ren1_uops_2_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_prs2 = _GEN ? r_uop_2_prs2 : ren1_uops_2_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_prs3 = _GEN ? r_uop_2_prs3 : ren1_uops_2_prs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ppred = _GEN ? r_uop_2_ppred : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_prs1_busy = _GEN & r_uop_2_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_prs2_busy = _GEN & r_uop_2_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_prs3_busy = _GEN & r_uop_2_prs3_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ppred_busy = _GEN & r_uop_2_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_stale_pdst = _GEN ? r_uop_2_stale_pdst : ren1_uops_2_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_exception = _GEN ? r_uop_2_exception : ren1_uops_2_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_exc_cause = _GEN ? r_uop_2_exc_cause : ren1_uops_2_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_bypassable = _GEN ? r_uop_2_bypassable : ren1_uops_2_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_mem_cmd = _GEN ? r_uop_2_mem_cmd : ren1_uops_2_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_mem_size = _GEN ? r_uop_2_mem_size : ren1_uops_2_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_mem_signed = _GEN ? r_uop_2_mem_signed : ren1_uops_2_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_fence = _GEN ? r_uop_2_is_fence : ren1_uops_2_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_fencei = _GEN ? r_uop_2_is_fencei : ren1_uops_2_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_amo = _GEN ? r_uop_2_is_amo : ren1_uops_2_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_uses_ldq = _GEN ? r_uop_2_uses_ldq : ren1_uops_2_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_uses_stq = _GEN ? r_uop_2_uses_stq : ren1_uops_2_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_sys_pc2epc = _GEN ? r_uop_2_is_sys_pc2epc : ren1_uops_2_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_is_unique = _GEN ? r_uop_2_is_unique : ren1_uops_2_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_flush_on_commit = _GEN ? r_uop_2_flush_on_commit : ren1_uops_2_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ldst_is_rs1 = _GEN & r_uop_2_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ldst = _GEN ? r_uop_2_ldst : ren1_uops_2_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_lrs1 = _GEN ? r_uop_2_lrs1 : ren1_uops_2_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_lrs2 = _GEN ? r_uop_2_lrs2 : ren1_uops_2_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_lrs3 = _GEN ? r_uop_2_lrs3 : ren1_uops_2_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_ldst_val = _GEN ? r_uop_2_ldst_val : ren1_uops_2_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_dst_rtype = _GEN ? r_uop_2_dst_rtype : ren1_uops_2_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_lrs1_rtype = _GEN ? r_uop_2_lrs1_rtype : ren1_uops_2_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_lrs2_rtype = _GEN ? r_uop_2_lrs2_rtype : ren1_uops_2_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_frs3_en = _GEN ? r_uop_2_frs3_en : ren1_uops_2_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_fp_val = _GEN ? r_uop_2_fp_val : ren1_uops_2_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_fp_single = _GEN ? r_uop_2_fp_single : ren1_uops_2_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_xcpt_pf_if = _GEN ? r_uop_2_xcpt_pf_if : ren1_uops_2_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_xcpt_ae_if = _GEN ? r_uop_2_xcpt_ae_if : ren1_uops_2_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_xcpt_ma_if = _GEN & r_uop_2_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_bp_debug_if = _GEN ? r_uop_2_bp_debug_if : ren1_uops_2_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_bp_xcpt_if = _GEN ? r_uop_2_bp_xcpt_if : ren1_uops_2_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_debug_fsrc = _GEN ? r_uop_2_debug_fsrc : ren1_uops_2_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30] assign next_uop_2_debug_tsrc = _GEN ? r_uop_2_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30] wire [6:0] r_uop_newuop_2_uopc = r_uop_bypassed_uop_2_uopc; // @[util.scala:73:26] wire [31:0] r_uop_newuop_2_inst = r_uop_bypassed_uop_2_inst; // @[util.scala:73:26] wire [31:0] r_uop_newuop_2_debug_inst = r_uop_bypassed_uop_2_debug_inst; // @[util.scala:73:26] wire r_uop_newuop_2_is_rvc = r_uop_bypassed_uop_2_is_rvc; // @[util.scala:73:26] wire [39:0] r_uop_newuop_2_debug_pc = r_uop_bypassed_uop_2_debug_pc; // @[util.scala:73:26] wire [2:0] r_uop_newuop_2_iq_type = r_uop_bypassed_uop_2_iq_type; // @[util.scala:73:26] wire [9:0] r_uop_newuop_2_fu_code = r_uop_bypassed_uop_2_fu_code; // @[util.scala:73:26] wire [3:0] r_uop_newuop_2_ctrl_br_type = r_uop_bypassed_uop_2_ctrl_br_type; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_ctrl_op1_sel = r_uop_bypassed_uop_2_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] r_uop_newuop_2_ctrl_op2_sel = r_uop_bypassed_uop_2_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] r_uop_newuop_2_ctrl_imm_sel = r_uop_bypassed_uop_2_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] r_uop_newuop_2_ctrl_op_fcn = r_uop_bypassed_uop_2_ctrl_op_fcn; // @[util.scala:73:26] wire r_uop_newuop_2_ctrl_fcn_dw = r_uop_bypassed_uop_2_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] r_uop_newuop_2_ctrl_csr_cmd = r_uop_bypassed_uop_2_ctrl_csr_cmd; // @[util.scala:73:26] wire r_uop_newuop_2_ctrl_is_load = r_uop_bypassed_uop_2_ctrl_is_load; // @[util.scala:73:26] wire r_uop_newuop_2_ctrl_is_sta = r_uop_bypassed_uop_2_ctrl_is_sta; // @[util.scala:73:26] wire r_uop_newuop_2_ctrl_is_std = r_uop_bypassed_uop_2_ctrl_is_std; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_iw_state = r_uop_bypassed_uop_2_iw_state; // @[util.scala:73:26] wire r_uop_newuop_2_iw_p1_poisoned = r_uop_bypassed_uop_2_iw_p1_poisoned; // @[util.scala:73:26] wire r_uop_newuop_2_iw_p2_poisoned = r_uop_bypassed_uop_2_iw_p2_poisoned; // @[util.scala:73:26] wire r_uop_newuop_2_is_br = r_uop_bypassed_uop_2_is_br; // @[util.scala:73:26] wire r_uop_newuop_2_is_jalr = r_uop_bypassed_uop_2_is_jalr; // @[util.scala:73:26] wire r_uop_newuop_2_is_jal = r_uop_bypassed_uop_2_is_jal; // @[util.scala:73:26] wire r_uop_newuop_2_is_sfb = r_uop_bypassed_uop_2_is_sfb; // @[util.scala:73:26] wire [3:0] r_uop_newuop_2_br_tag = r_uop_bypassed_uop_2_br_tag; // @[util.scala:73:26] wire [4:0] r_uop_newuop_2_ftq_idx = r_uop_bypassed_uop_2_ftq_idx; // @[util.scala:73:26] wire r_uop_newuop_2_edge_inst = r_uop_bypassed_uop_2_edge_inst; // @[util.scala:73:26] wire [5:0] r_uop_newuop_2_pc_lob = r_uop_bypassed_uop_2_pc_lob; // @[util.scala:73:26] wire r_uop_newuop_2_taken = r_uop_bypassed_uop_2_taken; // @[util.scala:73:26] wire [19:0] r_uop_newuop_2_imm_packed = r_uop_bypassed_uop_2_imm_packed; // @[util.scala:73:26] wire [11:0] r_uop_newuop_2_csr_addr = r_uop_bypassed_uop_2_csr_addr; // @[util.scala:73:26] wire [6:0] r_uop_newuop_2_rob_idx = r_uop_bypassed_uop_2_rob_idx; // @[util.scala:73:26] wire [4:0] r_uop_newuop_2_ldq_idx = r_uop_bypassed_uop_2_ldq_idx; // @[util.scala:73:26] wire [4:0] r_uop_newuop_2_stq_idx = r_uop_bypassed_uop_2_stq_idx; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_rxq_idx = r_uop_bypassed_uop_2_rxq_idx; // @[util.scala:73:26] wire [6:0] r_uop_newuop_2_pdst = r_uop_bypassed_uop_2_pdst; // @[util.scala:73:26] wire [6:0] r_uop_newuop_2_prs1 = r_uop_bypassed_uop_2_prs1; // @[util.scala:73:26] wire [6:0] r_uop_newuop_2_prs2 = r_uop_bypassed_uop_2_prs2; // @[util.scala:73:26] wire [6:0] r_uop_newuop_2_prs3 = r_uop_bypassed_uop_2_prs3; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs1_busy_T_2; // @[rename-stage.scala:199:45] wire [4:0] r_uop_newuop_2_ppred = r_uop_bypassed_uop_2_ppred; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs2_busy_T_2; // @[rename-stage.scala:200:45] wire r_uop_newuop_2_prs1_busy = r_uop_bypassed_uop_2_prs1_busy; // @[util.scala:73:26] wire _r_uop_bypassed_uop_prs3_busy_T_2; // @[rename-stage.scala:201:45] wire r_uop_newuop_2_prs2_busy = r_uop_bypassed_uop_2_prs2_busy; // @[util.scala:73:26] wire r_uop_newuop_2_prs3_busy = r_uop_bypassed_uop_2_prs3_busy; // @[util.scala:73:26] wire r_uop_newuop_2_ppred_busy = r_uop_bypassed_uop_2_ppred_busy; // @[util.scala:73:26] wire [6:0] r_uop_newuop_2_stale_pdst = r_uop_bypassed_uop_2_stale_pdst; // @[util.scala:73:26] wire r_uop_newuop_2_exception = r_uop_bypassed_uop_2_exception; // @[util.scala:73:26] wire [63:0] r_uop_newuop_2_exc_cause = r_uop_bypassed_uop_2_exc_cause; // @[util.scala:73:26] wire r_uop_newuop_2_bypassable = r_uop_bypassed_uop_2_bypassable; // @[util.scala:73:26] wire [4:0] r_uop_newuop_2_mem_cmd = r_uop_bypassed_uop_2_mem_cmd; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_mem_size = r_uop_bypassed_uop_2_mem_size; // @[util.scala:73:26] wire r_uop_newuop_2_mem_signed = r_uop_bypassed_uop_2_mem_signed; // @[util.scala:73:26] wire r_uop_newuop_2_is_fence = r_uop_bypassed_uop_2_is_fence; // @[util.scala:73:26] wire r_uop_newuop_2_is_fencei = r_uop_bypassed_uop_2_is_fencei; // @[util.scala:73:26] wire r_uop_newuop_2_is_amo = r_uop_bypassed_uop_2_is_amo; // @[util.scala:73:26] wire r_uop_newuop_2_uses_ldq = r_uop_bypassed_uop_2_uses_ldq; // @[util.scala:73:26] wire r_uop_newuop_2_uses_stq = r_uop_bypassed_uop_2_uses_stq; // @[util.scala:73:26] wire r_uop_newuop_2_is_sys_pc2epc = r_uop_bypassed_uop_2_is_sys_pc2epc; // @[util.scala:73:26] wire r_uop_newuop_2_is_unique = r_uop_bypassed_uop_2_is_unique; // @[util.scala:73:26] wire r_uop_newuop_2_flush_on_commit = r_uop_bypassed_uop_2_flush_on_commit; // @[util.scala:73:26] wire r_uop_newuop_2_ldst_is_rs1 = r_uop_bypassed_uop_2_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] r_uop_newuop_2_ldst = r_uop_bypassed_uop_2_ldst; // @[util.scala:73:26] wire [5:0] r_uop_newuop_2_lrs1 = r_uop_bypassed_uop_2_lrs1; // @[util.scala:73:26] wire [5:0] r_uop_newuop_2_lrs2 = r_uop_bypassed_uop_2_lrs2; // @[util.scala:73:26] wire [5:0] r_uop_newuop_2_lrs3 = r_uop_bypassed_uop_2_lrs3; // @[util.scala:73:26] wire r_uop_newuop_2_ldst_val = r_uop_bypassed_uop_2_ldst_val; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_dst_rtype = r_uop_bypassed_uop_2_dst_rtype; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_lrs1_rtype = r_uop_bypassed_uop_2_lrs1_rtype; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_lrs2_rtype = r_uop_bypassed_uop_2_lrs2_rtype; // @[util.scala:73:26] wire r_uop_newuop_2_frs3_en = r_uop_bypassed_uop_2_frs3_en; // @[util.scala:73:26] wire r_uop_newuop_2_fp_val = r_uop_bypassed_uop_2_fp_val; // @[util.scala:73:26] wire r_uop_newuop_2_fp_single = r_uop_bypassed_uop_2_fp_single; // @[util.scala:73:26] wire r_uop_newuop_2_xcpt_pf_if = r_uop_bypassed_uop_2_xcpt_pf_if; // @[util.scala:73:26] wire r_uop_newuop_2_xcpt_ae_if = r_uop_bypassed_uop_2_xcpt_ae_if; // @[util.scala:73:26] wire r_uop_newuop_2_xcpt_ma_if = r_uop_bypassed_uop_2_xcpt_ma_if; // @[util.scala:73:26] wire r_uop_newuop_2_bp_debug_if = r_uop_bypassed_uop_2_bp_debug_if; // @[util.scala:73:26] wire r_uop_newuop_2_bp_xcpt_if = r_uop_bypassed_uop_2_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_debug_fsrc = r_uop_bypassed_uop_2_debug_fsrc; // @[util.scala:73:26] wire [1:0] r_uop_newuop_2_debug_tsrc = r_uop_bypassed_uop_2_debug_tsrc; // @[util.scala:73:26] wire _r_uop_bypass_hits_rs1_T_6 = ren2_uops_0_ldst == next_uop_2_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T_6; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs1_T_7 = ren2_uops_1_ldst == next_uop_2_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs1_T_7; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs1_T_8 = ren2_uops_2_ldst == next_uop_2_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87] wire r_uop_bypass_hits_rs1_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs1_T_8; // @[rename-stage.scala:109:29, :177:{77,87}] wire _r_uop_bypass_hits_rs2_T_6 = ren2_uops_0_ldst == next_uop_2_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T_6; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs2_T_7 = ren2_uops_1_ldst == next_uop_2_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs2_T_7; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs2_T_8 = ren2_uops_2_ldst == next_uop_2_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87] wire r_uop_bypass_hits_rs2_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs2_T_8; // @[rename-stage.scala:109:29, :178:{77,87}] wire _r_uop_bypass_hits_rs3_T_6 = ren2_uops_0_ldst == next_uop_2_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T_6; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_rs3_T_7 = ren2_uops_1_ldst == next_uop_2_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs3_T_7; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_rs3_T_8 = ren2_uops_2_ldst == next_uop_2_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87] wire r_uop_bypass_hits_rs3_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs3_T_8; // @[rename-stage.scala:109:29, :179:{77,87}] wire _r_uop_bypass_hits_dst_T_6 = ren2_uops_0_ldst == next_uop_2_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T_6; // @[rename-stage.scala:109:29, :180:{77,87}] wire _r_uop_bypass_hits_dst_T_7 = ren2_uops_1_ldst == next_uop_2_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_dst_T_7; // @[rename-stage.scala:109:29, :180:{77,87}] wire _r_uop_bypass_hits_dst_T_8 = ren2_uops_2_ldst == next_uop_2_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87] wire r_uop_bypass_hits_dst_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_dst_T_8; // @[rename-stage.scala:109:29, :180:{77,87}] wire [2:0] _r_uop_bypass_sel_rs1_enc_T_4 = {r_uop_bypass_hits_rs1_0_2, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs1_enc_T_5 = r_uop_bypass_hits_rs1_1_2 ? 3'h2 : _r_uop_bypass_sel_rs1_enc_T_4; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs1_enc_2 = r_uop_bypass_hits_rs1_2_2 ? 3'h1 : _r_uop_bypass_sel_rs1_enc_T_5; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs1_2_2 = r_uop_bypass_sel_rs1_enc_2[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs1_1_2 = r_uop_bypass_sel_rs1_enc_2[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs1_0_2 = r_uop_bypass_sel_rs1_enc_2[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_rs2_enc_T_4 = {r_uop_bypass_hits_rs2_0_2, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs2_enc_T_5 = r_uop_bypass_hits_rs2_1_2 ? 3'h2 : _r_uop_bypass_sel_rs2_enc_T_4; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs2_enc_2 = r_uop_bypass_hits_rs2_2_2 ? 3'h1 : _r_uop_bypass_sel_rs2_enc_T_5; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs2_2_2 = r_uop_bypass_sel_rs2_enc_2[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs2_1_2 = r_uop_bypass_sel_rs2_enc_2[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs2_0_2 = r_uop_bypass_sel_rs2_enc_2[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_rs3_enc_T_4 = {r_uop_bypass_hits_rs3_0_2, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_rs3_enc_T_5 = r_uop_bypass_hits_rs3_1_2 ? 3'h2 : _r_uop_bypass_sel_rs3_enc_T_4; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_rs3_enc_2 = r_uop_bypass_hits_rs3_2_2 ? 3'h1 : _r_uop_bypass_sel_rs3_enc_T_5; // @[Mux.scala:50:70] wire r_uop_bypass_sel_rs3_2_2 = r_uop_bypass_sel_rs3_enc_2[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs3_1_2 = r_uop_bypass_sel_rs3_enc_2[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_rs3_0_2 = r_uop_bypass_sel_rs3_enc_2[2]; // @[OneHot.scala:83:30] wire [2:0] _r_uop_bypass_sel_dst_enc_T_4 = {r_uop_bypass_hits_dst_0_2, 2'h0}; // @[Mux.scala:50:70] wire [2:0] _r_uop_bypass_sel_dst_enc_T_5 = r_uop_bypass_hits_dst_1_2 ? 3'h2 : _r_uop_bypass_sel_dst_enc_T_4; // @[Mux.scala:50:70] wire [2:0] r_uop_bypass_sel_dst_enc_2 = r_uop_bypass_hits_dst_2_2 ? 3'h1 : _r_uop_bypass_sel_dst_enc_T_5; // @[Mux.scala:50:70] wire r_uop_bypass_sel_dst_2_2 = r_uop_bypass_sel_dst_enc_2[0]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_dst_1_2 = r_uop_bypass_sel_dst_enc_2[1]; // @[OneHot.scala:83:30] wire r_uop_bypass_sel_dst_0_2 = r_uop_bypass_sel_dst_enc_2[2]; // @[OneHot.scala:83:30] wire _r_uop_do_bypass_rs1_T_2 = r_uop_bypass_hits_rs1_0_2 | r_uop_bypass_hits_rs1_1_2; // @[rename-stage.scala:177:77, :187:49] wire r_uop_do_bypass_rs1_2 = _r_uop_do_bypass_rs1_T_2 | r_uop_bypass_hits_rs1_2_2; // @[rename-stage.scala:177:77, :187:49] wire _r_uop_do_bypass_rs2_T_2 = r_uop_bypass_hits_rs2_0_2 | r_uop_bypass_hits_rs2_1_2; // @[rename-stage.scala:178:77, :188:49] wire r_uop_do_bypass_rs2_2 = _r_uop_do_bypass_rs2_T_2 | r_uop_bypass_hits_rs2_2_2; // @[rename-stage.scala:178:77, :188:49] wire _r_uop_do_bypass_rs3_T_2 = r_uop_bypass_hits_rs3_0_2 | r_uop_bypass_hits_rs3_1_2; // @[rename-stage.scala:179:77, :189:49] wire r_uop_do_bypass_rs3_2 = _r_uop_do_bypass_rs3_T_2 | r_uop_bypass_hits_rs3_2_2; // @[rename-stage.scala:179:77, :189:49] wire _r_uop_do_bypass_dst_T_2 = r_uop_bypass_hits_dst_0_2 | r_uop_bypass_hits_dst_1_2; // @[rename-stage.scala:180:77, :190:49] wire r_uop_do_bypass_dst_2 = _r_uop_do_bypass_dst_T_2 | r_uop_bypass_hits_dst_2_2; // @[rename-stage.scala:180:77, :190:49] wire [6:0] _r_uop_bypassed_uop_prs1_T_10 = r_uop_bypass_sel_rs1_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_11 = r_uop_bypass_sel_rs1_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_12 = r_uop_bypass_sel_rs1_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs1_T_13 = _r_uop_bypassed_uop_prs1_T_10 | _r_uop_bypassed_uop_prs1_T_11; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs1_T_14 = _r_uop_bypassed_uop_prs1_T_13 | _r_uop_bypassed_uop_prs1_T_12; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs1_WIRE_2 = _r_uop_bypassed_uop_prs1_T_14; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_2_prs1 = r_uop_do_bypass_rs1_2 ? _r_uop_bypassed_uop_prs1_WIRE_2 : next_uop_2_prs1; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_T_10 = r_uop_bypass_sel_rs2_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_11 = r_uop_bypass_sel_rs2_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_12 = r_uop_bypass_sel_rs2_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs2_T_13 = _r_uop_bypassed_uop_prs2_T_10 | _r_uop_bypassed_uop_prs2_T_11; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_T_14 = _r_uop_bypassed_uop_prs2_T_13 | _r_uop_bypassed_uop_prs2_T_12; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs2_WIRE_2 = _r_uop_bypassed_uop_prs2_T_14; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_2_prs2 = r_uop_do_bypass_rs2_2 ? _r_uop_bypassed_uop_prs2_WIRE_2 : next_uop_2_prs2; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_T_10 = r_uop_bypass_sel_rs3_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_11 = r_uop_bypass_sel_rs3_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_12 = r_uop_bypass_sel_rs3_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_prs3_T_13 = _r_uop_bypassed_uop_prs3_T_10 | _r_uop_bypassed_uop_prs3_T_11; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_T_14 = _r_uop_bypassed_uop_prs3_T_13 | _r_uop_bypassed_uop_prs3_T_12; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_prs3_WIRE_2 = _r_uop_bypassed_uop_prs3_T_14; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_2_prs3 = r_uop_do_bypass_rs3_2 ? _r_uop_bypassed_uop_prs3_WIRE_2 : next_uop_2_prs3; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_10 = r_uop_bypass_sel_dst_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_11 = r_uop_bypass_sel_dst_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_12 = r_uop_bypass_sel_dst_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_13 = _r_uop_bypassed_uop_stale_pdst_T_10 | _r_uop_bypassed_uop_stale_pdst_T_11; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_14 = _r_uop_bypassed_uop_stale_pdst_T_13 | _r_uop_bypassed_uop_stale_pdst_T_12; // @[Mux.scala:30:73] wire [6:0] _r_uop_bypassed_uop_stale_pdst_WIRE_2 = _r_uop_bypassed_uop_stale_pdst_T_14; // @[Mux.scala:30:73] assign r_uop_bypassed_uop_2_stale_pdst = r_uop_do_bypass_dst_2 ? _r_uop_bypassed_uop_stale_pdst_WIRE_2 : next_uop_2_stale_pdst; // @[Mux.scala:30:73] assign _r_uop_bypassed_uop_prs1_busy_T_2 = next_uop_2_prs1_busy | r_uop_do_bypass_rs1_2; // @[rename-stage.scala:123:24, :187:49, :199:45] assign r_uop_bypassed_uop_2_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T_2; // @[rename-stage.scala:174:28, :199:45] assign _r_uop_bypassed_uop_prs2_busy_T_2 = next_uop_2_prs2_busy | r_uop_do_bypass_rs2_2; // @[rename-stage.scala:123:24, :188:49, :200:45] assign r_uop_bypassed_uop_2_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T_2; // @[rename-stage.scala:174:28, :200:45] assign _r_uop_bypassed_uop_prs3_busy_T_2 = next_uop_2_prs3_busy | r_uop_do_bypass_rs3_2; // @[rename-stage.scala:123:24, :189:49, :201:45] assign r_uop_bypassed_uop_2_prs3_busy = _r_uop_bypassed_uop_prs3_busy_T_2; // @[rename-stage.scala:174:28, :201:45] wire [15:0] _r_uop_newuop_br_mask_T_5; // @[util.scala:74:35] wire [15:0] r_uop_newuop_2_br_mask; // @[util.scala:73:26] wire [15:0] _r_uop_newuop_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37] assign _r_uop_newuop_br_mask_T_5 = r_uop_bypassed_uop_2_br_mask & _r_uop_newuop_br_mask_T_4; // @[util.scala:74:{35,37}] assign r_uop_newuop_2_br_mask = _r_uop_newuop_br_mask_T_5; // @[util.scala:73:26, :74:35] wire _ren2_br_tags_0_valid_T_3; // @[rename-stage.scala:241:43] wire _ren2_br_tags_1_valid_T_3; // @[rename-stage.scala:241:43] wire _ren2_br_tags_2_valid_T_3; // @[rename-stage.scala:241:43] wire ren2_br_tags_0_valid; // @[rename-stage.scala:233:29] wire ren2_br_tags_1_valid; // @[rename-stage.scala:233:29] wire ren2_br_tags_2_valid; // @[rename-stage.scala:233:29] wire _com_valids_0_T_2; // @[rename-stage.scala:243:92] wire _com_valids_1_T_2; // @[rename-stage.scala:243:92] wire _com_valids_2_T_2; // @[rename-stage.scala:243:92] wire com_valids_0; // @[rename-stage.scala:236:29] wire com_valids_1; // @[rename-stage.scala:236:29] wire com_valids_2; // @[rename-stage.scala:236:29] wire _rbk_valids_0_T_2; // @[rename-stage.scala:244:92] wire _rbk_valids_1_T_2; // @[rename-stage.scala:244:92] wire _rbk_valids_2_T_2; // @[rename-stage.scala:244:92] wire rbk_valids_0; // @[rename-stage.scala:237:29] wire rbk_valids_1; // @[rename-stage.scala:237:29] wire rbk_valids_2; // @[rename-stage.scala:237:29] wire _GEN_0 = ren2_uops_0_dst_rtype == 2'h1; // @[rename-stage.scala:108:29, :240:78] wire _ren2_alloc_reqs_0_T; // @[rename-stage.scala:240:78] assign _ren2_alloc_reqs_0_T = _GEN_0; // @[rename-stage.scala:240:78] wire _io_ren_stalls_0_T; // @[rename-stage.scala:339:49] assign _io_ren_stalls_0_T = _GEN_0; // @[rename-stage.scala:240:78, :339:49] wire _ren2_alloc_reqs_0_T_1 = ren2_uops_0_ldst_val & _ren2_alloc_reqs_0_T; // @[rename-stage.scala:108:29, :240:{52,78}] assign _ren2_alloc_reqs_0_T_2 = _ren2_alloc_reqs_0_T_1 & io_dis_fire_0_0; // @[rename-stage.scala:160:7, :240:{52,88}] assign ren2_alloc_reqs_0 = _ren2_alloc_reqs_0_T_2; // @[rename-stage.scala:109:29, :240:88] wire _ren2_br_tags_0_valid_T = ~ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29] wire _ren2_br_tags_0_valid_T_1 = ren2_uops_0_is_br & _ren2_br_tags_0_valid_T; // @[rename-stage.scala:108:29] wire _ren2_br_tags_0_valid_T_2 = _ren2_br_tags_0_valid_T_1 | ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29] assign _ren2_br_tags_0_valid_T_3 = io_dis_fire_0_0 & _ren2_br_tags_0_valid_T_2; // @[rename-stage.scala:160:7, :241:43] assign ren2_br_tags_0_valid = _ren2_br_tags_0_valid_T_3; // @[rename-stage.scala:233:29, :241:43] wire _GEN_1 = io_com_uops_0_dst_rtype_0 == 2'h1; // @[rename-stage.scala:160:7, :243:82] wire _com_valids_0_T; // @[rename-stage.scala:243:82] assign _com_valids_0_T = _GEN_1; // @[rename-stage.scala:243:82] wire _rbk_valids_0_T; // @[rename-stage.scala:244:82] assign _rbk_valids_0_T = _GEN_1; // @[rename-stage.scala:243:82, :244:82] wire _com_valids_0_T_1 = io_com_uops_0_ldst_val_0 & _com_valids_0_T; // @[rename-stage.scala:160:7, :243:{54,82}] assign _com_valids_0_T_2 = _com_valids_0_T_1 & io_com_valids_0_0; // @[rename-stage.scala:160:7, :243:{54,92}] assign com_valids_0 = _com_valids_0_T_2; // @[rename-stage.scala:236:29, :243:92] wire _rbk_valids_0_T_1 = io_com_uops_0_ldst_val_0 & _rbk_valids_0_T; // @[rename-stage.scala:160:7, :244:{54,82}] assign _rbk_valids_0_T_2 = _rbk_valids_0_T_1 & io_rbk_valids_0_0; // @[rename-stage.scala:160:7, :244:{54,92}] assign rbk_valids_0 = _rbk_valids_0_T_2; // @[rename-stage.scala:237:29, :244:92] wire _GEN_2 = ren2_uops_1_dst_rtype == 2'h1; // @[rename-stage.scala:108:29, :240:78] wire _ren2_alloc_reqs_1_T; // @[rename-stage.scala:240:78] assign _ren2_alloc_reqs_1_T = _GEN_2; // @[rename-stage.scala:240:78] wire _io_ren_stalls_1_T; // @[rename-stage.scala:339:49] assign _io_ren_stalls_1_T = _GEN_2; // @[rename-stage.scala:240:78, :339:49] wire _ren2_alloc_reqs_1_T_1 = ren2_uops_1_ldst_val & _ren2_alloc_reqs_1_T; // @[rename-stage.scala:108:29, :240:{52,78}] assign _ren2_alloc_reqs_1_T_2 = _ren2_alloc_reqs_1_T_1 & io_dis_fire_1_0; // @[rename-stage.scala:160:7, :240:{52,88}] assign ren2_alloc_reqs_1 = _ren2_alloc_reqs_1_T_2; // @[rename-stage.scala:109:29, :240:88] wire _ren2_br_tags_1_valid_T = ~ren2_uops_1_is_sfb; // @[rename-stage.scala:108:29] wire _ren2_br_tags_1_valid_T_1 = ren2_uops_1_is_br & _ren2_br_tags_1_valid_T; // @[rename-stage.scala:108:29] wire _ren2_br_tags_1_valid_T_2 = _ren2_br_tags_1_valid_T_1 | ren2_uops_1_is_jalr; // @[rename-stage.scala:108:29] assign _ren2_br_tags_1_valid_T_3 = io_dis_fire_1_0 & _ren2_br_tags_1_valid_T_2; // @[rename-stage.scala:160:7, :241:43] assign ren2_br_tags_1_valid = _ren2_br_tags_1_valid_T_3; // @[rename-stage.scala:233:29, :241:43] wire _GEN_3 = io_com_uops_1_dst_rtype_0 == 2'h1; // @[rename-stage.scala:160:7, :243:82] wire _com_valids_1_T; // @[rename-stage.scala:243:82] assign _com_valids_1_T = _GEN_3; // @[rename-stage.scala:243:82] wire _rbk_valids_1_T; // @[rename-stage.scala:244:82] assign _rbk_valids_1_T = _GEN_3; // @[rename-stage.scala:243:82, :244:82] wire _com_valids_1_T_1 = io_com_uops_1_ldst_val_0 & _com_valids_1_T; // @[rename-stage.scala:160:7, :243:{54,82}] assign _com_valids_1_T_2 = _com_valids_1_T_1 & io_com_valids_1_0; // @[rename-stage.scala:160:7, :243:{54,92}] assign com_valids_1 = _com_valids_1_T_2; // @[rename-stage.scala:236:29, :243:92] wire _rbk_valids_1_T_1 = io_com_uops_1_ldst_val_0 & _rbk_valids_1_T; // @[rename-stage.scala:160:7, :244:{54,82}] assign _rbk_valids_1_T_2 = _rbk_valids_1_T_1 & io_rbk_valids_1_0; // @[rename-stage.scala:160:7, :244:{54,92}] assign rbk_valids_1 = _rbk_valids_1_T_2; // @[rename-stage.scala:237:29, :244:92] wire _GEN_4 = ren2_uops_2_dst_rtype == 2'h1; // @[rename-stage.scala:108:29, :240:78] wire _ren2_alloc_reqs_2_T; // @[rename-stage.scala:240:78] assign _ren2_alloc_reqs_2_T = _GEN_4; // @[rename-stage.scala:240:78] wire _io_ren_stalls_2_T; // @[rename-stage.scala:339:49] assign _io_ren_stalls_2_T = _GEN_4; // @[rename-stage.scala:240:78, :339:49] wire _ren2_alloc_reqs_2_T_1 = ren2_uops_2_ldst_val & _ren2_alloc_reqs_2_T; // @[rename-stage.scala:108:29, :240:{52,78}] assign _ren2_alloc_reqs_2_T_2 = _ren2_alloc_reqs_2_T_1 & io_dis_fire_2_0; // @[rename-stage.scala:160:7, :240:{52,88}] assign ren2_alloc_reqs_2 = _ren2_alloc_reqs_2_T_2; // @[rename-stage.scala:109:29, :240:88] wire _ren2_br_tags_2_valid_T = ~ren2_uops_2_is_sfb; // @[rename-stage.scala:108:29] wire _ren2_br_tags_2_valid_T_1 = ren2_uops_2_is_br & _ren2_br_tags_2_valid_T; // @[rename-stage.scala:108:29] wire _ren2_br_tags_2_valid_T_2 = _ren2_br_tags_2_valid_T_1 | ren2_uops_2_is_jalr; // @[rename-stage.scala:108:29] assign _ren2_br_tags_2_valid_T_3 = io_dis_fire_2_0 & _ren2_br_tags_2_valid_T_2; // @[rename-stage.scala:160:7, :241:43] assign ren2_br_tags_2_valid = _ren2_br_tags_2_valid_T_3; // @[rename-stage.scala:233:29, :241:43] wire _GEN_5 = io_com_uops_2_dst_rtype_0 == 2'h1; // @[rename-stage.scala:160:7, :243:82] wire _com_valids_2_T; // @[rename-stage.scala:243:82] assign _com_valids_2_T = _GEN_5; // @[rename-stage.scala:243:82] wire _rbk_valids_2_T; // @[rename-stage.scala:244:82] assign _rbk_valids_2_T = _GEN_5; // @[rename-stage.scala:243:82, :244:82] wire _com_valids_2_T_1 = io_com_uops_2_ldst_val_0 & _com_valids_2_T; // @[rename-stage.scala:160:7, :243:{54,82}] assign _com_valids_2_T_2 = _com_valids_2_T_1 & io_com_valids_2_0; // @[rename-stage.scala:160:7, :243:{54,92}] assign com_valids_2 = _com_valids_2_T_2; // @[rename-stage.scala:236:29, :243:92] wire _rbk_valids_2_T_1 = io_com_uops_2_ldst_val_0 & _rbk_valids_2_T; // @[rename-stage.scala:160:7, :244:{54,82}] assign _rbk_valids_2_T_2 = _rbk_valids_2_T_1 & io_rbk_valids_2_0; // @[rename-stage.scala:160:7, :244:{54,92}] assign rbk_valids_2 = _rbk_valids_2_T_2; // @[rename-stage.scala:237:29, :244:92] wire [5:0] _remap_reqs_0_ldst_T; // @[rename-stage.scala:262:30] wire [6:0] _remap_reqs_0_pdst_T; // @[rename-stage.scala:263:30] wire _remap_reqs_0_valid_T; // @[rename-stage.scala:266:38] wire [5:0] _remap_reqs_1_ldst_T; // @[rename-stage.scala:262:30] wire [6:0] _remap_reqs_1_pdst_T; // @[rename-stage.scala:263:30] wire _remap_reqs_1_valid_T; // @[rename-stage.scala:266:38] wire [5:0] _remap_reqs_2_ldst_T; // @[rename-stage.scala:262:30] wire [6:0] _remap_reqs_2_pdst_T; // @[rename-stage.scala:263:30] wire _remap_reqs_2_valid_T; // @[rename-stage.scala:266:38] wire [5:0] remap_reqs_0_ldst; // @[rename-stage.scala:253:24] wire [6:0] remap_reqs_0_pdst; // @[rename-stage.scala:253:24] wire remap_reqs_0_valid; // @[rename-stage.scala:253:24] wire [5:0] remap_reqs_1_ldst; // @[rename-stage.scala:253:24] wire [6:0] remap_reqs_1_pdst; // @[rename-stage.scala:253:24] wire remap_reqs_1_valid; // @[rename-stage.scala:253:24] wire [5:0] remap_reqs_2_ldst; // @[rename-stage.scala:253:24] wire [6:0] remap_reqs_2_pdst; // @[rename-stage.scala:253:24] wire remap_reqs_2_valid; // @[rename-stage.scala:253:24] assign _remap_reqs_0_ldst_T = io_rollback_0 ? io_com_uops_2_ldst_0 : ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30] assign remap_reqs_0_ldst = _remap_reqs_0_ldst_T; // @[rename-stage.scala:253:24, :262:30] assign _remap_reqs_0_pdst_T = io_rollback_0 ? io_com_uops_2_stale_pdst_0 : ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30] assign remap_reqs_0_pdst = _remap_reqs_0_pdst_T; // @[rename-stage.scala:253:24, :263:30] assign _remap_reqs_1_ldst_T = io_rollback_0 ? io_com_uops_1_ldst_0 : ren2_uops_1_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30] assign remap_reqs_1_ldst = _remap_reqs_1_ldst_T; // @[rename-stage.scala:253:24, :262:30] assign _remap_reqs_1_pdst_T = io_rollback_0 ? io_com_uops_1_stale_pdst_0 : ren2_uops_1_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30] assign remap_reqs_1_pdst = _remap_reqs_1_pdst_T; // @[rename-stage.scala:253:24, :263:30] assign _remap_reqs_2_ldst_T = io_rollback_0 ? io_com_uops_0_ldst_0 : ren2_uops_2_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30] assign remap_reqs_2_ldst = _remap_reqs_2_ldst_T; // @[rename-stage.scala:253:24, :262:30] assign _remap_reqs_2_pdst_T = io_rollback_0 ? io_com_uops_0_stale_pdst_0 : ren2_uops_2_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30] assign remap_reqs_2_pdst = _remap_reqs_2_pdst_T; // @[rename-stage.scala:253:24, :263:30] assign _remap_reqs_0_valid_T = ren2_alloc_reqs_0 | rbk_valids_2; // @[rename-stage.scala:109:29, :237:29, :266:38] assign remap_reqs_0_valid = _remap_reqs_0_valid_T; // @[rename-stage.scala:253:24, :266:38] assign _remap_reqs_1_valid_T = ren2_alloc_reqs_1 | rbk_valids_1; // @[rename-stage.scala:109:29, :237:29, :266:38] assign remap_reqs_1_valid = _remap_reqs_1_valid_T; // @[rename-stage.scala:253:24, :266:38] assign _remap_reqs_2_valid_T = ren2_alloc_reqs_2 | rbk_valids_0; // @[rename-stage.scala:109:29, :237:29, :266:38] assign remap_reqs_2_valid = _remap_reqs_2_valid_T; // @[rename-stage.scala:253:24, :266:38] wire _freelist_io_dealloc_pregs_0_valid_T = com_valids_0 | rbk_valids_0; // @[rename-stage.scala:236:29, :237:29, :293:37] wire _freelist_io_dealloc_pregs_1_valid_T = com_valids_1 | rbk_valids_1; // @[rename-stage.scala:236:29, :237:29, :293:37] wire _freelist_io_dealloc_pregs_2_valid_T = com_valids_2 | rbk_valids_2; // @[rename-stage.scala:236:29, :237:29, :293:37] wire [6:0] _freelist_io_dealloc_pregs_0_bits_T = io_rollback_0 ? io_com_uops_0_pdst_0 : io_com_uops_0_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33] wire [6:0] _freelist_io_dealloc_pregs_1_bits_T = io_rollback_0 ? io_com_uops_1_pdst_0 : io_com_uops_1_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33] wire [6:0] _freelist_io_dealloc_pregs_2_bits_T = io_rollback_0 ? io_com_uops_2_pdst_0 : io_com_uops_2_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33] wire _ren2_uops_0_pdst_T = |ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :306:30] assign ren2_uops_0_pdst = _ren2_uops_0_pdst_T_2; // @[rename-stage.scala:108:29, :306:20] wire _ren2_uops_1_pdst_T = |ren2_uops_1_ldst; // @[rename-stage.scala:108:29, :306:30] assign ren2_uops_1_pdst = _ren2_uops_1_pdst_T_2; // @[rename-stage.scala:108:29, :306:20] wire _ren2_uops_2_pdst_T = |ren2_uops_2_ldst; // @[rename-stage.scala:108:29, :306:30] assign ren2_uops_2_pdst = _ren2_uops_2_pdst_T_2; // @[rename-stage.scala:108:29, :306:20]
Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter_5 : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg s1_id : UInt, clock reg s2_id : UInt, clock connect s2_id, s1_id node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) connect io.mem.req.valid, _io_mem_req_valid_T connect io.requestor[0].req.ready, io.mem.req.ready node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 connect io.mem.req.bits, io.requestor[1].req.bits node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T connect s1_id, UInt<1>(0h1) connect io.mem.s1_kill, io.requestor[1].s1_kill connect io.mem.s1_data, io.requestor[1].s1_data connect io.mem.s2_kill, io.requestor[1].s2_kill when io.requestor[0].req.valid : connect io.mem.req.bits, io.requestor[0].req.bits node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 connect s1_id, UInt<1>(0h0) node _T = eq(s1_id, UInt<1>(0h0)) when _T : connect io.mem.s1_kill, io.requestor[0].s1_kill connect io.mem.s1_data, io.requestor[0].s1_data node _T_1 = eq(s2_id, UInt<1>(0h0)) when _T_1 : connect io.mem.s2_kill, io.requestor[0].s2_kill node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt connect io.requestor[0].s2_gpa, io.mem.s2_gpa connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[0].ordered, io.mem.ordered connect io.requestor[0].store_pending, io.mem.store_pending connect io.requestor[0].perf, io.mem.perf node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[0].s2_uncached, io.mem.s2_uncached connect io.requestor[0].s2_paddr, io.mem.s2_paddr connect io.requestor[0].clock_enabled, io.mem.clock_enabled connect io.requestor[0].resp.bits, io.mem.resp.bits node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T connect io.requestor[0].replay_next, io.mem.replay_next node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt connect io.requestor[1].s2_gpa, io.mem.s2_gpa connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[1].ordered, io.mem.ordered connect io.requestor[1].store_pending, io.mem.store_pending connect io.requestor[1].perf, io.mem.perf node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[1].s2_uncached, io.mem.s2_uncached connect io.requestor[1].s2_paddr, io.mem.s2_paddr connect io.requestor[1].clock_enabled, io.mem.clock_enabled connect io.requestor[1].resp.bits, io.mem.resp.bits node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T connect io.requestor[1].replay_next, io.mem.replay_next
module HellaCacheArbiter_5( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [6:0] io_requestor_1_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_1_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [6:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed_0 = io_requestor_1_req_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp_0 = io_requestor_1_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled_0 = io_requestor_1_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [7:0] io_requestor_1_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [7:0] _io_mem_req_bits_tag_T_1 = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [6:0] io_requestor_0_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :34:29] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_mem_keep_clock_enabled_T = io_requestor_1_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] reg s1_id; // @[HellaCacheArbiter.scala:20:20] reg s2_id; // @[HellaCacheArbiter.scala:21:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58] assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T; // @[HellaCacheArbiter.scala:10:7, :23:81] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire [7:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[HellaCacheArbiter.scala:10:7, :34:35] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? 5'h0 : io_requestor_1_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_no_resp_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 7'h0 : _io_mem_req_bits_tag_T[6:0]; // @[HellaCacheArbiter.scala:10:7, :12:14, :34:{29,35}, :50:26] assign io_mem_s1_kill_0 = s1_id ? io_requestor_1_s1_kill_0 : io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:30] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :20:20, :33:25, :39:24, :50:26, :51:30] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_50 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_50 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module INToRecFN_i1_e8_s24_50(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_50 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControlRemapper : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn
module ReRoCCManagerControlRemapper( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_20 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_204 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_20( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_204 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_188 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_444 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_188( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_444 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget64 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<64>, data : UInt<512>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<512>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<64>, data : UInt<512>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<512>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a32d512s1k3z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<64>, data : UInt<512>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 511, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<6>(0h3f), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 5, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 5, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128) node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192) node _repeat_anonOut_a_bits_data_mux_T_4 = bits(cated.bits.data, 319, 256) node _repeat_anonOut_a_bits_data_mux_T_5 = bits(cated.bits.data, 383, 320) node _repeat_anonOut_a_bits_data_mux_T_6 = bits(cated.bits.data, 447, 384) node _repeat_anonOut_a_bits_data_mux_T_7 = bits(cated.bits.data, 511, 448) wire repeat_anonOut_a_bits_data_mux : UInt<64>[8] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2 connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3 connect repeat_anonOut_a_bits_data_mux[4], _repeat_anonOut_a_bits_data_mux_T_4 connect repeat_anonOut_a_bits_data_mux[5], _repeat_anonOut_a_bits_data_mux_T_5 connect repeat_anonOut_a_bits_data_mux[6], _repeat_anonOut_a_bits_data_mux_T_6 connect repeat_anonOut_a_bits_data_mux[7], _repeat_anonOut_a_bits_data_mux_T_7 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16) node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24) node _repeat_anonOut_a_bits_mask_mux_T_4 = bits(cated.bits.mask, 39, 32) node _repeat_anonOut_a_bits_mask_mux_T_5 = bits(cated.bits.mask, 47, 40) node _repeat_anonOut_a_bits_mask_mux_T_6 = bits(cated.bits.mask, 55, 48) node _repeat_anonOut_a_bits_mask_mux_T_7 = bits(cated.bits.mask, 63, 56) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[8] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2 connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3 connect repeat_anonOut_a_bits_mask_mux[4], _repeat_anonOut_a_bits_mask_mux_T_4 connect repeat_anonOut_a_bits_mask_mux[5], _repeat_anonOut_a_bits_mask_mux_T_5 connect repeat_anonOut_a_bits_mask_mux[6], _repeat_anonOut_a_bits_mask_mux_T_6 connect repeat_anonOut_a_bits_mask_mux[7], _repeat_anonOut_a_bits_mask_mux_T_7 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<6>(0h3f), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 5, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<3>, clock, reset, UInt<3>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) node _enable_T_6 = xor(count, UInt<2>(0h2)) node _enable_T_7 = and(_enable_T_6, limit) node _enable_T_8 = orr(_enable_T_7) node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) node _enable_T_9 = xor(count, UInt<2>(0h3)) node _enable_T_10 = and(_enable_T_9, limit) node _enable_T_11 = orr(_enable_T_10) node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) node _enable_T_12 = xor(count, UInt<3>(0h4)) node _enable_T_13 = and(_enable_T_12, limit) node _enable_T_14 = orr(_enable_T_13) node enable_4 = eq(_enable_T_14, UInt<1>(0h0)) node _enable_T_15 = xor(count, UInt<3>(0h5)) node _enable_T_16 = and(_enable_T_15, limit) node _enable_T_17 = orr(_enable_T_16) node enable_5 = eq(_enable_T_17, UInt<1>(0h0)) node _enable_T_18 = xor(count, UInt<3>(0h6)) node _enable_T_19 = and(_enable_T_18, limit) node _enable_T_20 = orr(_enable_T_19) node enable_6 = eq(_enable_T_20, UInt<1>(0h0)) node _enable_T_21 = xor(count, UInt<3>(0h7)) node _enable_T_22 = and(_enable_T_21, limit) node _enable_T_23 = orr(_enable_T_22) node enable_7 = eq(_enable_T_23, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2) node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3) node _anonIn_d_bits_data_masked_enable_T_4 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_4 = or(enable_4, _anonIn_d_bits_data_masked_enable_T_4) node _anonIn_d_bits_data_masked_enable_T_5 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_5 = or(enable_5, _anonIn_d_bits_data_masked_enable_T_5) node _anonIn_d_bits_data_masked_enable_T_6 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_6 = or(enable_6, _anonIn_d_bits_data_masked_enable_T_6) node _anonIn_d_bits_data_masked_enable_T_7 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_7 = or(enable_7, _anonIn_d_bits_data_masked_enable_T_7) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data wire anonIn_d_bits_data_odata_2 : UInt connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data wire anonIn_d_bits_data_odata_3 : UInt connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data wire anonIn_d_bits_data_odata_4 : UInt connect anonIn_d_bits_data_odata_4, anonOut.d.bits.data wire anonIn_d_bits_data_odata_5 : UInt connect anonIn_d_bits_data_odata_5, anonOut.d.bits.data wire anonIn_d_bits_data_odata_6 : UInt connect anonIn_d_bits_data_odata_6, anonOut.d.bits.data wire anonIn_d_bits_data_odata_7 : UInt connect anonIn_d_bits_data_odata_7, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[7], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1]) node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2]) node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonIn_d_bits_data_rdata[3]) node anonIn_d_bits_data_mdata_4 = mux(anonIn_d_bits_data_masked_enable_4, anonIn_d_bits_data_odata_4, anonIn_d_bits_data_rdata[4]) node anonIn_d_bits_data_mdata_5 = mux(anonIn_d_bits_data_masked_enable_5, anonIn_d_bits_data_odata_5, anonIn_d_bits_data_rdata[5]) node anonIn_d_bits_data_mdata_6 = mux(anonIn_d_bits_data_masked_enable_6, anonIn_d_bits_data_odata_6, anonIn_d_bits_data_rdata[6]) node anonIn_d_bits_data_mdata_7 = mux(anonIn_d_bits_data_masked_enable_7, anonIn_d_bits_data_odata_7, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1 connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2 connect anonIn_d_bits_data_rdata[3], anonIn_d_bits_data_mdata_3 connect anonIn_d_bits_data_rdata[4], anonIn_d_bits_data_mdata_4 connect anonIn_d_bits_data_rdata[5], anonIn_d_bits_data_mdata_5 connect anonIn_d_bits_data_rdata[6], anonIn_d_bits_data_mdata_6 node anonIn_d_bits_data_lo_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) node anonIn_d_bits_data_lo_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2) node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_lo_hi, anonIn_d_bits_data_lo_lo) node anonIn_d_bits_data_hi_lo = cat(anonIn_d_bits_data_mdata_5, anonIn_d_bits_data_mdata_4) node anonIn_d_bits_data_hi_hi = cat(anonIn_d_bits_data_mdata_7, anonIn_d_bits_data_mdata_6) node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_hi_hi, anonIn_d_bits_data_hi_lo) node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<64>, data : UInt<512>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<512>(0h0) connect _WIRE.bits.mask, UInt<64>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<64>, data : UInt<512>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<512>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<512>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<512>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLWidthWidget64( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [511:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [511:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [511:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [511:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [63:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [511:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [511:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [511:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [511:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_4 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_5 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_6 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_7 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [511:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [511:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [447:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[511:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [20:0] _repeat_limit_T = 21'h3F << cated_bits_size; // @[package.scala:243:71] wire [5:0] _repeat_limit_T_1 = _repeat_limit_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] repeat_limit = _repeat_limit_T_2[5:3]; // @[package.scala:243:46] reg [2:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24] wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24] wire [2:0] repeat_sel = cated_bits_address[5:3]; // @[WidthWidget.scala:116:39, :161:25] wire [2:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_4 = cated_bits_data[319:256]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_4 = _repeat_anonOut_a_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_5 = cated_bits_data[383:320]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_5 = _repeat_anonOut_a_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_6 = cated_bits_data[447:384]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_6 = _repeat_anonOut_a_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_7 = cated_bits_data[511:448]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_7 = _repeat_anonOut_a_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_7}, {repeat_anonOut_a_bits_data_mux_6}, {repeat_anonOut_a_bits_data_mux_5}, {repeat_anonOut_a_bits_data_mux_4}, {repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_4 = cated_bits_mask[39:32]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_4 = _repeat_anonOut_a_bits_mask_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_5 = cated_bits_mask[47:40]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_5 = _repeat_anonOut_a_bits_mask_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_6 = cated_bits_mask[55:48]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_6 = _repeat_anonOut_a_bits_mask_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_7 = cated_bits_mask[63:56]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_7 = _repeat_anonOut_a_bits_mask_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_7}, {repeat_anonOut_a_bits_mask_mux_6}, {repeat_anonOut_a_bits_mask_mux_5}, {repeat_anonOut_a_bits_mask_mux_4}, {repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [20:0] _limit_T = 21'h3F << anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] _limit_T_1 = _limit_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] limit = _limit_T_2[5:3]; // @[package.scala:243:46] reg [2:0] count; // @[WidthWidget.scala:40:27] wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_14 = |_enable_T_13; // @[WidthWidget.scala:43:{63,72}] wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_17 = |_enable_T_16; // @[WidthWidget.scala:43:{63,72}] wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_20 = |_enable_T_19; // @[WidthWidget.scala:43:{63,72}] wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_23 = |_enable_T_22; // @[WidthWidget.scala:43:{63,72}] wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24] wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_4 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_4 = enable_4 | _anonIn_d_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_5 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_5 = enable_5 | _anonIn_d_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_6 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_6 = enable_6 | _anonIn_d_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_7 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_7 = enable_7 | _anonIn_d_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_3; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_4; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_5; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_6; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonIn_d_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_4 = anonIn_d_bits_data_masked_enable_4 ? anonIn_d_bits_data_odata_4 : anonIn_d_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_5 = anonIn_d_bits_data_masked_enable_5 ? anonIn_d_bits_data_odata_5 : anonIn_d_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_6 = anonIn_d_bits_data_masked_enable_6 ? anonIn_d_bits_data_odata_6 : anonIn_d_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_7 = anonIn_d_bits_data_masked_enable_7 ? anonIn_d_bits_data_odata_7 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_lo_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [255:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_lo_hi, anonIn_d_bits_data_lo_lo}; // @[WidthWidget.scala:73:12] wire [127:0] anonIn_d_bits_data_hi_lo = {anonIn_d_bits_data_mdata_5, anonIn_d_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi_hi = {anonIn_d_bits_data_mdata_7, anonIn_d_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [255:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_hi_hi, anonIn_d_bits_data_hi_lo}; // @[WidthWidget.scala:73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 3'h0; // @[WidthWidget.scala:105:26] count <= 3'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_3 <= anonIn_d_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_4 <= anonIn_d_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_5 <= anonIn_d_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_6 <= anonIn_d_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d512s1k3z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<17>(0h10000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<18>(0h2f000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<27>(0h4000000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<13>(0h1000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<15>(0h4000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_144, _T_149) node _T_181 = or(_T_180, _T_154) node _T_182 = or(_T_181, _T_159) node _T_183 = or(_T_182, _T_164) node _T_184 = or(_T_183, _T_169) node _T_185 = or(_T_184, _T_174) node _T_186 = or(_T_185, _T_179) node _T_187 = and(_T_139, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_138, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<14>(0h2000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<13>(0h1000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<17>(0h10000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<18>(0h2f000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<17>(0h10000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<15>(0h4000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_201, _T_206) node _T_238 = or(_T_237, _T_211) node _T_239 = or(_T_238, _T_216) node _T_240 = or(_T_239, _T_221) node _T_241 = or(_T_240, _T_226) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_236) node _T_244 = and(_T_196, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = and(UInt<1>(0h0), _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_246, UInt<1>(0h1), "") : assert_3 node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(source_ok, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_253 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_253, UInt<1>(0h1), "") : assert_5 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(is_aligned, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_260 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_260, UInt<1>(0h1), "") : assert_7 node _T_264 = not(io.in.a.bits.mask) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_265, UInt<1>(0h1), "") : assert_8 node _T_269 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_269, UInt<1>(0h1), "") : assert_9 node _T_273 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h0)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_8) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h1)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_9) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h2)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_10) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h3)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_11) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_305 = or(_T_277, _T_283) node _T_306 = or(_T_305, _T_289) node _T_307 = or(_T_306, _T_295) node _T_308 = or(_T_307, _T_301) node _T_309 = or(_T_308, _T_302) node _T_310 = or(_T_309, _T_303) node _T_311 = or(_T_310, _T_304) node _T_312 = and(_T_276, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<17>(0h10000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<18>(0h2f000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<17>(0h10000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<27>(0h4000000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<15>(0h4000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = or(_T_319, _T_324) node _T_356 = or(_T_355, _T_329) node _T_357 = or(_T_356, _T_334) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_344) node _T_360 = or(_T_359, _T_349) node _T_361 = or(_T_360, _T_354) node _T_362 = and(_T_314, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = and(_T_313, _T_363) node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(_T_364, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_364, UInt<1>(0h1), "") : assert_10 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<14>(0h2000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<13>(0h1000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<18>(0h2f000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<15>(0h4000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_376, _T_381) node _T_413 = or(_T_412, _T_386) node _T_414 = or(_T_413, _T_391) node _T_415 = or(_T_414, _T_396) node _T_416 = or(_T_415, _T_401) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_411) node _T_419 = and(_T_371, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = and(UInt<1>(0h0), _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_421, UInt<1>(0h1), "") : assert_11 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(source_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_428 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_428, UInt<1>(0h1), "") : assert_13 node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(is_aligned, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_435 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_435, UInt<1>(0h1), "") : assert_15 node _T_439 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_439, UInt<1>(0h1), "") : assert_16 node _T_443 = not(io.in.a.bits.mask) node _T_444 = eq(_T_443, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_444, UInt<1>(0h1), "") : assert_17 node _T_448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_448, UInt<1>(0h1), "") : assert_18 node _T_452 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_452 : node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_12) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<1>(0h1)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_13) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_469 = shr(io.in.a.bits.source, 2) node _T_470 = eq(_T_469, UInt<2>(0h2)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_14) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_474 = and(_T_472, _T_473) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_475 = shr(io.in.a.bits.source, 2) node _T_476 = eq(_T_475, UInt<2>(0h3)) node _T_477 = leq(UInt<1>(0h0), uncommonBits_15) node _T_478 = and(_T_476, _T_477) node _T_479 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_484 = or(_T_456, _T_462) node _T_485 = or(_T_484, _T_468) node _T_486 = or(_T_485, _T_474) node _T_487 = or(_T_486, _T_480) node _T_488 = or(_T_487, _T_481) node _T_489 = or(_T_488, _T_482) node _T_490 = or(_T_489, _T_483) node _T_491 = and(_T_455, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_492, UInt<1>(0h1), "") : assert_19 node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_498 = and(_T_496, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = and(_T_499, _T_504) node _T_506 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_507 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_508 = and(_T_506, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<14>(0h2000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<17>(0h10000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_531 = cvt(_T_530) node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000))) node _T_533 = asSInt(_T_532) node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0))) node _T_535 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<13>(0h1000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<15>(0h4000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = or(_T_514, _T_519) node _T_546 = or(_T_545, _T_524) node _T_547 = or(_T_546, _T_529) node _T_548 = or(_T_547, _T_534) node _T_549 = or(_T_548, _T_539) node _T_550 = or(_T_549, _T_544) node _T_551 = and(_T_509, _T_550) node _T_552 = or(UInt<1>(0h0), _T_505) node _T_553 = or(_T_552, _T_551) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_553, UInt<1>(0h1), "") : assert_20 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(is_aligned, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_563 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_563, UInt<1>(0h1), "") : assert_23 node _T_567 = eq(io.in.a.bits.mask, mask) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_567, UInt<1>(0h1), "") : assert_24 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_571, UInt<1>(0h1), "") : assert_25 node _T_575 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h0)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_16) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h1)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_17) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h2)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_18) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h3)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_19) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_579, _T_585) node _T_608 = or(_T_607, _T_591) node _T_609 = or(_T_608, _T_597) node _T_610 = or(_T_609, _T_603) node _T_611 = or(_T_610, _T_604) node _T_612 = or(_T_611, _T_605) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<27>(0h4000000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<13>(0h1000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<15>(0h4000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_634, _T_639) node _T_661 = or(_T_660, _T_644) node _T_662 = or(_T_661, _T_649) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_659) node _T_665 = and(_T_629, _T_664) node _T_666 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_625) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_672) node _T_676 = and(_T_615, _T_675) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_676, UInt<1>(0h1), "") : assert_26 node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(source_ok, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(is_aligned, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_686 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_686, UInt<1>(0h1), "") : assert_29 node _T_690 = eq(io.in.a.bits.mask, mask) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_690, UInt<1>(0h1), "") : assert_30 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_20) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_21) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_22) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_23) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_726 = or(_T_698, _T_704) node _T_727 = or(_T_726, _T_710) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = and(_T_697, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_736 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_737 = and(_T_735, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = and(_T_738, _T_743) node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<14>(0h2000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<18>(0h2f000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<27>(0h4000000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<13>(0h1000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<15>(0h4000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = or(_T_753, _T_758) node _T_780 = or(_T_779, _T_763) node _T_781 = or(_T_780, _T_768) node _T_782 = or(_T_781, _T_773) node _T_783 = or(_T_782, _T_778) node _T_784 = and(_T_748, _T_783) node _T_785 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = and(_T_785, _T_790) node _T_792 = or(UInt<1>(0h0), _T_744) node _T_793 = or(_T_792, _T_784) node _T_794 = or(_T_793, _T_791) node _T_795 = and(_T_734, _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_795, UInt<1>(0h1), "") : assert_31 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(is_aligned, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_805 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_805, UInt<1>(0h1), "") : assert_34 node _T_809 = not(mask) node _T_810 = and(io.in.a.bits.mask, _T_809) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_811, UInt<1>(0h1), "") : assert_35 node _T_815 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_815 : node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h0)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_24) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h1)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_25) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_26) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<2>(0h3)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_27) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_819, _T_825) node _T_848 = or(_T_847, _T_831) node _T_849 = or(_T_848, _T_837) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = and(_T_818, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<15>(0h5000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<13>(0h1000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = or(_T_864, _T_869) node _T_871 = and(_T_859, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<18>(0h2f000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<17>(0h10000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<27>(0h4000000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = or(_T_877, _T_882) node _T_899 = or(_T_898, _T_887) node _T_900 = or(_T_899, _T_892) node _T_901 = or(_T_900, _T_897) node _T_902 = and(_T_872, _T_901) node _T_903 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_904 = or(UInt<1>(0h0), _T_903) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<15>(0h4000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = and(_T_904, _T_909) node _T_911 = or(UInt<1>(0h0), _T_871) node _T_912 = or(_T_911, _T_902) node _T_913 = or(_T_912, _T_910) node _T_914 = and(_T_855, _T_913) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_914, UInt<1>(0h1), "") : assert_36 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(source_ok, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(is_aligned, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_924 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_924, UInt<1>(0h1), "") : assert_39 node _T_928 = eq(io.in.a.bits.mask, mask) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_928, UInt<1>(0h1), "") : assert_40 node _T_932 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_932 : node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_934 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_935 = and(_T_933, _T_934) node _T_936 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_937 = shr(io.in.a.bits.source, 2) node _T_938 = eq(_T_937, UInt<1>(0h0)) node _T_939 = leq(UInt<1>(0h0), uncommonBits_28) node _T_940 = and(_T_938, _T_939) node _T_941 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_942 = and(_T_940, _T_941) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_943 = shr(io.in.a.bits.source, 2) node _T_944 = eq(_T_943, UInt<1>(0h1)) node _T_945 = leq(UInt<1>(0h0), uncommonBits_29) node _T_946 = and(_T_944, _T_945) node _T_947 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_948 = and(_T_946, _T_947) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_949 = shr(io.in.a.bits.source, 2) node _T_950 = eq(_T_949, UInt<2>(0h2)) node _T_951 = leq(UInt<1>(0h0), uncommonBits_30) node _T_952 = and(_T_950, _T_951) node _T_953 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_954 = and(_T_952, _T_953) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_955 = shr(io.in.a.bits.source, 2) node _T_956 = eq(_T_955, UInt<2>(0h3)) node _T_957 = leq(UInt<1>(0h0), uncommonBits_31) node _T_958 = and(_T_956, _T_957) node _T_959 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_960 = and(_T_958, _T_959) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_963 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_964 = or(_T_936, _T_942) node _T_965 = or(_T_964, _T_948) node _T_966 = or(_T_965, _T_954) node _T_967 = or(_T_966, _T_960) node _T_968 = or(_T_967, _T_961) node _T_969 = or(_T_968, _T_962) node _T_970 = or(_T_969, _T_963) node _T_971 = and(_T_935, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_974 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_975 = and(_T_973, _T_974) node _T_976 = or(UInt<1>(0h0), _T_975) node _T_977 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<15>(0h5000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = or(_T_981, _T_986) node _T_988 = and(_T_976, _T_987) node _T_989 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_990 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_991 = cvt(_T_990) node _T_992 = and(_T_991, asSInt(UInt<13>(0h1000))) node _T_993 = asSInt(_T_992) node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0))) node _T_995 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_996 = cvt(_T_995) node _T_997 = and(_T_996, asSInt(UInt<17>(0h10000))) node _T_998 = asSInt(_T_997) node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0))) node _T_1000 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<18>(0h2f000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<17>(0h10000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<27>(0h4000000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = or(_T_994, _T_999) node _T_1016 = or(_T_1015, _T_1004) node _T_1017 = or(_T_1016, _T_1009) node _T_1018 = or(_T_1017, _T_1014) node _T_1019 = and(_T_989, _T_1018) node _T_1020 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_1021 = or(UInt<1>(0h0), _T_1020) node _T_1022 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<15>(0h4000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = and(_T_1021, _T_1026) node _T_1028 = or(UInt<1>(0h0), _T_988) node _T_1029 = or(_T_1028, _T_1019) node _T_1030 = or(_T_1029, _T_1027) node _T_1031 = and(_T_972, _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_41 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(source_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(is_aligned, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1041 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_44 node _T_1045 = eq(io.in.a.bits.mask, mask) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_45 node _T_1049 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1049 : node _T_1050 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1051 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<1>(0h1)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<2>(0h2)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1072 = shr(io.in.a.bits.source, 2) node _T_1073 = eq(_T_1072, UInt<2>(0h3)) node _T_1074 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1081 = or(_T_1053, _T_1059) node _T_1082 = or(_T_1081, _T_1065) node _T_1083 = or(_T_1082, _T_1071) node _T_1084 = or(_T_1083, _T_1077) node _T_1085 = or(_T_1084, _T_1078) node _T_1086 = or(_T_1085, _T_1079) node _T_1087 = or(_T_1086, _T_1080) node _T_1088 = and(_T_1052, _T_1087) node _T_1089 = or(UInt<1>(0h0), _T_1088) node _T_1090 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1091 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = or(UInt<1>(0h0), _T_1092) node _T_1094 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1095 = cvt(_T_1094) node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000))) node _T_1097 = asSInt(_T_1096) node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0))) node _T_1099 = and(_T_1093, _T_1098) node _T_1100 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<14>(0h2000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<17>(0h10000))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1112 = cvt(_T_1111) node _T_1113 = and(_T_1112, asSInt(UInt<18>(0h2f000))) node _T_1114 = asSInt(_T_1113) node _T_1115 = eq(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1117 = cvt(_T_1116) node _T_1118 = and(_T_1117, asSInt(UInt<17>(0h10000))) node _T_1119 = asSInt(_T_1118) node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0))) node _T_1121 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<27>(0h4000000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1127 = cvt(_T_1126) node _T_1128 = and(_T_1127, asSInt(UInt<13>(0h1000))) node _T_1129 = asSInt(_T_1128) node _T_1130 = eq(_T_1129, asSInt(UInt<1>(0h0))) node _T_1131 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1132 = cvt(_T_1131) node _T_1133 = and(_T_1132, asSInt(UInt<15>(0h4000))) node _T_1134 = asSInt(_T_1133) node _T_1135 = eq(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = or(_T_1105, _T_1110) node _T_1137 = or(_T_1136, _T_1115) node _T_1138 = or(_T_1137, _T_1120) node _T_1139 = or(_T_1138, _T_1125) node _T_1140 = or(_T_1139, _T_1130) node _T_1141 = or(_T_1140, _T_1135) node _T_1142 = and(_T_1100, _T_1141) node _T_1143 = or(UInt<1>(0h0), _T_1099) node _T_1144 = or(_T_1143, _T_1142) node _T_1145 = and(_T_1089, _T_1144) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_46 node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(source_ok, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(is_aligned, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1155 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_49 node _T_1159 = eq(io.in.a.bits.mask, mask) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_50 node _T_1163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1167 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1171 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(source_ok_1, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1175 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_54 node _T_1179 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_55 node _T_1183 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_56 node _T_1187 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_57 node _T_1191 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1191 : node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(source_ok_1, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(sink_ok, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1198 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_60 node _T_1202 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_61 node _T_1206 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_62 node _T_1210 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_63 node _T_1214 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1215 = or(UInt<1>(0h1), _T_1214) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_64 node _T_1219 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1219 : node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(source_ok_1, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(sink_ok, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1226 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_67 node _T_1230 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_68 node _T_1234 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_69 node _T_1238 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1239 = or(_T_1238, io.in.d.bits.corrupt) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_70 node _T_1243 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1244 = or(UInt<1>(0h1), _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_71 node _T_1248 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1248 : node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(source_ok_1, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1252 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_73 node _T_1256 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_74 node _T_1260 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1261 = or(UInt<1>(0h1), _T_1260) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_75 node _T_1265 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1265 : node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(source_ok_1, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1269 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_77 node _T_1273 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1274 = or(_T_1273, io.in.d.bits.corrupt) node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(_T_1274, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1274, UInt<1>(0h1), "") : assert_78 node _T_1278 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1279 = or(UInt<1>(0h1), _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_79 node _T_1283 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1283 : node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(source_ok_1, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1287 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_81 node _T_1291 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_82 node _T_1295 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1296 = or(UInt<1>(0h1), _T_1295) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1300 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1304 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1308 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1312 = eq(a_first, UInt<1>(0h0)) node _T_1313 = and(io.in.a.valid, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.a.bits.opcode, opcode) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_87 node _T_1318 = eq(io.in.a.bits.param, param) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_88 node _T_1322 = eq(io.in.a.bits.size, size) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_89 node _T_1326 = eq(io.in.a.bits.source, source) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_90 node _T_1330 = eq(io.in.a.bits.address, address) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_91 node _T_1334 = and(io.in.a.ready, io.in.a.valid) node _T_1335 = and(_T_1334, a_first) when _T_1335 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1336 = eq(d_first, UInt<1>(0h0)) node _T_1337 = and(io.in.d.valid, _T_1336) when _T_1337 : node _T_1338 = eq(io.in.d.bits.opcode, opcode_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_92 node _T_1342 = eq(io.in.d.bits.param, param_1) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_93 node _T_1346 = eq(io.in.d.bits.size, size_1) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_94 node _T_1350 = eq(io.in.d.bits.source, source_1) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_95 node _T_1354 = eq(io.in.d.bits.sink, sink) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_96 node _T_1358 = eq(io.in.d.bits.denied, denied) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_97 node _T_1362 = and(io.in.d.ready, io.in.d.valid) node _T_1363 = and(_T_1362, d_first) when _T_1363 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1364 = and(io.in.a.valid, a_first_1) node _T_1365 = and(_T_1364, UInt<1>(0h1)) when _T_1365 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1366 = and(io.in.a.ready, io.in.a.valid) node _T_1367 = and(_T_1366, a_first_1) node _T_1368 = and(_T_1367, UInt<1>(0h1)) when _T_1368 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1369 = dshr(inflight, io.in.a.bits.source) node _T_1370 = bits(_T_1369, 0, 0) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1375 = and(io.in.d.valid, d_first_1) node _T_1376 = and(_T_1375, UInt<1>(0h1)) node _T_1377 = eq(d_release_ack, UInt<1>(0h0)) node _T_1378 = and(_T_1376, _T_1377) when _T_1378 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1379 = and(io.in.d.ready, io.in.d.valid) node _T_1380 = and(_T_1379, d_first_1) node _T_1381 = and(_T_1380, UInt<1>(0h1)) node _T_1382 = eq(d_release_ack, UInt<1>(0h0)) node _T_1383 = and(_T_1381, _T_1382) when _T_1383 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1384 = and(io.in.d.valid, d_first_1) node _T_1385 = and(_T_1384, UInt<1>(0h1)) node _T_1386 = eq(d_release_ack, UInt<1>(0h0)) node _T_1387 = and(_T_1385, _T_1386) when _T_1387 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1388 = dshr(inflight, io.in.d.bits.source) node _T_1389 = bits(_T_1388, 0, 0) node _T_1390 = or(_T_1389, same_cycle_resp) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1394 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1395 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1396 = or(_T_1394, _T_1395) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_100 node _T_1400 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_101 else : node _T_1404 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1406 = or(_T_1404, _T_1405) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_102 node _T_1410 = eq(io.in.d.bits.size, a_size_lookup) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_103 node _T_1414 = and(io.in.d.valid, d_first_1) node _T_1415 = and(_T_1414, a_first_1) node _T_1416 = and(_T_1415, io.in.a.valid) node _T_1417 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1418 = and(_T_1416, _T_1417) node _T_1419 = eq(d_release_ack, UInt<1>(0h0)) node _T_1420 = and(_T_1418, _T_1419) when _T_1420 : node _T_1421 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1422 = or(_T_1421, io.in.a.ready) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_32 node _T_1426 = orr(inflight) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) node _T_1428 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1429 = or(_T_1427, _T_1428) node _T_1430 = lt(watchdog, plusarg_reader.out) node _T_1431 = or(_T_1429, _T_1430) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1435 = and(io.in.a.ready, io.in.a.valid) node _T_1436 = and(io.in.d.ready, io.in.d.valid) node _T_1437 = or(_T_1435, _T_1436) when _T_1437 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1438 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1439 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1440 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1441 = and(_T_1439, _T_1440) node _T_1442 = and(_T_1438, _T_1441) when _T_1442 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1443 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1444 = and(_T_1443, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1445 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1446 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1447 = and(_T_1445, _T_1446) node _T_1448 = and(_T_1444, _T_1447) when _T_1448 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1449 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1450 = bits(_T_1449, 0, 0) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1455 = and(io.in.d.valid, d_first_2) node _T_1456 = and(_T_1455, UInt<1>(0h1)) node _T_1457 = and(_T_1456, d_release_ack_1) when _T_1457 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1458 = and(io.in.d.ready, io.in.d.valid) node _T_1459 = and(_T_1458, d_first_2) node _T_1460 = and(_T_1459, UInt<1>(0h1)) node _T_1461 = and(_T_1460, d_release_ack_1) when _T_1461 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1462 = and(io.in.d.valid, d_first_2) node _T_1463 = and(_T_1462, UInt<1>(0h1)) node _T_1464 = and(_T_1463, d_release_ack_1) when _T_1464 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1465 = dshr(inflight_1, io.in.d.bits.source) node _T_1466 = bits(_T_1465, 0, 0) node _T_1467 = or(_T_1466, same_cycle_resp_1) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1471 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(_T_1471, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1471, UInt<1>(0h1), "") : assert_108 else : node _T_1475 = eq(io.in.d.bits.size, c_size_lookup) node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(_T_1475, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1475, UInt<1>(0h1), "") : assert_109 node _T_1479 = and(io.in.d.valid, d_first_2) node _T_1480 = and(_T_1479, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1481 = and(_T_1480, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1482 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1483 = and(_T_1481, _T_1482) node _T_1484 = and(_T_1483, d_release_ack_1) node _T_1485 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1486 = and(_T_1484, _T_1485) when _T_1486 : node _T_1487 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1488 = or(_T_1487, _WIRE_23.ready) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_33 node _T_1492 = orr(inflight_1) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) node _T_1494 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1495 = or(_T_1493, _T_1494) node _T_1496 = lt(watchdog_1, plusarg_reader_1.out) node _T_1497 = or(_T_1495, _T_1496) node _T_1498 = asUInt(reset) node _T_1499 = eq(_T_1498, UInt<1>(0h0)) when _T_1499 : node _T_1500 = eq(_T_1497, UInt<1>(0h0)) when _T_1500 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1497, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1501 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1502 = and(io.in.d.ready, io.in.d.valid) node _T_1503 = or(_T_1501, _T_1502) when _T_1503 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1435 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1435; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1435; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1503 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1503; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1503; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1503; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1368 = _T_1435 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1368 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1368 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1368 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1368 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1368 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1414 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1414 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1383 = _T_1503 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1383 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1383 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1383 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1479 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1479 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1461 = _T_1503 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1461 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1461 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1461 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_0ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[7], sa_stall : UInt[7]}, routers_egress_nodes_out_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, routers_egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect routers.auto.ingress_nodes_in_2, auto.routers_ingress_nodes_in_2 connect routers.auto.ingress_nodes_in_3, auto.routers_ingress_nodes_in_3 connect routers.auto.ingress_nodes_in_4, auto.routers_ingress_nodes_in_4 connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready connect auto.routers_egress_nodes_out_2.flit.bits, routers.auto.egress_nodes_out_2.flit.bits connect auto.routers_egress_nodes_out_2.flit.valid, routers.auto.egress_nodes_out_2.flit.valid connect routers.auto.egress_nodes_out_2.flit.ready, auto.routers_egress_nodes_out_2.flit.ready connect auto.routers_egress_nodes_out_3.flit.bits, routers.auto.egress_nodes_out_3.flit.bits connect auto.routers_egress_nodes_out_3.flit.valid, routers.auto.egress_nodes_out_3.flit.valid connect routers.auto.egress_nodes_out_3.flit.ready, auto.routers_egress_nodes_out_3.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLSplitACDxBENoC_acd_router_0ClockSinkDomain( // @[ClockDomain.scala:14:9] output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_5, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_6, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_5, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_6, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_3_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_3_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_3_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_4_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_4_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_4_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_4_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_4_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_ingress_nodes_in_4_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_3_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_3_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_3_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_3_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_3_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_va_stall_5 (auto_routers_debug_out_va_stall_5), .auto_debug_out_va_stall_6 (auto_routers_debug_out_va_stall_6), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_debug_out_sa_stall_5 (auto_routers_debug_out_sa_stall_5), .auto_debug_out_sa_stall_6 (auto_routers_debug_out_sa_stall_6), .auto_egress_nodes_out_3_flit_ready (auto_routers_egress_nodes_out_3_flit_ready), .auto_egress_nodes_out_3_flit_valid (auto_routers_egress_nodes_out_3_flit_valid), .auto_egress_nodes_out_3_flit_bits_head (auto_routers_egress_nodes_out_3_flit_bits_head), .auto_egress_nodes_out_3_flit_bits_tail (auto_routers_egress_nodes_out_3_flit_bits_tail), .auto_egress_nodes_out_2_flit_ready (auto_routers_egress_nodes_out_2_flit_ready), .auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid), .auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head), .auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail), .auto_egress_nodes_out_2_flit_bits_payload (auto_routers_egress_nodes_out_2_flit_bits_payload), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_4_flit_ready (auto_routers_ingress_nodes_in_4_flit_ready), .auto_ingress_nodes_in_4_flit_valid (auto_routers_ingress_nodes_in_4_flit_valid), .auto_ingress_nodes_in_4_flit_bits_head (auto_routers_ingress_nodes_in_4_flit_bits_head), .auto_ingress_nodes_in_4_flit_bits_tail (auto_routers_ingress_nodes_in_4_flit_bits_tail), .auto_ingress_nodes_in_4_flit_bits_payload (auto_routers_ingress_nodes_in_4_flit_bits_payload), .auto_ingress_nodes_in_4_flit_bits_egress_id (auto_routers_ingress_nodes_in_4_flit_bits_egress_id), .auto_ingress_nodes_in_3_flit_ready (auto_routers_ingress_nodes_in_3_flit_ready), .auto_ingress_nodes_in_3_flit_valid (auto_routers_ingress_nodes_in_3_flit_valid), .auto_ingress_nodes_in_3_flit_bits_head (auto_routers_ingress_nodes_in_3_flit_bits_head), .auto_ingress_nodes_in_3_flit_bits_tail (auto_routers_ingress_nodes_in_3_flit_bits_tail), .auto_ingress_nodes_in_3_flit_bits_payload (auto_routers_ingress_nodes_in_3_flit_bits_payload), .auto_ingress_nodes_in_3_flit_bits_egress_id (auto_routers_ingress_nodes_in_3_flit_bits_egress_id), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_tail (auto_routers_ingress_nodes_in_2_flit_bits_tail), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BankedStore_1 : input clock : Clock input reset : Reset output io : { flip sinkC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip sinkC_dat : { data : UInt<128>}, flip sinkD_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<3>, mask : UInt<1>}}, flip sinkD_dat : { data : UInt<64>}, flip sourceC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<3>, mask : UInt<1>}}, sourceC_dat : { data : UInt<64>}, flip sourceD_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, sourceD_rdat : { data : UInt<128>}, flip sourceD_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip sourceD_wdat : { data : UInt<128>}} smem cc_banks_0 : UInt<64> [32768] smem cc_banks_1 : UInt<64> [32768] smem cc_banks_2 : UInt<64> [32768] smem cc_banks_3 : UInt<64> [32768] smem cc_banks_4 : UInt<64> [32768] smem cc_banks_5 : UInt<64> [32768] smem cc_banks_6 : UInt<64> [32768] smem cc_banks_7 : UInt<64> [32768] node sinkC_req_words_0 = bits(io.sinkC_dat.data, 63, 0) node sinkC_req_words_1 = bits(io.sinkC_dat.data, 127, 64) node sinkC_req_a_hi = cat(io.sinkC_adr.bits.way, io.sinkC_adr.bits.set) node sinkC_req_a = cat(sinkC_req_a_hi, io.sinkC_adr.bits.beat) wire sinkC_req : { wen : UInt<1>, index : UInt<15>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sinkC_req_select_T = bits(sinkC_req_a, 1, 0) node sinkC_req_select_shiftAmount = bits(_sinkC_req_select_T, 1, 0) node _sinkC_req_select_T_1 = dshl(UInt<1>(0h1), sinkC_req_select_shiftAmount) node sinkC_req_select = bits(_sinkC_req_select_T_1, 3, 0) node _sinkC_req_ready_T = bits(sinkC_req.bankSum, 1, 0) node _sinkC_req_ready_T_1 = and(_sinkC_req_ready_T, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_2 = orr(_sinkC_req_ready_T_1) node _sinkC_req_ready_T_3 = eq(_sinkC_req_ready_T_2, UInt<1>(0h0)) node _sinkC_req_ready_T_4 = bits(sinkC_req.bankSum, 3, 2) node _sinkC_req_ready_T_5 = and(_sinkC_req_ready_T_4, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_6 = orr(_sinkC_req_ready_T_5) node _sinkC_req_ready_T_7 = eq(_sinkC_req_ready_T_6, UInt<1>(0h0)) node _sinkC_req_ready_T_8 = bits(sinkC_req.bankSum, 5, 4) node _sinkC_req_ready_T_9 = and(_sinkC_req_ready_T_8, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_10 = orr(_sinkC_req_ready_T_9) node _sinkC_req_ready_T_11 = eq(_sinkC_req_ready_T_10, UInt<1>(0h0)) node _sinkC_req_ready_T_12 = bits(sinkC_req.bankSum, 7, 6) node _sinkC_req_ready_T_13 = and(_sinkC_req_ready_T_12, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_14 = orr(_sinkC_req_ready_T_13) node _sinkC_req_ready_T_15 = eq(_sinkC_req_ready_T_14, UInt<1>(0h0)) node sinkC_req_ready_lo = cat(_sinkC_req_ready_T_7, _sinkC_req_ready_T_3) node sinkC_req_ready_hi = cat(_sinkC_req_ready_T_15, _sinkC_req_ready_T_11) node sinkC_req_ready = cat(sinkC_req_ready_hi, sinkC_req_ready_lo) node _sinkC_req_io_sinkC_adr_ready_T = bits(sinkC_req_a, 1, 0) node _sinkC_req_io_sinkC_adr_ready_T_1 = dshr(sinkC_req_ready, _sinkC_req_io_sinkC_adr_ready_T) node _sinkC_req_io_sinkC_adr_ready_T_2 = bits(_sinkC_req_io_sinkC_adr_ready_T_1, 0, 0) connect io.sinkC_adr.ready, _sinkC_req_io_sinkC_adr_ready_T_2 connect sinkC_req.wen, UInt<1>(0h1) node _sinkC_req_out_index_T = shr(sinkC_req_a, 2) connect sinkC_req.index, _sinkC_req_out_index_T node _sinkC_req_out_bankSel_T = bits(sinkC_req_select, 0, 0) node _sinkC_req_out_bankSel_T_1 = bits(sinkC_req_select, 1, 1) node _sinkC_req_out_bankSel_T_2 = bits(sinkC_req_select, 2, 2) node _sinkC_req_out_bankSel_T_3 = bits(sinkC_req_select, 3, 3) node _sinkC_req_out_bankSel_T_4 = mux(_sinkC_req_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_5 = mux(_sinkC_req_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_6 = mux(_sinkC_req_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_7 = mux(_sinkC_req_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sinkC_req_out_bankSel_lo = cat(_sinkC_req_out_bankSel_T_5, _sinkC_req_out_bankSel_T_4) node sinkC_req_out_bankSel_hi = cat(_sinkC_req_out_bankSel_T_7, _sinkC_req_out_bankSel_T_6) node _sinkC_req_out_bankSel_T_8 = cat(sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo) node _sinkC_req_out_bankSel_T_9 = cat(io.sinkC_adr.bits.mask, io.sinkC_adr.bits.mask) node _sinkC_req_out_bankSel_T_10 = cat(_sinkC_req_out_bankSel_T_9, _sinkC_req_out_bankSel_T_9) node _sinkC_req_out_bankSel_T_11 = and(_sinkC_req_out_bankSel_T_8, _sinkC_req_out_bankSel_T_10) node _sinkC_req_out_bankSel_T_12 = mux(io.sinkC_adr.valid, _sinkC_req_out_bankSel_T_11, UInt<1>(0h0)) connect sinkC_req.bankSel, _sinkC_req_out_bankSel_T_12 node _sinkC_req_out_bankEn_T = bits(sinkC_req_ready, 0, 0) node _sinkC_req_out_bankEn_T_1 = bits(sinkC_req_ready, 1, 1) node _sinkC_req_out_bankEn_T_2 = bits(sinkC_req_ready, 2, 2) node _sinkC_req_out_bankEn_T_3 = bits(sinkC_req_ready, 3, 3) node _sinkC_req_out_bankEn_T_4 = mux(_sinkC_req_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_5 = mux(_sinkC_req_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_6 = mux(_sinkC_req_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_7 = mux(_sinkC_req_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sinkC_req_out_bankEn_lo = cat(_sinkC_req_out_bankEn_T_5, _sinkC_req_out_bankEn_T_4) node sinkC_req_out_bankEn_hi = cat(_sinkC_req_out_bankEn_T_7, _sinkC_req_out_bankEn_T_6) node _sinkC_req_out_bankEn_T_8 = cat(sinkC_req_out_bankEn_hi, sinkC_req_out_bankEn_lo) node _sinkC_req_out_bankEn_T_9 = and(sinkC_req.bankSel, _sinkC_req_out_bankEn_T_8) node _sinkC_req_out_bankEn_T_10 = mux(io.sinkC_adr.bits.noop, UInt<1>(0h0), _sinkC_req_out_bankEn_T_9) connect sinkC_req.bankEn, _sinkC_req_out_bankEn_T_10 connect sinkC_req.data[0], sinkC_req_words_0 connect sinkC_req.data[1], sinkC_req_words_1 connect sinkC_req.data[2], sinkC_req_words_0 connect sinkC_req.data[3], sinkC_req_words_1 connect sinkC_req.data[4], sinkC_req_words_0 connect sinkC_req.data[5], sinkC_req_words_1 connect sinkC_req.data[6], sinkC_req_words_0 connect sinkC_req.data[7], sinkC_req_words_1 node sinkD_req_words_0 = bits(io.sinkD_dat.data, 63, 0) node sinkD_req_a_hi = cat(io.sinkD_adr.bits.way, io.sinkD_adr.bits.set) node sinkD_req_a = cat(sinkD_req_a_hi, io.sinkD_adr.bits.beat) wire sinkD_req : { wen : UInt<1>, index : UInt<15>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sinkD_req_select_T = bits(sinkD_req_a, 2, 0) node sinkD_req_select_shiftAmount = bits(_sinkD_req_select_T, 2, 0) node _sinkD_req_select_T_1 = dshl(UInt<1>(0h1), sinkD_req_select_shiftAmount) node sinkD_req_select = bits(_sinkD_req_select_T_1, 7, 0) node _sinkD_req_ready_T = bits(sinkD_req.bankSum, 0, 0) node _sinkD_req_ready_T_1 = and(_sinkD_req_ready_T, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_2 = orr(_sinkD_req_ready_T_1) node _sinkD_req_ready_T_3 = eq(_sinkD_req_ready_T_2, UInt<1>(0h0)) node _sinkD_req_ready_T_4 = bits(sinkD_req.bankSum, 1, 1) node _sinkD_req_ready_T_5 = and(_sinkD_req_ready_T_4, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_6 = orr(_sinkD_req_ready_T_5) node _sinkD_req_ready_T_7 = eq(_sinkD_req_ready_T_6, UInt<1>(0h0)) node _sinkD_req_ready_T_8 = bits(sinkD_req.bankSum, 2, 2) node _sinkD_req_ready_T_9 = and(_sinkD_req_ready_T_8, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_10 = orr(_sinkD_req_ready_T_9) node _sinkD_req_ready_T_11 = eq(_sinkD_req_ready_T_10, UInt<1>(0h0)) node _sinkD_req_ready_T_12 = bits(sinkD_req.bankSum, 3, 3) node _sinkD_req_ready_T_13 = and(_sinkD_req_ready_T_12, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_14 = orr(_sinkD_req_ready_T_13) node _sinkD_req_ready_T_15 = eq(_sinkD_req_ready_T_14, UInt<1>(0h0)) node _sinkD_req_ready_T_16 = bits(sinkD_req.bankSum, 4, 4) node _sinkD_req_ready_T_17 = and(_sinkD_req_ready_T_16, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_18 = orr(_sinkD_req_ready_T_17) node _sinkD_req_ready_T_19 = eq(_sinkD_req_ready_T_18, UInt<1>(0h0)) node _sinkD_req_ready_T_20 = bits(sinkD_req.bankSum, 5, 5) node _sinkD_req_ready_T_21 = and(_sinkD_req_ready_T_20, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_22 = orr(_sinkD_req_ready_T_21) node _sinkD_req_ready_T_23 = eq(_sinkD_req_ready_T_22, UInt<1>(0h0)) node _sinkD_req_ready_T_24 = bits(sinkD_req.bankSum, 6, 6) node _sinkD_req_ready_T_25 = and(_sinkD_req_ready_T_24, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_26 = orr(_sinkD_req_ready_T_25) node _sinkD_req_ready_T_27 = eq(_sinkD_req_ready_T_26, UInt<1>(0h0)) node _sinkD_req_ready_T_28 = bits(sinkD_req.bankSum, 7, 7) node _sinkD_req_ready_T_29 = and(_sinkD_req_ready_T_28, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_30 = orr(_sinkD_req_ready_T_29) node _sinkD_req_ready_T_31 = eq(_sinkD_req_ready_T_30, UInt<1>(0h0)) node sinkD_req_ready_lo_lo = cat(_sinkD_req_ready_T_7, _sinkD_req_ready_T_3) node sinkD_req_ready_lo_hi = cat(_sinkD_req_ready_T_15, _sinkD_req_ready_T_11) node sinkD_req_ready_lo = cat(sinkD_req_ready_lo_hi, sinkD_req_ready_lo_lo) node sinkD_req_ready_hi_lo = cat(_sinkD_req_ready_T_23, _sinkD_req_ready_T_19) node sinkD_req_ready_hi_hi = cat(_sinkD_req_ready_T_31, _sinkD_req_ready_T_27) node sinkD_req_ready_hi = cat(sinkD_req_ready_hi_hi, sinkD_req_ready_hi_lo) node sinkD_req_ready = cat(sinkD_req_ready_hi, sinkD_req_ready_lo) node _sinkD_req_io_sinkD_adr_ready_T = bits(sinkD_req_a, 2, 0) node _sinkD_req_io_sinkD_adr_ready_T_1 = dshr(sinkD_req_ready, _sinkD_req_io_sinkD_adr_ready_T) node _sinkD_req_io_sinkD_adr_ready_T_2 = bits(_sinkD_req_io_sinkD_adr_ready_T_1, 0, 0) connect io.sinkD_adr.ready, _sinkD_req_io_sinkD_adr_ready_T_2 connect sinkD_req.wen, UInt<1>(0h1) node _sinkD_req_out_index_T = shr(sinkD_req_a, 3) connect sinkD_req.index, _sinkD_req_out_index_T node _sinkD_req_out_bankSel_T = bits(sinkD_req_select, 0, 0) node _sinkD_req_out_bankSel_T_1 = bits(sinkD_req_select, 1, 1) node _sinkD_req_out_bankSel_T_2 = bits(sinkD_req_select, 2, 2) node _sinkD_req_out_bankSel_T_3 = bits(sinkD_req_select, 3, 3) node _sinkD_req_out_bankSel_T_4 = bits(sinkD_req_select, 4, 4) node _sinkD_req_out_bankSel_T_5 = bits(sinkD_req_select, 5, 5) node _sinkD_req_out_bankSel_T_6 = bits(sinkD_req_select, 6, 6) node _sinkD_req_out_bankSel_T_7 = bits(sinkD_req_select, 7, 7) node sinkD_req_out_bankSel_lo_lo = cat(_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T) node sinkD_req_out_bankSel_lo_hi = cat(_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2) node sinkD_req_out_bankSel_lo = cat(sinkD_req_out_bankSel_lo_hi, sinkD_req_out_bankSel_lo_lo) node sinkD_req_out_bankSel_hi_lo = cat(_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4) node sinkD_req_out_bankSel_hi_hi = cat(_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6) node sinkD_req_out_bankSel_hi = cat(sinkD_req_out_bankSel_hi_hi, sinkD_req_out_bankSel_hi_lo) node _sinkD_req_out_bankSel_T_8 = cat(sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo) node _sinkD_req_out_bankSel_T_9 = bits(io.sinkD_adr.bits.mask, 0, 0) node _sinkD_req_out_bankSel_T_10 = mux(_sinkD_req_out_bankSel_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sinkD_req_out_bankSel_T_11 = and(_sinkD_req_out_bankSel_T_8, _sinkD_req_out_bankSel_T_10) node _sinkD_req_out_bankSel_T_12 = mux(io.sinkD_adr.valid, _sinkD_req_out_bankSel_T_11, UInt<1>(0h0)) connect sinkD_req.bankSel, _sinkD_req_out_bankSel_T_12 node _sinkD_req_out_bankEn_T = bits(sinkD_req_ready, 0, 0) node _sinkD_req_out_bankEn_T_1 = bits(sinkD_req_ready, 1, 1) node _sinkD_req_out_bankEn_T_2 = bits(sinkD_req_ready, 2, 2) node _sinkD_req_out_bankEn_T_3 = bits(sinkD_req_ready, 3, 3) node _sinkD_req_out_bankEn_T_4 = bits(sinkD_req_ready, 4, 4) node _sinkD_req_out_bankEn_T_5 = bits(sinkD_req_ready, 5, 5) node _sinkD_req_out_bankEn_T_6 = bits(sinkD_req_ready, 6, 6) node _sinkD_req_out_bankEn_T_7 = bits(sinkD_req_ready, 7, 7) node sinkD_req_out_bankEn_lo_lo = cat(_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T) node sinkD_req_out_bankEn_lo_hi = cat(_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2) node sinkD_req_out_bankEn_lo = cat(sinkD_req_out_bankEn_lo_hi, sinkD_req_out_bankEn_lo_lo) node sinkD_req_out_bankEn_hi_lo = cat(_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4) node sinkD_req_out_bankEn_hi_hi = cat(_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6) node sinkD_req_out_bankEn_hi = cat(sinkD_req_out_bankEn_hi_hi, sinkD_req_out_bankEn_hi_lo) node _sinkD_req_out_bankEn_T_8 = cat(sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo) node _sinkD_req_out_bankEn_T_9 = and(sinkD_req.bankSel, _sinkD_req_out_bankEn_T_8) node _sinkD_req_out_bankEn_T_10 = mux(io.sinkD_adr.bits.noop, UInt<1>(0h0), _sinkD_req_out_bankEn_T_9) connect sinkD_req.bankEn, _sinkD_req_out_bankEn_T_10 connect sinkD_req.data[0], sinkD_req_words_0 connect sinkD_req.data[1], sinkD_req_words_0 connect sinkD_req.data[2], sinkD_req_words_0 connect sinkD_req.data[3], sinkD_req_words_0 connect sinkD_req.data[4], sinkD_req_words_0 connect sinkD_req.data[5], sinkD_req_words_0 connect sinkD_req.data[6], sinkD_req_words_0 connect sinkD_req.data[7], sinkD_req_words_0 node sourceC_req_a_hi = cat(io.sourceC_adr.bits.way, io.sourceC_adr.bits.set) node sourceC_req_a = cat(sourceC_req_a_hi, io.sourceC_adr.bits.beat) wire sourceC_req : { wen : UInt<1>, index : UInt<15>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceC_req_select_T = bits(sourceC_req_a, 2, 0) node sourceC_req_select_shiftAmount = bits(_sourceC_req_select_T, 2, 0) node _sourceC_req_select_T_1 = dshl(UInt<1>(0h1), sourceC_req_select_shiftAmount) node sourceC_req_select = bits(_sourceC_req_select_T_1, 7, 0) node _sourceC_req_ready_T = bits(sourceC_req.bankSum, 0, 0) node _sourceC_req_ready_T_1 = and(_sourceC_req_ready_T, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_2 = orr(_sourceC_req_ready_T_1) node _sourceC_req_ready_T_3 = eq(_sourceC_req_ready_T_2, UInt<1>(0h0)) node _sourceC_req_ready_T_4 = bits(sourceC_req.bankSum, 1, 1) node _sourceC_req_ready_T_5 = and(_sourceC_req_ready_T_4, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_6 = orr(_sourceC_req_ready_T_5) node _sourceC_req_ready_T_7 = eq(_sourceC_req_ready_T_6, UInt<1>(0h0)) node _sourceC_req_ready_T_8 = bits(sourceC_req.bankSum, 2, 2) node _sourceC_req_ready_T_9 = and(_sourceC_req_ready_T_8, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_10 = orr(_sourceC_req_ready_T_9) node _sourceC_req_ready_T_11 = eq(_sourceC_req_ready_T_10, UInt<1>(0h0)) node _sourceC_req_ready_T_12 = bits(sourceC_req.bankSum, 3, 3) node _sourceC_req_ready_T_13 = and(_sourceC_req_ready_T_12, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_14 = orr(_sourceC_req_ready_T_13) node _sourceC_req_ready_T_15 = eq(_sourceC_req_ready_T_14, UInt<1>(0h0)) node _sourceC_req_ready_T_16 = bits(sourceC_req.bankSum, 4, 4) node _sourceC_req_ready_T_17 = and(_sourceC_req_ready_T_16, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_18 = orr(_sourceC_req_ready_T_17) node _sourceC_req_ready_T_19 = eq(_sourceC_req_ready_T_18, UInt<1>(0h0)) node _sourceC_req_ready_T_20 = bits(sourceC_req.bankSum, 5, 5) node _sourceC_req_ready_T_21 = and(_sourceC_req_ready_T_20, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_22 = orr(_sourceC_req_ready_T_21) node _sourceC_req_ready_T_23 = eq(_sourceC_req_ready_T_22, UInt<1>(0h0)) node _sourceC_req_ready_T_24 = bits(sourceC_req.bankSum, 6, 6) node _sourceC_req_ready_T_25 = and(_sourceC_req_ready_T_24, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_26 = orr(_sourceC_req_ready_T_25) node _sourceC_req_ready_T_27 = eq(_sourceC_req_ready_T_26, UInt<1>(0h0)) node _sourceC_req_ready_T_28 = bits(sourceC_req.bankSum, 7, 7) node _sourceC_req_ready_T_29 = and(_sourceC_req_ready_T_28, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_30 = orr(_sourceC_req_ready_T_29) node _sourceC_req_ready_T_31 = eq(_sourceC_req_ready_T_30, UInt<1>(0h0)) node sourceC_req_ready_lo_lo = cat(_sourceC_req_ready_T_7, _sourceC_req_ready_T_3) node sourceC_req_ready_lo_hi = cat(_sourceC_req_ready_T_15, _sourceC_req_ready_T_11) node sourceC_req_ready_lo = cat(sourceC_req_ready_lo_hi, sourceC_req_ready_lo_lo) node sourceC_req_ready_hi_lo = cat(_sourceC_req_ready_T_23, _sourceC_req_ready_T_19) node sourceC_req_ready_hi_hi = cat(_sourceC_req_ready_T_31, _sourceC_req_ready_T_27) node sourceC_req_ready_hi = cat(sourceC_req_ready_hi_hi, sourceC_req_ready_hi_lo) node sourceC_req_ready = cat(sourceC_req_ready_hi, sourceC_req_ready_lo) node _sourceC_req_io_sourceC_adr_ready_T = bits(sourceC_req_a, 2, 0) node _sourceC_req_io_sourceC_adr_ready_T_1 = dshr(sourceC_req_ready, _sourceC_req_io_sourceC_adr_ready_T) node _sourceC_req_io_sourceC_adr_ready_T_2 = bits(_sourceC_req_io_sourceC_adr_ready_T_1, 0, 0) connect io.sourceC_adr.ready, _sourceC_req_io_sourceC_adr_ready_T_2 connect sourceC_req.wen, UInt<1>(0h0) node _sourceC_req_out_index_T = shr(sourceC_req_a, 3) connect sourceC_req.index, _sourceC_req_out_index_T node _sourceC_req_out_bankSel_T = bits(sourceC_req_select, 0, 0) node _sourceC_req_out_bankSel_T_1 = bits(sourceC_req_select, 1, 1) node _sourceC_req_out_bankSel_T_2 = bits(sourceC_req_select, 2, 2) node _sourceC_req_out_bankSel_T_3 = bits(sourceC_req_select, 3, 3) node _sourceC_req_out_bankSel_T_4 = bits(sourceC_req_select, 4, 4) node _sourceC_req_out_bankSel_T_5 = bits(sourceC_req_select, 5, 5) node _sourceC_req_out_bankSel_T_6 = bits(sourceC_req_select, 6, 6) node _sourceC_req_out_bankSel_T_7 = bits(sourceC_req_select, 7, 7) node sourceC_req_out_bankSel_lo_lo = cat(_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T) node sourceC_req_out_bankSel_lo_hi = cat(_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2) node sourceC_req_out_bankSel_lo = cat(sourceC_req_out_bankSel_lo_hi, sourceC_req_out_bankSel_lo_lo) node sourceC_req_out_bankSel_hi_lo = cat(_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4) node sourceC_req_out_bankSel_hi_hi = cat(_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6) node sourceC_req_out_bankSel_hi = cat(sourceC_req_out_bankSel_hi_hi, sourceC_req_out_bankSel_hi_lo) node _sourceC_req_out_bankSel_T_8 = cat(sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo) node _sourceC_req_out_bankSel_T_9 = bits(io.sourceC_adr.bits.mask, 0, 0) node _sourceC_req_out_bankSel_T_10 = mux(_sourceC_req_out_bankSel_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sourceC_req_out_bankSel_T_11 = and(_sourceC_req_out_bankSel_T_8, _sourceC_req_out_bankSel_T_10) node _sourceC_req_out_bankSel_T_12 = mux(io.sourceC_adr.valid, _sourceC_req_out_bankSel_T_11, UInt<1>(0h0)) connect sourceC_req.bankSel, _sourceC_req_out_bankSel_T_12 node _sourceC_req_out_bankEn_T = bits(sourceC_req_ready, 0, 0) node _sourceC_req_out_bankEn_T_1 = bits(sourceC_req_ready, 1, 1) node _sourceC_req_out_bankEn_T_2 = bits(sourceC_req_ready, 2, 2) node _sourceC_req_out_bankEn_T_3 = bits(sourceC_req_ready, 3, 3) node _sourceC_req_out_bankEn_T_4 = bits(sourceC_req_ready, 4, 4) node _sourceC_req_out_bankEn_T_5 = bits(sourceC_req_ready, 5, 5) node _sourceC_req_out_bankEn_T_6 = bits(sourceC_req_ready, 6, 6) node _sourceC_req_out_bankEn_T_7 = bits(sourceC_req_ready, 7, 7) node sourceC_req_out_bankEn_lo_lo = cat(_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T) node sourceC_req_out_bankEn_lo_hi = cat(_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2) node sourceC_req_out_bankEn_lo = cat(sourceC_req_out_bankEn_lo_hi, sourceC_req_out_bankEn_lo_lo) node sourceC_req_out_bankEn_hi_lo = cat(_sourceC_req_out_bankEn_T_5, _sourceC_req_out_bankEn_T_4) node sourceC_req_out_bankEn_hi_hi = cat(_sourceC_req_out_bankEn_T_7, _sourceC_req_out_bankEn_T_6) node sourceC_req_out_bankEn_hi = cat(sourceC_req_out_bankEn_hi_hi, sourceC_req_out_bankEn_hi_lo) node _sourceC_req_out_bankEn_T_8 = cat(sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo) node _sourceC_req_out_bankEn_T_9 = and(sourceC_req.bankSel, _sourceC_req_out_bankEn_T_8) node _sourceC_req_out_bankEn_T_10 = mux(io.sourceC_adr.bits.noop, UInt<1>(0h0), _sourceC_req_out_bankEn_T_9) connect sourceC_req.bankEn, _sourceC_req_out_bankEn_T_10 connect sourceC_req.data[0], UInt<64>(0h0) connect sourceC_req.data[1], UInt<64>(0h0) connect sourceC_req.data[2], UInt<64>(0h0) connect sourceC_req.data[3], UInt<64>(0h0) connect sourceC_req.data[4], UInt<64>(0h0) connect sourceC_req.data[5], UInt<64>(0h0) connect sourceC_req.data[6], UInt<64>(0h0) connect sourceC_req.data[7], UInt<64>(0h0) node sourceD_rreq_a_hi = cat(io.sourceD_radr.bits.way, io.sourceD_radr.bits.set) node sourceD_rreq_a = cat(sourceD_rreq_a_hi, io.sourceD_radr.bits.beat) wire sourceD_rreq : { wen : UInt<1>, index : UInt<15>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceD_rreq_select_T = bits(sourceD_rreq_a, 1, 0) node sourceD_rreq_select_shiftAmount = bits(_sourceD_rreq_select_T, 1, 0) node _sourceD_rreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_rreq_select_shiftAmount) node sourceD_rreq_select = bits(_sourceD_rreq_select_T_1, 3, 0) node _sourceD_rreq_ready_T = bits(sourceD_rreq.bankSum, 1, 0) node _sourceD_rreq_ready_T_1 = and(_sourceD_rreq_ready_T, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_2 = orr(_sourceD_rreq_ready_T_1) node _sourceD_rreq_ready_T_3 = eq(_sourceD_rreq_ready_T_2, UInt<1>(0h0)) node _sourceD_rreq_ready_T_4 = bits(sourceD_rreq.bankSum, 3, 2) node _sourceD_rreq_ready_T_5 = and(_sourceD_rreq_ready_T_4, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_6 = orr(_sourceD_rreq_ready_T_5) node _sourceD_rreq_ready_T_7 = eq(_sourceD_rreq_ready_T_6, UInt<1>(0h0)) node _sourceD_rreq_ready_T_8 = bits(sourceD_rreq.bankSum, 5, 4) node _sourceD_rreq_ready_T_9 = and(_sourceD_rreq_ready_T_8, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_10 = orr(_sourceD_rreq_ready_T_9) node _sourceD_rreq_ready_T_11 = eq(_sourceD_rreq_ready_T_10, UInt<1>(0h0)) node _sourceD_rreq_ready_T_12 = bits(sourceD_rreq.bankSum, 7, 6) node _sourceD_rreq_ready_T_13 = and(_sourceD_rreq_ready_T_12, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_14 = orr(_sourceD_rreq_ready_T_13) node _sourceD_rreq_ready_T_15 = eq(_sourceD_rreq_ready_T_14, UInt<1>(0h0)) node sourceD_rreq_ready_lo = cat(_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3) node sourceD_rreq_ready_hi = cat(_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11) node sourceD_rreq_ready = cat(sourceD_rreq_ready_hi, sourceD_rreq_ready_lo) node _sourceD_rreq_io_sourceD_radr_ready_T = bits(sourceD_rreq_a, 1, 0) node _sourceD_rreq_io_sourceD_radr_ready_T_1 = dshr(sourceD_rreq_ready, _sourceD_rreq_io_sourceD_radr_ready_T) node _sourceD_rreq_io_sourceD_radr_ready_T_2 = bits(_sourceD_rreq_io_sourceD_radr_ready_T_1, 0, 0) connect io.sourceD_radr.ready, _sourceD_rreq_io_sourceD_radr_ready_T_2 connect sourceD_rreq.wen, UInt<1>(0h0) node _sourceD_rreq_out_index_T = shr(sourceD_rreq_a, 2) connect sourceD_rreq.index, _sourceD_rreq_out_index_T node _sourceD_rreq_out_bankSel_T = bits(sourceD_rreq_select, 0, 0) node _sourceD_rreq_out_bankSel_T_1 = bits(sourceD_rreq_select, 1, 1) node _sourceD_rreq_out_bankSel_T_2 = bits(sourceD_rreq_select, 2, 2) node _sourceD_rreq_out_bankSel_T_3 = bits(sourceD_rreq_select, 3, 3) node _sourceD_rreq_out_bankSel_T_4 = mux(_sourceD_rreq_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_5 = mux(_sourceD_rreq_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_6 = mux(_sourceD_rreq_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_7 = mux(_sourceD_rreq_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_rreq_out_bankSel_lo = cat(_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4) node sourceD_rreq_out_bankSel_hi = cat(_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6) node _sourceD_rreq_out_bankSel_T_8 = cat(sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo) node _sourceD_rreq_out_bankSel_T_9 = cat(io.sourceD_radr.bits.mask, io.sourceD_radr.bits.mask) node _sourceD_rreq_out_bankSel_T_10 = cat(_sourceD_rreq_out_bankSel_T_9, _sourceD_rreq_out_bankSel_T_9) node _sourceD_rreq_out_bankSel_T_11 = and(_sourceD_rreq_out_bankSel_T_8, _sourceD_rreq_out_bankSel_T_10) node _sourceD_rreq_out_bankSel_T_12 = mux(io.sourceD_radr.valid, _sourceD_rreq_out_bankSel_T_11, UInt<1>(0h0)) connect sourceD_rreq.bankSel, _sourceD_rreq_out_bankSel_T_12 node _sourceD_rreq_out_bankEn_T = bits(sourceD_rreq_ready, 0, 0) node _sourceD_rreq_out_bankEn_T_1 = bits(sourceD_rreq_ready, 1, 1) node _sourceD_rreq_out_bankEn_T_2 = bits(sourceD_rreq_ready, 2, 2) node _sourceD_rreq_out_bankEn_T_3 = bits(sourceD_rreq_ready, 3, 3) node _sourceD_rreq_out_bankEn_T_4 = mux(_sourceD_rreq_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_5 = mux(_sourceD_rreq_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_6 = mux(_sourceD_rreq_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_7 = mux(_sourceD_rreq_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_rreq_out_bankEn_lo = cat(_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4) node sourceD_rreq_out_bankEn_hi = cat(_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6) node _sourceD_rreq_out_bankEn_T_8 = cat(sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo) node _sourceD_rreq_out_bankEn_T_9 = and(sourceD_rreq.bankSel, _sourceD_rreq_out_bankEn_T_8) node _sourceD_rreq_out_bankEn_T_10 = mux(io.sourceD_radr.bits.noop, UInt<1>(0h0), _sourceD_rreq_out_bankEn_T_9) connect sourceD_rreq.bankEn, _sourceD_rreq_out_bankEn_T_10 connect sourceD_rreq.data[0], UInt<64>(0h0) connect sourceD_rreq.data[1], UInt<64>(0h0) connect sourceD_rreq.data[2], UInt<64>(0h0) connect sourceD_rreq.data[3], UInt<64>(0h0) connect sourceD_rreq.data[4], UInt<64>(0h0) connect sourceD_rreq.data[5], UInt<64>(0h0) connect sourceD_rreq.data[6], UInt<64>(0h0) connect sourceD_rreq.data[7], UInt<64>(0h0) node sourceD_wreq_words_0 = bits(io.sourceD_wdat.data, 63, 0) node sourceD_wreq_words_1 = bits(io.sourceD_wdat.data, 127, 64) node sourceD_wreq_a_hi = cat(io.sourceD_wadr.bits.way, io.sourceD_wadr.bits.set) node sourceD_wreq_a = cat(sourceD_wreq_a_hi, io.sourceD_wadr.bits.beat) wire sourceD_wreq : { wen : UInt<1>, index : UInt<15>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceD_wreq_select_T = bits(sourceD_wreq_a, 1, 0) node sourceD_wreq_select_shiftAmount = bits(_sourceD_wreq_select_T, 1, 0) node _sourceD_wreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_wreq_select_shiftAmount) node sourceD_wreq_select = bits(_sourceD_wreq_select_T_1, 3, 0) node _sourceD_wreq_ready_T = bits(sourceD_wreq.bankSum, 1, 0) node _sourceD_wreq_ready_T_1 = and(_sourceD_wreq_ready_T, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_2 = orr(_sourceD_wreq_ready_T_1) node _sourceD_wreq_ready_T_3 = eq(_sourceD_wreq_ready_T_2, UInt<1>(0h0)) node _sourceD_wreq_ready_T_4 = bits(sourceD_wreq.bankSum, 3, 2) node _sourceD_wreq_ready_T_5 = and(_sourceD_wreq_ready_T_4, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_6 = orr(_sourceD_wreq_ready_T_5) node _sourceD_wreq_ready_T_7 = eq(_sourceD_wreq_ready_T_6, UInt<1>(0h0)) node _sourceD_wreq_ready_T_8 = bits(sourceD_wreq.bankSum, 5, 4) node _sourceD_wreq_ready_T_9 = and(_sourceD_wreq_ready_T_8, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_10 = orr(_sourceD_wreq_ready_T_9) node _sourceD_wreq_ready_T_11 = eq(_sourceD_wreq_ready_T_10, UInt<1>(0h0)) node _sourceD_wreq_ready_T_12 = bits(sourceD_wreq.bankSum, 7, 6) node _sourceD_wreq_ready_T_13 = and(_sourceD_wreq_ready_T_12, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_14 = orr(_sourceD_wreq_ready_T_13) node _sourceD_wreq_ready_T_15 = eq(_sourceD_wreq_ready_T_14, UInt<1>(0h0)) node sourceD_wreq_ready_lo = cat(_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3) node sourceD_wreq_ready_hi = cat(_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11) node sourceD_wreq_ready = cat(sourceD_wreq_ready_hi, sourceD_wreq_ready_lo) node _sourceD_wreq_io_sourceD_wadr_ready_T = bits(sourceD_wreq_a, 1, 0) node _sourceD_wreq_io_sourceD_wadr_ready_T_1 = dshr(sourceD_wreq_ready, _sourceD_wreq_io_sourceD_wadr_ready_T) node _sourceD_wreq_io_sourceD_wadr_ready_T_2 = bits(_sourceD_wreq_io_sourceD_wadr_ready_T_1, 0, 0) connect io.sourceD_wadr.ready, _sourceD_wreq_io_sourceD_wadr_ready_T_2 connect sourceD_wreq.wen, UInt<1>(0h1) node _sourceD_wreq_out_index_T = shr(sourceD_wreq_a, 2) connect sourceD_wreq.index, _sourceD_wreq_out_index_T node _sourceD_wreq_out_bankSel_T = bits(sourceD_wreq_select, 0, 0) node _sourceD_wreq_out_bankSel_T_1 = bits(sourceD_wreq_select, 1, 1) node _sourceD_wreq_out_bankSel_T_2 = bits(sourceD_wreq_select, 2, 2) node _sourceD_wreq_out_bankSel_T_3 = bits(sourceD_wreq_select, 3, 3) node _sourceD_wreq_out_bankSel_T_4 = mux(_sourceD_wreq_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_5 = mux(_sourceD_wreq_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_6 = mux(_sourceD_wreq_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_7 = mux(_sourceD_wreq_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_wreq_out_bankSel_lo = cat(_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4) node sourceD_wreq_out_bankSel_hi = cat(_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6) node _sourceD_wreq_out_bankSel_T_8 = cat(sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo) node _sourceD_wreq_out_bankSel_T_9 = cat(io.sourceD_wadr.bits.mask, io.sourceD_wadr.bits.mask) node _sourceD_wreq_out_bankSel_T_10 = cat(_sourceD_wreq_out_bankSel_T_9, _sourceD_wreq_out_bankSel_T_9) node _sourceD_wreq_out_bankSel_T_11 = and(_sourceD_wreq_out_bankSel_T_8, _sourceD_wreq_out_bankSel_T_10) node _sourceD_wreq_out_bankSel_T_12 = mux(io.sourceD_wadr.valid, _sourceD_wreq_out_bankSel_T_11, UInt<1>(0h0)) connect sourceD_wreq.bankSel, _sourceD_wreq_out_bankSel_T_12 node _sourceD_wreq_out_bankEn_T = bits(sourceD_wreq_ready, 0, 0) node _sourceD_wreq_out_bankEn_T_1 = bits(sourceD_wreq_ready, 1, 1) node _sourceD_wreq_out_bankEn_T_2 = bits(sourceD_wreq_ready, 2, 2) node _sourceD_wreq_out_bankEn_T_3 = bits(sourceD_wreq_ready, 3, 3) node _sourceD_wreq_out_bankEn_T_4 = mux(_sourceD_wreq_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_5 = mux(_sourceD_wreq_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_6 = mux(_sourceD_wreq_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_7 = mux(_sourceD_wreq_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_wreq_out_bankEn_lo = cat(_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4) node sourceD_wreq_out_bankEn_hi = cat(_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6) node _sourceD_wreq_out_bankEn_T_8 = cat(sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo) node _sourceD_wreq_out_bankEn_T_9 = and(sourceD_wreq.bankSel, _sourceD_wreq_out_bankEn_T_8) node _sourceD_wreq_out_bankEn_T_10 = mux(io.sourceD_wadr.bits.noop, UInt<1>(0h0), _sourceD_wreq_out_bankEn_T_9) connect sourceD_wreq.bankEn, _sourceD_wreq_out_bankEn_T_10 connect sourceD_wreq.data[0], sourceD_wreq_words_0 connect sourceD_wreq.data[1], sourceD_wreq_words_1 connect sourceD_wreq.data[2], sourceD_wreq_words_0 connect sourceD_wreq.data[3], sourceD_wreq_words_1 connect sourceD_wreq.data[4], sourceD_wreq_words_0 connect sourceD_wreq.data[5], sourceD_wreq_words_1 connect sourceD_wreq.data[6], sourceD_wreq_words_0 connect sourceD_wreq.data[7], sourceD_wreq_words_1 connect sinkC_req.bankSum, UInt<1>(0h0) node _T = or(sinkC_req.bankSel, UInt<1>(0h0)) connect sourceC_req.bankSum, _T node _T_1 = or(sourceC_req.bankSel, _T) connect sinkD_req.bankSum, _T_1 node _T_2 = or(sinkD_req.bankSel, _T_1) connect sourceD_wreq.bankSum, _T_2 node _T_3 = or(sourceD_wreq.bankSel, _T_2) connect sourceD_rreq.bankSum, _T_3 node _T_4 = or(sourceD_rreq.bankSel, _T_3) node _regout_en_T = bits(sinkC_req.bankEn, 0, 0) node _regout_en_T_1 = bits(sourceC_req.bankEn, 0, 0) node _regout_en_T_2 = bits(sinkD_req.bankEn, 0, 0) node _regout_en_T_3 = bits(sourceD_wreq.bankEn, 0, 0) node _regout_en_T_4 = bits(sourceD_rreq.bankEn, 0, 0) node _regout_en_T_5 = or(_regout_en_T, _regout_en_T_1) node _regout_en_T_6 = or(_regout_en_T_5, _regout_en_T_2) node _regout_en_T_7 = or(_regout_en_T_6, _regout_en_T_3) node regout_en = or(_regout_en_T_7, _regout_en_T_4) node regout_sel_0 = bits(sinkC_req.bankSel, 0, 0) node regout_sel_1 = bits(sourceC_req.bankSel, 0, 0) node regout_sel_2 = bits(sinkD_req.bankSel, 0, 0) node regout_sel_3 = bits(sourceD_wreq.bankSel, 0, 0) node regout_sel_4 = bits(sourceD_rreq.bankSel, 0, 0) node _regout_wen_T = mux(regout_sel_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_1 = mux(regout_sel_2, sinkD_req.wen, _regout_wen_T) node _regout_wen_T_2 = mux(regout_sel_1, sourceC_req.wen, _regout_wen_T_1) node regout_wen = mux(regout_sel_0, sinkC_req.wen, _regout_wen_T_2) node _regout_idx_T = mux(regout_sel_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_1 = mux(regout_sel_2, sinkD_req.index, _regout_idx_T) node _regout_idx_T_2 = mux(regout_sel_1, sourceC_req.index, _regout_idx_T_1) node regout_idx = mux(regout_sel_0, sinkC_req.index, _regout_idx_T_2) node _regout_data_T = mux(regout_sel_3, sourceD_wreq.data[0], sourceD_rreq.data[0]) node _regout_data_T_1 = mux(regout_sel_2, sinkD_req.data[0], _regout_data_T) node _regout_data_T_2 = mux(regout_sel_1, sourceC_req.data[0], _regout_data_T_1) node regout_data = mux(regout_sel_0, sinkC_req.data[0], _regout_data_T_2) node _regout_T = and(regout_wen, regout_en) when _regout_T : write mport regout_MPORT = cc_banks_0[regout_idx], clock connect regout_MPORT, regout_data node _regout_T_1 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_2 = and(_regout_T_1, regout_en) wire _regout_WIRE : UInt<15> invalidate _regout_WIRE when _regout_T_2 : connect _regout_WIRE, regout_idx read mport regout_MPORT_1 = cc_banks_0[_regout_WIRE], clock node _regout_T_3 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_4 = and(_regout_T_3, regout_en) reg regout_REG : UInt<1>, clock connect regout_REG, _regout_T_4 reg regout_r : UInt<64>, clock when regout_REG : connect regout_r, regout_MPORT_1 node _regout_en_T_8 = bits(sinkC_req.bankEn, 1, 1) node _regout_en_T_9 = bits(sourceC_req.bankEn, 1, 1) node _regout_en_T_10 = bits(sinkD_req.bankEn, 1, 1) node _regout_en_T_11 = bits(sourceD_wreq.bankEn, 1, 1) node _regout_en_T_12 = bits(sourceD_rreq.bankEn, 1, 1) node _regout_en_T_13 = or(_regout_en_T_8, _regout_en_T_9) node _regout_en_T_14 = or(_regout_en_T_13, _regout_en_T_10) node _regout_en_T_15 = or(_regout_en_T_14, _regout_en_T_11) node regout_en_1 = or(_regout_en_T_15, _regout_en_T_12) node regout_sel_0_1 = bits(sinkC_req.bankSel, 1, 1) node regout_sel_1_1 = bits(sourceC_req.bankSel, 1, 1) node regout_sel_2_1 = bits(sinkD_req.bankSel, 1, 1) node regout_sel_3_1 = bits(sourceD_wreq.bankSel, 1, 1) node regout_sel_4_1 = bits(sourceD_rreq.bankSel, 1, 1) node _regout_wen_T_3 = mux(regout_sel_3_1, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_4 = mux(regout_sel_2_1, sinkD_req.wen, _regout_wen_T_3) node _regout_wen_T_5 = mux(regout_sel_1_1, sourceC_req.wen, _regout_wen_T_4) node regout_wen_1 = mux(regout_sel_0_1, sinkC_req.wen, _regout_wen_T_5) node _regout_idx_T_3 = mux(regout_sel_3_1, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_4 = mux(regout_sel_2_1, sinkD_req.index, _regout_idx_T_3) node _regout_idx_T_5 = mux(regout_sel_1_1, sourceC_req.index, _regout_idx_T_4) node regout_idx_1 = mux(regout_sel_0_1, sinkC_req.index, _regout_idx_T_5) node _regout_data_T_3 = mux(regout_sel_3_1, sourceD_wreq.data[1], sourceD_rreq.data[1]) node _regout_data_T_4 = mux(regout_sel_2_1, sinkD_req.data[1], _regout_data_T_3) node _regout_data_T_5 = mux(regout_sel_1_1, sourceC_req.data[1], _regout_data_T_4) node regout_data_1 = mux(regout_sel_0_1, sinkC_req.data[1], _regout_data_T_5) node _regout_T_5 = and(regout_wen_1, regout_en_1) when _regout_T_5 : write mport regout_MPORT_2 = cc_banks_1[regout_idx_1], clock connect regout_MPORT_2, regout_data_1 node _regout_T_6 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_7 = and(_regout_T_6, regout_en_1) wire _regout_WIRE_1 : UInt<15> invalidate _regout_WIRE_1 when _regout_T_7 : connect _regout_WIRE_1, regout_idx_1 read mport regout_MPORT_3 = cc_banks_1[_regout_WIRE_1], clock node _regout_T_8 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_9 = and(_regout_T_8, regout_en_1) reg regout_REG_1 : UInt<1>, clock connect regout_REG_1, _regout_T_9 reg regout_r_1 : UInt<64>, clock when regout_REG_1 : connect regout_r_1, regout_MPORT_3 node _regout_en_T_16 = bits(sinkC_req.bankEn, 2, 2) node _regout_en_T_17 = bits(sourceC_req.bankEn, 2, 2) node _regout_en_T_18 = bits(sinkD_req.bankEn, 2, 2) node _regout_en_T_19 = bits(sourceD_wreq.bankEn, 2, 2) node _regout_en_T_20 = bits(sourceD_rreq.bankEn, 2, 2) node _regout_en_T_21 = or(_regout_en_T_16, _regout_en_T_17) node _regout_en_T_22 = or(_regout_en_T_21, _regout_en_T_18) node _regout_en_T_23 = or(_regout_en_T_22, _regout_en_T_19) node regout_en_2 = or(_regout_en_T_23, _regout_en_T_20) node regout_sel_0_2 = bits(sinkC_req.bankSel, 2, 2) node regout_sel_1_2 = bits(sourceC_req.bankSel, 2, 2) node regout_sel_2_2 = bits(sinkD_req.bankSel, 2, 2) node regout_sel_3_2 = bits(sourceD_wreq.bankSel, 2, 2) node regout_sel_4_2 = bits(sourceD_rreq.bankSel, 2, 2) node _regout_wen_T_6 = mux(regout_sel_3_2, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_7 = mux(regout_sel_2_2, sinkD_req.wen, _regout_wen_T_6) node _regout_wen_T_8 = mux(regout_sel_1_2, sourceC_req.wen, _regout_wen_T_7) node regout_wen_2 = mux(regout_sel_0_2, sinkC_req.wen, _regout_wen_T_8) node _regout_idx_T_6 = mux(regout_sel_3_2, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_7 = mux(regout_sel_2_2, sinkD_req.index, _regout_idx_T_6) node _regout_idx_T_8 = mux(regout_sel_1_2, sourceC_req.index, _regout_idx_T_7) node regout_idx_2 = mux(regout_sel_0_2, sinkC_req.index, _regout_idx_T_8) node _regout_data_T_6 = mux(regout_sel_3_2, sourceD_wreq.data[2], sourceD_rreq.data[2]) node _regout_data_T_7 = mux(regout_sel_2_2, sinkD_req.data[2], _regout_data_T_6) node _regout_data_T_8 = mux(regout_sel_1_2, sourceC_req.data[2], _regout_data_T_7) node regout_data_2 = mux(regout_sel_0_2, sinkC_req.data[2], _regout_data_T_8) node _regout_T_10 = and(regout_wen_2, regout_en_2) when _regout_T_10 : write mport regout_MPORT_4 = cc_banks_2[regout_idx_2], clock connect regout_MPORT_4, regout_data_2 node _regout_T_11 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_12 = and(_regout_T_11, regout_en_2) wire _regout_WIRE_2 : UInt<15> invalidate _regout_WIRE_2 when _regout_T_12 : connect _regout_WIRE_2, regout_idx_2 read mport regout_MPORT_5 = cc_banks_2[_regout_WIRE_2], clock node _regout_T_13 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_14 = and(_regout_T_13, regout_en_2) reg regout_REG_2 : UInt<1>, clock connect regout_REG_2, _regout_T_14 reg regout_r_2 : UInt<64>, clock when regout_REG_2 : connect regout_r_2, regout_MPORT_5 node _regout_en_T_24 = bits(sinkC_req.bankEn, 3, 3) node _regout_en_T_25 = bits(sourceC_req.bankEn, 3, 3) node _regout_en_T_26 = bits(sinkD_req.bankEn, 3, 3) node _regout_en_T_27 = bits(sourceD_wreq.bankEn, 3, 3) node _regout_en_T_28 = bits(sourceD_rreq.bankEn, 3, 3) node _regout_en_T_29 = or(_regout_en_T_24, _regout_en_T_25) node _regout_en_T_30 = or(_regout_en_T_29, _regout_en_T_26) node _regout_en_T_31 = or(_regout_en_T_30, _regout_en_T_27) node regout_en_3 = or(_regout_en_T_31, _regout_en_T_28) node regout_sel_0_3 = bits(sinkC_req.bankSel, 3, 3) node regout_sel_1_3 = bits(sourceC_req.bankSel, 3, 3) node regout_sel_2_3 = bits(sinkD_req.bankSel, 3, 3) node regout_sel_3_3 = bits(sourceD_wreq.bankSel, 3, 3) node regout_sel_4_3 = bits(sourceD_rreq.bankSel, 3, 3) node _regout_wen_T_9 = mux(regout_sel_3_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_10 = mux(regout_sel_2_3, sinkD_req.wen, _regout_wen_T_9) node _regout_wen_T_11 = mux(regout_sel_1_3, sourceC_req.wen, _regout_wen_T_10) node regout_wen_3 = mux(regout_sel_0_3, sinkC_req.wen, _regout_wen_T_11) node _regout_idx_T_9 = mux(regout_sel_3_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_10 = mux(regout_sel_2_3, sinkD_req.index, _regout_idx_T_9) node _regout_idx_T_11 = mux(regout_sel_1_3, sourceC_req.index, _regout_idx_T_10) node regout_idx_3 = mux(regout_sel_0_3, sinkC_req.index, _regout_idx_T_11) node _regout_data_T_9 = mux(regout_sel_3_3, sourceD_wreq.data[3], sourceD_rreq.data[3]) node _regout_data_T_10 = mux(regout_sel_2_3, sinkD_req.data[3], _regout_data_T_9) node _regout_data_T_11 = mux(regout_sel_1_3, sourceC_req.data[3], _regout_data_T_10) node regout_data_3 = mux(regout_sel_0_3, sinkC_req.data[3], _regout_data_T_11) node _regout_T_15 = and(regout_wen_3, regout_en_3) when _regout_T_15 : write mport regout_MPORT_6 = cc_banks_3[regout_idx_3], clock connect regout_MPORT_6, regout_data_3 node _regout_T_16 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_17 = and(_regout_T_16, regout_en_3) wire _regout_WIRE_3 : UInt<15> invalidate _regout_WIRE_3 when _regout_T_17 : connect _regout_WIRE_3, regout_idx_3 read mport regout_MPORT_7 = cc_banks_3[_regout_WIRE_3], clock node _regout_T_18 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_19 = and(_regout_T_18, regout_en_3) reg regout_REG_3 : UInt<1>, clock connect regout_REG_3, _regout_T_19 reg regout_r_3 : UInt<64>, clock when regout_REG_3 : connect regout_r_3, regout_MPORT_7 node _regout_en_T_32 = bits(sinkC_req.bankEn, 4, 4) node _regout_en_T_33 = bits(sourceC_req.bankEn, 4, 4) node _regout_en_T_34 = bits(sinkD_req.bankEn, 4, 4) node _regout_en_T_35 = bits(sourceD_wreq.bankEn, 4, 4) node _regout_en_T_36 = bits(sourceD_rreq.bankEn, 4, 4) node _regout_en_T_37 = or(_regout_en_T_32, _regout_en_T_33) node _regout_en_T_38 = or(_regout_en_T_37, _regout_en_T_34) node _regout_en_T_39 = or(_regout_en_T_38, _regout_en_T_35) node regout_en_4 = or(_regout_en_T_39, _regout_en_T_36) node regout_sel_0_4 = bits(sinkC_req.bankSel, 4, 4) node regout_sel_1_4 = bits(sourceC_req.bankSel, 4, 4) node regout_sel_2_4 = bits(sinkD_req.bankSel, 4, 4) node regout_sel_3_4 = bits(sourceD_wreq.bankSel, 4, 4) node regout_sel_4_4 = bits(sourceD_rreq.bankSel, 4, 4) node _regout_wen_T_12 = mux(regout_sel_3_4, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_13 = mux(regout_sel_2_4, sinkD_req.wen, _regout_wen_T_12) node _regout_wen_T_14 = mux(regout_sel_1_4, sourceC_req.wen, _regout_wen_T_13) node regout_wen_4 = mux(regout_sel_0_4, sinkC_req.wen, _regout_wen_T_14) node _regout_idx_T_12 = mux(regout_sel_3_4, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_13 = mux(regout_sel_2_4, sinkD_req.index, _regout_idx_T_12) node _regout_idx_T_14 = mux(regout_sel_1_4, sourceC_req.index, _regout_idx_T_13) node regout_idx_4 = mux(regout_sel_0_4, sinkC_req.index, _regout_idx_T_14) node _regout_data_T_12 = mux(regout_sel_3_4, sourceD_wreq.data[4], sourceD_rreq.data[4]) node _regout_data_T_13 = mux(regout_sel_2_4, sinkD_req.data[4], _regout_data_T_12) node _regout_data_T_14 = mux(regout_sel_1_4, sourceC_req.data[4], _regout_data_T_13) node regout_data_4 = mux(regout_sel_0_4, sinkC_req.data[4], _regout_data_T_14) node _regout_T_20 = and(regout_wen_4, regout_en_4) when _regout_T_20 : write mport regout_MPORT_8 = cc_banks_4[regout_idx_4], clock connect regout_MPORT_8, regout_data_4 node _regout_T_21 = eq(regout_wen_4, UInt<1>(0h0)) node _regout_T_22 = and(_regout_T_21, regout_en_4) wire _regout_WIRE_4 : UInt<15> invalidate _regout_WIRE_4 when _regout_T_22 : connect _regout_WIRE_4, regout_idx_4 read mport regout_MPORT_9 = cc_banks_4[_regout_WIRE_4], clock node _regout_T_23 = eq(regout_wen_4, UInt<1>(0h0)) node _regout_T_24 = and(_regout_T_23, regout_en_4) reg regout_REG_4 : UInt<1>, clock connect regout_REG_4, _regout_T_24 reg regout_r_4 : UInt<64>, clock when regout_REG_4 : connect regout_r_4, regout_MPORT_9 node _regout_en_T_40 = bits(sinkC_req.bankEn, 5, 5) node _regout_en_T_41 = bits(sourceC_req.bankEn, 5, 5) node _regout_en_T_42 = bits(sinkD_req.bankEn, 5, 5) node _regout_en_T_43 = bits(sourceD_wreq.bankEn, 5, 5) node _regout_en_T_44 = bits(sourceD_rreq.bankEn, 5, 5) node _regout_en_T_45 = or(_regout_en_T_40, _regout_en_T_41) node _regout_en_T_46 = or(_regout_en_T_45, _regout_en_T_42) node _regout_en_T_47 = or(_regout_en_T_46, _regout_en_T_43) node regout_en_5 = or(_regout_en_T_47, _regout_en_T_44) node regout_sel_0_5 = bits(sinkC_req.bankSel, 5, 5) node regout_sel_1_5 = bits(sourceC_req.bankSel, 5, 5) node regout_sel_2_5 = bits(sinkD_req.bankSel, 5, 5) node regout_sel_3_5 = bits(sourceD_wreq.bankSel, 5, 5) node regout_sel_4_5 = bits(sourceD_rreq.bankSel, 5, 5) node _regout_wen_T_15 = mux(regout_sel_3_5, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_16 = mux(regout_sel_2_5, sinkD_req.wen, _regout_wen_T_15) node _regout_wen_T_17 = mux(regout_sel_1_5, sourceC_req.wen, _regout_wen_T_16) node regout_wen_5 = mux(regout_sel_0_5, sinkC_req.wen, _regout_wen_T_17) node _regout_idx_T_15 = mux(regout_sel_3_5, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_16 = mux(regout_sel_2_5, sinkD_req.index, _regout_idx_T_15) node _regout_idx_T_17 = mux(regout_sel_1_5, sourceC_req.index, _regout_idx_T_16) node regout_idx_5 = mux(regout_sel_0_5, sinkC_req.index, _regout_idx_T_17) node _regout_data_T_15 = mux(regout_sel_3_5, sourceD_wreq.data[5], sourceD_rreq.data[5]) node _regout_data_T_16 = mux(regout_sel_2_5, sinkD_req.data[5], _regout_data_T_15) node _regout_data_T_17 = mux(regout_sel_1_5, sourceC_req.data[5], _regout_data_T_16) node regout_data_5 = mux(regout_sel_0_5, sinkC_req.data[5], _regout_data_T_17) node _regout_T_25 = and(regout_wen_5, regout_en_5) when _regout_T_25 : write mport regout_MPORT_10 = cc_banks_5[regout_idx_5], clock connect regout_MPORT_10, regout_data_5 node _regout_T_26 = eq(regout_wen_5, UInt<1>(0h0)) node _regout_T_27 = and(_regout_T_26, regout_en_5) wire _regout_WIRE_5 : UInt<15> invalidate _regout_WIRE_5 when _regout_T_27 : connect _regout_WIRE_5, regout_idx_5 read mport regout_MPORT_11 = cc_banks_5[_regout_WIRE_5], clock node _regout_T_28 = eq(regout_wen_5, UInt<1>(0h0)) node _regout_T_29 = and(_regout_T_28, regout_en_5) reg regout_REG_5 : UInt<1>, clock connect regout_REG_5, _regout_T_29 reg regout_r_5 : UInt<64>, clock when regout_REG_5 : connect regout_r_5, regout_MPORT_11 node _regout_en_T_48 = bits(sinkC_req.bankEn, 6, 6) node _regout_en_T_49 = bits(sourceC_req.bankEn, 6, 6) node _regout_en_T_50 = bits(sinkD_req.bankEn, 6, 6) node _regout_en_T_51 = bits(sourceD_wreq.bankEn, 6, 6) node _regout_en_T_52 = bits(sourceD_rreq.bankEn, 6, 6) node _regout_en_T_53 = or(_regout_en_T_48, _regout_en_T_49) node _regout_en_T_54 = or(_regout_en_T_53, _regout_en_T_50) node _regout_en_T_55 = or(_regout_en_T_54, _regout_en_T_51) node regout_en_6 = or(_regout_en_T_55, _regout_en_T_52) node regout_sel_0_6 = bits(sinkC_req.bankSel, 6, 6) node regout_sel_1_6 = bits(sourceC_req.bankSel, 6, 6) node regout_sel_2_6 = bits(sinkD_req.bankSel, 6, 6) node regout_sel_3_6 = bits(sourceD_wreq.bankSel, 6, 6) node regout_sel_4_6 = bits(sourceD_rreq.bankSel, 6, 6) node _regout_wen_T_18 = mux(regout_sel_3_6, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_19 = mux(regout_sel_2_6, sinkD_req.wen, _regout_wen_T_18) node _regout_wen_T_20 = mux(regout_sel_1_6, sourceC_req.wen, _regout_wen_T_19) node regout_wen_6 = mux(regout_sel_0_6, sinkC_req.wen, _regout_wen_T_20) node _regout_idx_T_18 = mux(regout_sel_3_6, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_19 = mux(regout_sel_2_6, sinkD_req.index, _regout_idx_T_18) node _regout_idx_T_20 = mux(regout_sel_1_6, sourceC_req.index, _regout_idx_T_19) node regout_idx_6 = mux(regout_sel_0_6, sinkC_req.index, _regout_idx_T_20) node _regout_data_T_18 = mux(regout_sel_3_6, sourceD_wreq.data[6], sourceD_rreq.data[6]) node _regout_data_T_19 = mux(regout_sel_2_6, sinkD_req.data[6], _regout_data_T_18) node _regout_data_T_20 = mux(regout_sel_1_6, sourceC_req.data[6], _regout_data_T_19) node regout_data_6 = mux(regout_sel_0_6, sinkC_req.data[6], _regout_data_T_20) node _regout_T_30 = and(regout_wen_6, regout_en_6) when _regout_T_30 : write mport regout_MPORT_12 = cc_banks_6[regout_idx_6], clock connect regout_MPORT_12, regout_data_6 node _regout_T_31 = eq(regout_wen_6, UInt<1>(0h0)) node _regout_T_32 = and(_regout_T_31, regout_en_6) wire _regout_WIRE_6 : UInt<15> invalidate _regout_WIRE_6 when _regout_T_32 : connect _regout_WIRE_6, regout_idx_6 read mport regout_MPORT_13 = cc_banks_6[_regout_WIRE_6], clock node _regout_T_33 = eq(regout_wen_6, UInt<1>(0h0)) node _regout_T_34 = and(_regout_T_33, regout_en_6) reg regout_REG_6 : UInt<1>, clock connect regout_REG_6, _regout_T_34 reg regout_r_6 : UInt<64>, clock when regout_REG_6 : connect regout_r_6, regout_MPORT_13 node _regout_en_T_56 = bits(sinkC_req.bankEn, 7, 7) node _regout_en_T_57 = bits(sourceC_req.bankEn, 7, 7) node _regout_en_T_58 = bits(sinkD_req.bankEn, 7, 7) node _regout_en_T_59 = bits(sourceD_wreq.bankEn, 7, 7) node _regout_en_T_60 = bits(sourceD_rreq.bankEn, 7, 7) node _regout_en_T_61 = or(_regout_en_T_56, _regout_en_T_57) node _regout_en_T_62 = or(_regout_en_T_61, _regout_en_T_58) node _regout_en_T_63 = or(_regout_en_T_62, _regout_en_T_59) node regout_en_7 = or(_regout_en_T_63, _regout_en_T_60) node regout_sel_0_7 = bits(sinkC_req.bankSel, 7, 7) node regout_sel_1_7 = bits(sourceC_req.bankSel, 7, 7) node regout_sel_2_7 = bits(sinkD_req.bankSel, 7, 7) node regout_sel_3_7 = bits(sourceD_wreq.bankSel, 7, 7) node regout_sel_4_7 = bits(sourceD_rreq.bankSel, 7, 7) node _regout_wen_T_21 = mux(regout_sel_3_7, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_22 = mux(regout_sel_2_7, sinkD_req.wen, _regout_wen_T_21) node _regout_wen_T_23 = mux(regout_sel_1_7, sourceC_req.wen, _regout_wen_T_22) node regout_wen_7 = mux(regout_sel_0_7, sinkC_req.wen, _regout_wen_T_23) node _regout_idx_T_21 = mux(regout_sel_3_7, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_22 = mux(regout_sel_2_7, sinkD_req.index, _regout_idx_T_21) node _regout_idx_T_23 = mux(regout_sel_1_7, sourceC_req.index, _regout_idx_T_22) node regout_idx_7 = mux(regout_sel_0_7, sinkC_req.index, _regout_idx_T_23) node _regout_data_T_21 = mux(regout_sel_3_7, sourceD_wreq.data[7], sourceD_rreq.data[7]) node _regout_data_T_22 = mux(regout_sel_2_7, sinkD_req.data[7], _regout_data_T_21) node _regout_data_T_23 = mux(regout_sel_1_7, sourceC_req.data[7], _regout_data_T_22) node regout_data_7 = mux(regout_sel_0_7, sinkC_req.data[7], _regout_data_T_23) node _regout_T_35 = and(regout_wen_7, regout_en_7) when _regout_T_35 : write mport regout_MPORT_14 = cc_banks_7[regout_idx_7], clock connect regout_MPORT_14, regout_data_7 node _regout_T_36 = eq(regout_wen_7, UInt<1>(0h0)) node _regout_T_37 = and(_regout_T_36, regout_en_7) wire _regout_WIRE_7 : UInt<15> invalidate _regout_WIRE_7 when _regout_T_37 : connect _regout_WIRE_7, regout_idx_7 read mport regout_MPORT_15 = cc_banks_7[_regout_WIRE_7], clock node _regout_T_38 = eq(regout_wen_7, UInt<1>(0h0)) node _regout_T_39 = and(_regout_T_38, regout_en_7) reg regout_REG_7 : UInt<1>, clock connect regout_REG_7, _regout_T_39 reg regout_r_7 : UInt<64>, clock when regout_REG_7 : connect regout_r_7, regout_MPORT_15 wire regout : UInt<64>[8] connect regout[0], regout_r connect regout[1], regout_r_1 connect regout[2], regout_r_2 connect regout[3], regout_r_3 connect regout[4], regout_r_4 connect regout[5], regout_r_5 connect regout[6], regout_r_6 connect regout[7], regout_r_7 reg regsel_sourceC_REG : UInt, clock connect regsel_sourceC_REG, sourceC_req.bankEn reg regsel_sourceC : UInt, clock connect regsel_sourceC, regsel_sourceC_REG reg regsel_sourceD_REG : UInt, clock connect regsel_sourceD_REG, sourceD_rreq.bankEn reg regsel_sourceD : UInt, clock connect regsel_sourceD, regsel_sourceD_REG node _decodeC_T = bits(regsel_sourceC, 0, 0) node _decodeC_T_1 = mux(_decodeC_T, regout[0], UInt<1>(0h0)) node _decodeC_T_2 = bits(regsel_sourceC, 1, 1) node _decodeC_T_3 = mux(_decodeC_T_2, regout[1], UInt<1>(0h0)) node _decodeC_T_4 = bits(regsel_sourceC, 2, 2) node _decodeC_T_5 = mux(_decodeC_T_4, regout[2], UInt<1>(0h0)) node _decodeC_T_6 = bits(regsel_sourceC, 3, 3) node _decodeC_T_7 = mux(_decodeC_T_6, regout[3], UInt<1>(0h0)) node _decodeC_T_8 = bits(regsel_sourceC, 4, 4) node _decodeC_T_9 = mux(_decodeC_T_8, regout[4], UInt<1>(0h0)) node _decodeC_T_10 = bits(regsel_sourceC, 5, 5) node _decodeC_T_11 = mux(_decodeC_T_10, regout[5], UInt<1>(0h0)) node _decodeC_T_12 = bits(regsel_sourceC, 6, 6) node _decodeC_T_13 = mux(_decodeC_T_12, regout[6], UInt<1>(0h0)) node _decodeC_T_14 = bits(regsel_sourceC, 7, 7) node _decodeC_T_15 = mux(_decodeC_T_14, regout[7], UInt<1>(0h0)) node _decodeC_T_16 = or(_decodeC_T_1, _decodeC_T_3) node _decodeC_T_17 = or(_decodeC_T_16, _decodeC_T_5) node _decodeC_T_18 = or(_decodeC_T_17, _decodeC_T_7) node _decodeC_T_19 = or(_decodeC_T_18, _decodeC_T_9) node _decodeC_T_20 = or(_decodeC_T_19, _decodeC_T_11) node _decodeC_T_21 = or(_decodeC_T_20, _decodeC_T_13) node decodeC_0 = or(_decodeC_T_21, _decodeC_T_15) connect io.sourceC_dat.data, decodeC_0 node _decodeD_T = bits(regsel_sourceD, 0, 0) node _decodeD_T_1 = mux(_decodeD_T, regout[0], UInt<1>(0h0)) node _decodeD_T_2 = bits(regsel_sourceD, 1, 1) node _decodeD_T_3 = mux(_decodeD_T_2, regout[1], UInt<1>(0h0)) node _decodeD_T_4 = bits(regsel_sourceD, 2, 2) node _decodeD_T_5 = mux(_decodeD_T_4, regout[2], UInt<1>(0h0)) node _decodeD_T_6 = bits(regsel_sourceD, 3, 3) node _decodeD_T_7 = mux(_decodeD_T_6, regout[3], UInt<1>(0h0)) node _decodeD_T_8 = bits(regsel_sourceD, 4, 4) node _decodeD_T_9 = mux(_decodeD_T_8, regout[4], UInt<1>(0h0)) node _decodeD_T_10 = bits(regsel_sourceD, 5, 5) node _decodeD_T_11 = mux(_decodeD_T_10, regout[5], UInt<1>(0h0)) node _decodeD_T_12 = bits(regsel_sourceD, 6, 6) node _decodeD_T_13 = mux(_decodeD_T_12, regout[6], UInt<1>(0h0)) node _decodeD_T_14 = bits(regsel_sourceD, 7, 7) node _decodeD_T_15 = mux(_decodeD_T_14, regout[7], UInt<1>(0h0)) node _decodeD_T_16 = or(_decodeD_T_1, _decodeD_T_5) node _decodeD_T_17 = or(_decodeD_T_16, _decodeD_T_9) node decodeD_0 = or(_decodeD_T_17, _decodeD_T_13) node _decodeD_T_18 = or(_decodeD_T_3, _decodeD_T_7) node _decodeD_T_19 = or(_decodeD_T_18, _decodeD_T_11) node decodeD_1 = or(_decodeD_T_19, _decodeD_T_15) node _io_sourceD_rdat_data_T = cat(decodeD_1, decodeD_0) connect io.sourceD_rdat.data, _io_sourceD_rdat_data_T
module BankedStore_1( // @[BankedStore.scala:59:7] input clock, // @[BankedStore.scala:59:7] input reset, // @[BankedStore.scala:59:7] output io_sinkC_adr_ready, // @[BankedStore.scala:61:14] input io_sinkC_adr_valid, // @[BankedStore.scala:61:14] input io_sinkC_adr_bits_noop, // @[BankedStore.scala:61:14] input [3:0] io_sinkC_adr_bits_way, // @[BankedStore.scala:61:14] input [10:0] io_sinkC_adr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sinkC_adr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sinkC_adr_bits_mask, // @[BankedStore.scala:61:14] input [127:0] io_sinkC_dat_data, // @[BankedStore.scala:61:14] output io_sinkD_adr_ready, // @[BankedStore.scala:61:14] input io_sinkD_adr_valid, // @[BankedStore.scala:61:14] input io_sinkD_adr_bits_noop, // @[BankedStore.scala:61:14] input [3:0] io_sinkD_adr_bits_way, // @[BankedStore.scala:61:14] input [10:0] io_sinkD_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_beat, // @[BankedStore.scala:61:14] input [63:0] io_sinkD_dat_data, // @[BankedStore.scala:61:14] output io_sourceC_adr_ready, // @[BankedStore.scala:61:14] input io_sourceC_adr_valid, // @[BankedStore.scala:61:14] input [3:0] io_sourceC_adr_bits_way, // @[BankedStore.scala:61:14] input [10:0] io_sourceC_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_beat, // @[BankedStore.scala:61:14] output [63:0] io_sourceC_dat_data, // @[BankedStore.scala:61:14] output io_sourceD_radr_ready, // @[BankedStore.scala:61:14] input io_sourceD_radr_valid, // @[BankedStore.scala:61:14] input [3:0] io_sourceD_radr_bits_way, // @[BankedStore.scala:61:14] input [10:0] io_sourceD_radr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_radr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_radr_bits_mask, // @[BankedStore.scala:61:14] output [127:0] io_sourceD_rdat_data, // @[BankedStore.scala:61:14] output io_sourceD_wadr_ready, // @[BankedStore.scala:61:14] input io_sourceD_wadr_valid, // @[BankedStore.scala:61:14] input [3:0] io_sourceD_wadr_bits_way, // @[BankedStore.scala:61:14] input [10:0] io_sourceD_wadr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_wadr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_wadr_bits_mask, // @[BankedStore.scala:61:14] input [127:0] io_sourceD_wdat_data // @[BankedStore.scala:61:14] ); wire [7:0] sinkC_req_bankSel; // @[BankedStore.scala:128:19] wire [63:0] _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_sinkC_adr_valid_0 = io_sinkC_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkC_adr_bits_noop_0 = io_sinkC_adr_bits_noop; // @[BankedStore.scala:59:7] wire [3:0] io_sinkC_adr_bits_way_0 = io_sinkC_adr_bits_way; // @[BankedStore.scala:59:7] wire [10:0] io_sinkC_adr_bits_set_0 = io_sinkC_adr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sinkC_adr_bits_beat_0 = io_sinkC_adr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sinkC_adr_bits_mask_0 = io_sinkC_adr_bits_mask; // @[BankedStore.scala:59:7] wire [127:0] io_sinkC_dat_data_0 = io_sinkC_dat_data; // @[BankedStore.scala:59:7] wire io_sinkD_adr_valid_0 = io_sinkD_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkD_adr_bits_noop_0 = io_sinkD_adr_bits_noop; // @[BankedStore.scala:59:7] wire [3:0] io_sinkD_adr_bits_way_0 = io_sinkD_adr_bits_way; // @[BankedStore.scala:59:7] wire [10:0] io_sinkD_adr_bits_set_0 = io_sinkD_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_beat_0 = io_sinkD_adr_bits_beat; // @[BankedStore.scala:59:7] wire [63:0] io_sinkD_dat_data_0 = io_sinkD_dat_data; // @[BankedStore.scala:59:7] wire io_sourceC_adr_valid_0 = io_sourceC_adr_valid; // @[BankedStore.scala:59:7] wire [3:0] io_sourceC_adr_bits_way_0 = io_sourceC_adr_bits_way; // @[BankedStore.scala:59:7] wire [10:0] io_sourceC_adr_bits_set_0 = io_sourceC_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_beat_0 = io_sourceC_adr_bits_beat; // @[BankedStore.scala:59:7] wire io_sourceD_radr_valid_0 = io_sourceD_radr_valid; // @[BankedStore.scala:59:7] wire [3:0] io_sourceD_radr_bits_way_0 = io_sourceD_radr_bits_way; // @[BankedStore.scala:59:7] wire [10:0] io_sourceD_radr_bits_set_0 = io_sourceD_radr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_radr_bits_beat_0 = io_sourceD_radr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_radr_bits_mask_0 = io_sourceD_radr_bits_mask; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_valid_0 = io_sourceD_wadr_valid; // @[BankedStore.scala:59:7] wire [3:0] io_sourceD_wadr_bits_way_0 = io_sourceD_wadr_bits_way; // @[BankedStore.scala:59:7] wire [10:0] io_sourceD_wadr_bits_set_0 = io_sourceD_wadr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_wadr_bits_beat_0 = io_sourceD_wadr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_wadr_bits_mask_0 = io_sourceD_wadr_bits_mask; // @[BankedStore.scala:59:7] wire [127:0] io_sourceD_wdat_data_0 = io_sourceD_wdat_data; // @[BankedStore.scala:59:7] wire [7:0] sinkC_req_bankSum = 8'h0; // @[BankedStore.scala:128:19] wire [1:0] _sinkC_req_ready_T = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_1 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_4 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_5 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_8 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_9 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_12 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_13 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] sinkC_req_ready_lo = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_ready_hi = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] _sinkC_req_out_bankEn_T_4 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_5 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_6 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_7 = 2'h3; // @[BankedStore.scala:137:72] wire [3:0] sinkC_req_ready = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [3:0] sinkC_req_out_bankEn_lo = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [3:0] sinkC_req_out_bankEn_hi = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [7:0] _sinkC_req_out_bankEn_T_8 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [7:0] _sinkD_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [7:0] _sourceC_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [63:0] sourceC_req_data_0 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_1 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_2 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_3 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_4 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_5 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_6 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_7 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_0 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_1 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_2 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_3 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_4 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_5 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_6 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_7 = 64'h0; // @[BankedStore.scala:128:19] wire io_sourceC_adr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire _sinkC_req_ready_T_2 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_6 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_10 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_14 = 1'h0; // @[BankedStore.scala:131:101] wire sourceC_req_wen = 1'h0; // @[BankedStore.scala:128:19] wire sourceD_rreq_wen = 1'h0; // @[BankedStore.scala:128:19] wire io_sinkD_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7] wire io_sourceC_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7] wire sinkC_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkC_req_ready_T_3 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_7 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_11 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_15 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire _sinkC_req_out_bankEn_T = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_1 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_2 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_3 = 1'h1; // @[BankedStore.scala:137:72] wire sinkD_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_out_bankSel_T_9 = 1'h1; // @[BankedStore.scala:136:71] wire _sourceC_req_out_bankSel_T_9 = 1'h1; // @[BankedStore.scala:136:71] wire sourceD_wreq_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] sinkD_req_words_0 = io_sinkD_dat_data_0; // @[BankedStore.scala:59:7, :123:19] wire _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] decodeC_0; // @[BankedStore.scala:180:85] wire _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:132:21] wire [127:0] _io_sourceD_rdat_data_T; // @[BankedStore.scala:189:30] wire _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:132:21] wire io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] wire [63:0] io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] wire [127:0] io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] wire [14:0] regout_idx; // @[Mux.scala:50:70] wire _regout_T; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE; // @[BankedStore.scala:172:21] wire _regout_T_2; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_1; // @[Mux.scala:50:70] wire _regout_T_5; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_1; // @[BankedStore.scala:172:21] wire _regout_T_7; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_2; // @[Mux.scala:50:70] wire _regout_T_10; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_2; // @[BankedStore.scala:172:21] wire _regout_T_12; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_3; // @[Mux.scala:50:70] wire _regout_T_15; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_3; // @[BankedStore.scala:172:21] wire _regout_T_17; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_4; // @[Mux.scala:50:70] wire _regout_T_20; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_4; // @[BankedStore.scala:172:21] wire _regout_T_22; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_5; // @[Mux.scala:50:70] wire _regout_T_25; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_5; // @[BankedStore.scala:172:21] wire _regout_T_27; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_6; // @[Mux.scala:50:70] wire _regout_T_30; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_6; // @[BankedStore.scala:172:21] wire _regout_T_32; // @[BankedStore.scala:172:32] wire [14:0] regout_idx_7; // @[Mux.scala:50:70] wire _regout_T_35; // @[BankedStore.scala:171:15] wire [14:0] _regout_WIRE_7; // @[BankedStore.scala:172:21] wire _regout_T_37; // @[BankedStore.scala:172:32] wire [63:0] sinkC_req_words_0 = io_sinkC_dat_data_0[63:0]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sinkC_req_data_0 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_2 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_4 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_6 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_words_1 = io_sinkC_dat_data_0[127:64]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sinkC_req_data_1 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_3 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_5 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_7 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [14:0] sinkC_req_a_hi = {io_sinkC_adr_bits_way_0, io_sinkC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [16:0] sinkC_req_a = {sinkC_req_a_hi, io_sinkC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] _sinkC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sinkC_req_out_bankEn_T_9 = sinkC_req_bankSel; // @[BankedStore.scala:128:19, :137:55] wire [7:0] sourceC_req_bankSum = sinkC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] _sinkC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [14:0] sinkC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkC_req_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sinkC_req_select_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sinkC_req_io_sinkC_adr_ready_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sinkC_req_select_shiftAmount = _sinkC_req_select_T; // @[OneHot.scala:64:49] wire [3:0] _sinkC_req_select_T_1 = 4'h1 << sinkC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sinkC_req_select = _sinkC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 4'hF >> _sinkC_req_io_sinkC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}, :137:72] assign _sinkC_req_io_sinkC_adr_ready_T_2 = _sinkC_req_io_sinkC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkC_adr_ready_0 = _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkC_req_out_index_T = sinkC_req_a[16:2]; // @[BankedStore.scala:126:91, :135:23] assign sinkC_req_index = _sinkC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkC_req_out_bankSel_T = sinkC_req_select[0]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_1 = sinkC_req_select[1]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_2 = sinkC_req_select[2]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_3 = sinkC_req_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sinkC_req_out_bankSel_T_4 = {2{_sinkC_req_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_5 = {2{_sinkC_req_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_6 = {2{_sinkC_req_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_7 = {2{_sinkC_req_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_lo = {_sinkC_req_out_bankSel_T_5, _sinkC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_hi = {_sinkC_req_out_bankSel_T_7, _sinkC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sinkC_req_out_bankSel_T_8 = {sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sinkC_req_out_bankSel_T_9 = {2{io_sinkC_adr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sinkC_req_out_bankSel_T_10 = {2{_sinkC_req_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sinkC_req_out_bankSel_T_11 = _sinkC_req_out_bankSel_T_8 & _sinkC_req_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sinkC_req_out_bankSel_T_12 = io_sinkC_adr_valid_0 ? _sinkC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkC_req_bankSel = _sinkC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] assign _sinkC_req_out_bankEn_T_10 = io_sinkC_adr_bits_noop_0 ? 8'h0 : _sinkC_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkC_req_bankEn = _sinkC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [63:0] sinkD_req_data_0 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_1 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_2 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_3 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_4 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_5 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_6 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_7 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [14:0] sinkD_req_a_hi = {io_sinkD_adr_bits_way_0, io_sinkD_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [17:0] sinkD_req_a = {sinkD_req_a_hi, io_sinkD_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] _sinkD_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [14:0] sinkD_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sinkD_req_select_T = sinkD_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sinkD_req_io_sinkD_adr_ready_T = sinkD_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sinkD_req_select_shiftAmount = _sinkD_req_select_T; // @[OneHot.scala:64:49] wire [7:0] _sinkD_req_select_T_1 = 8'h1 << sinkD_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] sinkD_req_select = _sinkD_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sinkD_req_ready_T = sinkD_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_1 = _sinkD_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_2 = _sinkD_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_3 = ~_sinkD_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_4 = sinkD_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_5 = _sinkD_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_6 = _sinkD_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_7 = ~_sinkD_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_8 = sinkD_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_9 = _sinkD_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_10 = _sinkD_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_11 = ~_sinkD_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_12 = sinkD_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_13 = _sinkD_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_14 = _sinkD_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_15 = ~_sinkD_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_16 = sinkD_req_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_17 = _sinkD_req_ready_T_16; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_18 = _sinkD_req_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_19 = ~_sinkD_req_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_20 = sinkD_req_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_21 = _sinkD_req_ready_T_20; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_22 = _sinkD_req_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_23 = ~_sinkD_req_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_24 = sinkD_req_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_25 = _sinkD_req_ready_T_24; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_26 = _sinkD_req_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_27 = ~_sinkD_req_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_28 = sinkD_req_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_29 = _sinkD_req_ready_T_28; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_30 = _sinkD_req_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_31 = ~_sinkD_req_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sinkD_req_ready_lo_lo = {_sinkD_req_ready_T_7, _sinkD_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_lo_hi = {_sinkD_req_ready_T_15, _sinkD_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready_lo = {sinkD_req_ready_lo_hi, sinkD_req_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sinkD_req_ready_hi_lo = {_sinkD_req_ready_T_23, _sinkD_req_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_hi_hi = {_sinkD_req_ready_T_31, _sinkD_req_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready_hi = {sinkD_req_ready_hi_hi, sinkD_req_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sinkD_req_ready = {sinkD_req_ready_hi, sinkD_req_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> _sinkD_req_io_sinkD_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sinkD_req_io_sinkD_adr_ready_T_2 = _sinkD_req_io_sinkD_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkD_adr_ready_0 = _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkD_req_out_index_T = sinkD_req_a[17:3]; // @[BankedStore.scala:126:91, :135:23] assign sinkD_req_index = _sinkD_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkD_req_out_bankSel_T = sinkD_req_select[0]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_1 = sinkD_req_select[1]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_2 = sinkD_req_select[2]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_3 = sinkD_req_select[3]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_4 = sinkD_req_select[4]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_5 = sinkD_req_select[5]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_6 = sinkD_req_select[6]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_7 = sinkD_req_select[7]; // @[OneHot.scala:65:27] wire [1:0] sinkD_req_out_bankSel_lo_lo = {_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_lo_hi = {_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_lo = {sinkD_req_out_bankSel_lo_hi, sinkD_req_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_hi_lo = {_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_hi_hi = {_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_hi = {sinkD_req_out_bankSel_hi_hi, sinkD_req_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_8 = {sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_11 = _sinkD_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sinkD_req_out_bankSel_T_12 = io_sinkD_adr_valid_0 ? _sinkD_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkD_req_bankSel = _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sinkD_req_out_bankEn_T = sinkD_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_1 = sinkD_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_2 = sinkD_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_3 = sinkD_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_4 = sinkD_req_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_5 = sinkD_req_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_6 = sinkD_req_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_7 = sinkD_req_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sinkD_req_out_bankEn_lo_lo = {_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_lo_hi = {_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_lo = {sinkD_req_out_bankEn_lo_hi, sinkD_req_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_hi_lo = {_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_hi_hi = {_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_hi = {sinkD_req_out_bankEn_hi_hi, sinkD_req_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_8 = {sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_9 = sinkD_req_bankSel & _sinkD_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sinkD_req_out_bankEn_T_10 = io_sinkD_adr_bits_noop_0 ? 8'h0 : _sinkD_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkD_req_bankEn = _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [14:0] sourceC_req_a_hi = {io_sourceC_adr_bits_way_0, io_sourceC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [17:0] sourceC_req_a = {sourceC_req_a_hi, io_sourceC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] _sourceC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [14:0] sourceC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sourceC_req_select_T = sourceC_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sourceC_req_io_sourceC_adr_ready_T = sourceC_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sourceC_req_select_shiftAmount = _sourceC_req_select_T; // @[OneHot.scala:64:49] wire [7:0] _sourceC_req_select_T_1 = 8'h1 << sourceC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] sourceC_req_select = _sourceC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sourceC_req_ready_T = sourceC_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_1 = _sourceC_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_2 = _sourceC_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_3 = ~_sourceC_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_4 = sourceC_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_5 = _sourceC_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_6 = _sourceC_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_7 = ~_sourceC_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_8 = sourceC_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_9 = _sourceC_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_10 = _sourceC_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_11 = ~_sourceC_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_12 = sourceC_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_13 = _sourceC_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_14 = _sourceC_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_15 = ~_sourceC_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_16 = sourceC_req_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_17 = _sourceC_req_ready_T_16; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_18 = _sourceC_req_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_19 = ~_sourceC_req_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_20 = sourceC_req_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_21 = _sourceC_req_ready_T_20; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_22 = _sourceC_req_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_23 = ~_sourceC_req_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_24 = sourceC_req_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_25 = _sourceC_req_ready_T_24; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_26 = _sourceC_req_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_27 = ~_sourceC_req_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_28 = sourceC_req_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_29 = _sourceC_req_ready_T_28; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_30 = _sourceC_req_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_31 = ~_sourceC_req_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceC_req_ready_lo_lo = {_sourceC_req_ready_T_7, _sourceC_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceC_req_ready_lo_hi = {_sourceC_req_ready_T_15, _sourceC_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceC_req_ready_lo = {sourceC_req_ready_lo_hi, sourceC_req_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sourceC_req_ready_hi_lo = {_sourceC_req_ready_T_23, _sourceC_req_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceC_req_ready_hi_hi = {_sourceC_req_ready_T_31, _sourceC_req_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceC_req_ready_hi = {sourceC_req_ready_hi_hi, sourceC_req_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sourceC_req_ready = {sourceC_req_ready_hi, sourceC_req_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sourceC_req_io_sourceC_adr_ready_T_1 = sourceC_req_ready >> _sourceC_req_io_sourceC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceC_req_io_sourceC_adr_ready_T_2 = _sourceC_req_io_sourceC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceC_adr_ready_0 = _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceC_req_out_index_T = sourceC_req_a[17:3]; // @[BankedStore.scala:126:91, :135:23] assign sourceC_req_index = _sourceC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceC_req_out_bankSel_T = sourceC_req_select[0]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_1 = sourceC_req_select[1]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_2 = sourceC_req_select[2]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_3 = sourceC_req_select[3]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_4 = sourceC_req_select[4]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_5 = sourceC_req_select[5]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_6 = sourceC_req_select[6]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_7 = sourceC_req_select[7]; // @[OneHot.scala:65:27] wire [1:0] sourceC_req_out_bankSel_lo_lo = {_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_lo_hi = {_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_lo = {sourceC_req_out_bankSel_lo_hi, sourceC_req_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_hi_lo = {_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_hi_hi = {_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_hi = {sourceC_req_out_bankSel_hi_hi, sourceC_req_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_8 = {sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_11 = _sourceC_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sourceC_req_out_bankSel_T_12 = io_sourceC_adr_valid_0 ? _sourceC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceC_req_bankSel = _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceC_req_out_bankEn_T = sourceC_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_1 = sourceC_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_2 = sourceC_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_3 = sourceC_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_4 = sourceC_req_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_5 = sourceC_req_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_6 = sourceC_req_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_7 = sourceC_req_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sourceC_req_out_bankEn_lo_lo = {_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_lo_hi = {_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sourceC_req_out_bankEn_lo = {sourceC_req_out_bankEn_lo_hi, sourceC_req_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_hi_lo = {_sourceC_req_out_bankEn_T_5, _sourceC_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_hi_hi = {_sourceC_req_out_bankEn_T_7, _sourceC_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sourceC_req_out_bankEn_hi = {sourceC_req_out_bankEn_hi_hi, sourceC_req_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceC_req_out_bankEn_T_8 = {sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceC_req_out_bankEn_T_9 = sourceC_req_bankSel & _sourceC_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceC_req_out_bankEn_T_10 = _sourceC_req_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceC_req_bankEn = _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [14:0] sourceD_rreq_a_hi = {io_sourceD_radr_bits_way_0, io_sourceD_radr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [16:0] sourceD_rreq_a = {sourceD_rreq_a_hi, io_sourceD_radr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] _sourceD_rreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [14:0] sourceD_rreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceD_rreq_select_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceD_rreq_io_sourceD_radr_ready_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceD_rreq_select_shiftAmount = _sourceD_rreq_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceD_rreq_select_T_1 = 4'h1 << sourceD_rreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceD_rreq_select = _sourceD_rreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sourceD_rreq_ready_T = sourceD_rreq_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_1 = _sourceD_rreq_ready_T & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_2 = |_sourceD_rreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_3 = ~_sourceD_rreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_4 = sourceD_rreq_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_5 = _sourceD_rreq_ready_T_4 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_6 = |_sourceD_rreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_7 = ~_sourceD_rreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_8 = sourceD_rreq_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_9 = _sourceD_rreq_ready_T_8 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_10 = |_sourceD_rreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_11 = ~_sourceD_rreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_12 = sourceD_rreq_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_13 = _sourceD_rreq_ready_T_12 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_14 = |_sourceD_rreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_15 = ~_sourceD_rreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_rreq_ready_lo = {_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_rreq_ready_hi = {_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_rreq_ready = {sourceD_rreq_ready_hi, sourceD_rreq_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> _sourceD_rreq_io_sourceD_radr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_rreq_io_sourceD_radr_ready_T_2 = _sourceD_rreq_io_sourceD_radr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_radr_ready_0 = _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_rreq_out_index_T = sourceD_rreq_a[16:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_rreq_index = _sourceD_rreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_rreq_out_bankSel_T = sourceD_rreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_1 = sourceD_rreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_2 = sourceD_rreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_3 = sourceD_rreq_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceD_rreq_out_bankSel_T_4 = {2{_sourceD_rreq_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_5 = {2{_sourceD_rreq_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_6 = {2{_sourceD_rreq_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_7 = {2{_sourceD_rreq_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_lo = {_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_hi = {_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_rreq_out_bankSel_T_8 = {sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sourceD_rreq_out_bankSel_T_9 = {2{io_sourceD_radr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_10 = {2{_sourceD_rreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_11 = _sourceD_rreq_out_bankSel_T_8 & _sourceD_rreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_rreq_out_bankSel_T_12 = io_sourceD_radr_valid_0 ? _sourceD_rreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_rreq_bankSel = _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_rreq_out_bankEn_T = sourceD_rreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_1 = sourceD_rreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_2 = sourceD_rreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_3 = sourceD_rreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_4 = {2{_sourceD_rreq_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_5 = {2{_sourceD_rreq_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_6 = {2{_sourceD_rreq_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_7 = {2{_sourceD_rreq_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_lo = {_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_hi = {_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_8 = {sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_9 = sourceD_rreq_bankSel & _sourceD_rreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_rreq_out_bankEn_T_10 = _sourceD_rreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_rreq_bankEn = _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [63:0] sourceD_wreq_words_0 = io_sourceD_wdat_data_0[63:0]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sourceD_wreq_data_0 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_2 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_4 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_6 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_words_1 = io_sourceD_wdat_data_0[127:64]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sourceD_wreq_data_1 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_3 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_5 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_7 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [14:0] sourceD_wreq_a_hi = {io_sourceD_wadr_bits_way_0, io_sourceD_wadr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [16:0] sourceD_wreq_a = {sourceD_wreq_a_hi, io_sourceD_wadr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] _sourceD_wreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [14:0] sourceD_wreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceD_wreq_select_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceD_wreq_io_sourceD_wadr_ready_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceD_wreq_select_shiftAmount = _sourceD_wreq_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceD_wreq_select_T_1 = 4'h1 << sourceD_wreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceD_wreq_select = _sourceD_wreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sourceD_wreq_ready_T = sourceD_wreq_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_1 = _sourceD_wreq_ready_T & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_2 = |_sourceD_wreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_3 = ~_sourceD_wreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_4 = sourceD_wreq_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_5 = _sourceD_wreq_ready_T_4 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_6 = |_sourceD_wreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_7 = ~_sourceD_wreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_8 = sourceD_wreq_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_9 = _sourceD_wreq_ready_T_8 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_10 = |_sourceD_wreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_11 = ~_sourceD_wreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_12 = sourceD_wreq_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_13 = _sourceD_wreq_ready_T_12 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_14 = |_sourceD_wreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_15 = ~_sourceD_wreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_wreq_ready_lo = {_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_wreq_ready_hi = {_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_wreq_ready = {sourceD_wreq_ready_hi, sourceD_wreq_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> _sourceD_wreq_io_sourceD_wadr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_wreq_io_sourceD_wadr_ready_T_2 = _sourceD_wreq_io_sourceD_wadr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_wadr_ready_0 = _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_wreq_out_index_T = sourceD_wreq_a[16:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_wreq_index = _sourceD_wreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_wreq_out_bankSel_T = sourceD_wreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_1 = sourceD_wreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_2 = sourceD_wreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_3 = sourceD_wreq_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceD_wreq_out_bankSel_T_4 = {2{_sourceD_wreq_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_5 = {2{_sourceD_wreq_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_6 = {2{_sourceD_wreq_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_7 = {2{_sourceD_wreq_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_lo = {_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_hi = {_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_wreq_out_bankSel_T_8 = {sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sourceD_wreq_out_bankSel_T_9 = {2{io_sourceD_wadr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_10 = {2{_sourceD_wreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_11 = _sourceD_wreq_out_bankSel_T_8 & _sourceD_wreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_wreq_out_bankSel_T_12 = io_sourceD_wadr_valid_0 ? _sourceD_wreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_wreq_bankSel = _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_wreq_out_bankEn_T = sourceD_wreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_1 = sourceD_wreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_2 = sourceD_wreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_3 = sourceD_wreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_4 = {2{_sourceD_wreq_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_5 = {2{_sourceD_wreq_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_6 = {2{_sourceD_wreq_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_7 = {2{_sourceD_wreq_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_lo = {_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_hi = {_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_8 = {sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_9 = sourceD_wreq_bankSel & _sourceD_wreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_wreq_out_bankEn_T_10 = _sourceD_wreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_wreq_bankEn = _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] assign sinkD_req_bankSum = sourceC_req_bankSel | sinkC_req_bankSel; // @[BankedStore.scala:128:19, :161:17] assign sourceD_wreq_bankSum = sinkD_req_bankSel | sinkD_req_bankSum; // @[BankedStore.scala:128:19, :161:17] assign sourceD_rreq_bankSum = sourceD_wreq_bankSel | sourceD_wreq_bankSum; // @[BankedStore.scala:128:19, :161:17] wire _regout_en_T = sinkC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_1 = sourceC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_2 = sinkD_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_3 = sourceD_wreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_4 = sourceD_rreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_5 = _regout_en_T | _regout_en_T_1; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_6 = _regout_en_T_5 | _regout_en_T_2; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_7 = _regout_en_T_6 | _regout_en_T_3; // @[BankedStore.scala:165:{32,45}] wire regout_en = _regout_en_T_7 | _regout_en_T_4; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0 = sinkC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1 = sourceC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2 = sinkD_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3 = sourceD_wreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T = regout_sel_3; // @[Mux.scala:50:70] wire regout_sel_4 = sourceD_rreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_1 = regout_sel_2 | _regout_wen_T; // @[Mux.scala:50:70] wire _regout_wen_T_2 = ~regout_sel_1 & _regout_wen_T_1; // @[Mux.scala:50:70] wire regout_wen = regout_sel_0 | _regout_wen_T_2; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T = regout_sel_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_1 = regout_sel_2 ? sinkD_req_index : _regout_idx_T; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_2 = regout_sel_1 ? sourceC_req_index : _regout_idx_T_1; // @[Mux.scala:50:70] assign regout_idx = regout_sel_0 ? sinkC_req_index : _regout_idx_T_2; // @[Mux.scala:50:70] assign _regout_WIRE = regout_idx; // @[Mux.scala:50:70] wire [63:0] _regout_data_T = regout_sel_3 ? sourceD_wreq_data_0 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_1 = regout_sel_2 ? sinkD_req_data_0 : _regout_data_T; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_2 = regout_sel_1 ? 64'h0 : _regout_data_T_1; // @[Mux.scala:50:70] wire [63:0] regout_data = regout_sel_0 ? sinkC_req_data_0 : _regout_data_T_2; // @[Mux.scala:50:70] assign _regout_T = regout_wen & regout_en; // @[Mux.scala:50:70] wire _regout_T_1 = ~regout_wen; // @[Mux.scala:50:70] assign _regout_T_2 = _regout_T_1 & regout_en; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_3 = ~regout_wen; // @[Mux.scala:50:70] wire _regout_T_4 = _regout_T_3 & regout_en; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG; // @[BankedStore.scala:172:47] reg [63:0] regout_r; // @[BankedStore.scala:172:14] wire [63:0] regout_0 = regout_r; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_8 = sinkC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_9 = sourceC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_10 = sinkD_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_11 = sourceD_wreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_12 = sourceD_rreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_13 = _regout_en_T_8 | _regout_en_T_9; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_14 = _regout_en_T_13 | _regout_en_T_10; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_15 = _regout_en_T_14 | _regout_en_T_11; // @[BankedStore.scala:165:{32,45}] wire regout_en_1 = _regout_en_T_15 | _regout_en_T_12; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_1 = sinkC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_1 = sourceC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_1 = sinkD_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_1 = sourceD_wreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_3 = regout_sel_3_1; // @[Mux.scala:50:70] wire regout_sel_4_1 = sourceD_rreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_4 = regout_sel_2_1 | _regout_wen_T_3; // @[Mux.scala:50:70] wire _regout_wen_T_5 = ~regout_sel_1_1 & _regout_wen_T_4; // @[Mux.scala:50:70] wire regout_wen_1 = regout_sel_0_1 | _regout_wen_T_5; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_3 = regout_sel_3_1 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_4 = regout_sel_2_1 ? sinkD_req_index : _regout_idx_T_3; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_5 = regout_sel_1_1 ? sourceC_req_index : _regout_idx_T_4; // @[Mux.scala:50:70] assign regout_idx_1 = regout_sel_0_1 ? sinkC_req_index : _regout_idx_T_5; // @[Mux.scala:50:70] assign _regout_WIRE_1 = regout_idx_1; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_3 = regout_sel_3_1 ? sourceD_wreq_data_1 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_4 = regout_sel_2_1 ? sinkD_req_data_1 : _regout_data_T_3; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_5 = regout_sel_1_1 ? 64'h0 : _regout_data_T_4; // @[Mux.scala:50:70] wire [63:0] regout_data_1 = regout_sel_0_1 ? sinkC_req_data_1 : _regout_data_T_5; // @[Mux.scala:50:70] assign _regout_T_5 = regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] wire _regout_T_6 = ~regout_wen_1; // @[Mux.scala:50:70] assign _regout_T_7 = _regout_T_6 & regout_en_1; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_8 = ~regout_wen_1; // @[Mux.scala:50:70] wire _regout_T_9 = _regout_T_8 & regout_en_1; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_1; // @[BankedStore.scala:172:47] reg [63:0] regout_r_1; // @[BankedStore.scala:172:14] wire [63:0] regout_1 = regout_r_1; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_16 = sinkC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_17 = sourceC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_18 = sinkD_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_19 = sourceD_wreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_20 = sourceD_rreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_21 = _regout_en_T_16 | _regout_en_T_17; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_22 = _regout_en_T_21 | _regout_en_T_18; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_23 = _regout_en_T_22 | _regout_en_T_19; // @[BankedStore.scala:165:{32,45}] wire regout_en_2 = _regout_en_T_23 | _regout_en_T_20; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_2 = sinkC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_2 = sourceC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_2 = sinkD_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_2 = sourceD_wreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_6 = regout_sel_3_2; // @[Mux.scala:50:70] wire regout_sel_4_2 = sourceD_rreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_7 = regout_sel_2_2 | _regout_wen_T_6; // @[Mux.scala:50:70] wire _regout_wen_T_8 = ~regout_sel_1_2 & _regout_wen_T_7; // @[Mux.scala:50:70] wire regout_wen_2 = regout_sel_0_2 | _regout_wen_T_8; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_6 = regout_sel_3_2 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_7 = regout_sel_2_2 ? sinkD_req_index : _regout_idx_T_6; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_8 = regout_sel_1_2 ? sourceC_req_index : _regout_idx_T_7; // @[Mux.scala:50:70] assign regout_idx_2 = regout_sel_0_2 ? sinkC_req_index : _regout_idx_T_8; // @[Mux.scala:50:70] assign _regout_WIRE_2 = regout_idx_2; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_6 = regout_sel_3_2 ? sourceD_wreq_data_2 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_7 = regout_sel_2_2 ? sinkD_req_data_2 : _regout_data_T_6; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_8 = regout_sel_1_2 ? 64'h0 : _regout_data_T_7; // @[Mux.scala:50:70] wire [63:0] regout_data_2 = regout_sel_0_2 ? sinkC_req_data_2 : _regout_data_T_8; // @[Mux.scala:50:70] assign _regout_T_10 = regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] wire _regout_T_11 = ~regout_wen_2; // @[Mux.scala:50:70] assign _regout_T_12 = _regout_T_11 & regout_en_2; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_13 = ~regout_wen_2; // @[Mux.scala:50:70] wire _regout_T_14 = _regout_T_13 & regout_en_2; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_2; // @[BankedStore.scala:172:47] reg [63:0] regout_r_2; // @[BankedStore.scala:172:14] wire [63:0] regout_2 = regout_r_2; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_24 = sinkC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_25 = sourceC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_26 = sinkD_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_27 = sourceD_wreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_28 = sourceD_rreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_29 = _regout_en_T_24 | _regout_en_T_25; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_30 = _regout_en_T_29 | _regout_en_T_26; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_31 = _regout_en_T_30 | _regout_en_T_27; // @[BankedStore.scala:165:{32,45}] wire regout_en_3 = _regout_en_T_31 | _regout_en_T_28; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_3 = sinkC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_3 = sourceC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_3 = sinkD_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_3 = sourceD_wreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_9 = regout_sel_3_3; // @[Mux.scala:50:70] wire regout_sel_4_3 = sourceD_rreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_10 = regout_sel_2_3 | _regout_wen_T_9; // @[Mux.scala:50:70] wire _regout_wen_T_11 = ~regout_sel_1_3 & _regout_wen_T_10; // @[Mux.scala:50:70] wire regout_wen_3 = regout_sel_0_3 | _regout_wen_T_11; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_9 = regout_sel_3_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_10 = regout_sel_2_3 ? sinkD_req_index : _regout_idx_T_9; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_11 = regout_sel_1_3 ? sourceC_req_index : _regout_idx_T_10; // @[Mux.scala:50:70] assign regout_idx_3 = regout_sel_0_3 ? sinkC_req_index : _regout_idx_T_11; // @[Mux.scala:50:70] assign _regout_WIRE_3 = regout_idx_3; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_9 = regout_sel_3_3 ? sourceD_wreq_data_3 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_10 = regout_sel_2_3 ? sinkD_req_data_3 : _regout_data_T_9; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_11 = regout_sel_1_3 ? 64'h0 : _regout_data_T_10; // @[Mux.scala:50:70] wire [63:0] regout_data_3 = regout_sel_0_3 ? sinkC_req_data_3 : _regout_data_T_11; // @[Mux.scala:50:70] assign _regout_T_15 = regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] wire _regout_T_16 = ~regout_wen_3; // @[Mux.scala:50:70] assign _regout_T_17 = _regout_T_16 & regout_en_3; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_18 = ~regout_wen_3; // @[Mux.scala:50:70] wire _regout_T_19 = _regout_T_18 & regout_en_3; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_3; // @[BankedStore.scala:172:47] reg [63:0] regout_r_3; // @[BankedStore.scala:172:14] wire [63:0] regout_3 = regout_r_3; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_32 = sinkC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_33 = sourceC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_34 = sinkD_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_35 = sourceD_wreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_36 = sourceD_rreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_37 = _regout_en_T_32 | _regout_en_T_33; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_38 = _regout_en_T_37 | _regout_en_T_34; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_39 = _regout_en_T_38 | _regout_en_T_35; // @[BankedStore.scala:165:{32,45}] wire regout_en_4 = _regout_en_T_39 | _regout_en_T_36; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_4 = sinkC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_4 = sourceC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_4 = sinkD_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_4 = sourceD_wreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_12 = regout_sel_3_4; // @[Mux.scala:50:70] wire regout_sel_4_4 = sourceD_rreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_13 = regout_sel_2_4 | _regout_wen_T_12; // @[Mux.scala:50:70] wire _regout_wen_T_14 = ~regout_sel_1_4 & _regout_wen_T_13; // @[Mux.scala:50:70] wire regout_wen_4 = regout_sel_0_4 | _regout_wen_T_14; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_12 = regout_sel_3_4 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_13 = regout_sel_2_4 ? sinkD_req_index : _regout_idx_T_12; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_14 = regout_sel_1_4 ? sourceC_req_index : _regout_idx_T_13; // @[Mux.scala:50:70] assign regout_idx_4 = regout_sel_0_4 ? sinkC_req_index : _regout_idx_T_14; // @[Mux.scala:50:70] assign _regout_WIRE_4 = regout_idx_4; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_12 = regout_sel_3_4 ? sourceD_wreq_data_4 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_13 = regout_sel_2_4 ? sinkD_req_data_4 : _regout_data_T_12; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_14 = regout_sel_1_4 ? 64'h0 : _regout_data_T_13; // @[Mux.scala:50:70] wire [63:0] regout_data_4 = regout_sel_0_4 ? sinkC_req_data_4 : _regout_data_T_14; // @[Mux.scala:50:70] assign _regout_T_20 = regout_wen_4 & regout_en_4; // @[Mux.scala:50:70] wire _regout_T_21 = ~regout_wen_4; // @[Mux.scala:50:70] assign _regout_T_22 = _regout_T_21 & regout_en_4; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_23 = ~regout_wen_4; // @[Mux.scala:50:70] wire _regout_T_24 = _regout_T_23 & regout_en_4; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_4; // @[BankedStore.scala:172:47] reg [63:0] regout_r_4; // @[BankedStore.scala:172:14] wire [63:0] regout_4 = regout_r_4; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_40 = sinkC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_41 = sourceC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_42 = sinkD_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_43 = sourceD_wreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_44 = sourceD_rreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_45 = _regout_en_T_40 | _regout_en_T_41; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_46 = _regout_en_T_45 | _regout_en_T_42; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_47 = _regout_en_T_46 | _regout_en_T_43; // @[BankedStore.scala:165:{32,45}] wire regout_en_5 = _regout_en_T_47 | _regout_en_T_44; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_5 = sinkC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_5 = sourceC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_5 = sinkD_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_5 = sourceD_wreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_15 = regout_sel_3_5; // @[Mux.scala:50:70] wire regout_sel_4_5 = sourceD_rreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_16 = regout_sel_2_5 | _regout_wen_T_15; // @[Mux.scala:50:70] wire _regout_wen_T_17 = ~regout_sel_1_5 & _regout_wen_T_16; // @[Mux.scala:50:70] wire regout_wen_5 = regout_sel_0_5 | _regout_wen_T_17; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_15 = regout_sel_3_5 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_16 = regout_sel_2_5 ? sinkD_req_index : _regout_idx_T_15; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_17 = regout_sel_1_5 ? sourceC_req_index : _regout_idx_T_16; // @[Mux.scala:50:70] assign regout_idx_5 = regout_sel_0_5 ? sinkC_req_index : _regout_idx_T_17; // @[Mux.scala:50:70] assign _regout_WIRE_5 = regout_idx_5; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_15 = regout_sel_3_5 ? sourceD_wreq_data_5 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_16 = regout_sel_2_5 ? sinkD_req_data_5 : _regout_data_T_15; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_17 = regout_sel_1_5 ? 64'h0 : _regout_data_T_16; // @[Mux.scala:50:70] wire [63:0] regout_data_5 = regout_sel_0_5 ? sinkC_req_data_5 : _regout_data_T_17; // @[Mux.scala:50:70] assign _regout_T_25 = regout_wen_5 & regout_en_5; // @[Mux.scala:50:70] wire _regout_T_26 = ~regout_wen_5; // @[Mux.scala:50:70] assign _regout_T_27 = _regout_T_26 & regout_en_5; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_28 = ~regout_wen_5; // @[Mux.scala:50:70] wire _regout_T_29 = _regout_T_28 & regout_en_5; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_5; // @[BankedStore.scala:172:47] reg [63:0] regout_r_5; // @[BankedStore.scala:172:14] wire [63:0] regout_5 = regout_r_5; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_48 = sinkC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_49 = sourceC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_50 = sinkD_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_51 = sourceD_wreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_52 = sourceD_rreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_53 = _regout_en_T_48 | _regout_en_T_49; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_54 = _regout_en_T_53 | _regout_en_T_50; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_55 = _regout_en_T_54 | _regout_en_T_51; // @[BankedStore.scala:165:{32,45}] wire regout_en_6 = _regout_en_T_55 | _regout_en_T_52; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_6 = sinkC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_6 = sourceC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_6 = sinkD_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_6 = sourceD_wreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_18 = regout_sel_3_6; // @[Mux.scala:50:70] wire regout_sel_4_6 = sourceD_rreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_19 = regout_sel_2_6 | _regout_wen_T_18; // @[Mux.scala:50:70] wire _regout_wen_T_20 = ~regout_sel_1_6 & _regout_wen_T_19; // @[Mux.scala:50:70] wire regout_wen_6 = regout_sel_0_6 | _regout_wen_T_20; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_18 = regout_sel_3_6 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_19 = regout_sel_2_6 ? sinkD_req_index : _regout_idx_T_18; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_20 = regout_sel_1_6 ? sourceC_req_index : _regout_idx_T_19; // @[Mux.scala:50:70] assign regout_idx_6 = regout_sel_0_6 ? sinkC_req_index : _regout_idx_T_20; // @[Mux.scala:50:70] assign _regout_WIRE_6 = regout_idx_6; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_18 = regout_sel_3_6 ? sourceD_wreq_data_6 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_19 = regout_sel_2_6 ? sinkD_req_data_6 : _regout_data_T_18; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_20 = regout_sel_1_6 ? 64'h0 : _regout_data_T_19; // @[Mux.scala:50:70] wire [63:0] regout_data_6 = regout_sel_0_6 ? sinkC_req_data_6 : _regout_data_T_20; // @[Mux.scala:50:70] assign _regout_T_30 = regout_wen_6 & regout_en_6; // @[Mux.scala:50:70] wire _regout_T_31 = ~regout_wen_6; // @[Mux.scala:50:70] assign _regout_T_32 = _regout_T_31 & regout_en_6; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_33 = ~regout_wen_6; // @[Mux.scala:50:70] wire _regout_T_34 = _regout_T_33 & regout_en_6; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_6; // @[BankedStore.scala:172:47] reg [63:0] regout_r_6; // @[BankedStore.scala:172:14] wire [63:0] regout_6 = regout_r_6; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_56 = sinkC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_57 = sourceC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_58 = sinkD_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_59 = sourceD_wreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_60 = sourceD_rreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_61 = _regout_en_T_56 | _regout_en_T_57; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_62 = _regout_en_T_61 | _regout_en_T_58; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_63 = _regout_en_T_62 | _regout_en_T_59; // @[BankedStore.scala:165:{32,45}] wire regout_en_7 = _regout_en_T_63 | _regout_en_T_60; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_7 = sinkC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_7 = sourceC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_7 = sinkD_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_7 = sourceD_wreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_21 = regout_sel_3_7; // @[Mux.scala:50:70] wire regout_sel_4_7 = sourceD_rreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_22 = regout_sel_2_7 | _regout_wen_T_21; // @[Mux.scala:50:70] wire _regout_wen_T_23 = ~regout_sel_1_7 & _regout_wen_T_22; // @[Mux.scala:50:70] wire regout_wen_7 = regout_sel_0_7 | _regout_wen_T_23; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_21 = regout_sel_3_7 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_22 = regout_sel_2_7 ? sinkD_req_index : _regout_idx_T_21; // @[Mux.scala:50:70] wire [14:0] _regout_idx_T_23 = regout_sel_1_7 ? sourceC_req_index : _regout_idx_T_22; // @[Mux.scala:50:70] assign regout_idx_7 = regout_sel_0_7 ? sinkC_req_index : _regout_idx_T_23; // @[Mux.scala:50:70] assign _regout_WIRE_7 = regout_idx_7; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_21 = regout_sel_3_7 ? sourceD_wreq_data_7 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_22 = regout_sel_2_7 ? sinkD_req_data_7 : _regout_data_T_21; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_23 = regout_sel_1_7 ? 64'h0 : _regout_data_T_22; // @[Mux.scala:50:70] wire [63:0] regout_data_7 = regout_sel_0_7 ? sinkC_req_data_7 : _regout_data_T_23; // @[Mux.scala:50:70] assign _regout_T_35 = regout_wen_7 & regout_en_7; // @[Mux.scala:50:70] wire _regout_T_36 = ~regout_wen_7; // @[Mux.scala:50:70] assign _regout_T_37 = _regout_T_36 & regout_en_7; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_38 = ~regout_wen_7; // @[Mux.scala:50:70] wire _regout_T_39 = _regout_T_38 & regout_en_7; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_7; // @[BankedStore.scala:172:47] reg [63:0] regout_r_7; // @[BankedStore.scala:172:14] wire [63:0] regout_7 = regout_r_7; // @[BankedStore.scala:164:23, :172:14] reg [7:0] regsel_sourceC_REG; // @[BankedStore.scala:175:39] reg [7:0] regsel_sourceC; // @[BankedStore.scala:175:31] reg [7:0] regsel_sourceD_REG; // @[BankedStore.scala:176:39] reg [7:0] regsel_sourceD; // @[BankedStore.scala:176:31] wire _decodeC_T = regsel_sourceC[0]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_1 = _decodeC_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_2 = regsel_sourceC[1]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_3 = _decodeC_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_4 = regsel_sourceC[2]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_5 = _decodeC_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_6 = regsel_sourceC[3]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_7 = _decodeC_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_8 = regsel_sourceC[4]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_9 = _decodeC_T_8 ? regout_4 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_10 = regsel_sourceC[5]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_11 = _decodeC_T_10 ? regout_5 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_12 = regsel_sourceC[6]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_13 = _decodeC_T_12 ? regout_6 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_14 = regsel_sourceC[7]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_15 = _decodeC_T_14 ? regout_7 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire [63:0] _decodeC_T_16 = _decodeC_T_1 | _decodeC_T_3; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_17 = _decodeC_T_16 | _decodeC_T_5; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_18 = _decodeC_T_17 | _decodeC_T_7; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_19 = _decodeC_T_18 | _decodeC_T_9; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_20 = _decodeC_T_19 | _decodeC_T_11; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_21 = _decodeC_T_20 | _decodeC_T_13; // @[BankedStore.scala:179:23, :180:85] assign decodeC_0 = _decodeC_T_21 | _decodeC_T_15; // @[BankedStore.scala:179:23, :180:85] assign io_sourceC_dat_data_0 = decodeC_0; // @[BankedStore.scala:59:7, :180:85] wire _decodeD_T = regsel_sourceD[0]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_1 = _decodeD_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_2 = regsel_sourceD[1]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_3 = _decodeD_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_4 = regsel_sourceD[2]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_5 = _decodeD_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_6 = regsel_sourceD[3]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_7 = _decodeD_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_8 = regsel_sourceD[4]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_9 = _decodeD_T_8 ? regout_4 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_10 = regsel_sourceD[5]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_11 = _decodeD_T_10 ? regout_5 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_12 = regsel_sourceD[6]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_13 = _decodeD_T_12 ? regout_6 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_14 = regsel_sourceD[7]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_15 = _decodeD_T_14 ? regout_7 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire [63:0] _decodeD_T_16 = _decodeD_T_1 | _decodeD_T_5; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_17 = _decodeD_T_16 | _decodeD_T_9; // @[BankedStore.scala:186:23, :187:85] wire [63:0] decodeD_0 = _decodeD_T_17 | _decodeD_T_13; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_18 = _decodeD_T_3 | _decodeD_T_7; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_19 = _decodeD_T_18 | _decodeD_T_11; // @[BankedStore.scala:186:23, :187:85] wire [63:0] decodeD_1 = _decodeD_T_19 | _decodeD_T_15; // @[BankedStore.scala:186:23, :187:85] assign _io_sourceD_rdat_data_T = {decodeD_1, decodeD_0}; // @[BankedStore.scala:187:85, :189:30] assign io_sourceD_rdat_data_0 = _io_sourceD_rdat_data_T; // @[BankedStore.scala:59:7, :189:30] always @(posedge clock) begin // @[BankedStore.scala:59:7] regout_REG <= _regout_T_4; // @[BankedStore.scala:172:{47,53}] if (regout_REG) // @[BankedStore.scala:172:47] regout_r <= _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_1 <= _regout_T_9; // @[BankedStore.scala:172:{47,53}] if (regout_REG_1) // @[BankedStore.scala:172:47] regout_r_1 <= _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_2 <= _regout_T_14; // @[BankedStore.scala:172:{47,53}] if (regout_REG_2) // @[BankedStore.scala:172:47] regout_r_2 <= _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_3 <= _regout_T_19; // @[BankedStore.scala:172:{47,53}] if (regout_REG_3) // @[BankedStore.scala:172:47] regout_r_3 <= _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_4 <= _regout_T_24; // @[BankedStore.scala:172:{47,53}] if (regout_REG_4) // @[BankedStore.scala:172:47] regout_r_4 <= _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_5 <= _regout_T_29; // @[BankedStore.scala:172:{47,53}] if (regout_REG_5) // @[BankedStore.scala:172:47] regout_r_5 <= _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_6 <= _regout_T_34; // @[BankedStore.scala:172:{47,53}] if (regout_REG_6) // @[BankedStore.scala:172:47] regout_r_6 <= _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_7 <= _regout_T_39; // @[BankedStore.scala:172:{47,53}] if (regout_REG_7) // @[BankedStore.scala:172:47] regout_r_7 <= _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] regsel_sourceC_REG <= sourceC_req_bankEn; // @[BankedStore.scala:128:19, :175:39] regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala:175:{31,39}] regsel_sourceD_REG <= sourceD_rreq_bankEn; // @[BankedStore.scala:128:19, :176:39] regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala:176:{31,39}] always @(posedge) cc_banks_0_0 cc_banks_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T ? regout_idx : _regout_WIRE), // @[Mux.scala:50:70] .RW0_en (_regout_T_2 | _regout_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen), // @[Mux.scala:50:70] .RW0_wdata (regout_data), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_1_0 cc_banks_1 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_5 ? regout_idx_1 : _regout_WIRE_1), // @[Mux.scala:50:70] .RW0_en (_regout_T_7 | _regout_T_5), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_1), // @[Mux.scala:50:70] .RW0_wdata (regout_data_1), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_1_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_2_0 cc_banks_2 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_10 ? regout_idx_2 : _regout_WIRE_2), // @[Mux.scala:50:70] .RW0_en (_regout_T_12 | _regout_T_10), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_2), // @[Mux.scala:50:70] .RW0_wdata (regout_data_2), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_2_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_3_0 cc_banks_3 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_15 ? regout_idx_3 : _regout_WIRE_3), // @[Mux.scala:50:70] .RW0_en (_regout_T_17 | _regout_T_15), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_3), // @[Mux.scala:50:70] .RW0_wdata (regout_data_3), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_3_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_4_0 cc_banks_4 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_20 ? regout_idx_4 : _regout_WIRE_4), // @[Mux.scala:50:70] .RW0_en (_regout_T_22 | _regout_T_20), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_4), // @[Mux.scala:50:70] .RW0_wdata (regout_data_4), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_4_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_5_0 cc_banks_5 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_25 ? regout_idx_5 : _regout_WIRE_5), // @[Mux.scala:50:70] .RW0_en (_regout_T_27 | _regout_T_25), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_5), // @[Mux.scala:50:70] .RW0_wdata (regout_data_5), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_5_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_6_0 cc_banks_6 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_30 ? regout_idx_6 : _regout_WIRE_6), // @[Mux.scala:50:70] .RW0_en (_regout_T_32 | _regout_T_30), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_6), // @[Mux.scala:50:70] .RW0_wdata (regout_data_6), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_6_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_7_0 cc_banks_7 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_35 ? regout_idx_7 : _regout_WIRE_7), // @[Mux.scala:50:70] .RW0_en (_regout_T_37 | _regout_T_35), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_7), // @[Mux.scala:50:70] .RW0_wdata (regout_data_7), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_7_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] assign io_sinkC_adr_ready = io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sinkD_adr_ready = io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_adr_ready = io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_dat_data = io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_radr_ready = io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceD_rdat_data = io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_wadr_ready = io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_4 : input clock : Clock input reset : Reset output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1]} connect io.xcpt_if, UInt<1>(0h0) connect io.xcpt_ld, UInt<1>(0h0) connect io.xcpt_st, UInt<1>(0h0) connect io.debug_if, UInt<1>(0h0) connect io.debug_ld, UInt<1>(0h0) connect io.debug_st, UInt<1>(0h0) node _en_T = eq(io.status.debug, UInt<1>(0h0)) node en_lo = cat(io.bp[0].control.s, io.bp[0].control.u) node en_hi = cat(io.bp[0].control.m, io.bp[0].control.h) node _en_T_1 = cat(en_hi, en_lo) node _en_T_2 = dshr(_en_T_1, io.status.prv) node _en_T_3 = bits(_en_T_2, 0, 0) node en = and(_en_T, _en_T_3) node cx = and(UInt<1>(0h1), UInt<1>(0h1)) node _r_T = and(en, io.bp[0].control.r) node _r_T_1 = bits(io.bp[0].control.tmatch, 1, 1) node _r_T_2 = geq(io.ea, io.bp[0].address) node _r_T_3 = bits(io.bp[0].control.tmatch, 0, 0) node _r_T_4 = xor(_r_T_2, _r_T_3) node _r_T_5 = not(io.ea) node _r_T_6 = bits(io.bp[0].control.tmatch, 0, 0) node _r_T_7 = bits(io.bp[0].address, 0, 0) node _r_T_8 = and(_r_T_6, _r_T_7) node _r_T_9 = bits(io.bp[0].address, 1, 1) node _r_T_10 = and(_r_T_8, _r_T_9) node _r_T_11 = bits(io.bp[0].address, 2, 2) node _r_T_12 = and(_r_T_10, _r_T_11) node r_lo = cat(_r_T_8, _r_T_6) node r_hi = cat(_r_T_12, _r_T_10) node _r_T_13 = cat(r_hi, r_lo) node _r_T_14 = or(_r_T_5, _r_T_13) node _r_T_15 = not(io.bp[0].address) node _r_T_16 = bits(io.bp[0].control.tmatch, 0, 0) node _r_T_17 = bits(io.bp[0].address, 0, 0) node _r_T_18 = and(_r_T_16, _r_T_17) node _r_T_19 = bits(io.bp[0].address, 1, 1) node _r_T_20 = and(_r_T_18, _r_T_19) node _r_T_21 = bits(io.bp[0].address, 2, 2) node _r_T_22 = and(_r_T_20, _r_T_21) node r_lo_1 = cat(_r_T_18, _r_T_16) node r_hi_1 = cat(_r_T_22, _r_T_20) node _r_T_23 = cat(r_hi_1, r_lo_1) node _r_T_24 = or(_r_T_15, _r_T_23) node _r_T_25 = eq(_r_T_14, _r_T_24) node _r_T_26 = mux(_r_T_1, _r_T_4, _r_T_25) node _r_T_27 = and(_r_T, _r_T_26) node r = and(_r_T_27, cx) node _w_T = and(en, io.bp[0].control.w) node _w_T_1 = bits(io.bp[0].control.tmatch, 1, 1) node _w_T_2 = geq(io.ea, io.bp[0].address) node _w_T_3 = bits(io.bp[0].control.tmatch, 0, 0) node _w_T_4 = xor(_w_T_2, _w_T_3) node _w_T_5 = not(io.ea) node _w_T_6 = bits(io.bp[0].control.tmatch, 0, 0) node _w_T_7 = bits(io.bp[0].address, 0, 0) node _w_T_8 = and(_w_T_6, _w_T_7) node _w_T_9 = bits(io.bp[0].address, 1, 1) node _w_T_10 = and(_w_T_8, _w_T_9) node _w_T_11 = bits(io.bp[0].address, 2, 2) node _w_T_12 = and(_w_T_10, _w_T_11) node w_lo = cat(_w_T_8, _w_T_6) node w_hi = cat(_w_T_12, _w_T_10) node _w_T_13 = cat(w_hi, w_lo) node _w_T_14 = or(_w_T_5, _w_T_13) node _w_T_15 = not(io.bp[0].address) node _w_T_16 = bits(io.bp[0].control.tmatch, 0, 0) node _w_T_17 = bits(io.bp[0].address, 0, 0) node _w_T_18 = and(_w_T_16, _w_T_17) node _w_T_19 = bits(io.bp[0].address, 1, 1) node _w_T_20 = and(_w_T_18, _w_T_19) node _w_T_21 = bits(io.bp[0].address, 2, 2) node _w_T_22 = and(_w_T_20, _w_T_21) node w_lo_1 = cat(_w_T_18, _w_T_16) node w_hi_1 = cat(_w_T_22, _w_T_20) node _w_T_23 = cat(w_hi_1, w_lo_1) node _w_T_24 = or(_w_T_15, _w_T_23) node _w_T_25 = eq(_w_T_14, _w_T_24) node _w_T_26 = mux(_w_T_1, _w_T_4, _w_T_25) node _w_T_27 = and(_w_T, _w_T_26) node w = and(_w_T_27, cx) node _x_T = and(en, io.bp[0].control.x) node _x_T_1 = bits(io.bp[0].control.tmatch, 1, 1) node _x_T_2 = geq(io.pc, io.bp[0].address) node _x_T_3 = bits(io.bp[0].control.tmatch, 0, 0) node _x_T_4 = xor(_x_T_2, _x_T_3) node _x_T_5 = not(io.pc) node _x_T_6 = bits(io.bp[0].control.tmatch, 0, 0) node _x_T_7 = bits(io.bp[0].address, 0, 0) node _x_T_8 = and(_x_T_6, _x_T_7) node _x_T_9 = bits(io.bp[0].address, 1, 1) node _x_T_10 = and(_x_T_8, _x_T_9) node _x_T_11 = bits(io.bp[0].address, 2, 2) node _x_T_12 = and(_x_T_10, _x_T_11) node x_lo = cat(_x_T_8, _x_T_6) node x_hi = cat(_x_T_12, _x_T_10) node _x_T_13 = cat(x_hi, x_lo) node _x_T_14 = or(_x_T_5, _x_T_13) node _x_T_15 = not(io.bp[0].address) node _x_T_16 = bits(io.bp[0].control.tmatch, 0, 0) node _x_T_17 = bits(io.bp[0].address, 0, 0) node _x_T_18 = and(_x_T_16, _x_T_17) node _x_T_19 = bits(io.bp[0].address, 1, 1) node _x_T_20 = and(_x_T_18, _x_T_19) node _x_T_21 = bits(io.bp[0].address, 2, 2) node _x_T_22 = and(_x_T_20, _x_T_21) node x_lo_1 = cat(_x_T_18, _x_T_16) node x_hi_1 = cat(_x_T_22, _x_T_20) node _x_T_23 = cat(x_hi_1, x_lo_1) node _x_T_24 = or(_x_T_15, _x_T_23) node _x_T_25 = eq(_x_T_14, _x_T_24) node _x_T_26 = mux(_x_T_1, _x_T_4, _x_T_25) node _x_T_27 = and(_x_T, _x_T_26) node x = and(_x_T_27, cx) node end = eq(io.bp[0].control.chain, UInt<1>(0h0)) connect io.bpwatch[0].action, io.bp[0].control.action connect io.bpwatch[0].valid[0], UInt<1>(0h0) connect io.bpwatch[0].rvalid[0], UInt<1>(0h0) connect io.bpwatch[0].wvalid[0], UInt<1>(0h0) connect io.bpwatch[0].ivalid[0], UInt<1>(0h0) node _T = and(end, r) node _T_1 = and(_T, UInt<1>(0h1)) when _T_1 : node _io_xcpt_ld_T = eq(io.bp[0].control.action, UInt<1>(0h0)) connect io.xcpt_ld, _io_xcpt_ld_T node _io_debug_ld_T = eq(io.bp[0].control.action, UInt<1>(0h1)) connect io.debug_ld, _io_debug_ld_T connect io.bpwatch[0].valid[0], UInt<1>(0h1) connect io.bpwatch[0].rvalid[0], UInt<1>(0h1) node _T_2 = and(end, w) node _T_3 = and(_T_2, UInt<1>(0h1)) when _T_3 : node _io_xcpt_st_T = eq(io.bp[0].control.action, UInt<1>(0h0)) connect io.xcpt_st, _io_xcpt_st_T node _io_debug_st_T = eq(io.bp[0].control.action, UInt<1>(0h1)) connect io.debug_st, _io_debug_st_T connect io.bpwatch[0].valid[0], UInt<1>(0h1) connect io.bpwatch[0].wvalid[0], UInt<1>(0h1) node _T_4 = and(end, x) node _T_5 = and(_T_4, UInt<1>(0h1)) when _T_5 : node _io_xcpt_if_T = eq(io.bp[0].control.action, UInt<1>(0h0)) connect io.xcpt_if, _io_xcpt_if_T node _io_debug_if_T = eq(io.bp[0].control.action, UInt<1>(0h1)) connect io.debug_if, _io_debug_if_T connect io.bpwatch[0].valid[0], UInt<1>(0h1) connect io.bpwatch[0].ivalid[0], UInt<1>(0h1) node _T_6 = or(end, r) node _T_7 = or(end, w) node _T_8 = or(end, x)
module BreakpointUnit_4( // @[Breakpoint.scala:79:7] input clock, // @[Breakpoint.scala:79:7] input reset, // @[Breakpoint.scala:79:7] input io_status_debug, // @[Breakpoint.scala:80:14] input io_status_cease, // @[Breakpoint.scala:80:14] input io_status_wfi, // @[Breakpoint.scala:80:14] input [31:0] io_status_isa, // @[Breakpoint.scala:80:14] input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14] input io_status_dv, // @[Breakpoint.scala:80:14] input [1:0] io_status_prv, // @[Breakpoint.scala:80:14] input io_status_v, // @[Breakpoint.scala:80:14] input io_status_sd, // @[Breakpoint.scala:80:14] input io_status_mpv, // @[Breakpoint.scala:80:14] input io_status_gva, // @[Breakpoint.scala:80:14] input io_status_tsr, // @[Breakpoint.scala:80:14] input io_status_tw, // @[Breakpoint.scala:80:14] input io_status_tvm, // @[Breakpoint.scala:80:14] input io_status_mxr, // @[Breakpoint.scala:80:14] input io_status_sum, // @[Breakpoint.scala:80:14] input io_status_mprv, // @[Breakpoint.scala:80:14] input [1:0] io_status_fs, // @[Breakpoint.scala:80:14] input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14] input io_status_spp, // @[Breakpoint.scala:80:14] input io_status_mpie, // @[Breakpoint.scala:80:14] input io_status_spie, // @[Breakpoint.scala:80:14] input io_status_mie, // @[Breakpoint.scala:80:14] input io_status_sie, // @[Breakpoint.scala:80:14] input io_bp_0_control_dmode, // @[Breakpoint.scala:80:14] input io_bp_0_control_action, // @[Breakpoint.scala:80:14] input [1:0] io_bp_0_control_tmatch, // @[Breakpoint.scala:80:14] input io_bp_0_control_m, // @[Breakpoint.scala:80:14] input io_bp_0_control_s, // @[Breakpoint.scala:80:14] input io_bp_0_control_u, // @[Breakpoint.scala:80:14] input io_bp_0_control_x, // @[Breakpoint.scala:80:14] input io_bp_0_control_w, // @[Breakpoint.scala:80:14] input io_bp_0_control_r, // @[Breakpoint.scala:80:14] input [38:0] io_bp_0_address, // @[Breakpoint.scala:80:14] input [47:0] io_bp_0_textra_pad2, // @[Breakpoint.scala:80:14] input io_bp_0_textra_pad1, // @[Breakpoint.scala:80:14] input [38:0] io_pc, // @[Breakpoint.scala:80:14] input [38:0] io_ea, // @[Breakpoint.scala:80:14] output io_xcpt_if, // @[Breakpoint.scala:80:14] output io_xcpt_ld, // @[Breakpoint.scala:80:14] output io_xcpt_st, // @[Breakpoint.scala:80:14] output io_debug_if, // @[Breakpoint.scala:80:14] output io_debug_ld, // @[Breakpoint.scala:80:14] output io_debug_st, // @[Breakpoint.scala:80:14] output io_bpwatch_0_rvalid_0, // @[Breakpoint.scala:80:14] output io_bpwatch_0_wvalid_0, // @[Breakpoint.scala:80:14] output io_bpwatch_0_ivalid_0 // @[Breakpoint.scala:80:14] ); wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7] wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7] wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7] wire [31:0] io_status_isa_0 = io_status_isa; // @[Breakpoint.scala:79:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7] wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7] wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7] wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7] wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7] wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7] wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7] wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7] wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7] wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7] wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7] wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7] wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7] wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7] wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7] wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7] wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7] wire io_bp_0_control_dmode_0 = io_bp_0_control_dmode; // @[Breakpoint.scala:79:7] wire io_bp_0_control_action_0 = io_bp_0_control_action; // @[Breakpoint.scala:79:7] wire [1:0] io_bp_0_control_tmatch_0 = io_bp_0_control_tmatch; // @[Breakpoint.scala:79:7] wire io_bp_0_control_m_0 = io_bp_0_control_m; // @[Breakpoint.scala:79:7] wire io_bp_0_control_s_0 = io_bp_0_control_s; // @[Breakpoint.scala:79:7] wire io_bp_0_control_u_0 = io_bp_0_control_u; // @[Breakpoint.scala:79:7] wire io_bp_0_control_x_0 = io_bp_0_control_x; // @[Breakpoint.scala:79:7] wire io_bp_0_control_w_0 = io_bp_0_control_w; // @[Breakpoint.scala:79:7] wire io_bp_0_control_r_0 = io_bp_0_control_r; // @[Breakpoint.scala:79:7] wire [38:0] io_bp_0_address_0 = io_bp_0_address; // @[Breakpoint.scala:79:7] wire [47:0] io_bp_0_textra_pad2_0 = io_bp_0_textra_pad2; // @[Breakpoint.scala:79:7] wire io_bp_0_textra_pad1_0 = io_bp_0_textra_pad1; // @[Breakpoint.scala:79:7] wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7] wire [38:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7] wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire cx = 1'h1; // @[Breakpoint.scala:55:126] wire end_0 = 1'h1; // @[Breakpoint.scala:109:15] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[Breakpoint.scala:79:7, :80:14] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[Breakpoint.scala:79:7, :80:14] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_bp_0_control_zero = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14] wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_control_chain = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_control_h = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_textra_mselect = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_textra_sselect = 1'h0; // @[Breakpoint.scala:79:7] wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14] wire _io_debug_ld_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:84] wire _io_debug_st_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :119:84] wire _io_debug_if_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :120:84] wire r; // @[Breakpoint.scala:106:58] wire w; // @[Breakpoint.scala:107:58] wire x; // @[Breakpoint.scala:108:58] wire io_bpwatch_0_valid_0; // @[Breakpoint.scala:79:7] wire io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7] wire io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7] wire io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7] wire [2:0] io_bpwatch_0_action; // @[Breakpoint.scala:79:7] wire io_xcpt_if_0; // @[Breakpoint.scala:79:7] wire io_xcpt_ld_0; // @[Breakpoint.scala:79:7] wire io_xcpt_st_0; // @[Breakpoint.scala:79:7] wire io_debug_if_0; // @[Breakpoint.scala:79:7] wire io_debug_ld_0; // @[Breakpoint.scala:79:7] wire io_debug_st_0; // @[Breakpoint.scala:79:7] wire _en_T = ~io_status_debug_0; // @[Breakpoint.scala:30:35, :79:7] wire [1:0] en_lo = {io_bp_0_control_s_0, io_bp_0_control_u_0}; // @[Breakpoint.scala:30:56, :79:7] wire [1:0] en_hi = {io_bp_0_control_m_0, 1'h0}; // @[Breakpoint.scala:30:56, :79:7] wire [3:0] _en_T_1 = {en_hi, en_lo}; // @[Breakpoint.scala:30:56] wire [3:0] _en_T_2 = _en_T_1 >> io_status_prv_0; // @[Breakpoint.scala:30:{56,68}, :79:7] wire _en_T_3 = _en_T_2[0]; // @[Breakpoint.scala:30:68] wire en = _en_T & _en_T_3; // @[Breakpoint.scala:30:{35,50,68}] wire _r_T = en & io_bp_0_control_r_0; // @[Breakpoint.scala:30:50, :79:7, :106:16] wire _r_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7] wire _w_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7] wire _x_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7] wire _GEN = io_ea_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7] wire _r_T_2; // @[Breakpoint.scala:65:8] assign _r_T_2 = _GEN; // @[Breakpoint.scala:65:8] wire _w_T_2; // @[Breakpoint.scala:65:8] assign _w_T_2 = _GEN; // @[Breakpoint.scala:65:8] wire _r_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7] wire _r_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _r_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _w_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7] wire _w_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _w_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _x_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7] wire _x_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _x_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _r_T_4 = _r_T_2 ^ _r_T_3; // @[Breakpoint.scala:65:{8,20,36}] wire [38:0] _r_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7] wire _r_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_8 = _r_T_6 & _r_T_7; // @[Breakpoint.scala:59:{56,73,83}] wire _r_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_10 = _r_T_8 & _r_T_9; // @[Breakpoint.scala:59:{73,83}] wire _r_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_12 = _r_T_10 & _r_T_11; // @[Breakpoint.scala:59:{73,83}] wire [1:0] r_lo = {_r_T_8, _r_T_6}; // @[package.scala:45:27] wire [1:0] r_hi = {_r_T_12, _r_T_10}; // @[package.scala:45:27] wire [3:0] _r_T_13 = {r_hi, r_lo}; // @[package.scala:45:27] wire [38:0] _r_T_14 = {_r_T_5[38:4], _r_T_5[3:0] | _r_T_13}; // @[package.scala:45:27] wire [38:0] _r_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7] wire _r_T_18 = _r_T_16 & _r_T_17; // @[Breakpoint.scala:59:{56,73,83}] wire _r_T_20 = _r_T_18 & _r_T_19; // @[Breakpoint.scala:59:{73,83}] wire _r_T_22 = _r_T_20 & _r_T_21; // @[Breakpoint.scala:59:{73,83}] wire [1:0] r_lo_1 = {_r_T_18, _r_T_16}; // @[package.scala:45:27] wire [1:0] r_hi_1 = {_r_T_22, _r_T_20}; // @[package.scala:45:27] wire [3:0] _r_T_23 = {r_hi_1, r_lo_1}; // @[package.scala:45:27] wire [38:0] _r_T_24 = {_r_T_15[38:4], _r_T_15[3:0] | _r_T_23}; // @[package.scala:45:27] wire _r_T_25 = _r_T_14 == _r_T_24; // @[Breakpoint.scala:62:{9,19,33}] wire _r_T_26 = _r_T_1 ? _r_T_4 : _r_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}] wire _r_T_27 = _r_T & _r_T_26; // @[Breakpoint.scala:68:8, :106:{16,32}] assign r = _r_T_27; // @[Breakpoint.scala:106:{32,58}] assign io_bpwatch_0_rvalid_0_0 = r; // @[Breakpoint.scala:79:7, :106:58] wire _w_T = en & io_bp_0_control_w_0; // @[Breakpoint.scala:30:50, :79:7, :107:16] wire _w_T_4 = _w_T_2 ^ _w_T_3; // @[Breakpoint.scala:65:{8,20,36}] wire [38:0] _w_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7] wire _w_T_8 = _w_T_6 & _w_T_7; // @[Breakpoint.scala:59:{56,73,83}] wire _w_T_10 = _w_T_8 & _w_T_9; // @[Breakpoint.scala:59:{73,83}] wire _w_T_12 = _w_T_10 & _w_T_11; // @[Breakpoint.scala:59:{73,83}] wire [1:0] w_lo = {_w_T_8, _w_T_6}; // @[package.scala:45:27] wire [1:0] w_hi = {_w_T_12, _w_T_10}; // @[package.scala:45:27] wire [3:0] _w_T_13 = {w_hi, w_lo}; // @[package.scala:45:27] wire [38:0] _w_T_14 = {_w_T_5[38:4], _w_T_5[3:0] | _w_T_13}; // @[package.scala:45:27] wire [38:0] _w_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7] wire _w_T_18 = _w_T_16 & _w_T_17; // @[Breakpoint.scala:59:{56,73,83}] wire _w_T_20 = _w_T_18 & _w_T_19; // @[Breakpoint.scala:59:{73,83}] wire _w_T_22 = _w_T_20 & _w_T_21; // @[Breakpoint.scala:59:{73,83}] wire [1:0] w_lo_1 = {_w_T_18, _w_T_16}; // @[package.scala:45:27] wire [1:0] w_hi_1 = {_w_T_22, _w_T_20}; // @[package.scala:45:27] wire [3:0] _w_T_23 = {w_hi_1, w_lo_1}; // @[package.scala:45:27] wire [38:0] _w_T_24 = {_w_T_15[38:4], _w_T_15[3:0] | _w_T_23}; // @[package.scala:45:27] wire _w_T_25 = _w_T_14 == _w_T_24; // @[Breakpoint.scala:62:{9,19,33}] wire _w_T_26 = _w_T_1 ? _w_T_4 : _w_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}] wire _w_T_27 = _w_T & _w_T_26; // @[Breakpoint.scala:68:8, :107:{16,32}] assign w = _w_T_27; // @[Breakpoint.scala:107:{32,58}] assign io_bpwatch_0_wvalid_0_0 = w; // @[Breakpoint.scala:79:7, :107:58] wire _x_T = en & io_bp_0_control_x_0; // @[Breakpoint.scala:30:50, :79:7, :108:16] wire _x_T_2 = io_pc_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7] wire _x_T_4 = _x_T_2 ^ _x_T_3; // @[Breakpoint.scala:65:{8,20,36}] wire [38:0] _x_T_5 = ~io_pc_0; // @[Breakpoint.scala:62:6, :79:7] wire _x_T_8 = _x_T_6 & _x_T_7; // @[Breakpoint.scala:59:{56,73,83}] wire _x_T_10 = _x_T_8 & _x_T_9; // @[Breakpoint.scala:59:{73,83}] wire _x_T_12 = _x_T_10 & _x_T_11; // @[Breakpoint.scala:59:{73,83}] wire [1:0] x_lo = {_x_T_8, _x_T_6}; // @[package.scala:45:27] wire [1:0] x_hi = {_x_T_12, _x_T_10}; // @[package.scala:45:27] wire [3:0] _x_T_13 = {x_hi, x_lo}; // @[package.scala:45:27] wire [38:0] _x_T_14 = {_x_T_5[38:4], _x_T_5[3:0] | _x_T_13}; // @[package.scala:45:27] wire [38:0] _x_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7] wire _x_T_18 = _x_T_16 & _x_T_17; // @[Breakpoint.scala:59:{56,73,83}] wire _x_T_20 = _x_T_18 & _x_T_19; // @[Breakpoint.scala:59:{73,83}] wire _x_T_22 = _x_T_20 & _x_T_21; // @[Breakpoint.scala:59:{73,83}] wire [1:0] x_lo_1 = {_x_T_18, _x_T_16}; // @[package.scala:45:27] wire [1:0] x_hi_1 = {_x_T_22, _x_T_20}; // @[package.scala:45:27] wire [3:0] _x_T_23 = {x_hi_1, x_lo_1}; // @[package.scala:45:27] wire [38:0] _x_T_24 = {_x_T_15[38:4], _x_T_15[3:0] | _x_T_23}; // @[package.scala:45:27] wire _x_T_25 = _x_T_14 == _x_T_24; // @[Breakpoint.scala:62:{9,19,33}] wire _x_T_26 = _x_T_1 ? _x_T_4 : _x_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}] wire _x_T_27 = _x_T & _x_T_26; // @[Breakpoint.scala:68:8, :108:{16,32}] assign x = _x_T_27; // @[Breakpoint.scala:108:{32,58}] assign io_bpwatch_0_ivalid_0_0 = x; // @[Breakpoint.scala:79:7, :108:58] assign io_bpwatch_0_action = {2'h0, io_bp_0_control_action_0}; // @[Breakpoint.scala:79:7, :80:14, :112:16] wire _io_xcpt_ld_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51] assign io_xcpt_ld_0 = r & _io_xcpt_ld_T; // @[Breakpoint.scala:79:7, :97:14, :106:58, :118:{27,40,51}] assign io_debug_ld_0 = r & _io_debug_ld_T; // @[Breakpoint.scala:79:7, :100:15, :106:58, :118:{27,73,84}] wire _io_xcpt_st_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :119:51] assign io_xcpt_st_0 = w & _io_xcpt_st_T; // @[Breakpoint.scala:79:7, :98:14, :107:58, :119:{27,40,51}] assign io_debug_st_0 = w & _io_debug_st_T; // @[Breakpoint.scala:79:7, :101:15, :107:58, :119:{27,73,84}] wire _io_xcpt_if_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :120:51] assign io_xcpt_if_0 = x & _io_xcpt_if_T; // @[Breakpoint.scala:79:7, :96:14, :108:58, :120:{27,40,51}] assign io_debug_if_0 = x & _io_debug_if_T; // @[Breakpoint.scala:79:7, :99:15, :108:58, :120:{27,73,84}] assign io_bpwatch_0_valid_0 = x | w | r; // @[Breakpoint.scala:79:7, :106:58, :107:58, :108:58, :118:27, :119:{27,107}, :120:{27,107}] assign io_xcpt_if = io_xcpt_if_0; // @[Breakpoint.scala:79:7] assign io_xcpt_ld = io_xcpt_ld_0; // @[Breakpoint.scala:79:7] assign io_xcpt_st = io_xcpt_st_0; // @[Breakpoint.scala:79:7] assign io_debug_if = io_debug_if_0; // @[Breakpoint.scala:79:7] assign io_debug_ld = io_debug_ld_0; // @[Breakpoint.scala:79:7] assign io_debug_st = io_debug_st_0; // @[Breakpoint.scala:79:7] assign io_bpwatch_0_rvalid_0 = io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7] assign io_bpwatch_0_wvalid_0 = io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7] assign io_bpwatch_0_ivalid_0 = io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_device_named_uart_0 : input clock : Clock input reset : Reset output auto : { control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_UART connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn connect fragmenter.auto.anon_in, tlOut connect fragmenter.auto.anon_out.d, controlXingIn.d connect controlXingIn.a.bits, fragmenter.auto.anon_out.a.bits connect controlXingIn.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, controlXingIn.a.ready connect tlIn, auto.tl_in connect auto.control_xing_out, controlXingOut extmodule plusarg_reader_20 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_21 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLInterconnectCoupler_pbus_to_device_named_uart_0( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire [6:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire auto_control_xing_out_a_ready_0 = auto_control_xing_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_control_xing_out_d_valid_0 = auto_control_xing_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_control_xing_out_d_bits_opcode_0 = auto_control_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_control_xing_out_d_bits_size_0 = auto_control_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [10:0] auto_control_xing_out_d_bits_source_0 = auto_control_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_control_xing_out_d_bits_data_0 = auto_control_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [6:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_control_xing_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_control_xing_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_control_xing_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire controlXingOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire controlXingOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire controlXingOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire controlXingIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire controlXingIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire controlXingIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_control_xing_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire controlXingOut_a_ready = auto_control_xing_out_a_ready_0; // @[MixedNode.scala:542:17] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire controlXingOut_d_valid = auto_control_xing_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] controlXingOut_d_bits_opcode = auto_control_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] controlXingOut_d_bits_size = auto_control_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [10:0] controlXingOut_d_bits_source = auto_control_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [63:0] controlXingOut_d_bits_data = auto_control_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [6:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [28:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire [2:0] auto_control_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_control_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_control_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [10:0] auto_control_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_control_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_control_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_control_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_control_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_control_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_control_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [6:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire controlXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_valid_0 = controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] controlXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_opcode_0 = controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] controlXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_param_0 = controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_size_0 = controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] controlXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_source_0 = controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] controlXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_address_0 = controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] controlXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_mask_0 = controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] controlXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_data_0 = controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire controlXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_control_xing_out_a_bits_corrupt_0 = controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire controlXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_control_xing_out_d_ready_0 = controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [10:0] controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [63:0] controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] TLFragmenter_UART fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_out_a_ready (controlXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (controlXingIn_a_valid), .auto_anon_out_a_bits_opcode (controlXingIn_a_bits_opcode), .auto_anon_out_a_bits_param (controlXingIn_a_bits_param), .auto_anon_out_a_bits_size (controlXingIn_a_bits_size), .auto_anon_out_a_bits_source (controlXingIn_a_bits_source), .auto_anon_out_a_bits_address (controlXingIn_a_bits_address), .auto_anon_out_a_bits_mask (controlXingIn_a_bits_mask), .auto_anon_out_a_bits_data (controlXingIn_a_bits_data), .auto_anon_out_a_bits_corrupt (controlXingIn_a_bits_corrupt), .auto_anon_out_d_ready (controlXingIn_d_ready), .auto_anon_out_d_valid (controlXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (controlXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (controlXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (controlXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (controlXingIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Fragmenter.scala:345:34] assign auto_control_xing_out_a_valid = auto_control_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_opcode = auto_control_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_param = auto_control_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_size = auto_control_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_source = auto_control_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_address = auto_control_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_mask = auto_control_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_data = auto_control_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_a_bits_corrupt = auto_control_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_control_xing_out_d_ready = auto_control_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_115 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_116 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_7 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_7 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut
module DivSqrtRecFMToRaw_small_e5_s11_7( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_7 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NBDTLB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}[1], miss_rdy : UInt<1>, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.gstatus.uie invalidate io.ptw.gstatus.sie invalidate io.ptw.gstatus.hie invalidate io.ptw.gstatus.mie invalidate io.ptw.gstatus.upie invalidate io.ptw.gstatus.spie invalidate io.ptw.gstatus.ube invalidate io.ptw.gstatus.mpie invalidate io.ptw.gstatus.spp invalidate io.ptw.gstatus.vs invalidate io.ptw.gstatus.mpp invalidate io.ptw.gstatus.fs invalidate io.ptw.gstatus.xs invalidate io.ptw.gstatus.mprv invalidate io.ptw.gstatus.sum invalidate io.ptw.gstatus.mxr invalidate io.ptw.gstatus.tvm invalidate io.ptw.gstatus.tw invalidate io.ptw.gstatus.tsr invalidate io.ptw.gstatus.zero1 invalidate io.ptw.gstatus.sd_rv32 invalidate io.ptw.gstatus.uxl invalidate io.ptw.gstatus.sxl invalidate io.ptw.gstatus.sbe invalidate io.ptw.gstatus.mbe invalidate io.ptw.gstatus.gva invalidate io.ptw.gstatus.mpv invalidate io.ptw.gstatus.zero2 invalidate io.ptw.gstatus.sd invalidate io.ptw.gstatus.v invalidate io.ptw.gstatus.prv invalidate io.ptw.gstatus.dv invalidate io.ptw.gstatus.dprv invalidate io.ptw.gstatus.isa invalidate io.ptw.gstatus.wfi invalidate io.ptw.gstatus.cease invalidate io.ptw.gstatus.debug invalidate io.ptw.hstatus.zero1 invalidate io.ptw.hstatus.vsbe invalidate io.ptw.hstatus.gva invalidate io.ptw.hstatus.spv invalidate io.ptw.hstatus.spvp invalidate io.ptw.hstatus.hu invalidate io.ptw.hstatus.zero2 invalidate io.ptw.hstatus.vgein invalidate io.ptw.hstatus.zero3 invalidate io.ptw.hstatus.vtvm invalidate io.ptw.hstatus.vtw invalidate io.ptw.hstatus.vtsr invalidate io.ptw.hstatus.zero5 invalidate io.ptw.hstatus.vsxl invalidate io.ptw.hstatus.zero6 invalidate io.ptw.status.uie invalidate io.ptw.status.sie invalidate io.ptw.status.hie invalidate io.ptw.status.mie invalidate io.ptw.status.upie invalidate io.ptw.status.spie invalidate io.ptw.status.ube invalidate io.ptw.status.mpie invalidate io.ptw.status.spp invalidate io.ptw.status.vs invalidate io.ptw.status.mpp invalidate io.ptw.status.fs invalidate io.ptw.status.xs invalidate io.ptw.status.mprv invalidate io.ptw.status.sum invalidate io.ptw.status.mxr invalidate io.ptw.status.tvm invalidate io.ptw.status.tw invalidate io.ptw.status.tsr invalidate io.ptw.status.zero1 invalidate io.ptw.status.sd_rv32 invalidate io.ptw.status.uxl invalidate io.ptw.status.sxl invalidate io.ptw.status.sbe invalidate io.ptw.status.mbe invalidate io.ptw.status.gva invalidate io.ptw.status.mpv invalidate io.ptw.status.zero2 invalidate io.ptw.status.sd invalidate io.ptw.status.v invalidate io.ptw.status.prv invalidate io.ptw.status.dv invalidate io.ptw.status.dprv invalidate io.ptw.status.isa invalidate io.ptw.status.wfi invalidate io.ptw.status.cease invalidate io.ptw.status.debug invalidate io.ptw.vsatp.ppn invalidate io.ptw.vsatp.asid invalidate io.ptw.vsatp.mode invalidate io.ptw.hgatp.ppn invalidate io.ptw.hgatp.asid invalidate io.ptw.hgatp.mode invalidate io.ptw.ptbr.ppn invalidate io.ptw.ptbr.asid invalidate io.ptw.ptbr.mode invalidate io.ptw.resp.bits.gpa_is_pte invalidate io.ptw.resp.bits.gpa.bits invalidate io.ptw.resp.bits.gpa.valid invalidate io.ptw.resp.bits.homogeneous invalidate io.ptw.resp.bits.fragmented_superpage invalidate io.ptw.resp.bits.level invalidate io.ptw.resp.bits.pte.v invalidate io.ptw.resp.bits.pte.r invalidate io.ptw.resp.bits.pte.w invalidate io.ptw.resp.bits.pte.x invalidate io.ptw.resp.bits.pte.u invalidate io.ptw.resp.bits.pte.g invalidate io.ptw.resp.bits.pte.a invalidate io.ptw.resp.bits.pte.d invalidate io.ptw.resp.bits.pte.reserved_for_software invalidate io.ptw.resp.bits.pte.ppn invalidate io.ptw.resp.bits.pte.reserved_for_future invalidate io.ptw.resp.bits.hx invalidate io.ptw.resp.bits.hw invalidate io.ptw.resp.bits.hr invalidate io.ptw.resp.bits.gf invalidate io.ptw.resp.bits.pf invalidate io.ptw.resp.bits.ae_final invalidate io.ptw.resp.bits.ae_ptw invalidate io.ptw.resp.valid invalidate io.ptw.req.bits.bits.stage2 invalidate io.ptw.req.bits.bits.vstage1 invalidate io.ptw.req.bits.bits.need_gpa invalidate io.ptw.req.bits.bits.addr invalidate io.ptw.req.bits.valid invalidate io.ptw.req.valid invalidate io.ptw.req.ready invalidate io.resp[0].cmd invalidate io.resp[0].size invalidate io.resp[0].prefetchable invalidate io.resp[0].must_alloc invalidate io.resp[0].cacheable invalidate io.resp[0].ma.inst invalidate io.resp[0].ma.st invalidate io.resp[0].ma.ld invalidate io.resp[0].ae.inst invalidate io.resp[0].ae.st invalidate io.resp[0].ae.ld invalidate io.resp[0].gf.inst invalidate io.resp[0].gf.st invalidate io.resp[0].gf.ld invalidate io.resp[0].pf.inst invalidate io.resp[0].pf.st invalidate io.resp[0].pf.ld invalidate io.resp[0].gpa_is_pte invalidate io.resp[0].gpa invalidate io.resp[0].paddr invalidate io.resp[0].miss reg sectored_entries : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[4], valid : UInt<1>[4]}[8], clock reg superpage_entries : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<21>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit_addr : UInt<3>, clock reg r_sectored_hit : UInt<1>, clock node priv_s = bits(io.ptw.status.dprv, 0, 0) node priv_uses_vm = leq(io.ptw.status.dprv, UInt<1>(0h1)) node _vm_enabled_T = bits(io.ptw.ptbr.mode, 3, 3) node _vm_enabled_T_1 = and(UInt<1>(0h0), _vm_enabled_T) node _vm_enabled_T_2 = and(_vm_enabled_T_1, priv_uses_vm) node _vm_enabled_T_3 = eq(io.req[0].bits.passthrough, UInt<1>(0h0)) node _vm_enabled_T_4 = and(_vm_enabled_T_2, _vm_enabled_T_3) wire vm_enabled : UInt<1>[1] connect vm_enabled[0], _vm_enabled_T_4 node _vpn_T = bits(io.req[0].bits.vaddr, 32, 12) wire vpn : UInt<21>[1] connect vpn[0], _vpn_T node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled[0], UInt<1>(0h1)) wire _mpu_ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_data_WIRE_1 : UInt<34> connect _mpu_ppn_data_WIRE_1, special_entry.data[0] node _mpu_ppn_data_T = bits(_mpu_ppn_data_WIRE_1, 0, 0) connect _mpu_ppn_data_WIRE.fragmented_superpage, _mpu_ppn_data_T node _mpu_ppn_data_T_1 = bits(_mpu_ppn_data_WIRE_1, 1, 1) connect _mpu_ppn_data_WIRE.c, _mpu_ppn_data_T_1 node _mpu_ppn_data_T_2 = bits(_mpu_ppn_data_WIRE_1, 2, 2) connect _mpu_ppn_data_WIRE.eff, _mpu_ppn_data_T_2 node _mpu_ppn_data_T_3 = bits(_mpu_ppn_data_WIRE_1, 3, 3) connect _mpu_ppn_data_WIRE.paa, _mpu_ppn_data_T_3 node _mpu_ppn_data_T_4 = bits(_mpu_ppn_data_WIRE_1, 4, 4) connect _mpu_ppn_data_WIRE.pal, _mpu_ppn_data_T_4 node _mpu_ppn_data_T_5 = bits(_mpu_ppn_data_WIRE_1, 5, 5) connect _mpu_ppn_data_WIRE.pr, _mpu_ppn_data_T_5 node _mpu_ppn_data_T_6 = bits(_mpu_ppn_data_WIRE_1, 6, 6) connect _mpu_ppn_data_WIRE.px, _mpu_ppn_data_T_6 node _mpu_ppn_data_T_7 = bits(_mpu_ppn_data_WIRE_1, 7, 7) connect _mpu_ppn_data_WIRE.pw, _mpu_ppn_data_T_7 node _mpu_ppn_data_T_8 = bits(_mpu_ppn_data_WIRE_1, 8, 8) connect _mpu_ppn_data_WIRE.sr, _mpu_ppn_data_T_8 node _mpu_ppn_data_T_9 = bits(_mpu_ppn_data_WIRE_1, 9, 9) connect _mpu_ppn_data_WIRE.sx, _mpu_ppn_data_T_9 node _mpu_ppn_data_T_10 = bits(_mpu_ppn_data_WIRE_1, 10, 10) connect _mpu_ppn_data_WIRE.sw, _mpu_ppn_data_T_10 node _mpu_ppn_data_T_11 = bits(_mpu_ppn_data_WIRE_1, 11, 11) connect _mpu_ppn_data_WIRE.ae, _mpu_ppn_data_T_11 node _mpu_ppn_data_T_12 = bits(_mpu_ppn_data_WIRE_1, 12, 12) connect _mpu_ppn_data_WIRE.g, _mpu_ppn_data_T_12 node _mpu_ppn_data_T_13 = bits(_mpu_ppn_data_WIRE_1, 13, 13) connect _mpu_ppn_data_WIRE.u, _mpu_ppn_data_T_13 node _mpu_ppn_data_T_14 = bits(_mpu_ppn_data_WIRE_1, 33, 14) connect _mpu_ppn_data_WIRE.ppn, _mpu_ppn_data_T_14 inst mpu_ppn_data_barrier of OptimizationBarrier_EntryData connect mpu_ppn_data_barrier.clock, clock connect mpu_ppn_data_barrier.reset, reset connect mpu_ppn_data_barrier.io.x.fragmented_superpage, _mpu_ppn_data_WIRE.fragmented_superpage connect mpu_ppn_data_barrier.io.x.c, _mpu_ppn_data_WIRE.c connect mpu_ppn_data_barrier.io.x.eff, _mpu_ppn_data_WIRE.eff connect mpu_ppn_data_barrier.io.x.paa, _mpu_ppn_data_WIRE.paa connect mpu_ppn_data_barrier.io.x.pal, _mpu_ppn_data_WIRE.pal connect mpu_ppn_data_barrier.io.x.pr, _mpu_ppn_data_WIRE.pr connect mpu_ppn_data_barrier.io.x.px, _mpu_ppn_data_WIRE.px connect mpu_ppn_data_barrier.io.x.pw, _mpu_ppn_data_WIRE.pw connect mpu_ppn_data_barrier.io.x.sr, _mpu_ppn_data_WIRE.sr connect mpu_ppn_data_barrier.io.x.sx, _mpu_ppn_data_WIRE.sx connect mpu_ppn_data_barrier.io.x.sw, _mpu_ppn_data_WIRE.sw connect mpu_ppn_data_barrier.io.x.ae, _mpu_ppn_data_WIRE.ae connect mpu_ppn_data_barrier.io.x.g, _mpu_ppn_data_WIRE.g connect mpu_ppn_data_barrier.io.x.u, _mpu_ppn_data_WIRE.u connect mpu_ppn_data_barrier.io.x.ppn, _mpu_ppn_data_WIRE.ppn node _mpu_ppn_T_1 = shr(io.req[0].bits.vaddr, 12) node _mpu_ppn_T_2 = mux(_mpu_ppn_T, mpu_ppn_data_barrier.io.y.ppn, _mpu_ppn_T_1) node _mpu_ppn_T_3 = mux(do_refill, refill_ppn, _mpu_ppn_T_2) wire mpu_ppn : UInt<22>[1] connect mpu_ppn[0], _mpu_ppn_T_3 node _mpu_physaddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _mpu_physaddr_T_1 = cat(mpu_ppn[0], _mpu_physaddr_T) wire mpu_physaddr : UInt<34>[1] connect mpu_physaddr[0], _mpu_physaddr_T_1 inst pmp_0 of PMPChecker_s3 connect pmp_0.clock, clock connect pmp_0.reset, reset connect pmp_0.io.addr, mpu_physaddr[0] connect pmp_0.io.size, io.req[0].bits.size node _pmp_0_io_prv_T = or(do_refill, io.req[0].bits.passthrough) node _pmp_0_io_prv_T_1 = and(UInt<1>(0h0), _pmp_0_io_prv_T) node _pmp_0_io_prv_T_2 = mux(_pmp_0_io_prv_T_1, UInt<1>(0h1), io.ptw.status.dprv) connect pmp_0.io.prv, _pmp_0_io_prv_T_2 node _legal_address_T = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(mpu_physaddr[0], UInt<21>(0h110000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<13>(0h1000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<29>(0h10000000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[5] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 node _legal_address_T_25 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_26 = or(_legal_address_T_25, _legal_address_WIRE[2]) node _legal_address_T_27 = or(_legal_address_T_26, _legal_address_WIRE[3]) node _legal_address_T_28 = or(_legal_address_T_27, _legal_address_WIRE[4]) wire legal_address : UInt<1>[1] connect legal_address[0], _legal_address_T_28 node _cacheable_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _cacheable_T_1 = cvt(_cacheable_T) node _cacheable_T_2 = and(_cacheable_T_1, asSInt(UInt<33>(0h80000000))) node _cacheable_T_3 = asSInt(_cacheable_T_2) node _cacheable_T_4 = eq(_cacheable_T_3, asSInt(UInt<1>(0h0))) node _cacheable_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _cacheable_T_6 = cvt(_cacheable_T_5) node _cacheable_T_7 = and(_cacheable_T_6, asSInt(UInt<33>(0h80000000))) node _cacheable_T_8 = asSInt(_cacheable_T_7) node _cacheable_T_9 = eq(_cacheable_T_8, asSInt(UInt<1>(0h0))) node _cacheable_T_10 = mux(_cacheable_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _cacheable_T_11 = mux(_cacheable_T_9, UInt<1>(0h1), UInt<1>(0h0)) node _cacheable_T_12 = or(_cacheable_T_10, _cacheable_T_11) wire _cacheable_WIRE : UInt<1> connect _cacheable_WIRE, _cacheable_T_12 node _cacheable_T_13 = and(legal_address[0], _cacheable_WIRE) node _cacheable_T_14 = and(_cacheable_T_13, UInt<1>(0h1)) wire cacheable : UInt<1>[1] connect cacheable[0], _cacheable_T_14 node _homogeneous_T = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<13>(0h1000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<13>(0h1000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_21 = or(_homogeneous_T_20, _homogeneous_T_9) node _homogeneous_T_22 = or(_homogeneous_T_21, _homogeneous_T_14) node _homogeneous_T_23 = or(_homogeneous_T_22, _homogeneous_T_19) node _homogeneous_T_24 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_25 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_26 = xor(mpu_physaddr[0], UInt<1>(0h0)) node _homogeneous_T_27 = cvt(_homogeneous_T_26) node _homogeneous_T_28 = and(_homogeneous_T_27, asSInt(UInt<33>(0h80002000))) node _homogeneous_T_29 = asSInt(_homogeneous_T_28) node _homogeneous_T_30 = eq(_homogeneous_T_29, asSInt(UInt<1>(0h0))) node _homogeneous_T_31 = or(UInt<1>(0h0), _homogeneous_T_30) node _homogeneous_T_32 = eq(_homogeneous_T_31, UInt<1>(0h0)) node _homogeneous_T_33 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_34 = cvt(_homogeneous_T_33) node _homogeneous_T_35 = and(_homogeneous_T_34, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_36 = asSInt(_homogeneous_T_35) node _homogeneous_T_37 = eq(_homogeneous_T_36, asSInt(UInt<1>(0h0))) node _homogeneous_T_38 = or(UInt<1>(0h0), _homogeneous_T_37) node _homogeneous_T_39 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_40 = eq(UInt<1>(0h0), UInt<1>(0h0)) wire homogeneous : UInt<1>[1] connect homogeneous[0], _homogeneous_T_23 node _prot_r_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_r_T_1 = cvt(_prot_r_T) node _prot_r_T_2 = and(_prot_r_T_1, asSInt(UInt<1>(0h0))) node _prot_r_T_3 = asSInt(_prot_r_T_2) node _prot_r_T_4 = eq(_prot_r_T_3, asSInt(UInt<1>(0h0))) node _prot_r_T_5 = and(legal_address[0], UInt<1>(0h1)) node _prot_r_T_6 = and(_prot_r_T_5, pmp_0.io.r) wire prot_r : UInt<1>[1] connect prot_r[0], _prot_r_T_6 node _prot_w_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_w_T_1 = cvt(_prot_w_T) node _prot_w_T_2 = and(_prot_w_T_1, asSInt(UInt<1>(0h0))) node _prot_w_T_3 = asSInt(_prot_w_T_2) node _prot_w_T_4 = eq(_prot_w_T_3, asSInt(UInt<1>(0h0))) node _prot_w_T_5 = and(legal_address[0], UInt<1>(0h1)) node _prot_w_T_6 = and(_prot_w_T_5, pmp_0.io.w) wire prot_w : UInt<1>[1] connect prot_w[0], _prot_w_T_6 node _prot_al_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_al_T_1 = cvt(_prot_al_T) node _prot_al_T_2 = and(_prot_al_T_1, asSInt(UInt<1>(0h0))) node _prot_al_T_3 = asSInt(_prot_al_T_2) node _prot_al_T_4 = eq(_prot_al_T_3, asSInt(UInt<1>(0h0))) node _prot_al_T_5 = and(legal_address[0], UInt<1>(0h1)) wire prot_al : UInt<1>[1] connect prot_al[0], _prot_al_T_5 node _prot_aa_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_aa_T_1 = cvt(_prot_aa_T) node _prot_aa_T_2 = and(_prot_aa_T_1, asSInt(UInt<1>(0h0))) node _prot_aa_T_3 = asSInt(_prot_aa_T_2) node _prot_aa_T_4 = eq(_prot_aa_T_3, asSInt(UInt<1>(0h0))) node _prot_aa_T_5 = and(legal_address[0], UInt<1>(0h1)) wire prot_aa : UInt<1>[1] connect prot_aa[0], _prot_aa_T_5 node _prot_x_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_x_T_1 = cvt(_prot_x_T) node _prot_x_T_2 = and(_prot_x_T_1, asSInt(UInt<33>(0h80110000))) node _prot_x_T_3 = asSInt(_prot_x_T_2) node _prot_x_T_4 = eq(_prot_x_T_3, asSInt(UInt<1>(0h0))) node _prot_x_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_x_T_6 = cvt(_prot_x_T_5) node _prot_x_T_7 = and(_prot_x_T_6, asSInt(UInt<33>(0h80000000))) node _prot_x_T_8 = asSInt(_prot_x_T_7) node _prot_x_T_9 = eq(_prot_x_T_8, asSInt(UInt<1>(0h0))) node _prot_x_T_10 = or(_prot_x_T_4, _prot_x_T_9) node _prot_x_T_11 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_x_T_12 = cvt(_prot_x_T_11) node _prot_x_T_13 = and(_prot_x_T_12, asSInt(UInt<33>(0h80110000))) node _prot_x_T_14 = asSInt(_prot_x_T_13) node _prot_x_T_15 = eq(_prot_x_T_14, asSInt(UInt<1>(0h0))) node _prot_x_T_16 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_x_T_17 = cvt(_prot_x_T_16) node _prot_x_T_18 = and(_prot_x_T_17, asSInt(UInt<33>(0h80100000))) node _prot_x_T_19 = asSInt(_prot_x_T_18) node _prot_x_T_20 = eq(_prot_x_T_19, asSInt(UInt<1>(0h0))) node _prot_x_T_21 = or(_prot_x_T_15, _prot_x_T_20) node _prot_x_T_22 = mux(_prot_x_T_10, UInt<1>(0h1), UInt<1>(0h0)) node _prot_x_T_23 = mux(_prot_x_T_21, UInt<1>(0h0), UInt<1>(0h0)) node _prot_x_T_24 = or(_prot_x_T_22, _prot_x_T_23) wire _prot_x_WIRE : UInt<1> connect _prot_x_WIRE, _prot_x_T_24 node _prot_x_T_25 = and(legal_address[0], _prot_x_WIRE) node _prot_x_T_26 = and(_prot_x_T_25, pmp_0.io.x) wire prot_x : UInt<1>[1] connect prot_x[0], _prot_x_T_26 node _prot_eff_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_eff_T_1 = cvt(_prot_eff_T) node _prot_eff_T_2 = and(_prot_eff_T_1, asSInt(UInt<33>(0h80110000))) node _prot_eff_T_3 = asSInt(_prot_eff_T_2) node _prot_eff_T_4 = eq(_prot_eff_T_3, asSInt(UInt<1>(0h0))) node _prot_eff_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_eff_T_6 = cvt(_prot_eff_T_5) node _prot_eff_T_7 = and(_prot_eff_T_6, asSInt(UInt<33>(0h80000000))) node _prot_eff_T_8 = asSInt(_prot_eff_T_7) node _prot_eff_T_9 = eq(_prot_eff_T_8, asSInt(UInt<1>(0h0))) node _prot_eff_T_10 = or(_prot_eff_T_4, _prot_eff_T_9) node _prot_eff_T_11 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_eff_T_12 = cvt(_prot_eff_T_11) node _prot_eff_T_13 = and(_prot_eff_T_12, asSInt(UInt<33>(0h80110000))) node _prot_eff_T_14 = asSInt(_prot_eff_T_13) node _prot_eff_T_15 = eq(_prot_eff_T_14, asSInt(UInt<1>(0h0))) node _prot_eff_T_16 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_eff_T_17 = cvt(_prot_eff_T_16) node _prot_eff_T_18 = and(_prot_eff_T_17, asSInt(UInt<33>(0h80100000))) node _prot_eff_T_19 = asSInt(_prot_eff_T_18) node _prot_eff_T_20 = eq(_prot_eff_T_19, asSInt(UInt<1>(0h0))) node _prot_eff_T_21 = or(_prot_eff_T_15, _prot_eff_T_20) node _prot_eff_T_22 = mux(_prot_eff_T_10, UInt<1>(0h0), UInt<1>(0h0)) node _prot_eff_T_23 = mux(_prot_eff_T_21, UInt<1>(0h1), UInt<1>(0h0)) node _prot_eff_T_24 = or(_prot_eff_T_22, _prot_eff_T_23) wire _prot_eff_WIRE : UInt<1> connect _prot_eff_WIRE, _prot_eff_T_24 node _prot_eff_T_25 = and(legal_address[0], _prot_eff_WIRE) wire prot_eff : UInt<1>[1] connect prot_eff[0], _prot_eff_T_25 node _sector_hits_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0].tag, vpn[0]) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = and(_sector_hits_T_2, _sector_hits_T_5) node _sector_hits_T_7 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1]) node _sector_hits_T_8 = or(_sector_hits_T_7, sectored_entries[1].valid[2]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[1].valid[3]) node _sector_hits_T_10 = xor(sectored_entries[1].tag, vpn[0]) node _sector_hits_T_11 = shr(_sector_hits_T_10, 2) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = and(_sector_hits_T_9, _sector_hits_T_12) node _sector_hits_T_14 = or(sectored_entries[2].valid[0], sectored_entries[2].valid[1]) node _sector_hits_T_15 = or(_sector_hits_T_14, sectored_entries[2].valid[2]) node _sector_hits_T_16 = or(_sector_hits_T_15, sectored_entries[2].valid[3]) node _sector_hits_T_17 = xor(sectored_entries[2].tag, vpn[0]) node _sector_hits_T_18 = shr(_sector_hits_T_17, 2) node _sector_hits_T_19 = eq(_sector_hits_T_18, UInt<1>(0h0)) node _sector_hits_T_20 = and(_sector_hits_T_16, _sector_hits_T_19) node _sector_hits_T_21 = or(sectored_entries[3].valid[0], sectored_entries[3].valid[1]) node _sector_hits_T_22 = or(_sector_hits_T_21, sectored_entries[3].valid[2]) node _sector_hits_T_23 = or(_sector_hits_T_22, sectored_entries[3].valid[3]) node _sector_hits_T_24 = xor(sectored_entries[3].tag, vpn[0]) node _sector_hits_T_25 = shr(_sector_hits_T_24, 2) node _sector_hits_T_26 = eq(_sector_hits_T_25, UInt<1>(0h0)) node _sector_hits_T_27 = and(_sector_hits_T_23, _sector_hits_T_26) node _sector_hits_T_28 = or(sectored_entries[4].valid[0], sectored_entries[4].valid[1]) node _sector_hits_T_29 = or(_sector_hits_T_28, sectored_entries[4].valid[2]) node _sector_hits_T_30 = or(_sector_hits_T_29, sectored_entries[4].valid[3]) node _sector_hits_T_31 = xor(sectored_entries[4].tag, vpn[0]) node _sector_hits_T_32 = shr(_sector_hits_T_31, 2) node _sector_hits_T_33 = eq(_sector_hits_T_32, UInt<1>(0h0)) node _sector_hits_T_34 = and(_sector_hits_T_30, _sector_hits_T_33) node _sector_hits_T_35 = or(sectored_entries[5].valid[0], sectored_entries[5].valid[1]) node _sector_hits_T_36 = or(_sector_hits_T_35, sectored_entries[5].valid[2]) node _sector_hits_T_37 = or(_sector_hits_T_36, sectored_entries[5].valid[3]) node _sector_hits_T_38 = xor(sectored_entries[5].tag, vpn[0]) node _sector_hits_T_39 = shr(_sector_hits_T_38, 2) node _sector_hits_T_40 = eq(_sector_hits_T_39, UInt<1>(0h0)) node _sector_hits_T_41 = and(_sector_hits_T_37, _sector_hits_T_40) node _sector_hits_T_42 = or(sectored_entries[6].valid[0], sectored_entries[6].valid[1]) node _sector_hits_T_43 = or(_sector_hits_T_42, sectored_entries[6].valid[2]) node _sector_hits_T_44 = or(_sector_hits_T_43, sectored_entries[6].valid[3]) node _sector_hits_T_45 = xor(sectored_entries[6].tag, vpn[0]) node _sector_hits_T_46 = shr(_sector_hits_T_45, 2) node _sector_hits_T_47 = eq(_sector_hits_T_46, UInt<1>(0h0)) node _sector_hits_T_48 = and(_sector_hits_T_44, _sector_hits_T_47) node _sector_hits_T_49 = or(sectored_entries[7].valid[0], sectored_entries[7].valid[1]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[7].valid[2]) node _sector_hits_T_51 = or(_sector_hits_T_50, sectored_entries[7].valid[3]) node _sector_hits_T_52 = xor(sectored_entries[7].tag, vpn[0]) node _sector_hits_T_53 = shr(_sector_hits_T_52, 2) node _sector_hits_T_54 = eq(_sector_hits_T_53, UInt<1>(0h0)) node _sector_hits_T_55 = and(_sector_hits_T_51, _sector_hits_T_54) wire _sector_hits_WIRE : UInt<1>[8] connect _sector_hits_WIRE[0], _sector_hits_T_6 connect _sector_hits_WIRE[1], _sector_hits_T_13 connect _sector_hits_WIRE[2], _sector_hits_T_20 connect _sector_hits_WIRE[3], _sector_hits_T_27 connect _sector_hits_WIRE[4], _sector_hits_T_34 connect _sector_hits_WIRE[5], _sector_hits_T_41 connect _sector_hits_WIRE[6], _sector_hits_T_48 connect _sector_hits_WIRE[7], _sector_hits_T_55 wire sector_hits : UInt<1>[8][1] connect sector_hits[0], _sector_hits_WIRE node _superpage_hits_T = xor(superpage_entries[0].tag, vpn[0]) node _superpage_hits_T_1 = shr(_superpage_hits_T, 0) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = and(superpage_entries[0].valid[0], _superpage_hits_T_2) node _superpage_hits_T_4 = xor(superpage_entries[1].tag, vpn[0]) node _superpage_hits_T_5 = shr(_superpage_hits_T_4, 0) node _superpage_hits_T_6 = eq(_superpage_hits_T_5, UInt<1>(0h0)) node _superpage_hits_T_7 = and(superpage_entries[1].valid[0], _superpage_hits_T_6) node _superpage_hits_T_8 = xor(superpage_entries[2].tag, vpn[0]) node _superpage_hits_T_9 = shr(_superpage_hits_T_8, 0) node _superpage_hits_T_10 = eq(_superpage_hits_T_9, UInt<1>(0h0)) node _superpage_hits_T_11 = and(superpage_entries[2].valid[0], _superpage_hits_T_10) node _superpage_hits_T_12 = xor(superpage_entries[3].tag, vpn[0]) node _superpage_hits_T_13 = shr(_superpage_hits_T_12, 0) node _superpage_hits_T_14 = eq(_superpage_hits_T_13, UInt<1>(0h0)) node _superpage_hits_T_15 = and(superpage_entries[3].valid[0], _superpage_hits_T_14) wire _superpage_hits_WIRE : UInt<1>[4] connect _superpage_hits_WIRE[0], _superpage_hits_T_3 connect _superpage_hits_WIRE[1], _superpage_hits_T_7 connect _superpage_hits_WIRE[2], _superpage_hits_T_11 connect _superpage_hits_WIRE[3], _superpage_hits_T_15 wire superpage_hits : UInt<1>[4][1] connect superpage_hits[0], _superpage_hits_WIRE node hitsVec_idx = bits(vpn[0], 1, 0) node _hitsVec_T = xor(sectored_entries[0].tag, vpn[0]) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = and(sectored_entries[0].valid[hitsVec_idx], _hitsVec_T_2) node _hitsVec_T_4 = and(vm_enabled[0], _hitsVec_T_3) node hitsVec_idx_1 = bits(vpn[0], 1, 0) node _hitsVec_T_5 = xor(sectored_entries[1].tag, vpn[0]) node _hitsVec_T_6 = shr(_hitsVec_T_5, 2) node _hitsVec_T_7 = eq(_hitsVec_T_6, UInt<1>(0h0)) node _hitsVec_T_8 = and(sectored_entries[1].valid[hitsVec_idx_1], _hitsVec_T_7) node _hitsVec_T_9 = and(vm_enabled[0], _hitsVec_T_8) node hitsVec_idx_2 = bits(vpn[0], 1, 0) node _hitsVec_T_10 = xor(sectored_entries[2].tag, vpn[0]) node _hitsVec_T_11 = shr(_hitsVec_T_10, 2) node _hitsVec_T_12 = eq(_hitsVec_T_11, UInt<1>(0h0)) node _hitsVec_T_13 = and(sectored_entries[2].valid[hitsVec_idx_2], _hitsVec_T_12) node _hitsVec_T_14 = and(vm_enabled[0], _hitsVec_T_13) node hitsVec_idx_3 = bits(vpn[0], 1, 0) node _hitsVec_T_15 = xor(sectored_entries[3].tag, vpn[0]) node _hitsVec_T_16 = shr(_hitsVec_T_15, 2) node _hitsVec_T_17 = eq(_hitsVec_T_16, UInt<1>(0h0)) node _hitsVec_T_18 = and(sectored_entries[3].valid[hitsVec_idx_3], _hitsVec_T_17) node _hitsVec_T_19 = and(vm_enabled[0], _hitsVec_T_18) node hitsVec_idx_4 = bits(vpn[0], 1, 0) node _hitsVec_T_20 = xor(sectored_entries[4].tag, vpn[0]) node _hitsVec_T_21 = shr(_hitsVec_T_20, 2) node _hitsVec_T_22 = eq(_hitsVec_T_21, UInt<1>(0h0)) node _hitsVec_T_23 = and(sectored_entries[4].valid[hitsVec_idx_4], _hitsVec_T_22) node _hitsVec_T_24 = and(vm_enabled[0], _hitsVec_T_23) node hitsVec_idx_5 = bits(vpn[0], 1, 0) node _hitsVec_T_25 = xor(sectored_entries[5].tag, vpn[0]) node _hitsVec_T_26 = shr(_hitsVec_T_25, 2) node _hitsVec_T_27 = eq(_hitsVec_T_26, UInt<1>(0h0)) node _hitsVec_T_28 = and(sectored_entries[5].valid[hitsVec_idx_5], _hitsVec_T_27) node _hitsVec_T_29 = and(vm_enabled[0], _hitsVec_T_28) node hitsVec_idx_6 = bits(vpn[0], 1, 0) node _hitsVec_T_30 = xor(sectored_entries[6].tag, vpn[0]) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = and(sectored_entries[6].valid[hitsVec_idx_6], _hitsVec_T_32) node _hitsVec_T_34 = and(vm_enabled[0], _hitsVec_T_33) node hitsVec_idx_7 = bits(vpn[0], 1, 0) node _hitsVec_T_35 = xor(sectored_entries[7].tag, vpn[0]) node _hitsVec_T_36 = shr(_hitsVec_T_35, 2) node _hitsVec_T_37 = eq(_hitsVec_T_36, UInt<1>(0h0)) node _hitsVec_T_38 = and(sectored_entries[7].valid[hitsVec_idx_7], _hitsVec_T_37) node _hitsVec_T_39 = and(vm_enabled[0], _hitsVec_T_38) node _hitsVec_T_40 = xor(superpage_entries[0].tag, vpn[0]) node _hitsVec_T_41 = shr(_hitsVec_T_40, 0) node _hitsVec_T_42 = eq(_hitsVec_T_41, UInt<1>(0h0)) node _hitsVec_T_43 = and(superpage_entries[0].valid[0], _hitsVec_T_42) node _hitsVec_T_44 = and(vm_enabled[0], _hitsVec_T_43) node _hitsVec_T_45 = xor(superpage_entries[1].tag, vpn[0]) node _hitsVec_T_46 = shr(_hitsVec_T_45, 0) node _hitsVec_T_47 = eq(_hitsVec_T_46, UInt<1>(0h0)) node _hitsVec_T_48 = and(superpage_entries[1].valid[0], _hitsVec_T_47) node _hitsVec_T_49 = and(vm_enabled[0], _hitsVec_T_48) node _hitsVec_T_50 = xor(superpage_entries[2].tag, vpn[0]) node _hitsVec_T_51 = shr(_hitsVec_T_50, 0) node _hitsVec_T_52 = eq(_hitsVec_T_51, UInt<1>(0h0)) node _hitsVec_T_53 = and(superpage_entries[2].valid[0], _hitsVec_T_52) node _hitsVec_T_54 = and(vm_enabled[0], _hitsVec_T_53) node _hitsVec_T_55 = xor(superpage_entries[3].tag, vpn[0]) node _hitsVec_T_56 = shr(_hitsVec_T_55, 0) node _hitsVec_T_57 = eq(_hitsVec_T_56, UInt<1>(0h0)) node _hitsVec_T_58 = and(superpage_entries[3].valid[0], _hitsVec_T_57) node _hitsVec_T_59 = and(vm_enabled[0], _hitsVec_T_58) node _hitsVec_T_60 = xor(special_entry.tag, vpn[0]) node _hitsVec_T_61 = shr(_hitsVec_T_60, 0) node _hitsVec_T_62 = eq(_hitsVec_T_61, UInt<1>(0h0)) node _hitsVec_T_63 = and(special_entry.valid[0], _hitsVec_T_62) node _hitsVec_T_64 = and(vm_enabled[0], _hitsVec_T_63) wire _hitsVec_WIRE : UInt<1>[13] connect _hitsVec_WIRE[0], _hitsVec_T_4 connect _hitsVec_WIRE[1], _hitsVec_T_9 connect _hitsVec_WIRE[2], _hitsVec_T_14 connect _hitsVec_WIRE[3], _hitsVec_T_19 connect _hitsVec_WIRE[4], _hitsVec_T_24 connect _hitsVec_WIRE[5], _hitsVec_T_29 connect _hitsVec_WIRE[6], _hitsVec_T_34 connect _hitsVec_WIRE[7], _hitsVec_T_39 connect _hitsVec_WIRE[8], _hitsVec_T_44 connect _hitsVec_WIRE[9], _hitsVec_T_49 connect _hitsVec_WIRE[10], _hitsVec_T_54 connect _hitsVec_WIRE[11], _hitsVec_T_59 connect _hitsVec_WIRE[12], _hitsVec_T_64 wire hitsVec : UInt<1>[13][1] connect hitsVec[0], _hitsVec_WIRE node real_hits_lo_lo_hi = cat(hitsVec[0][2], hitsVec[0][1]) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec[0][0]) node real_hits_lo_hi_hi = cat(hitsVec[0][5], hitsVec[0][4]) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec[0][3]) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec[0][8], hitsVec[0][7]) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec[0][6]) node real_hits_hi_hi_lo = cat(hitsVec[0][10], hitsVec[0][9]) node real_hits_hi_hi_hi = cat(hitsVec[0][12], hitsVec[0][11]) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node _real_hits_T = cat(real_hits_hi, real_hits_lo) wire real_hits : UInt<13>[1] connect real_hits[0], _real_hits_T node _hits_T = eq(vm_enabled[0], UInt<1>(0h0)) node _hits_T_1 = cat(_hits_T, real_hits[0]) wire hits : UInt<14>[1] connect hits[0], _hits_T_1 node _ppn_T = eq(vm_enabled[0], UInt<1>(0h0)) node _ppn_data_T = bits(vpn[0], 1, 0) wire _ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_1 : UInt<34> connect _ppn_data_WIRE_1, sectored_entries[0].data[_ppn_data_T] node _ppn_data_T_1 = bits(_ppn_data_WIRE_1, 0, 0) connect _ppn_data_WIRE.fragmented_superpage, _ppn_data_T_1 node _ppn_data_T_2 = bits(_ppn_data_WIRE_1, 1, 1) connect _ppn_data_WIRE.c, _ppn_data_T_2 node _ppn_data_T_3 = bits(_ppn_data_WIRE_1, 2, 2) connect _ppn_data_WIRE.eff, _ppn_data_T_3 node _ppn_data_T_4 = bits(_ppn_data_WIRE_1, 3, 3) connect _ppn_data_WIRE.paa, _ppn_data_T_4 node _ppn_data_T_5 = bits(_ppn_data_WIRE_1, 4, 4) connect _ppn_data_WIRE.pal, _ppn_data_T_5 node _ppn_data_T_6 = bits(_ppn_data_WIRE_1, 5, 5) connect _ppn_data_WIRE.pr, _ppn_data_T_6 node _ppn_data_T_7 = bits(_ppn_data_WIRE_1, 6, 6) connect _ppn_data_WIRE.px, _ppn_data_T_7 node _ppn_data_T_8 = bits(_ppn_data_WIRE_1, 7, 7) connect _ppn_data_WIRE.pw, _ppn_data_T_8 node _ppn_data_T_9 = bits(_ppn_data_WIRE_1, 8, 8) connect _ppn_data_WIRE.sr, _ppn_data_T_9 node _ppn_data_T_10 = bits(_ppn_data_WIRE_1, 9, 9) connect _ppn_data_WIRE.sx, _ppn_data_T_10 node _ppn_data_T_11 = bits(_ppn_data_WIRE_1, 10, 10) connect _ppn_data_WIRE.sw, _ppn_data_T_11 node _ppn_data_T_12 = bits(_ppn_data_WIRE_1, 11, 11) connect _ppn_data_WIRE.ae, _ppn_data_T_12 node _ppn_data_T_13 = bits(_ppn_data_WIRE_1, 12, 12) connect _ppn_data_WIRE.g, _ppn_data_T_13 node _ppn_data_T_14 = bits(_ppn_data_WIRE_1, 13, 13) connect _ppn_data_WIRE.u, _ppn_data_T_14 node _ppn_data_T_15 = bits(_ppn_data_WIRE_1, 33, 14) connect _ppn_data_WIRE.ppn, _ppn_data_T_15 inst ppn_data_barrier of OptimizationBarrier_EntryData_1 connect ppn_data_barrier.clock, clock connect ppn_data_barrier.reset, reset connect ppn_data_barrier.io.x.fragmented_superpage, _ppn_data_WIRE.fragmented_superpage connect ppn_data_barrier.io.x.c, _ppn_data_WIRE.c connect ppn_data_barrier.io.x.eff, _ppn_data_WIRE.eff connect ppn_data_barrier.io.x.paa, _ppn_data_WIRE.paa connect ppn_data_barrier.io.x.pal, _ppn_data_WIRE.pal connect ppn_data_barrier.io.x.pr, _ppn_data_WIRE.pr connect ppn_data_barrier.io.x.px, _ppn_data_WIRE.px connect ppn_data_barrier.io.x.pw, _ppn_data_WIRE.pw connect ppn_data_barrier.io.x.sr, _ppn_data_WIRE.sr connect ppn_data_barrier.io.x.sx, _ppn_data_WIRE.sx connect ppn_data_barrier.io.x.sw, _ppn_data_WIRE.sw connect ppn_data_barrier.io.x.ae, _ppn_data_WIRE.ae connect ppn_data_barrier.io.x.g, _ppn_data_WIRE.g connect ppn_data_barrier.io.x.u, _ppn_data_WIRE.u connect ppn_data_barrier.io.x.ppn, _ppn_data_WIRE.ppn node _ppn_data_T_16 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_3 : UInt<34> connect _ppn_data_WIRE_3, sectored_entries[1].data[_ppn_data_T_16] node _ppn_data_T_17 = bits(_ppn_data_WIRE_3, 0, 0) connect _ppn_data_WIRE_2.fragmented_superpage, _ppn_data_T_17 node _ppn_data_T_18 = bits(_ppn_data_WIRE_3, 1, 1) connect _ppn_data_WIRE_2.c, _ppn_data_T_18 node _ppn_data_T_19 = bits(_ppn_data_WIRE_3, 2, 2) connect _ppn_data_WIRE_2.eff, _ppn_data_T_19 node _ppn_data_T_20 = bits(_ppn_data_WIRE_3, 3, 3) connect _ppn_data_WIRE_2.paa, _ppn_data_T_20 node _ppn_data_T_21 = bits(_ppn_data_WIRE_3, 4, 4) connect _ppn_data_WIRE_2.pal, _ppn_data_T_21 node _ppn_data_T_22 = bits(_ppn_data_WIRE_3, 5, 5) connect _ppn_data_WIRE_2.pr, _ppn_data_T_22 node _ppn_data_T_23 = bits(_ppn_data_WIRE_3, 6, 6) connect _ppn_data_WIRE_2.px, _ppn_data_T_23 node _ppn_data_T_24 = bits(_ppn_data_WIRE_3, 7, 7) connect _ppn_data_WIRE_2.pw, _ppn_data_T_24 node _ppn_data_T_25 = bits(_ppn_data_WIRE_3, 8, 8) connect _ppn_data_WIRE_2.sr, _ppn_data_T_25 node _ppn_data_T_26 = bits(_ppn_data_WIRE_3, 9, 9) connect _ppn_data_WIRE_2.sx, _ppn_data_T_26 node _ppn_data_T_27 = bits(_ppn_data_WIRE_3, 10, 10) connect _ppn_data_WIRE_2.sw, _ppn_data_T_27 node _ppn_data_T_28 = bits(_ppn_data_WIRE_3, 11, 11) connect _ppn_data_WIRE_2.ae, _ppn_data_T_28 node _ppn_data_T_29 = bits(_ppn_data_WIRE_3, 12, 12) connect _ppn_data_WIRE_2.g, _ppn_data_T_29 node _ppn_data_T_30 = bits(_ppn_data_WIRE_3, 13, 13) connect _ppn_data_WIRE_2.u, _ppn_data_T_30 node _ppn_data_T_31 = bits(_ppn_data_WIRE_3, 33, 14) connect _ppn_data_WIRE_2.ppn, _ppn_data_T_31 inst ppn_data_barrier_1 of OptimizationBarrier_EntryData_2 connect ppn_data_barrier_1.clock, clock connect ppn_data_barrier_1.reset, reset connect ppn_data_barrier_1.io.x.fragmented_superpage, _ppn_data_WIRE_2.fragmented_superpage connect ppn_data_barrier_1.io.x.c, _ppn_data_WIRE_2.c connect ppn_data_barrier_1.io.x.eff, _ppn_data_WIRE_2.eff connect ppn_data_barrier_1.io.x.paa, _ppn_data_WIRE_2.paa connect ppn_data_barrier_1.io.x.pal, _ppn_data_WIRE_2.pal connect ppn_data_barrier_1.io.x.pr, _ppn_data_WIRE_2.pr connect ppn_data_barrier_1.io.x.px, _ppn_data_WIRE_2.px connect ppn_data_barrier_1.io.x.pw, _ppn_data_WIRE_2.pw connect ppn_data_barrier_1.io.x.sr, _ppn_data_WIRE_2.sr connect ppn_data_barrier_1.io.x.sx, _ppn_data_WIRE_2.sx connect ppn_data_barrier_1.io.x.sw, _ppn_data_WIRE_2.sw connect ppn_data_barrier_1.io.x.ae, _ppn_data_WIRE_2.ae connect ppn_data_barrier_1.io.x.g, _ppn_data_WIRE_2.g connect ppn_data_barrier_1.io.x.u, _ppn_data_WIRE_2.u connect ppn_data_barrier_1.io.x.ppn, _ppn_data_WIRE_2.ppn node _ppn_data_T_32 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_5 : UInt<34> connect _ppn_data_WIRE_5, sectored_entries[2].data[_ppn_data_T_32] node _ppn_data_T_33 = bits(_ppn_data_WIRE_5, 0, 0) connect _ppn_data_WIRE_4.fragmented_superpage, _ppn_data_T_33 node _ppn_data_T_34 = bits(_ppn_data_WIRE_5, 1, 1) connect _ppn_data_WIRE_4.c, _ppn_data_T_34 node _ppn_data_T_35 = bits(_ppn_data_WIRE_5, 2, 2) connect _ppn_data_WIRE_4.eff, _ppn_data_T_35 node _ppn_data_T_36 = bits(_ppn_data_WIRE_5, 3, 3) connect _ppn_data_WIRE_4.paa, _ppn_data_T_36 node _ppn_data_T_37 = bits(_ppn_data_WIRE_5, 4, 4) connect _ppn_data_WIRE_4.pal, _ppn_data_T_37 node _ppn_data_T_38 = bits(_ppn_data_WIRE_5, 5, 5) connect _ppn_data_WIRE_4.pr, _ppn_data_T_38 node _ppn_data_T_39 = bits(_ppn_data_WIRE_5, 6, 6) connect _ppn_data_WIRE_4.px, _ppn_data_T_39 node _ppn_data_T_40 = bits(_ppn_data_WIRE_5, 7, 7) connect _ppn_data_WIRE_4.pw, _ppn_data_T_40 node _ppn_data_T_41 = bits(_ppn_data_WIRE_5, 8, 8) connect _ppn_data_WIRE_4.sr, _ppn_data_T_41 node _ppn_data_T_42 = bits(_ppn_data_WIRE_5, 9, 9) connect _ppn_data_WIRE_4.sx, _ppn_data_T_42 node _ppn_data_T_43 = bits(_ppn_data_WIRE_5, 10, 10) connect _ppn_data_WIRE_4.sw, _ppn_data_T_43 node _ppn_data_T_44 = bits(_ppn_data_WIRE_5, 11, 11) connect _ppn_data_WIRE_4.ae, _ppn_data_T_44 node _ppn_data_T_45 = bits(_ppn_data_WIRE_5, 12, 12) connect _ppn_data_WIRE_4.g, _ppn_data_T_45 node _ppn_data_T_46 = bits(_ppn_data_WIRE_5, 13, 13) connect _ppn_data_WIRE_4.u, _ppn_data_T_46 node _ppn_data_T_47 = bits(_ppn_data_WIRE_5, 33, 14) connect _ppn_data_WIRE_4.ppn, _ppn_data_T_47 inst ppn_data_barrier_2 of OptimizationBarrier_EntryData_3 connect ppn_data_barrier_2.clock, clock connect ppn_data_barrier_2.reset, reset connect ppn_data_barrier_2.io.x.fragmented_superpage, _ppn_data_WIRE_4.fragmented_superpage connect ppn_data_barrier_2.io.x.c, _ppn_data_WIRE_4.c connect ppn_data_barrier_2.io.x.eff, _ppn_data_WIRE_4.eff connect ppn_data_barrier_2.io.x.paa, _ppn_data_WIRE_4.paa connect ppn_data_barrier_2.io.x.pal, _ppn_data_WIRE_4.pal connect ppn_data_barrier_2.io.x.pr, _ppn_data_WIRE_4.pr connect ppn_data_barrier_2.io.x.px, _ppn_data_WIRE_4.px connect ppn_data_barrier_2.io.x.pw, _ppn_data_WIRE_4.pw connect ppn_data_barrier_2.io.x.sr, _ppn_data_WIRE_4.sr connect ppn_data_barrier_2.io.x.sx, _ppn_data_WIRE_4.sx connect ppn_data_barrier_2.io.x.sw, _ppn_data_WIRE_4.sw connect ppn_data_barrier_2.io.x.ae, _ppn_data_WIRE_4.ae connect ppn_data_barrier_2.io.x.g, _ppn_data_WIRE_4.g connect ppn_data_barrier_2.io.x.u, _ppn_data_WIRE_4.u connect ppn_data_barrier_2.io.x.ppn, _ppn_data_WIRE_4.ppn node _ppn_data_T_48 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_7 : UInt<34> connect _ppn_data_WIRE_7, sectored_entries[3].data[_ppn_data_T_48] node _ppn_data_T_49 = bits(_ppn_data_WIRE_7, 0, 0) connect _ppn_data_WIRE_6.fragmented_superpage, _ppn_data_T_49 node _ppn_data_T_50 = bits(_ppn_data_WIRE_7, 1, 1) connect _ppn_data_WIRE_6.c, _ppn_data_T_50 node _ppn_data_T_51 = bits(_ppn_data_WIRE_7, 2, 2) connect _ppn_data_WIRE_6.eff, _ppn_data_T_51 node _ppn_data_T_52 = bits(_ppn_data_WIRE_7, 3, 3) connect _ppn_data_WIRE_6.paa, _ppn_data_T_52 node _ppn_data_T_53 = bits(_ppn_data_WIRE_7, 4, 4) connect _ppn_data_WIRE_6.pal, _ppn_data_T_53 node _ppn_data_T_54 = bits(_ppn_data_WIRE_7, 5, 5) connect _ppn_data_WIRE_6.pr, _ppn_data_T_54 node _ppn_data_T_55 = bits(_ppn_data_WIRE_7, 6, 6) connect _ppn_data_WIRE_6.px, _ppn_data_T_55 node _ppn_data_T_56 = bits(_ppn_data_WIRE_7, 7, 7) connect _ppn_data_WIRE_6.pw, _ppn_data_T_56 node _ppn_data_T_57 = bits(_ppn_data_WIRE_7, 8, 8) connect _ppn_data_WIRE_6.sr, _ppn_data_T_57 node _ppn_data_T_58 = bits(_ppn_data_WIRE_7, 9, 9) connect _ppn_data_WIRE_6.sx, _ppn_data_T_58 node _ppn_data_T_59 = bits(_ppn_data_WIRE_7, 10, 10) connect _ppn_data_WIRE_6.sw, _ppn_data_T_59 node _ppn_data_T_60 = bits(_ppn_data_WIRE_7, 11, 11) connect _ppn_data_WIRE_6.ae, _ppn_data_T_60 node _ppn_data_T_61 = bits(_ppn_data_WIRE_7, 12, 12) connect _ppn_data_WIRE_6.g, _ppn_data_T_61 node _ppn_data_T_62 = bits(_ppn_data_WIRE_7, 13, 13) connect _ppn_data_WIRE_6.u, _ppn_data_T_62 node _ppn_data_T_63 = bits(_ppn_data_WIRE_7, 33, 14) connect _ppn_data_WIRE_6.ppn, _ppn_data_T_63 inst ppn_data_barrier_3 of OptimizationBarrier_EntryData_4 connect ppn_data_barrier_3.clock, clock connect ppn_data_barrier_3.reset, reset connect ppn_data_barrier_3.io.x.fragmented_superpage, _ppn_data_WIRE_6.fragmented_superpage connect ppn_data_barrier_3.io.x.c, _ppn_data_WIRE_6.c connect ppn_data_barrier_3.io.x.eff, _ppn_data_WIRE_6.eff connect ppn_data_barrier_3.io.x.paa, _ppn_data_WIRE_6.paa connect ppn_data_barrier_3.io.x.pal, _ppn_data_WIRE_6.pal connect ppn_data_barrier_3.io.x.pr, _ppn_data_WIRE_6.pr connect ppn_data_barrier_3.io.x.px, _ppn_data_WIRE_6.px connect ppn_data_barrier_3.io.x.pw, _ppn_data_WIRE_6.pw connect ppn_data_barrier_3.io.x.sr, _ppn_data_WIRE_6.sr connect ppn_data_barrier_3.io.x.sx, _ppn_data_WIRE_6.sx connect ppn_data_barrier_3.io.x.sw, _ppn_data_WIRE_6.sw connect ppn_data_barrier_3.io.x.ae, _ppn_data_WIRE_6.ae connect ppn_data_barrier_3.io.x.g, _ppn_data_WIRE_6.g connect ppn_data_barrier_3.io.x.u, _ppn_data_WIRE_6.u connect ppn_data_barrier_3.io.x.ppn, _ppn_data_WIRE_6.ppn node _ppn_data_T_64 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_9 : UInt<34> connect _ppn_data_WIRE_9, sectored_entries[4].data[_ppn_data_T_64] node _ppn_data_T_65 = bits(_ppn_data_WIRE_9, 0, 0) connect _ppn_data_WIRE_8.fragmented_superpage, _ppn_data_T_65 node _ppn_data_T_66 = bits(_ppn_data_WIRE_9, 1, 1) connect _ppn_data_WIRE_8.c, _ppn_data_T_66 node _ppn_data_T_67 = bits(_ppn_data_WIRE_9, 2, 2) connect _ppn_data_WIRE_8.eff, _ppn_data_T_67 node _ppn_data_T_68 = bits(_ppn_data_WIRE_9, 3, 3) connect _ppn_data_WIRE_8.paa, _ppn_data_T_68 node _ppn_data_T_69 = bits(_ppn_data_WIRE_9, 4, 4) connect _ppn_data_WIRE_8.pal, _ppn_data_T_69 node _ppn_data_T_70 = bits(_ppn_data_WIRE_9, 5, 5) connect _ppn_data_WIRE_8.pr, _ppn_data_T_70 node _ppn_data_T_71 = bits(_ppn_data_WIRE_9, 6, 6) connect _ppn_data_WIRE_8.px, _ppn_data_T_71 node _ppn_data_T_72 = bits(_ppn_data_WIRE_9, 7, 7) connect _ppn_data_WIRE_8.pw, _ppn_data_T_72 node _ppn_data_T_73 = bits(_ppn_data_WIRE_9, 8, 8) connect _ppn_data_WIRE_8.sr, _ppn_data_T_73 node _ppn_data_T_74 = bits(_ppn_data_WIRE_9, 9, 9) connect _ppn_data_WIRE_8.sx, _ppn_data_T_74 node _ppn_data_T_75 = bits(_ppn_data_WIRE_9, 10, 10) connect _ppn_data_WIRE_8.sw, _ppn_data_T_75 node _ppn_data_T_76 = bits(_ppn_data_WIRE_9, 11, 11) connect _ppn_data_WIRE_8.ae, _ppn_data_T_76 node _ppn_data_T_77 = bits(_ppn_data_WIRE_9, 12, 12) connect _ppn_data_WIRE_8.g, _ppn_data_T_77 node _ppn_data_T_78 = bits(_ppn_data_WIRE_9, 13, 13) connect _ppn_data_WIRE_8.u, _ppn_data_T_78 node _ppn_data_T_79 = bits(_ppn_data_WIRE_9, 33, 14) connect _ppn_data_WIRE_8.ppn, _ppn_data_T_79 inst ppn_data_barrier_4 of OptimizationBarrier_EntryData_5 connect ppn_data_barrier_4.clock, clock connect ppn_data_barrier_4.reset, reset connect ppn_data_barrier_4.io.x.fragmented_superpage, _ppn_data_WIRE_8.fragmented_superpage connect ppn_data_barrier_4.io.x.c, _ppn_data_WIRE_8.c connect ppn_data_barrier_4.io.x.eff, _ppn_data_WIRE_8.eff connect ppn_data_barrier_4.io.x.paa, _ppn_data_WIRE_8.paa connect ppn_data_barrier_4.io.x.pal, _ppn_data_WIRE_8.pal connect ppn_data_barrier_4.io.x.pr, _ppn_data_WIRE_8.pr connect ppn_data_barrier_4.io.x.px, _ppn_data_WIRE_8.px connect ppn_data_barrier_4.io.x.pw, _ppn_data_WIRE_8.pw connect ppn_data_barrier_4.io.x.sr, _ppn_data_WIRE_8.sr connect ppn_data_barrier_4.io.x.sx, _ppn_data_WIRE_8.sx connect ppn_data_barrier_4.io.x.sw, _ppn_data_WIRE_8.sw connect ppn_data_barrier_4.io.x.ae, _ppn_data_WIRE_8.ae connect ppn_data_barrier_4.io.x.g, _ppn_data_WIRE_8.g connect ppn_data_barrier_4.io.x.u, _ppn_data_WIRE_8.u connect ppn_data_barrier_4.io.x.ppn, _ppn_data_WIRE_8.ppn node _ppn_data_T_80 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_11 : UInt<34> connect _ppn_data_WIRE_11, sectored_entries[5].data[_ppn_data_T_80] node _ppn_data_T_81 = bits(_ppn_data_WIRE_11, 0, 0) connect _ppn_data_WIRE_10.fragmented_superpage, _ppn_data_T_81 node _ppn_data_T_82 = bits(_ppn_data_WIRE_11, 1, 1) connect _ppn_data_WIRE_10.c, _ppn_data_T_82 node _ppn_data_T_83 = bits(_ppn_data_WIRE_11, 2, 2) connect _ppn_data_WIRE_10.eff, _ppn_data_T_83 node _ppn_data_T_84 = bits(_ppn_data_WIRE_11, 3, 3) connect _ppn_data_WIRE_10.paa, _ppn_data_T_84 node _ppn_data_T_85 = bits(_ppn_data_WIRE_11, 4, 4) connect _ppn_data_WIRE_10.pal, _ppn_data_T_85 node _ppn_data_T_86 = bits(_ppn_data_WIRE_11, 5, 5) connect _ppn_data_WIRE_10.pr, _ppn_data_T_86 node _ppn_data_T_87 = bits(_ppn_data_WIRE_11, 6, 6) connect _ppn_data_WIRE_10.px, _ppn_data_T_87 node _ppn_data_T_88 = bits(_ppn_data_WIRE_11, 7, 7) connect _ppn_data_WIRE_10.pw, _ppn_data_T_88 node _ppn_data_T_89 = bits(_ppn_data_WIRE_11, 8, 8) connect _ppn_data_WIRE_10.sr, _ppn_data_T_89 node _ppn_data_T_90 = bits(_ppn_data_WIRE_11, 9, 9) connect _ppn_data_WIRE_10.sx, _ppn_data_T_90 node _ppn_data_T_91 = bits(_ppn_data_WIRE_11, 10, 10) connect _ppn_data_WIRE_10.sw, _ppn_data_T_91 node _ppn_data_T_92 = bits(_ppn_data_WIRE_11, 11, 11) connect _ppn_data_WIRE_10.ae, _ppn_data_T_92 node _ppn_data_T_93 = bits(_ppn_data_WIRE_11, 12, 12) connect _ppn_data_WIRE_10.g, _ppn_data_T_93 node _ppn_data_T_94 = bits(_ppn_data_WIRE_11, 13, 13) connect _ppn_data_WIRE_10.u, _ppn_data_T_94 node _ppn_data_T_95 = bits(_ppn_data_WIRE_11, 33, 14) connect _ppn_data_WIRE_10.ppn, _ppn_data_T_95 inst ppn_data_barrier_5 of OptimizationBarrier_EntryData_6 connect ppn_data_barrier_5.clock, clock connect ppn_data_barrier_5.reset, reset connect ppn_data_barrier_5.io.x.fragmented_superpage, _ppn_data_WIRE_10.fragmented_superpage connect ppn_data_barrier_5.io.x.c, _ppn_data_WIRE_10.c connect ppn_data_barrier_5.io.x.eff, _ppn_data_WIRE_10.eff connect ppn_data_barrier_5.io.x.paa, _ppn_data_WIRE_10.paa connect ppn_data_barrier_5.io.x.pal, _ppn_data_WIRE_10.pal connect ppn_data_barrier_5.io.x.pr, _ppn_data_WIRE_10.pr connect ppn_data_barrier_5.io.x.px, _ppn_data_WIRE_10.px connect ppn_data_barrier_5.io.x.pw, _ppn_data_WIRE_10.pw connect ppn_data_barrier_5.io.x.sr, _ppn_data_WIRE_10.sr connect ppn_data_barrier_5.io.x.sx, _ppn_data_WIRE_10.sx connect ppn_data_barrier_5.io.x.sw, _ppn_data_WIRE_10.sw connect ppn_data_barrier_5.io.x.ae, _ppn_data_WIRE_10.ae connect ppn_data_barrier_5.io.x.g, _ppn_data_WIRE_10.g connect ppn_data_barrier_5.io.x.u, _ppn_data_WIRE_10.u connect ppn_data_barrier_5.io.x.ppn, _ppn_data_WIRE_10.ppn node _ppn_data_T_96 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_13 : UInt<34> connect _ppn_data_WIRE_13, sectored_entries[6].data[_ppn_data_T_96] node _ppn_data_T_97 = bits(_ppn_data_WIRE_13, 0, 0) connect _ppn_data_WIRE_12.fragmented_superpage, _ppn_data_T_97 node _ppn_data_T_98 = bits(_ppn_data_WIRE_13, 1, 1) connect _ppn_data_WIRE_12.c, _ppn_data_T_98 node _ppn_data_T_99 = bits(_ppn_data_WIRE_13, 2, 2) connect _ppn_data_WIRE_12.eff, _ppn_data_T_99 node _ppn_data_T_100 = bits(_ppn_data_WIRE_13, 3, 3) connect _ppn_data_WIRE_12.paa, _ppn_data_T_100 node _ppn_data_T_101 = bits(_ppn_data_WIRE_13, 4, 4) connect _ppn_data_WIRE_12.pal, _ppn_data_T_101 node _ppn_data_T_102 = bits(_ppn_data_WIRE_13, 5, 5) connect _ppn_data_WIRE_12.pr, _ppn_data_T_102 node _ppn_data_T_103 = bits(_ppn_data_WIRE_13, 6, 6) connect _ppn_data_WIRE_12.px, _ppn_data_T_103 node _ppn_data_T_104 = bits(_ppn_data_WIRE_13, 7, 7) connect _ppn_data_WIRE_12.pw, _ppn_data_T_104 node _ppn_data_T_105 = bits(_ppn_data_WIRE_13, 8, 8) connect _ppn_data_WIRE_12.sr, _ppn_data_T_105 node _ppn_data_T_106 = bits(_ppn_data_WIRE_13, 9, 9) connect _ppn_data_WIRE_12.sx, _ppn_data_T_106 node _ppn_data_T_107 = bits(_ppn_data_WIRE_13, 10, 10) connect _ppn_data_WIRE_12.sw, _ppn_data_T_107 node _ppn_data_T_108 = bits(_ppn_data_WIRE_13, 11, 11) connect _ppn_data_WIRE_12.ae, _ppn_data_T_108 node _ppn_data_T_109 = bits(_ppn_data_WIRE_13, 12, 12) connect _ppn_data_WIRE_12.g, _ppn_data_T_109 node _ppn_data_T_110 = bits(_ppn_data_WIRE_13, 13, 13) connect _ppn_data_WIRE_12.u, _ppn_data_T_110 node _ppn_data_T_111 = bits(_ppn_data_WIRE_13, 33, 14) connect _ppn_data_WIRE_12.ppn, _ppn_data_T_111 inst ppn_data_barrier_6 of OptimizationBarrier_EntryData_7 connect ppn_data_barrier_6.clock, clock connect ppn_data_barrier_6.reset, reset connect ppn_data_barrier_6.io.x.fragmented_superpage, _ppn_data_WIRE_12.fragmented_superpage connect ppn_data_barrier_6.io.x.c, _ppn_data_WIRE_12.c connect ppn_data_barrier_6.io.x.eff, _ppn_data_WIRE_12.eff connect ppn_data_barrier_6.io.x.paa, _ppn_data_WIRE_12.paa connect ppn_data_barrier_6.io.x.pal, _ppn_data_WIRE_12.pal connect ppn_data_barrier_6.io.x.pr, _ppn_data_WIRE_12.pr connect ppn_data_barrier_6.io.x.px, _ppn_data_WIRE_12.px connect ppn_data_barrier_6.io.x.pw, _ppn_data_WIRE_12.pw connect ppn_data_barrier_6.io.x.sr, _ppn_data_WIRE_12.sr connect ppn_data_barrier_6.io.x.sx, _ppn_data_WIRE_12.sx connect ppn_data_barrier_6.io.x.sw, _ppn_data_WIRE_12.sw connect ppn_data_barrier_6.io.x.ae, _ppn_data_WIRE_12.ae connect ppn_data_barrier_6.io.x.g, _ppn_data_WIRE_12.g connect ppn_data_barrier_6.io.x.u, _ppn_data_WIRE_12.u connect ppn_data_barrier_6.io.x.ppn, _ppn_data_WIRE_12.ppn node _ppn_data_T_112 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_15 : UInt<34> connect _ppn_data_WIRE_15, sectored_entries[7].data[_ppn_data_T_112] node _ppn_data_T_113 = bits(_ppn_data_WIRE_15, 0, 0) connect _ppn_data_WIRE_14.fragmented_superpage, _ppn_data_T_113 node _ppn_data_T_114 = bits(_ppn_data_WIRE_15, 1, 1) connect _ppn_data_WIRE_14.c, _ppn_data_T_114 node _ppn_data_T_115 = bits(_ppn_data_WIRE_15, 2, 2) connect _ppn_data_WIRE_14.eff, _ppn_data_T_115 node _ppn_data_T_116 = bits(_ppn_data_WIRE_15, 3, 3) connect _ppn_data_WIRE_14.paa, _ppn_data_T_116 node _ppn_data_T_117 = bits(_ppn_data_WIRE_15, 4, 4) connect _ppn_data_WIRE_14.pal, _ppn_data_T_117 node _ppn_data_T_118 = bits(_ppn_data_WIRE_15, 5, 5) connect _ppn_data_WIRE_14.pr, _ppn_data_T_118 node _ppn_data_T_119 = bits(_ppn_data_WIRE_15, 6, 6) connect _ppn_data_WIRE_14.px, _ppn_data_T_119 node _ppn_data_T_120 = bits(_ppn_data_WIRE_15, 7, 7) connect _ppn_data_WIRE_14.pw, _ppn_data_T_120 node _ppn_data_T_121 = bits(_ppn_data_WIRE_15, 8, 8) connect _ppn_data_WIRE_14.sr, _ppn_data_T_121 node _ppn_data_T_122 = bits(_ppn_data_WIRE_15, 9, 9) connect _ppn_data_WIRE_14.sx, _ppn_data_T_122 node _ppn_data_T_123 = bits(_ppn_data_WIRE_15, 10, 10) connect _ppn_data_WIRE_14.sw, _ppn_data_T_123 node _ppn_data_T_124 = bits(_ppn_data_WIRE_15, 11, 11) connect _ppn_data_WIRE_14.ae, _ppn_data_T_124 node _ppn_data_T_125 = bits(_ppn_data_WIRE_15, 12, 12) connect _ppn_data_WIRE_14.g, _ppn_data_T_125 node _ppn_data_T_126 = bits(_ppn_data_WIRE_15, 13, 13) connect _ppn_data_WIRE_14.u, _ppn_data_T_126 node _ppn_data_T_127 = bits(_ppn_data_WIRE_15, 33, 14) connect _ppn_data_WIRE_14.ppn, _ppn_data_T_127 inst ppn_data_barrier_7 of OptimizationBarrier_EntryData_8 connect ppn_data_barrier_7.clock, clock connect ppn_data_barrier_7.reset, reset connect ppn_data_barrier_7.io.x.fragmented_superpage, _ppn_data_WIRE_14.fragmented_superpage connect ppn_data_barrier_7.io.x.c, _ppn_data_WIRE_14.c connect ppn_data_barrier_7.io.x.eff, _ppn_data_WIRE_14.eff connect ppn_data_barrier_7.io.x.paa, _ppn_data_WIRE_14.paa connect ppn_data_barrier_7.io.x.pal, _ppn_data_WIRE_14.pal connect ppn_data_barrier_7.io.x.pr, _ppn_data_WIRE_14.pr connect ppn_data_barrier_7.io.x.px, _ppn_data_WIRE_14.px connect ppn_data_barrier_7.io.x.pw, _ppn_data_WIRE_14.pw connect ppn_data_barrier_7.io.x.sr, _ppn_data_WIRE_14.sr connect ppn_data_barrier_7.io.x.sx, _ppn_data_WIRE_14.sx connect ppn_data_barrier_7.io.x.sw, _ppn_data_WIRE_14.sw connect ppn_data_barrier_7.io.x.ae, _ppn_data_WIRE_14.ae connect ppn_data_barrier_7.io.x.g, _ppn_data_WIRE_14.g connect ppn_data_barrier_7.io.x.u, _ppn_data_WIRE_14.u connect ppn_data_barrier_7.io.x.ppn, _ppn_data_WIRE_14.ppn wire _ppn_data_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_17 : UInt<34> connect _ppn_data_WIRE_17, superpage_entries[0].data[0] node _ppn_data_T_128 = bits(_ppn_data_WIRE_17, 0, 0) connect _ppn_data_WIRE_16.fragmented_superpage, _ppn_data_T_128 node _ppn_data_T_129 = bits(_ppn_data_WIRE_17, 1, 1) connect _ppn_data_WIRE_16.c, _ppn_data_T_129 node _ppn_data_T_130 = bits(_ppn_data_WIRE_17, 2, 2) connect _ppn_data_WIRE_16.eff, _ppn_data_T_130 node _ppn_data_T_131 = bits(_ppn_data_WIRE_17, 3, 3) connect _ppn_data_WIRE_16.paa, _ppn_data_T_131 node _ppn_data_T_132 = bits(_ppn_data_WIRE_17, 4, 4) connect _ppn_data_WIRE_16.pal, _ppn_data_T_132 node _ppn_data_T_133 = bits(_ppn_data_WIRE_17, 5, 5) connect _ppn_data_WIRE_16.pr, _ppn_data_T_133 node _ppn_data_T_134 = bits(_ppn_data_WIRE_17, 6, 6) connect _ppn_data_WIRE_16.px, _ppn_data_T_134 node _ppn_data_T_135 = bits(_ppn_data_WIRE_17, 7, 7) connect _ppn_data_WIRE_16.pw, _ppn_data_T_135 node _ppn_data_T_136 = bits(_ppn_data_WIRE_17, 8, 8) connect _ppn_data_WIRE_16.sr, _ppn_data_T_136 node _ppn_data_T_137 = bits(_ppn_data_WIRE_17, 9, 9) connect _ppn_data_WIRE_16.sx, _ppn_data_T_137 node _ppn_data_T_138 = bits(_ppn_data_WIRE_17, 10, 10) connect _ppn_data_WIRE_16.sw, _ppn_data_T_138 node _ppn_data_T_139 = bits(_ppn_data_WIRE_17, 11, 11) connect _ppn_data_WIRE_16.ae, _ppn_data_T_139 node _ppn_data_T_140 = bits(_ppn_data_WIRE_17, 12, 12) connect _ppn_data_WIRE_16.g, _ppn_data_T_140 node _ppn_data_T_141 = bits(_ppn_data_WIRE_17, 13, 13) connect _ppn_data_WIRE_16.u, _ppn_data_T_141 node _ppn_data_T_142 = bits(_ppn_data_WIRE_17, 33, 14) connect _ppn_data_WIRE_16.ppn, _ppn_data_T_142 inst ppn_data_barrier_8 of OptimizationBarrier_EntryData_9 connect ppn_data_barrier_8.clock, clock connect ppn_data_barrier_8.reset, reset connect ppn_data_barrier_8.io.x.fragmented_superpage, _ppn_data_WIRE_16.fragmented_superpage connect ppn_data_barrier_8.io.x.c, _ppn_data_WIRE_16.c connect ppn_data_barrier_8.io.x.eff, _ppn_data_WIRE_16.eff connect ppn_data_barrier_8.io.x.paa, _ppn_data_WIRE_16.paa connect ppn_data_barrier_8.io.x.pal, _ppn_data_WIRE_16.pal connect ppn_data_barrier_8.io.x.pr, _ppn_data_WIRE_16.pr connect ppn_data_barrier_8.io.x.px, _ppn_data_WIRE_16.px connect ppn_data_barrier_8.io.x.pw, _ppn_data_WIRE_16.pw connect ppn_data_barrier_8.io.x.sr, _ppn_data_WIRE_16.sr connect ppn_data_barrier_8.io.x.sx, _ppn_data_WIRE_16.sx connect ppn_data_barrier_8.io.x.sw, _ppn_data_WIRE_16.sw connect ppn_data_barrier_8.io.x.ae, _ppn_data_WIRE_16.ae connect ppn_data_barrier_8.io.x.g, _ppn_data_WIRE_16.g connect ppn_data_barrier_8.io.x.u, _ppn_data_WIRE_16.u connect ppn_data_barrier_8.io.x.ppn, _ppn_data_WIRE_16.ppn wire _ppn_data_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_19 : UInt<34> connect _ppn_data_WIRE_19, superpage_entries[1].data[0] node _ppn_data_T_143 = bits(_ppn_data_WIRE_19, 0, 0) connect _ppn_data_WIRE_18.fragmented_superpage, _ppn_data_T_143 node _ppn_data_T_144 = bits(_ppn_data_WIRE_19, 1, 1) connect _ppn_data_WIRE_18.c, _ppn_data_T_144 node _ppn_data_T_145 = bits(_ppn_data_WIRE_19, 2, 2) connect _ppn_data_WIRE_18.eff, _ppn_data_T_145 node _ppn_data_T_146 = bits(_ppn_data_WIRE_19, 3, 3) connect _ppn_data_WIRE_18.paa, _ppn_data_T_146 node _ppn_data_T_147 = bits(_ppn_data_WIRE_19, 4, 4) connect _ppn_data_WIRE_18.pal, _ppn_data_T_147 node _ppn_data_T_148 = bits(_ppn_data_WIRE_19, 5, 5) connect _ppn_data_WIRE_18.pr, _ppn_data_T_148 node _ppn_data_T_149 = bits(_ppn_data_WIRE_19, 6, 6) connect _ppn_data_WIRE_18.px, _ppn_data_T_149 node _ppn_data_T_150 = bits(_ppn_data_WIRE_19, 7, 7) connect _ppn_data_WIRE_18.pw, _ppn_data_T_150 node _ppn_data_T_151 = bits(_ppn_data_WIRE_19, 8, 8) connect _ppn_data_WIRE_18.sr, _ppn_data_T_151 node _ppn_data_T_152 = bits(_ppn_data_WIRE_19, 9, 9) connect _ppn_data_WIRE_18.sx, _ppn_data_T_152 node _ppn_data_T_153 = bits(_ppn_data_WIRE_19, 10, 10) connect _ppn_data_WIRE_18.sw, _ppn_data_T_153 node _ppn_data_T_154 = bits(_ppn_data_WIRE_19, 11, 11) connect _ppn_data_WIRE_18.ae, _ppn_data_T_154 node _ppn_data_T_155 = bits(_ppn_data_WIRE_19, 12, 12) connect _ppn_data_WIRE_18.g, _ppn_data_T_155 node _ppn_data_T_156 = bits(_ppn_data_WIRE_19, 13, 13) connect _ppn_data_WIRE_18.u, _ppn_data_T_156 node _ppn_data_T_157 = bits(_ppn_data_WIRE_19, 33, 14) connect _ppn_data_WIRE_18.ppn, _ppn_data_T_157 inst ppn_data_barrier_9 of OptimizationBarrier_EntryData_10 connect ppn_data_barrier_9.clock, clock connect ppn_data_barrier_9.reset, reset connect ppn_data_barrier_9.io.x.fragmented_superpage, _ppn_data_WIRE_18.fragmented_superpage connect ppn_data_barrier_9.io.x.c, _ppn_data_WIRE_18.c connect ppn_data_barrier_9.io.x.eff, _ppn_data_WIRE_18.eff connect ppn_data_barrier_9.io.x.paa, _ppn_data_WIRE_18.paa connect ppn_data_barrier_9.io.x.pal, _ppn_data_WIRE_18.pal connect ppn_data_barrier_9.io.x.pr, _ppn_data_WIRE_18.pr connect ppn_data_barrier_9.io.x.px, _ppn_data_WIRE_18.px connect ppn_data_barrier_9.io.x.pw, _ppn_data_WIRE_18.pw connect ppn_data_barrier_9.io.x.sr, _ppn_data_WIRE_18.sr connect ppn_data_barrier_9.io.x.sx, _ppn_data_WIRE_18.sx connect ppn_data_barrier_9.io.x.sw, _ppn_data_WIRE_18.sw connect ppn_data_barrier_9.io.x.ae, _ppn_data_WIRE_18.ae connect ppn_data_barrier_9.io.x.g, _ppn_data_WIRE_18.g connect ppn_data_barrier_9.io.x.u, _ppn_data_WIRE_18.u connect ppn_data_barrier_9.io.x.ppn, _ppn_data_WIRE_18.ppn wire _ppn_data_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_21 : UInt<34> connect _ppn_data_WIRE_21, superpage_entries[2].data[0] node _ppn_data_T_158 = bits(_ppn_data_WIRE_21, 0, 0) connect _ppn_data_WIRE_20.fragmented_superpage, _ppn_data_T_158 node _ppn_data_T_159 = bits(_ppn_data_WIRE_21, 1, 1) connect _ppn_data_WIRE_20.c, _ppn_data_T_159 node _ppn_data_T_160 = bits(_ppn_data_WIRE_21, 2, 2) connect _ppn_data_WIRE_20.eff, _ppn_data_T_160 node _ppn_data_T_161 = bits(_ppn_data_WIRE_21, 3, 3) connect _ppn_data_WIRE_20.paa, _ppn_data_T_161 node _ppn_data_T_162 = bits(_ppn_data_WIRE_21, 4, 4) connect _ppn_data_WIRE_20.pal, _ppn_data_T_162 node _ppn_data_T_163 = bits(_ppn_data_WIRE_21, 5, 5) connect _ppn_data_WIRE_20.pr, _ppn_data_T_163 node _ppn_data_T_164 = bits(_ppn_data_WIRE_21, 6, 6) connect _ppn_data_WIRE_20.px, _ppn_data_T_164 node _ppn_data_T_165 = bits(_ppn_data_WIRE_21, 7, 7) connect _ppn_data_WIRE_20.pw, _ppn_data_T_165 node _ppn_data_T_166 = bits(_ppn_data_WIRE_21, 8, 8) connect _ppn_data_WIRE_20.sr, _ppn_data_T_166 node _ppn_data_T_167 = bits(_ppn_data_WIRE_21, 9, 9) connect _ppn_data_WIRE_20.sx, _ppn_data_T_167 node _ppn_data_T_168 = bits(_ppn_data_WIRE_21, 10, 10) connect _ppn_data_WIRE_20.sw, _ppn_data_T_168 node _ppn_data_T_169 = bits(_ppn_data_WIRE_21, 11, 11) connect _ppn_data_WIRE_20.ae, _ppn_data_T_169 node _ppn_data_T_170 = bits(_ppn_data_WIRE_21, 12, 12) connect _ppn_data_WIRE_20.g, _ppn_data_T_170 node _ppn_data_T_171 = bits(_ppn_data_WIRE_21, 13, 13) connect _ppn_data_WIRE_20.u, _ppn_data_T_171 node _ppn_data_T_172 = bits(_ppn_data_WIRE_21, 33, 14) connect _ppn_data_WIRE_20.ppn, _ppn_data_T_172 inst ppn_data_barrier_10 of OptimizationBarrier_EntryData_11 connect ppn_data_barrier_10.clock, clock connect ppn_data_barrier_10.reset, reset connect ppn_data_barrier_10.io.x.fragmented_superpage, _ppn_data_WIRE_20.fragmented_superpage connect ppn_data_barrier_10.io.x.c, _ppn_data_WIRE_20.c connect ppn_data_barrier_10.io.x.eff, _ppn_data_WIRE_20.eff connect ppn_data_barrier_10.io.x.paa, _ppn_data_WIRE_20.paa connect ppn_data_barrier_10.io.x.pal, _ppn_data_WIRE_20.pal connect ppn_data_barrier_10.io.x.pr, _ppn_data_WIRE_20.pr connect ppn_data_barrier_10.io.x.px, _ppn_data_WIRE_20.px connect ppn_data_barrier_10.io.x.pw, _ppn_data_WIRE_20.pw connect ppn_data_barrier_10.io.x.sr, _ppn_data_WIRE_20.sr connect ppn_data_barrier_10.io.x.sx, _ppn_data_WIRE_20.sx connect ppn_data_barrier_10.io.x.sw, _ppn_data_WIRE_20.sw connect ppn_data_barrier_10.io.x.ae, _ppn_data_WIRE_20.ae connect ppn_data_barrier_10.io.x.g, _ppn_data_WIRE_20.g connect ppn_data_barrier_10.io.x.u, _ppn_data_WIRE_20.u connect ppn_data_barrier_10.io.x.ppn, _ppn_data_WIRE_20.ppn wire _ppn_data_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_23 : UInt<34> connect _ppn_data_WIRE_23, superpage_entries[3].data[0] node _ppn_data_T_173 = bits(_ppn_data_WIRE_23, 0, 0) connect _ppn_data_WIRE_22.fragmented_superpage, _ppn_data_T_173 node _ppn_data_T_174 = bits(_ppn_data_WIRE_23, 1, 1) connect _ppn_data_WIRE_22.c, _ppn_data_T_174 node _ppn_data_T_175 = bits(_ppn_data_WIRE_23, 2, 2) connect _ppn_data_WIRE_22.eff, _ppn_data_T_175 node _ppn_data_T_176 = bits(_ppn_data_WIRE_23, 3, 3) connect _ppn_data_WIRE_22.paa, _ppn_data_T_176 node _ppn_data_T_177 = bits(_ppn_data_WIRE_23, 4, 4) connect _ppn_data_WIRE_22.pal, _ppn_data_T_177 node _ppn_data_T_178 = bits(_ppn_data_WIRE_23, 5, 5) connect _ppn_data_WIRE_22.pr, _ppn_data_T_178 node _ppn_data_T_179 = bits(_ppn_data_WIRE_23, 6, 6) connect _ppn_data_WIRE_22.px, _ppn_data_T_179 node _ppn_data_T_180 = bits(_ppn_data_WIRE_23, 7, 7) connect _ppn_data_WIRE_22.pw, _ppn_data_T_180 node _ppn_data_T_181 = bits(_ppn_data_WIRE_23, 8, 8) connect _ppn_data_WIRE_22.sr, _ppn_data_T_181 node _ppn_data_T_182 = bits(_ppn_data_WIRE_23, 9, 9) connect _ppn_data_WIRE_22.sx, _ppn_data_T_182 node _ppn_data_T_183 = bits(_ppn_data_WIRE_23, 10, 10) connect _ppn_data_WIRE_22.sw, _ppn_data_T_183 node _ppn_data_T_184 = bits(_ppn_data_WIRE_23, 11, 11) connect _ppn_data_WIRE_22.ae, _ppn_data_T_184 node _ppn_data_T_185 = bits(_ppn_data_WIRE_23, 12, 12) connect _ppn_data_WIRE_22.g, _ppn_data_T_185 node _ppn_data_T_186 = bits(_ppn_data_WIRE_23, 13, 13) connect _ppn_data_WIRE_22.u, _ppn_data_T_186 node _ppn_data_T_187 = bits(_ppn_data_WIRE_23, 33, 14) connect _ppn_data_WIRE_22.ppn, _ppn_data_T_187 inst ppn_data_barrier_11 of OptimizationBarrier_EntryData_12 connect ppn_data_barrier_11.clock, clock connect ppn_data_barrier_11.reset, reset connect ppn_data_barrier_11.io.x.fragmented_superpage, _ppn_data_WIRE_22.fragmented_superpage connect ppn_data_barrier_11.io.x.c, _ppn_data_WIRE_22.c connect ppn_data_barrier_11.io.x.eff, _ppn_data_WIRE_22.eff connect ppn_data_barrier_11.io.x.paa, _ppn_data_WIRE_22.paa connect ppn_data_barrier_11.io.x.pal, _ppn_data_WIRE_22.pal connect ppn_data_barrier_11.io.x.pr, _ppn_data_WIRE_22.pr connect ppn_data_barrier_11.io.x.px, _ppn_data_WIRE_22.px connect ppn_data_barrier_11.io.x.pw, _ppn_data_WIRE_22.pw connect ppn_data_barrier_11.io.x.sr, _ppn_data_WIRE_22.sr connect ppn_data_barrier_11.io.x.sx, _ppn_data_WIRE_22.sx connect ppn_data_barrier_11.io.x.sw, _ppn_data_WIRE_22.sw connect ppn_data_barrier_11.io.x.ae, _ppn_data_WIRE_22.ae connect ppn_data_barrier_11.io.x.g, _ppn_data_WIRE_22.g connect ppn_data_barrier_11.io.x.u, _ppn_data_WIRE_22.u connect ppn_data_barrier_11.io.x.ppn, _ppn_data_WIRE_22.ppn wire _ppn_data_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_25 : UInt<34> connect _ppn_data_WIRE_25, special_entry.data[0] node _ppn_data_T_188 = bits(_ppn_data_WIRE_25, 0, 0) connect _ppn_data_WIRE_24.fragmented_superpage, _ppn_data_T_188 node _ppn_data_T_189 = bits(_ppn_data_WIRE_25, 1, 1) connect _ppn_data_WIRE_24.c, _ppn_data_T_189 node _ppn_data_T_190 = bits(_ppn_data_WIRE_25, 2, 2) connect _ppn_data_WIRE_24.eff, _ppn_data_T_190 node _ppn_data_T_191 = bits(_ppn_data_WIRE_25, 3, 3) connect _ppn_data_WIRE_24.paa, _ppn_data_T_191 node _ppn_data_T_192 = bits(_ppn_data_WIRE_25, 4, 4) connect _ppn_data_WIRE_24.pal, _ppn_data_T_192 node _ppn_data_T_193 = bits(_ppn_data_WIRE_25, 5, 5) connect _ppn_data_WIRE_24.pr, _ppn_data_T_193 node _ppn_data_T_194 = bits(_ppn_data_WIRE_25, 6, 6) connect _ppn_data_WIRE_24.px, _ppn_data_T_194 node _ppn_data_T_195 = bits(_ppn_data_WIRE_25, 7, 7) connect _ppn_data_WIRE_24.pw, _ppn_data_T_195 node _ppn_data_T_196 = bits(_ppn_data_WIRE_25, 8, 8) connect _ppn_data_WIRE_24.sr, _ppn_data_T_196 node _ppn_data_T_197 = bits(_ppn_data_WIRE_25, 9, 9) connect _ppn_data_WIRE_24.sx, _ppn_data_T_197 node _ppn_data_T_198 = bits(_ppn_data_WIRE_25, 10, 10) connect _ppn_data_WIRE_24.sw, _ppn_data_T_198 node _ppn_data_T_199 = bits(_ppn_data_WIRE_25, 11, 11) connect _ppn_data_WIRE_24.ae, _ppn_data_T_199 node _ppn_data_T_200 = bits(_ppn_data_WIRE_25, 12, 12) connect _ppn_data_WIRE_24.g, _ppn_data_T_200 node _ppn_data_T_201 = bits(_ppn_data_WIRE_25, 13, 13) connect _ppn_data_WIRE_24.u, _ppn_data_T_201 node _ppn_data_T_202 = bits(_ppn_data_WIRE_25, 33, 14) connect _ppn_data_WIRE_24.ppn, _ppn_data_T_202 inst ppn_data_barrier_12 of OptimizationBarrier_EntryData_13 connect ppn_data_barrier_12.clock, clock connect ppn_data_barrier_12.reset, reset connect ppn_data_barrier_12.io.x.fragmented_superpage, _ppn_data_WIRE_24.fragmented_superpage connect ppn_data_barrier_12.io.x.c, _ppn_data_WIRE_24.c connect ppn_data_barrier_12.io.x.eff, _ppn_data_WIRE_24.eff connect ppn_data_barrier_12.io.x.paa, _ppn_data_WIRE_24.paa connect ppn_data_barrier_12.io.x.pal, _ppn_data_WIRE_24.pal connect ppn_data_barrier_12.io.x.pr, _ppn_data_WIRE_24.pr connect ppn_data_barrier_12.io.x.px, _ppn_data_WIRE_24.px connect ppn_data_barrier_12.io.x.pw, _ppn_data_WIRE_24.pw connect ppn_data_barrier_12.io.x.sr, _ppn_data_WIRE_24.sr connect ppn_data_barrier_12.io.x.sx, _ppn_data_WIRE_24.sx connect ppn_data_barrier_12.io.x.sw, _ppn_data_WIRE_24.sw connect ppn_data_barrier_12.io.x.ae, _ppn_data_WIRE_24.ae connect ppn_data_barrier_12.io.x.g, _ppn_data_WIRE_24.g connect ppn_data_barrier_12.io.x.u, _ppn_data_WIRE_24.u connect ppn_data_barrier_12.io.x.ppn, _ppn_data_WIRE_24.ppn node _ppn_T_1 = bits(vpn[0], 19, 0) node _ppn_T_2 = mux(hitsVec[0][0], ppn_data_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_3 = mux(hitsVec[0][1], ppn_data_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_4 = mux(hitsVec[0][2], ppn_data_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_5 = mux(hitsVec[0][3], ppn_data_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_6 = mux(hitsVec[0][4], ppn_data_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_7 = mux(hitsVec[0][5], ppn_data_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_8 = mux(hitsVec[0][6], ppn_data_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_9 = mux(hitsVec[0][7], ppn_data_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_10 = mux(hitsVec[0][8], ppn_data_barrier_8.io.y.ppn, UInt<1>(0h0)) node _ppn_T_11 = mux(hitsVec[0][9], ppn_data_barrier_9.io.y.ppn, UInt<1>(0h0)) node _ppn_T_12 = mux(hitsVec[0][10], ppn_data_barrier_10.io.y.ppn, UInt<1>(0h0)) node _ppn_T_13 = mux(hitsVec[0][11], ppn_data_barrier_11.io.y.ppn, UInt<1>(0h0)) node _ppn_T_14 = mux(hitsVec[0][12], ppn_data_barrier_12.io.y.ppn, UInt<1>(0h0)) node _ppn_T_15 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0)) node _ppn_T_16 = or(_ppn_T_2, _ppn_T_3) node _ppn_T_17 = or(_ppn_T_16, _ppn_T_4) node _ppn_T_18 = or(_ppn_T_17, _ppn_T_5) node _ppn_T_19 = or(_ppn_T_18, _ppn_T_6) node _ppn_T_20 = or(_ppn_T_19, _ppn_T_7) node _ppn_T_21 = or(_ppn_T_20, _ppn_T_8) node _ppn_T_22 = or(_ppn_T_21, _ppn_T_9) node _ppn_T_23 = or(_ppn_T_22, _ppn_T_10) node _ppn_T_24 = or(_ppn_T_23, _ppn_T_11) node _ppn_T_25 = or(_ppn_T_24, _ppn_T_12) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_13) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_14) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_15) wire _ppn_WIRE : UInt<20> connect _ppn_WIRE, _ppn_T_28 wire ppn : UInt<20>[1] connect ppn[0], _ppn_WIRE when do_refill : wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable[0] connect newEntry.u, io.ptw.resp.bits.pte.u connect newEntry.g, io.ptw.resp.bits.pte.g connect newEntry.ae, io.ptw.resp.bits.ae_final node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r[0] connect newEntry.pw, prot_w[0] connect newEntry.px, prot_x[0] connect newEntry.pal, prot_al[0] connect newEntry.paa, prot_aa[0] connect newEntry.eff, prot_eff[0] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag, r_refill_tag node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, newEntry.fragmented_superpage) node special_entry_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node special_entry_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node special_entry_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag, r_refill_tag node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_0_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_0_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag, r_refill_tag node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_1_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_1_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag, r_refill_tag node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_2_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_2_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag, r_refill_tag node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_3_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_3_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T else : node waddr = mux(r_sectored_hit, r_sectored_hit_addr, r_sectored_repl_addr) node _T_7 = eq(waddr, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) connect sectored_entries[0].tag, r_refill_tag connect sectored_entries[0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0].valid[idx], UInt<1>(0h1) node sectored_entries_0_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_0_data_lo_lo = cat(sectored_entries_0_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_0_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_lo_hi = cat(sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo) node sectored_entries_0_data_lo = cat(sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo) node sectored_entries_0_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_0_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_0_data_hi_lo = cat(sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo) node sectored_entries_0_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_0_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_hi_hi = cat(sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo) node sectored_entries_0_data_hi = cat(sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo) node _sectored_entries_0_data_T = cat(sectored_entries_0_data_hi, sectored_entries_0_data_lo) connect sectored_entries[0].data[idx], _sectored_entries_0_data_T node _T_9 = eq(waddr, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_10 : connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) connect sectored_entries[1].tag, r_refill_tag connect sectored_entries[1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[1].valid[idx_1], UInt<1>(0h1) node sectored_entries_1_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_1_data_lo_lo = cat(sectored_entries_1_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_1_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_lo_hi = cat(sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo) node sectored_entries_1_data_lo = cat(sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo) node sectored_entries_1_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_1_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_1_data_hi_lo = cat(sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo) node sectored_entries_1_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_1_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_hi_hi = cat(sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo) node sectored_entries_1_data_hi = cat(sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo) node _sectored_entries_1_data_T = cat(sectored_entries_1_data_hi, sectored_entries_1_data_lo) connect sectored_entries[1].data[idx_1], _sectored_entries_1_data_T node _T_11 = eq(waddr, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_12 : connect sectored_entries[2].valid[0], UInt<1>(0h0) connect sectored_entries[2].valid[1], UInt<1>(0h0) connect sectored_entries[2].valid[2], UInt<1>(0h0) connect sectored_entries[2].valid[3], UInt<1>(0h0) connect sectored_entries[2].tag, r_refill_tag connect sectored_entries[2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[2].valid[idx_2], UInt<1>(0h1) node sectored_entries_2_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_2_data_lo_lo = cat(sectored_entries_2_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_2_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_lo_hi = cat(sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo) node sectored_entries_2_data_lo = cat(sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo) node sectored_entries_2_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_2_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_2_data_hi_lo = cat(sectored_entries_2_data_hi_lo_hi, sectored_entries_2_data_hi_lo_lo) node sectored_entries_2_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_2_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_hi_hi = cat(sectored_entries_2_data_hi_hi_hi, sectored_entries_2_data_hi_hi_lo) node sectored_entries_2_data_hi = cat(sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo) node _sectored_entries_2_data_T = cat(sectored_entries_2_data_hi, sectored_entries_2_data_lo) connect sectored_entries[2].data[idx_2], _sectored_entries_2_data_T node _T_13 = eq(waddr, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_14 : connect sectored_entries[3].valid[0], UInt<1>(0h0) connect sectored_entries[3].valid[1], UInt<1>(0h0) connect sectored_entries[3].valid[2], UInt<1>(0h0) connect sectored_entries[3].valid[3], UInt<1>(0h0) connect sectored_entries[3].tag, r_refill_tag connect sectored_entries[3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[3].valid[idx_3], UInt<1>(0h1) node sectored_entries_3_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_3_data_lo_lo = cat(sectored_entries_3_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_3_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_lo_hi = cat(sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo) node sectored_entries_3_data_lo = cat(sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo) node sectored_entries_3_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_3_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_3_data_hi_lo = cat(sectored_entries_3_data_hi_lo_hi, sectored_entries_3_data_hi_lo_lo) node sectored_entries_3_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_3_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_hi_hi = cat(sectored_entries_3_data_hi_hi_hi, sectored_entries_3_data_hi_hi_lo) node sectored_entries_3_data_hi = cat(sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo) node _sectored_entries_3_data_T = cat(sectored_entries_3_data_hi, sectored_entries_3_data_lo) connect sectored_entries[3].data[idx_3], _sectored_entries_3_data_T node _T_15 = eq(waddr, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_16 : connect sectored_entries[4].valid[0], UInt<1>(0h0) connect sectored_entries[4].valid[1], UInt<1>(0h0) connect sectored_entries[4].valid[2], UInt<1>(0h0) connect sectored_entries[4].valid[3], UInt<1>(0h0) connect sectored_entries[4].tag, r_refill_tag connect sectored_entries[4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[4].valid[idx_4], UInt<1>(0h1) node sectored_entries_4_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_4_data_lo_lo = cat(sectored_entries_4_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_4_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_4_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_4_data_lo_hi = cat(sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo) node sectored_entries_4_data_lo = cat(sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo) node sectored_entries_4_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_4_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_4_data_hi_lo = cat(sectored_entries_4_data_hi_lo_hi, sectored_entries_4_data_hi_lo_lo) node sectored_entries_4_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_4_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_4_data_hi_hi = cat(sectored_entries_4_data_hi_hi_hi, sectored_entries_4_data_hi_hi_lo) node sectored_entries_4_data_hi = cat(sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo) node _sectored_entries_4_data_T = cat(sectored_entries_4_data_hi, sectored_entries_4_data_lo) connect sectored_entries[4].data[idx_4], _sectored_entries_4_data_T node _T_17 = eq(waddr, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_18 : connect sectored_entries[5].valid[0], UInt<1>(0h0) connect sectored_entries[5].valid[1], UInt<1>(0h0) connect sectored_entries[5].valid[2], UInt<1>(0h0) connect sectored_entries[5].valid[3], UInt<1>(0h0) connect sectored_entries[5].tag, r_refill_tag connect sectored_entries[5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[5].valid[idx_5], UInt<1>(0h1) node sectored_entries_5_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_5_data_lo_lo = cat(sectored_entries_5_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_5_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_5_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_5_data_lo_hi = cat(sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo) node sectored_entries_5_data_lo = cat(sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo) node sectored_entries_5_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_5_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_5_data_hi_lo = cat(sectored_entries_5_data_hi_lo_hi, sectored_entries_5_data_hi_lo_lo) node sectored_entries_5_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_5_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_5_data_hi_hi = cat(sectored_entries_5_data_hi_hi_hi, sectored_entries_5_data_hi_hi_lo) node sectored_entries_5_data_hi = cat(sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo) node _sectored_entries_5_data_T = cat(sectored_entries_5_data_hi, sectored_entries_5_data_lo) connect sectored_entries[5].data[idx_5], _sectored_entries_5_data_T node _T_19 = eq(waddr, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_20 : connect sectored_entries[6].valid[0], UInt<1>(0h0) connect sectored_entries[6].valid[1], UInt<1>(0h0) connect sectored_entries[6].valid[2], UInt<1>(0h0) connect sectored_entries[6].valid[3], UInt<1>(0h0) connect sectored_entries[6].tag, r_refill_tag connect sectored_entries[6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[6].valid[idx_6], UInt<1>(0h1) node sectored_entries_6_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_6_data_lo_lo = cat(sectored_entries_6_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_6_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_6_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_6_data_lo_hi = cat(sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo) node sectored_entries_6_data_lo = cat(sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo) node sectored_entries_6_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_6_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_6_data_hi_lo = cat(sectored_entries_6_data_hi_lo_hi, sectored_entries_6_data_hi_lo_lo) node sectored_entries_6_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_6_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_6_data_hi_hi = cat(sectored_entries_6_data_hi_hi_hi, sectored_entries_6_data_hi_hi_lo) node sectored_entries_6_data_hi = cat(sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo) node _sectored_entries_6_data_T = cat(sectored_entries_6_data_hi, sectored_entries_6_data_lo) connect sectored_entries[6].data[idx_6], _sectored_entries_6_data_T node _T_21 = eq(waddr, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_22 : connect sectored_entries[7].valid[0], UInt<1>(0h0) connect sectored_entries[7].valid[1], UInt<1>(0h0) connect sectored_entries[7].valid[2], UInt<1>(0h0) connect sectored_entries[7].valid[3], UInt<1>(0h0) connect sectored_entries[7].tag, r_refill_tag connect sectored_entries[7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[7].valid[idx_7], UInt<1>(0h1) node sectored_entries_7_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_7_data_lo_lo = cat(sectored_entries_7_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_7_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_7_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_7_data_lo_hi = cat(sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo) node sectored_entries_7_data_lo = cat(sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo) node sectored_entries_7_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_7_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_7_data_hi_lo = cat(sectored_entries_7_data_hi_lo_hi, sectored_entries_7_data_hi_lo_lo) node sectored_entries_7_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_7_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_7_data_hi_hi = cat(sectored_entries_7_data_hi_hi_hi, sectored_entries_7_data_hi_hi_lo) node sectored_entries_7_data_hi = cat(sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo) node _sectored_entries_7_data_T = cat(sectored_entries_7_data_hi, sectored_entries_7_data_lo) connect sectored_entries[7].data[idx_7], _sectored_entries_7_data_T node _entries_T = bits(vpn[0], 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<34> connect _entries_WIRE_1, sectored_entries[0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.sr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.sx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.sw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.ae, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.g, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.u, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 33, 14) connect _entries_WIRE.ppn, _entries_T_15 inst entries_barrier of OptimizationBarrier_EntryData_14 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.ae, _entries_WIRE.ae connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_16 = bits(vpn[0], 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<34> connect _entries_WIRE_3, sectored_entries[1].data[_entries_T_16] node _entries_T_17 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.pr, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.px, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.pw, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.sr, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.sx, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.sw, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.ae, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.g, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.u, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 33, 14) connect _entries_WIRE_2.ppn, _entries_T_31 inst entries_barrier_1 of OptimizationBarrier_EntryData_15 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.ae, _entries_WIRE_2.ae connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_32 = bits(vpn[0], 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<34> connect _entries_WIRE_5, sectored_entries[2].data[_entries_T_32] node _entries_T_33 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.pr, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.px, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.pw, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.sr, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.sx, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.sw, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.ae, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 33, 14) connect _entries_WIRE_4.ppn, _entries_T_47 inst entries_barrier_2 of OptimizationBarrier_EntryData_16 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.ae, _entries_WIRE_4.ae connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_48 = bits(vpn[0], 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<34> connect _entries_WIRE_7, sectored_entries[3].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.pr, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.px, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.pw, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.sr, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.sx, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.sw, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.ae, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.g, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.u, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_7, 33, 14) connect _entries_WIRE_6.ppn, _entries_T_63 inst entries_barrier_3 of OptimizationBarrier_EntryData_17 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.ae, _entries_WIRE_6.ae connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_64 = bits(vpn[0], 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<34> connect _entries_WIRE_9, sectored_entries[4].data[_entries_T_64] node _entries_T_65 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.pr, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.px, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.pw, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.sr, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.sx, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.sw, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.ae, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.g, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.u, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_9, 33, 14) connect _entries_WIRE_8.ppn, _entries_T_79 inst entries_barrier_4 of OptimizationBarrier_EntryData_18 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.ae, _entries_WIRE_8.ae connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_80 = bits(vpn[0], 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<34> connect _entries_WIRE_11, sectored_entries[5].data[_entries_T_80] node _entries_T_81 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.pr, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.px, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.pw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.sr, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.sx, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.sw, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.ae, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_11, 33, 14) connect _entries_WIRE_10.ppn, _entries_T_95 inst entries_barrier_5 of OptimizationBarrier_EntryData_19 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.ae, _entries_WIRE_10.ae connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_96 = bits(vpn[0], 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<34> connect _entries_WIRE_13, sectored_entries[6].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.pr, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.px, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.pw, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.sr, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.sx, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.sw, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.ae, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.g, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.u, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_13, 33, 14) connect _entries_WIRE_12.ppn, _entries_T_111 inst entries_barrier_6 of OptimizationBarrier_EntryData_20 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.ae, _entries_WIRE_12.ae connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_112 = bits(vpn[0], 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<34> connect _entries_WIRE_15, sectored_entries[7].data[_entries_T_112] node _entries_T_113 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.pr, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.px, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.pw, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.sr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.sx, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.sw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.ae, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.g, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.u, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_15, 33, 14) connect _entries_WIRE_14.ppn, _entries_T_127 inst entries_barrier_7 of OptimizationBarrier_EntryData_21 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.ae, _entries_WIRE_14.ae connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<34> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_128 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.pr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.px, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.pw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.sr, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.sx, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.sw, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.ae, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.g, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.u, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_17, 33, 14) connect _entries_WIRE_16.ppn, _entries_T_142 inst entries_barrier_8 of OptimizationBarrier_EntryData_22 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.ae, _entries_WIRE_16.ae connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<34> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_143 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_143 node _entries_T_144 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_144 node _entries_T_145 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.pr, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.px, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.pw, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.sr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.sx, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.sw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.ae, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.g, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.u, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_19, 33, 14) connect _entries_WIRE_18.ppn, _entries_T_157 inst entries_barrier_9 of OptimizationBarrier_EntryData_23 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.ae, _entries_WIRE_18.ae connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<34> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_158 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.pr, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.px, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.pw, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.sr, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.sx, _entries_T_167 node _entries_T_168 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.sw, _entries_T_168 node _entries_T_169 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.ae, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.g, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.u, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_21, 33, 14) connect _entries_WIRE_20.ppn, _entries_T_172 inst entries_barrier_10 of OptimizationBarrier_EntryData_24 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.ae, _entries_WIRE_20.ae connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<34> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_173 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.pr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.px, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.pw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.ae, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.g, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.u, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_23, 33, 14) connect _entries_WIRE_22.ppn, _entries_T_187 inst entries_barrier_11 of OptimizationBarrier_EntryData_25 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.ae, _entries_WIRE_22.ae connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<34> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_188 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_191 node _entries_T_192 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.pr, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.px, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.pw, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.sr, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.sx, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.sw, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.ae, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.g, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.u, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_25, 33, 14) connect _entries_WIRE_24.ppn, _entries_T_202 inst entries_barrier_12 of OptimizationBarrier_EntryData_26 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.ae, _entries_WIRE_24.ae connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn wire _entries_WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[13] connect _entries_WIRE_26[0], entries_barrier.io.y connect _entries_WIRE_26[1], entries_barrier_1.io.y connect _entries_WIRE_26[2], entries_barrier_2.io.y connect _entries_WIRE_26[3], entries_barrier_3.io.y connect _entries_WIRE_26[4], entries_barrier_4.io.y connect _entries_WIRE_26[5], entries_barrier_5.io.y connect _entries_WIRE_26[6], entries_barrier_6.io.y connect _entries_WIRE_26[7], entries_barrier_7.io.y connect _entries_WIRE_26[8], entries_barrier_8.io.y connect _entries_WIRE_26[9], entries_barrier_9.io.y connect _entries_WIRE_26[10], entries_barrier_10.io.y connect _entries_WIRE_26[11], entries_barrier_11.io.y connect _entries_WIRE_26[12], entries_barrier_12.io.y wire entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[13][1] connect entries[0], _entries_WIRE_26 node _normal_entries_T = bits(vpn[0], 1, 0) wire _normal_entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_1 : UInt<34> connect _normal_entries_WIRE_1, sectored_entries[0].data[_normal_entries_T] node _normal_entries_T_1 = bits(_normal_entries_WIRE_1, 0, 0) connect _normal_entries_WIRE.fragmented_superpage, _normal_entries_T_1 node _normal_entries_T_2 = bits(_normal_entries_WIRE_1, 1, 1) connect _normal_entries_WIRE.c, _normal_entries_T_2 node _normal_entries_T_3 = bits(_normal_entries_WIRE_1, 2, 2) connect _normal_entries_WIRE.eff, _normal_entries_T_3 node _normal_entries_T_4 = bits(_normal_entries_WIRE_1, 3, 3) connect _normal_entries_WIRE.paa, _normal_entries_T_4 node _normal_entries_T_5 = bits(_normal_entries_WIRE_1, 4, 4) connect _normal_entries_WIRE.pal, _normal_entries_T_5 node _normal_entries_T_6 = bits(_normal_entries_WIRE_1, 5, 5) connect _normal_entries_WIRE.pr, _normal_entries_T_6 node _normal_entries_T_7 = bits(_normal_entries_WIRE_1, 6, 6) connect _normal_entries_WIRE.px, _normal_entries_T_7 node _normal_entries_T_8 = bits(_normal_entries_WIRE_1, 7, 7) connect _normal_entries_WIRE.pw, _normal_entries_T_8 node _normal_entries_T_9 = bits(_normal_entries_WIRE_1, 8, 8) connect _normal_entries_WIRE.sr, _normal_entries_T_9 node _normal_entries_T_10 = bits(_normal_entries_WIRE_1, 9, 9) connect _normal_entries_WIRE.sx, _normal_entries_T_10 node _normal_entries_T_11 = bits(_normal_entries_WIRE_1, 10, 10) connect _normal_entries_WIRE.sw, _normal_entries_T_11 node _normal_entries_T_12 = bits(_normal_entries_WIRE_1, 11, 11) connect _normal_entries_WIRE.ae, _normal_entries_T_12 node _normal_entries_T_13 = bits(_normal_entries_WIRE_1, 12, 12) connect _normal_entries_WIRE.g, _normal_entries_T_13 node _normal_entries_T_14 = bits(_normal_entries_WIRE_1, 13, 13) connect _normal_entries_WIRE.u, _normal_entries_T_14 node _normal_entries_T_15 = bits(_normal_entries_WIRE_1, 33, 14) connect _normal_entries_WIRE.ppn, _normal_entries_T_15 inst normal_entries_barrier of OptimizationBarrier_EntryData_27 connect normal_entries_barrier.clock, clock connect normal_entries_barrier.reset, reset connect normal_entries_barrier.io.x.fragmented_superpage, _normal_entries_WIRE.fragmented_superpage connect normal_entries_barrier.io.x.c, _normal_entries_WIRE.c connect normal_entries_barrier.io.x.eff, _normal_entries_WIRE.eff connect normal_entries_barrier.io.x.paa, _normal_entries_WIRE.paa connect normal_entries_barrier.io.x.pal, _normal_entries_WIRE.pal connect normal_entries_barrier.io.x.pr, _normal_entries_WIRE.pr connect normal_entries_barrier.io.x.px, _normal_entries_WIRE.px connect normal_entries_barrier.io.x.pw, _normal_entries_WIRE.pw connect normal_entries_barrier.io.x.sr, _normal_entries_WIRE.sr connect normal_entries_barrier.io.x.sx, _normal_entries_WIRE.sx connect normal_entries_barrier.io.x.sw, _normal_entries_WIRE.sw connect normal_entries_barrier.io.x.ae, _normal_entries_WIRE.ae connect normal_entries_barrier.io.x.g, _normal_entries_WIRE.g connect normal_entries_barrier.io.x.u, _normal_entries_WIRE.u connect normal_entries_barrier.io.x.ppn, _normal_entries_WIRE.ppn node _normal_entries_T_16 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_3 : UInt<34> connect _normal_entries_WIRE_3, sectored_entries[1].data[_normal_entries_T_16] node _normal_entries_T_17 = bits(_normal_entries_WIRE_3, 0, 0) connect _normal_entries_WIRE_2.fragmented_superpage, _normal_entries_T_17 node _normal_entries_T_18 = bits(_normal_entries_WIRE_3, 1, 1) connect _normal_entries_WIRE_2.c, _normal_entries_T_18 node _normal_entries_T_19 = bits(_normal_entries_WIRE_3, 2, 2) connect _normal_entries_WIRE_2.eff, _normal_entries_T_19 node _normal_entries_T_20 = bits(_normal_entries_WIRE_3, 3, 3) connect _normal_entries_WIRE_2.paa, _normal_entries_T_20 node _normal_entries_T_21 = bits(_normal_entries_WIRE_3, 4, 4) connect _normal_entries_WIRE_2.pal, _normal_entries_T_21 node _normal_entries_T_22 = bits(_normal_entries_WIRE_3, 5, 5) connect _normal_entries_WIRE_2.pr, _normal_entries_T_22 node _normal_entries_T_23 = bits(_normal_entries_WIRE_3, 6, 6) connect _normal_entries_WIRE_2.px, _normal_entries_T_23 node _normal_entries_T_24 = bits(_normal_entries_WIRE_3, 7, 7) connect _normal_entries_WIRE_2.pw, _normal_entries_T_24 node _normal_entries_T_25 = bits(_normal_entries_WIRE_3, 8, 8) connect _normal_entries_WIRE_2.sr, _normal_entries_T_25 node _normal_entries_T_26 = bits(_normal_entries_WIRE_3, 9, 9) connect _normal_entries_WIRE_2.sx, _normal_entries_T_26 node _normal_entries_T_27 = bits(_normal_entries_WIRE_3, 10, 10) connect _normal_entries_WIRE_2.sw, _normal_entries_T_27 node _normal_entries_T_28 = bits(_normal_entries_WIRE_3, 11, 11) connect _normal_entries_WIRE_2.ae, _normal_entries_T_28 node _normal_entries_T_29 = bits(_normal_entries_WIRE_3, 12, 12) connect _normal_entries_WIRE_2.g, _normal_entries_T_29 node _normal_entries_T_30 = bits(_normal_entries_WIRE_3, 13, 13) connect _normal_entries_WIRE_2.u, _normal_entries_T_30 node _normal_entries_T_31 = bits(_normal_entries_WIRE_3, 33, 14) connect _normal_entries_WIRE_2.ppn, _normal_entries_T_31 inst normal_entries_barrier_1 of OptimizationBarrier_EntryData_28 connect normal_entries_barrier_1.clock, clock connect normal_entries_barrier_1.reset, reset connect normal_entries_barrier_1.io.x.fragmented_superpage, _normal_entries_WIRE_2.fragmented_superpage connect normal_entries_barrier_1.io.x.c, _normal_entries_WIRE_2.c connect normal_entries_barrier_1.io.x.eff, _normal_entries_WIRE_2.eff connect normal_entries_barrier_1.io.x.paa, _normal_entries_WIRE_2.paa connect normal_entries_barrier_1.io.x.pal, _normal_entries_WIRE_2.pal connect normal_entries_barrier_1.io.x.pr, _normal_entries_WIRE_2.pr connect normal_entries_barrier_1.io.x.px, _normal_entries_WIRE_2.px connect normal_entries_barrier_1.io.x.pw, _normal_entries_WIRE_2.pw connect normal_entries_barrier_1.io.x.sr, _normal_entries_WIRE_2.sr connect normal_entries_barrier_1.io.x.sx, _normal_entries_WIRE_2.sx connect normal_entries_barrier_1.io.x.sw, _normal_entries_WIRE_2.sw connect normal_entries_barrier_1.io.x.ae, _normal_entries_WIRE_2.ae connect normal_entries_barrier_1.io.x.g, _normal_entries_WIRE_2.g connect normal_entries_barrier_1.io.x.u, _normal_entries_WIRE_2.u connect normal_entries_barrier_1.io.x.ppn, _normal_entries_WIRE_2.ppn node _normal_entries_T_32 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_5 : UInt<34> connect _normal_entries_WIRE_5, sectored_entries[2].data[_normal_entries_T_32] node _normal_entries_T_33 = bits(_normal_entries_WIRE_5, 0, 0) connect _normal_entries_WIRE_4.fragmented_superpage, _normal_entries_T_33 node _normal_entries_T_34 = bits(_normal_entries_WIRE_5, 1, 1) connect _normal_entries_WIRE_4.c, _normal_entries_T_34 node _normal_entries_T_35 = bits(_normal_entries_WIRE_5, 2, 2) connect _normal_entries_WIRE_4.eff, _normal_entries_T_35 node _normal_entries_T_36 = bits(_normal_entries_WIRE_5, 3, 3) connect _normal_entries_WIRE_4.paa, _normal_entries_T_36 node _normal_entries_T_37 = bits(_normal_entries_WIRE_5, 4, 4) connect _normal_entries_WIRE_4.pal, _normal_entries_T_37 node _normal_entries_T_38 = bits(_normal_entries_WIRE_5, 5, 5) connect _normal_entries_WIRE_4.pr, _normal_entries_T_38 node _normal_entries_T_39 = bits(_normal_entries_WIRE_5, 6, 6) connect _normal_entries_WIRE_4.px, _normal_entries_T_39 node _normal_entries_T_40 = bits(_normal_entries_WIRE_5, 7, 7) connect _normal_entries_WIRE_4.pw, _normal_entries_T_40 node _normal_entries_T_41 = bits(_normal_entries_WIRE_5, 8, 8) connect _normal_entries_WIRE_4.sr, _normal_entries_T_41 node _normal_entries_T_42 = bits(_normal_entries_WIRE_5, 9, 9) connect _normal_entries_WIRE_4.sx, _normal_entries_T_42 node _normal_entries_T_43 = bits(_normal_entries_WIRE_5, 10, 10) connect _normal_entries_WIRE_4.sw, _normal_entries_T_43 node _normal_entries_T_44 = bits(_normal_entries_WIRE_5, 11, 11) connect _normal_entries_WIRE_4.ae, _normal_entries_T_44 node _normal_entries_T_45 = bits(_normal_entries_WIRE_5, 12, 12) connect _normal_entries_WIRE_4.g, _normal_entries_T_45 node _normal_entries_T_46 = bits(_normal_entries_WIRE_5, 13, 13) connect _normal_entries_WIRE_4.u, _normal_entries_T_46 node _normal_entries_T_47 = bits(_normal_entries_WIRE_5, 33, 14) connect _normal_entries_WIRE_4.ppn, _normal_entries_T_47 inst normal_entries_barrier_2 of OptimizationBarrier_EntryData_29 connect normal_entries_barrier_2.clock, clock connect normal_entries_barrier_2.reset, reset connect normal_entries_barrier_2.io.x.fragmented_superpage, _normal_entries_WIRE_4.fragmented_superpage connect normal_entries_barrier_2.io.x.c, _normal_entries_WIRE_4.c connect normal_entries_barrier_2.io.x.eff, _normal_entries_WIRE_4.eff connect normal_entries_barrier_2.io.x.paa, _normal_entries_WIRE_4.paa connect normal_entries_barrier_2.io.x.pal, _normal_entries_WIRE_4.pal connect normal_entries_barrier_2.io.x.pr, _normal_entries_WIRE_4.pr connect normal_entries_barrier_2.io.x.px, _normal_entries_WIRE_4.px connect normal_entries_barrier_2.io.x.pw, _normal_entries_WIRE_4.pw connect normal_entries_barrier_2.io.x.sr, _normal_entries_WIRE_4.sr connect normal_entries_barrier_2.io.x.sx, _normal_entries_WIRE_4.sx connect normal_entries_barrier_2.io.x.sw, _normal_entries_WIRE_4.sw connect normal_entries_barrier_2.io.x.ae, _normal_entries_WIRE_4.ae connect normal_entries_barrier_2.io.x.g, _normal_entries_WIRE_4.g connect normal_entries_barrier_2.io.x.u, _normal_entries_WIRE_4.u connect normal_entries_barrier_2.io.x.ppn, _normal_entries_WIRE_4.ppn node _normal_entries_T_48 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_7 : UInt<34> connect _normal_entries_WIRE_7, sectored_entries[3].data[_normal_entries_T_48] node _normal_entries_T_49 = bits(_normal_entries_WIRE_7, 0, 0) connect _normal_entries_WIRE_6.fragmented_superpage, _normal_entries_T_49 node _normal_entries_T_50 = bits(_normal_entries_WIRE_7, 1, 1) connect _normal_entries_WIRE_6.c, _normal_entries_T_50 node _normal_entries_T_51 = bits(_normal_entries_WIRE_7, 2, 2) connect _normal_entries_WIRE_6.eff, _normal_entries_T_51 node _normal_entries_T_52 = bits(_normal_entries_WIRE_7, 3, 3) connect _normal_entries_WIRE_6.paa, _normal_entries_T_52 node _normal_entries_T_53 = bits(_normal_entries_WIRE_7, 4, 4) connect _normal_entries_WIRE_6.pal, _normal_entries_T_53 node _normal_entries_T_54 = bits(_normal_entries_WIRE_7, 5, 5) connect _normal_entries_WIRE_6.pr, _normal_entries_T_54 node _normal_entries_T_55 = bits(_normal_entries_WIRE_7, 6, 6) connect _normal_entries_WIRE_6.px, _normal_entries_T_55 node _normal_entries_T_56 = bits(_normal_entries_WIRE_7, 7, 7) connect _normal_entries_WIRE_6.pw, _normal_entries_T_56 node _normal_entries_T_57 = bits(_normal_entries_WIRE_7, 8, 8) connect _normal_entries_WIRE_6.sr, _normal_entries_T_57 node _normal_entries_T_58 = bits(_normal_entries_WIRE_7, 9, 9) connect _normal_entries_WIRE_6.sx, _normal_entries_T_58 node _normal_entries_T_59 = bits(_normal_entries_WIRE_7, 10, 10) connect _normal_entries_WIRE_6.sw, _normal_entries_T_59 node _normal_entries_T_60 = bits(_normal_entries_WIRE_7, 11, 11) connect _normal_entries_WIRE_6.ae, _normal_entries_T_60 node _normal_entries_T_61 = bits(_normal_entries_WIRE_7, 12, 12) connect _normal_entries_WIRE_6.g, _normal_entries_T_61 node _normal_entries_T_62 = bits(_normal_entries_WIRE_7, 13, 13) connect _normal_entries_WIRE_6.u, _normal_entries_T_62 node _normal_entries_T_63 = bits(_normal_entries_WIRE_7, 33, 14) connect _normal_entries_WIRE_6.ppn, _normal_entries_T_63 inst normal_entries_barrier_3 of OptimizationBarrier_EntryData_30 connect normal_entries_barrier_3.clock, clock connect normal_entries_barrier_3.reset, reset connect normal_entries_barrier_3.io.x.fragmented_superpage, _normal_entries_WIRE_6.fragmented_superpage connect normal_entries_barrier_3.io.x.c, _normal_entries_WIRE_6.c connect normal_entries_barrier_3.io.x.eff, _normal_entries_WIRE_6.eff connect normal_entries_barrier_3.io.x.paa, _normal_entries_WIRE_6.paa connect normal_entries_barrier_3.io.x.pal, _normal_entries_WIRE_6.pal connect normal_entries_barrier_3.io.x.pr, _normal_entries_WIRE_6.pr connect normal_entries_barrier_3.io.x.px, _normal_entries_WIRE_6.px connect normal_entries_barrier_3.io.x.pw, _normal_entries_WIRE_6.pw connect normal_entries_barrier_3.io.x.sr, _normal_entries_WIRE_6.sr connect normal_entries_barrier_3.io.x.sx, _normal_entries_WIRE_6.sx connect normal_entries_barrier_3.io.x.sw, _normal_entries_WIRE_6.sw connect normal_entries_barrier_3.io.x.ae, _normal_entries_WIRE_6.ae connect normal_entries_barrier_3.io.x.g, _normal_entries_WIRE_6.g connect normal_entries_barrier_3.io.x.u, _normal_entries_WIRE_6.u connect normal_entries_barrier_3.io.x.ppn, _normal_entries_WIRE_6.ppn node _normal_entries_T_64 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_9 : UInt<34> connect _normal_entries_WIRE_9, sectored_entries[4].data[_normal_entries_T_64] node _normal_entries_T_65 = bits(_normal_entries_WIRE_9, 0, 0) connect _normal_entries_WIRE_8.fragmented_superpage, _normal_entries_T_65 node _normal_entries_T_66 = bits(_normal_entries_WIRE_9, 1, 1) connect _normal_entries_WIRE_8.c, _normal_entries_T_66 node _normal_entries_T_67 = bits(_normal_entries_WIRE_9, 2, 2) connect _normal_entries_WIRE_8.eff, _normal_entries_T_67 node _normal_entries_T_68 = bits(_normal_entries_WIRE_9, 3, 3) connect _normal_entries_WIRE_8.paa, _normal_entries_T_68 node _normal_entries_T_69 = bits(_normal_entries_WIRE_9, 4, 4) connect _normal_entries_WIRE_8.pal, _normal_entries_T_69 node _normal_entries_T_70 = bits(_normal_entries_WIRE_9, 5, 5) connect _normal_entries_WIRE_8.pr, _normal_entries_T_70 node _normal_entries_T_71 = bits(_normal_entries_WIRE_9, 6, 6) connect _normal_entries_WIRE_8.px, _normal_entries_T_71 node _normal_entries_T_72 = bits(_normal_entries_WIRE_9, 7, 7) connect _normal_entries_WIRE_8.pw, _normal_entries_T_72 node _normal_entries_T_73 = bits(_normal_entries_WIRE_9, 8, 8) connect _normal_entries_WIRE_8.sr, _normal_entries_T_73 node _normal_entries_T_74 = bits(_normal_entries_WIRE_9, 9, 9) connect _normal_entries_WIRE_8.sx, _normal_entries_T_74 node _normal_entries_T_75 = bits(_normal_entries_WIRE_9, 10, 10) connect _normal_entries_WIRE_8.sw, _normal_entries_T_75 node _normal_entries_T_76 = bits(_normal_entries_WIRE_9, 11, 11) connect _normal_entries_WIRE_8.ae, _normal_entries_T_76 node _normal_entries_T_77 = bits(_normal_entries_WIRE_9, 12, 12) connect _normal_entries_WIRE_8.g, _normal_entries_T_77 node _normal_entries_T_78 = bits(_normal_entries_WIRE_9, 13, 13) connect _normal_entries_WIRE_8.u, _normal_entries_T_78 node _normal_entries_T_79 = bits(_normal_entries_WIRE_9, 33, 14) connect _normal_entries_WIRE_8.ppn, _normal_entries_T_79 inst normal_entries_barrier_4 of OptimizationBarrier_EntryData_31 connect normal_entries_barrier_4.clock, clock connect normal_entries_barrier_4.reset, reset connect normal_entries_barrier_4.io.x.fragmented_superpage, _normal_entries_WIRE_8.fragmented_superpage connect normal_entries_barrier_4.io.x.c, _normal_entries_WIRE_8.c connect normal_entries_barrier_4.io.x.eff, _normal_entries_WIRE_8.eff connect normal_entries_barrier_4.io.x.paa, _normal_entries_WIRE_8.paa connect normal_entries_barrier_4.io.x.pal, _normal_entries_WIRE_8.pal connect normal_entries_barrier_4.io.x.pr, _normal_entries_WIRE_8.pr connect normal_entries_barrier_4.io.x.px, _normal_entries_WIRE_8.px connect normal_entries_barrier_4.io.x.pw, _normal_entries_WIRE_8.pw connect normal_entries_barrier_4.io.x.sr, _normal_entries_WIRE_8.sr connect normal_entries_barrier_4.io.x.sx, _normal_entries_WIRE_8.sx connect normal_entries_barrier_4.io.x.sw, _normal_entries_WIRE_8.sw connect normal_entries_barrier_4.io.x.ae, _normal_entries_WIRE_8.ae connect normal_entries_barrier_4.io.x.g, _normal_entries_WIRE_8.g connect normal_entries_barrier_4.io.x.u, _normal_entries_WIRE_8.u connect normal_entries_barrier_4.io.x.ppn, _normal_entries_WIRE_8.ppn node _normal_entries_T_80 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_11 : UInt<34> connect _normal_entries_WIRE_11, sectored_entries[5].data[_normal_entries_T_80] node _normal_entries_T_81 = bits(_normal_entries_WIRE_11, 0, 0) connect _normal_entries_WIRE_10.fragmented_superpage, _normal_entries_T_81 node _normal_entries_T_82 = bits(_normal_entries_WIRE_11, 1, 1) connect _normal_entries_WIRE_10.c, _normal_entries_T_82 node _normal_entries_T_83 = bits(_normal_entries_WIRE_11, 2, 2) connect _normal_entries_WIRE_10.eff, _normal_entries_T_83 node _normal_entries_T_84 = bits(_normal_entries_WIRE_11, 3, 3) connect _normal_entries_WIRE_10.paa, _normal_entries_T_84 node _normal_entries_T_85 = bits(_normal_entries_WIRE_11, 4, 4) connect _normal_entries_WIRE_10.pal, _normal_entries_T_85 node _normal_entries_T_86 = bits(_normal_entries_WIRE_11, 5, 5) connect _normal_entries_WIRE_10.pr, _normal_entries_T_86 node _normal_entries_T_87 = bits(_normal_entries_WIRE_11, 6, 6) connect _normal_entries_WIRE_10.px, _normal_entries_T_87 node _normal_entries_T_88 = bits(_normal_entries_WIRE_11, 7, 7) connect _normal_entries_WIRE_10.pw, _normal_entries_T_88 node _normal_entries_T_89 = bits(_normal_entries_WIRE_11, 8, 8) connect _normal_entries_WIRE_10.sr, _normal_entries_T_89 node _normal_entries_T_90 = bits(_normal_entries_WIRE_11, 9, 9) connect _normal_entries_WIRE_10.sx, _normal_entries_T_90 node _normal_entries_T_91 = bits(_normal_entries_WIRE_11, 10, 10) connect _normal_entries_WIRE_10.sw, _normal_entries_T_91 node _normal_entries_T_92 = bits(_normal_entries_WIRE_11, 11, 11) connect _normal_entries_WIRE_10.ae, _normal_entries_T_92 node _normal_entries_T_93 = bits(_normal_entries_WIRE_11, 12, 12) connect _normal_entries_WIRE_10.g, _normal_entries_T_93 node _normal_entries_T_94 = bits(_normal_entries_WIRE_11, 13, 13) connect _normal_entries_WIRE_10.u, _normal_entries_T_94 node _normal_entries_T_95 = bits(_normal_entries_WIRE_11, 33, 14) connect _normal_entries_WIRE_10.ppn, _normal_entries_T_95 inst normal_entries_barrier_5 of OptimizationBarrier_EntryData_32 connect normal_entries_barrier_5.clock, clock connect normal_entries_barrier_5.reset, reset connect normal_entries_barrier_5.io.x.fragmented_superpage, _normal_entries_WIRE_10.fragmented_superpage connect normal_entries_barrier_5.io.x.c, _normal_entries_WIRE_10.c connect normal_entries_barrier_5.io.x.eff, _normal_entries_WIRE_10.eff connect normal_entries_barrier_5.io.x.paa, _normal_entries_WIRE_10.paa connect normal_entries_barrier_5.io.x.pal, _normal_entries_WIRE_10.pal connect normal_entries_barrier_5.io.x.pr, _normal_entries_WIRE_10.pr connect normal_entries_barrier_5.io.x.px, _normal_entries_WIRE_10.px connect normal_entries_barrier_5.io.x.pw, _normal_entries_WIRE_10.pw connect normal_entries_barrier_5.io.x.sr, _normal_entries_WIRE_10.sr connect normal_entries_barrier_5.io.x.sx, _normal_entries_WIRE_10.sx connect normal_entries_barrier_5.io.x.sw, _normal_entries_WIRE_10.sw connect normal_entries_barrier_5.io.x.ae, _normal_entries_WIRE_10.ae connect normal_entries_barrier_5.io.x.g, _normal_entries_WIRE_10.g connect normal_entries_barrier_5.io.x.u, _normal_entries_WIRE_10.u connect normal_entries_barrier_5.io.x.ppn, _normal_entries_WIRE_10.ppn node _normal_entries_T_96 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_13 : UInt<34> connect _normal_entries_WIRE_13, sectored_entries[6].data[_normal_entries_T_96] node _normal_entries_T_97 = bits(_normal_entries_WIRE_13, 0, 0) connect _normal_entries_WIRE_12.fragmented_superpage, _normal_entries_T_97 node _normal_entries_T_98 = bits(_normal_entries_WIRE_13, 1, 1) connect _normal_entries_WIRE_12.c, _normal_entries_T_98 node _normal_entries_T_99 = bits(_normal_entries_WIRE_13, 2, 2) connect _normal_entries_WIRE_12.eff, _normal_entries_T_99 node _normal_entries_T_100 = bits(_normal_entries_WIRE_13, 3, 3) connect _normal_entries_WIRE_12.paa, _normal_entries_T_100 node _normal_entries_T_101 = bits(_normal_entries_WIRE_13, 4, 4) connect _normal_entries_WIRE_12.pal, _normal_entries_T_101 node _normal_entries_T_102 = bits(_normal_entries_WIRE_13, 5, 5) connect _normal_entries_WIRE_12.pr, _normal_entries_T_102 node _normal_entries_T_103 = bits(_normal_entries_WIRE_13, 6, 6) connect _normal_entries_WIRE_12.px, _normal_entries_T_103 node _normal_entries_T_104 = bits(_normal_entries_WIRE_13, 7, 7) connect _normal_entries_WIRE_12.pw, _normal_entries_T_104 node _normal_entries_T_105 = bits(_normal_entries_WIRE_13, 8, 8) connect _normal_entries_WIRE_12.sr, _normal_entries_T_105 node _normal_entries_T_106 = bits(_normal_entries_WIRE_13, 9, 9) connect _normal_entries_WIRE_12.sx, _normal_entries_T_106 node _normal_entries_T_107 = bits(_normal_entries_WIRE_13, 10, 10) connect _normal_entries_WIRE_12.sw, _normal_entries_T_107 node _normal_entries_T_108 = bits(_normal_entries_WIRE_13, 11, 11) connect _normal_entries_WIRE_12.ae, _normal_entries_T_108 node _normal_entries_T_109 = bits(_normal_entries_WIRE_13, 12, 12) connect _normal_entries_WIRE_12.g, _normal_entries_T_109 node _normal_entries_T_110 = bits(_normal_entries_WIRE_13, 13, 13) connect _normal_entries_WIRE_12.u, _normal_entries_T_110 node _normal_entries_T_111 = bits(_normal_entries_WIRE_13, 33, 14) connect _normal_entries_WIRE_12.ppn, _normal_entries_T_111 inst normal_entries_barrier_6 of OptimizationBarrier_EntryData_33 connect normal_entries_barrier_6.clock, clock connect normal_entries_barrier_6.reset, reset connect normal_entries_barrier_6.io.x.fragmented_superpage, _normal_entries_WIRE_12.fragmented_superpage connect normal_entries_barrier_6.io.x.c, _normal_entries_WIRE_12.c connect normal_entries_barrier_6.io.x.eff, _normal_entries_WIRE_12.eff connect normal_entries_barrier_6.io.x.paa, _normal_entries_WIRE_12.paa connect normal_entries_barrier_6.io.x.pal, _normal_entries_WIRE_12.pal connect normal_entries_barrier_6.io.x.pr, _normal_entries_WIRE_12.pr connect normal_entries_barrier_6.io.x.px, _normal_entries_WIRE_12.px connect normal_entries_barrier_6.io.x.pw, _normal_entries_WIRE_12.pw connect normal_entries_barrier_6.io.x.sr, _normal_entries_WIRE_12.sr connect normal_entries_barrier_6.io.x.sx, _normal_entries_WIRE_12.sx connect normal_entries_barrier_6.io.x.sw, _normal_entries_WIRE_12.sw connect normal_entries_barrier_6.io.x.ae, _normal_entries_WIRE_12.ae connect normal_entries_barrier_6.io.x.g, _normal_entries_WIRE_12.g connect normal_entries_barrier_6.io.x.u, _normal_entries_WIRE_12.u connect normal_entries_barrier_6.io.x.ppn, _normal_entries_WIRE_12.ppn node _normal_entries_T_112 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_15 : UInt<34> connect _normal_entries_WIRE_15, sectored_entries[7].data[_normal_entries_T_112] node _normal_entries_T_113 = bits(_normal_entries_WIRE_15, 0, 0) connect _normal_entries_WIRE_14.fragmented_superpage, _normal_entries_T_113 node _normal_entries_T_114 = bits(_normal_entries_WIRE_15, 1, 1) connect _normal_entries_WIRE_14.c, _normal_entries_T_114 node _normal_entries_T_115 = bits(_normal_entries_WIRE_15, 2, 2) connect _normal_entries_WIRE_14.eff, _normal_entries_T_115 node _normal_entries_T_116 = bits(_normal_entries_WIRE_15, 3, 3) connect _normal_entries_WIRE_14.paa, _normal_entries_T_116 node _normal_entries_T_117 = bits(_normal_entries_WIRE_15, 4, 4) connect _normal_entries_WIRE_14.pal, _normal_entries_T_117 node _normal_entries_T_118 = bits(_normal_entries_WIRE_15, 5, 5) connect _normal_entries_WIRE_14.pr, _normal_entries_T_118 node _normal_entries_T_119 = bits(_normal_entries_WIRE_15, 6, 6) connect _normal_entries_WIRE_14.px, _normal_entries_T_119 node _normal_entries_T_120 = bits(_normal_entries_WIRE_15, 7, 7) connect _normal_entries_WIRE_14.pw, _normal_entries_T_120 node _normal_entries_T_121 = bits(_normal_entries_WIRE_15, 8, 8) connect _normal_entries_WIRE_14.sr, _normal_entries_T_121 node _normal_entries_T_122 = bits(_normal_entries_WIRE_15, 9, 9) connect _normal_entries_WIRE_14.sx, _normal_entries_T_122 node _normal_entries_T_123 = bits(_normal_entries_WIRE_15, 10, 10) connect _normal_entries_WIRE_14.sw, _normal_entries_T_123 node _normal_entries_T_124 = bits(_normal_entries_WIRE_15, 11, 11) connect _normal_entries_WIRE_14.ae, _normal_entries_T_124 node _normal_entries_T_125 = bits(_normal_entries_WIRE_15, 12, 12) connect _normal_entries_WIRE_14.g, _normal_entries_T_125 node _normal_entries_T_126 = bits(_normal_entries_WIRE_15, 13, 13) connect _normal_entries_WIRE_14.u, _normal_entries_T_126 node _normal_entries_T_127 = bits(_normal_entries_WIRE_15, 33, 14) connect _normal_entries_WIRE_14.ppn, _normal_entries_T_127 inst normal_entries_barrier_7 of OptimizationBarrier_EntryData_34 connect normal_entries_barrier_7.clock, clock connect normal_entries_barrier_7.reset, reset connect normal_entries_barrier_7.io.x.fragmented_superpage, _normal_entries_WIRE_14.fragmented_superpage connect normal_entries_barrier_7.io.x.c, _normal_entries_WIRE_14.c connect normal_entries_barrier_7.io.x.eff, _normal_entries_WIRE_14.eff connect normal_entries_barrier_7.io.x.paa, _normal_entries_WIRE_14.paa connect normal_entries_barrier_7.io.x.pal, _normal_entries_WIRE_14.pal connect normal_entries_barrier_7.io.x.pr, _normal_entries_WIRE_14.pr connect normal_entries_barrier_7.io.x.px, _normal_entries_WIRE_14.px connect normal_entries_barrier_7.io.x.pw, _normal_entries_WIRE_14.pw connect normal_entries_barrier_7.io.x.sr, _normal_entries_WIRE_14.sr connect normal_entries_barrier_7.io.x.sx, _normal_entries_WIRE_14.sx connect normal_entries_barrier_7.io.x.sw, _normal_entries_WIRE_14.sw connect normal_entries_barrier_7.io.x.ae, _normal_entries_WIRE_14.ae connect normal_entries_barrier_7.io.x.g, _normal_entries_WIRE_14.g connect normal_entries_barrier_7.io.x.u, _normal_entries_WIRE_14.u connect normal_entries_barrier_7.io.x.ppn, _normal_entries_WIRE_14.ppn wire _normal_entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_17 : UInt<34> connect _normal_entries_WIRE_17, superpage_entries[0].data[0] node _normal_entries_T_128 = bits(_normal_entries_WIRE_17, 0, 0) connect _normal_entries_WIRE_16.fragmented_superpage, _normal_entries_T_128 node _normal_entries_T_129 = bits(_normal_entries_WIRE_17, 1, 1) connect _normal_entries_WIRE_16.c, _normal_entries_T_129 node _normal_entries_T_130 = bits(_normal_entries_WIRE_17, 2, 2) connect _normal_entries_WIRE_16.eff, _normal_entries_T_130 node _normal_entries_T_131 = bits(_normal_entries_WIRE_17, 3, 3) connect _normal_entries_WIRE_16.paa, _normal_entries_T_131 node _normal_entries_T_132 = bits(_normal_entries_WIRE_17, 4, 4) connect _normal_entries_WIRE_16.pal, _normal_entries_T_132 node _normal_entries_T_133 = bits(_normal_entries_WIRE_17, 5, 5) connect _normal_entries_WIRE_16.pr, _normal_entries_T_133 node _normal_entries_T_134 = bits(_normal_entries_WIRE_17, 6, 6) connect _normal_entries_WIRE_16.px, _normal_entries_T_134 node _normal_entries_T_135 = bits(_normal_entries_WIRE_17, 7, 7) connect _normal_entries_WIRE_16.pw, _normal_entries_T_135 node _normal_entries_T_136 = bits(_normal_entries_WIRE_17, 8, 8) connect _normal_entries_WIRE_16.sr, _normal_entries_T_136 node _normal_entries_T_137 = bits(_normal_entries_WIRE_17, 9, 9) connect _normal_entries_WIRE_16.sx, _normal_entries_T_137 node _normal_entries_T_138 = bits(_normal_entries_WIRE_17, 10, 10) connect _normal_entries_WIRE_16.sw, _normal_entries_T_138 node _normal_entries_T_139 = bits(_normal_entries_WIRE_17, 11, 11) connect _normal_entries_WIRE_16.ae, _normal_entries_T_139 node _normal_entries_T_140 = bits(_normal_entries_WIRE_17, 12, 12) connect _normal_entries_WIRE_16.g, _normal_entries_T_140 node _normal_entries_T_141 = bits(_normal_entries_WIRE_17, 13, 13) connect _normal_entries_WIRE_16.u, _normal_entries_T_141 node _normal_entries_T_142 = bits(_normal_entries_WIRE_17, 33, 14) connect _normal_entries_WIRE_16.ppn, _normal_entries_T_142 inst normal_entries_barrier_8 of OptimizationBarrier_EntryData_35 connect normal_entries_barrier_8.clock, clock connect normal_entries_barrier_8.reset, reset connect normal_entries_barrier_8.io.x.fragmented_superpage, _normal_entries_WIRE_16.fragmented_superpage connect normal_entries_barrier_8.io.x.c, _normal_entries_WIRE_16.c connect normal_entries_barrier_8.io.x.eff, _normal_entries_WIRE_16.eff connect normal_entries_barrier_8.io.x.paa, _normal_entries_WIRE_16.paa connect normal_entries_barrier_8.io.x.pal, _normal_entries_WIRE_16.pal connect normal_entries_barrier_8.io.x.pr, _normal_entries_WIRE_16.pr connect normal_entries_barrier_8.io.x.px, _normal_entries_WIRE_16.px connect normal_entries_barrier_8.io.x.pw, _normal_entries_WIRE_16.pw connect normal_entries_barrier_8.io.x.sr, _normal_entries_WIRE_16.sr connect normal_entries_barrier_8.io.x.sx, _normal_entries_WIRE_16.sx connect normal_entries_barrier_8.io.x.sw, _normal_entries_WIRE_16.sw connect normal_entries_barrier_8.io.x.ae, _normal_entries_WIRE_16.ae connect normal_entries_barrier_8.io.x.g, _normal_entries_WIRE_16.g connect normal_entries_barrier_8.io.x.u, _normal_entries_WIRE_16.u connect normal_entries_barrier_8.io.x.ppn, _normal_entries_WIRE_16.ppn wire _normal_entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_19 : UInt<34> connect _normal_entries_WIRE_19, superpage_entries[1].data[0] node _normal_entries_T_143 = bits(_normal_entries_WIRE_19, 0, 0) connect _normal_entries_WIRE_18.fragmented_superpage, _normal_entries_T_143 node _normal_entries_T_144 = bits(_normal_entries_WIRE_19, 1, 1) connect _normal_entries_WIRE_18.c, _normal_entries_T_144 node _normal_entries_T_145 = bits(_normal_entries_WIRE_19, 2, 2) connect _normal_entries_WIRE_18.eff, _normal_entries_T_145 node _normal_entries_T_146 = bits(_normal_entries_WIRE_19, 3, 3) connect _normal_entries_WIRE_18.paa, _normal_entries_T_146 node _normal_entries_T_147 = bits(_normal_entries_WIRE_19, 4, 4) connect _normal_entries_WIRE_18.pal, _normal_entries_T_147 node _normal_entries_T_148 = bits(_normal_entries_WIRE_19, 5, 5) connect _normal_entries_WIRE_18.pr, _normal_entries_T_148 node _normal_entries_T_149 = bits(_normal_entries_WIRE_19, 6, 6) connect _normal_entries_WIRE_18.px, _normal_entries_T_149 node _normal_entries_T_150 = bits(_normal_entries_WIRE_19, 7, 7) connect _normal_entries_WIRE_18.pw, _normal_entries_T_150 node _normal_entries_T_151 = bits(_normal_entries_WIRE_19, 8, 8) connect _normal_entries_WIRE_18.sr, _normal_entries_T_151 node _normal_entries_T_152 = bits(_normal_entries_WIRE_19, 9, 9) connect _normal_entries_WIRE_18.sx, _normal_entries_T_152 node _normal_entries_T_153 = bits(_normal_entries_WIRE_19, 10, 10) connect _normal_entries_WIRE_18.sw, _normal_entries_T_153 node _normal_entries_T_154 = bits(_normal_entries_WIRE_19, 11, 11) connect _normal_entries_WIRE_18.ae, _normal_entries_T_154 node _normal_entries_T_155 = bits(_normal_entries_WIRE_19, 12, 12) connect _normal_entries_WIRE_18.g, _normal_entries_T_155 node _normal_entries_T_156 = bits(_normal_entries_WIRE_19, 13, 13) connect _normal_entries_WIRE_18.u, _normal_entries_T_156 node _normal_entries_T_157 = bits(_normal_entries_WIRE_19, 33, 14) connect _normal_entries_WIRE_18.ppn, _normal_entries_T_157 inst normal_entries_barrier_9 of OptimizationBarrier_EntryData_36 connect normal_entries_barrier_9.clock, clock connect normal_entries_barrier_9.reset, reset connect normal_entries_barrier_9.io.x.fragmented_superpage, _normal_entries_WIRE_18.fragmented_superpage connect normal_entries_barrier_9.io.x.c, _normal_entries_WIRE_18.c connect normal_entries_barrier_9.io.x.eff, _normal_entries_WIRE_18.eff connect normal_entries_barrier_9.io.x.paa, _normal_entries_WIRE_18.paa connect normal_entries_barrier_9.io.x.pal, _normal_entries_WIRE_18.pal connect normal_entries_barrier_9.io.x.pr, _normal_entries_WIRE_18.pr connect normal_entries_barrier_9.io.x.px, _normal_entries_WIRE_18.px connect normal_entries_barrier_9.io.x.pw, _normal_entries_WIRE_18.pw connect normal_entries_barrier_9.io.x.sr, _normal_entries_WIRE_18.sr connect normal_entries_barrier_9.io.x.sx, _normal_entries_WIRE_18.sx connect normal_entries_barrier_9.io.x.sw, _normal_entries_WIRE_18.sw connect normal_entries_barrier_9.io.x.ae, _normal_entries_WIRE_18.ae connect normal_entries_barrier_9.io.x.g, _normal_entries_WIRE_18.g connect normal_entries_barrier_9.io.x.u, _normal_entries_WIRE_18.u connect normal_entries_barrier_9.io.x.ppn, _normal_entries_WIRE_18.ppn wire _normal_entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_21 : UInt<34> connect _normal_entries_WIRE_21, superpage_entries[2].data[0] node _normal_entries_T_158 = bits(_normal_entries_WIRE_21, 0, 0) connect _normal_entries_WIRE_20.fragmented_superpage, _normal_entries_T_158 node _normal_entries_T_159 = bits(_normal_entries_WIRE_21, 1, 1) connect _normal_entries_WIRE_20.c, _normal_entries_T_159 node _normal_entries_T_160 = bits(_normal_entries_WIRE_21, 2, 2) connect _normal_entries_WIRE_20.eff, _normal_entries_T_160 node _normal_entries_T_161 = bits(_normal_entries_WIRE_21, 3, 3) connect _normal_entries_WIRE_20.paa, _normal_entries_T_161 node _normal_entries_T_162 = bits(_normal_entries_WIRE_21, 4, 4) connect _normal_entries_WIRE_20.pal, _normal_entries_T_162 node _normal_entries_T_163 = bits(_normal_entries_WIRE_21, 5, 5) connect _normal_entries_WIRE_20.pr, _normal_entries_T_163 node _normal_entries_T_164 = bits(_normal_entries_WIRE_21, 6, 6) connect _normal_entries_WIRE_20.px, _normal_entries_T_164 node _normal_entries_T_165 = bits(_normal_entries_WIRE_21, 7, 7) connect _normal_entries_WIRE_20.pw, _normal_entries_T_165 node _normal_entries_T_166 = bits(_normal_entries_WIRE_21, 8, 8) connect _normal_entries_WIRE_20.sr, _normal_entries_T_166 node _normal_entries_T_167 = bits(_normal_entries_WIRE_21, 9, 9) connect _normal_entries_WIRE_20.sx, _normal_entries_T_167 node _normal_entries_T_168 = bits(_normal_entries_WIRE_21, 10, 10) connect _normal_entries_WIRE_20.sw, _normal_entries_T_168 node _normal_entries_T_169 = bits(_normal_entries_WIRE_21, 11, 11) connect _normal_entries_WIRE_20.ae, _normal_entries_T_169 node _normal_entries_T_170 = bits(_normal_entries_WIRE_21, 12, 12) connect _normal_entries_WIRE_20.g, _normal_entries_T_170 node _normal_entries_T_171 = bits(_normal_entries_WIRE_21, 13, 13) connect _normal_entries_WIRE_20.u, _normal_entries_T_171 node _normal_entries_T_172 = bits(_normal_entries_WIRE_21, 33, 14) connect _normal_entries_WIRE_20.ppn, _normal_entries_T_172 inst normal_entries_barrier_10 of OptimizationBarrier_EntryData_37 connect normal_entries_barrier_10.clock, clock connect normal_entries_barrier_10.reset, reset connect normal_entries_barrier_10.io.x.fragmented_superpage, _normal_entries_WIRE_20.fragmented_superpage connect normal_entries_barrier_10.io.x.c, _normal_entries_WIRE_20.c connect normal_entries_barrier_10.io.x.eff, _normal_entries_WIRE_20.eff connect normal_entries_barrier_10.io.x.paa, _normal_entries_WIRE_20.paa connect normal_entries_barrier_10.io.x.pal, _normal_entries_WIRE_20.pal connect normal_entries_barrier_10.io.x.pr, _normal_entries_WIRE_20.pr connect normal_entries_barrier_10.io.x.px, _normal_entries_WIRE_20.px connect normal_entries_barrier_10.io.x.pw, _normal_entries_WIRE_20.pw connect normal_entries_barrier_10.io.x.sr, _normal_entries_WIRE_20.sr connect normal_entries_barrier_10.io.x.sx, _normal_entries_WIRE_20.sx connect normal_entries_barrier_10.io.x.sw, _normal_entries_WIRE_20.sw connect normal_entries_barrier_10.io.x.ae, _normal_entries_WIRE_20.ae connect normal_entries_barrier_10.io.x.g, _normal_entries_WIRE_20.g connect normal_entries_barrier_10.io.x.u, _normal_entries_WIRE_20.u connect normal_entries_barrier_10.io.x.ppn, _normal_entries_WIRE_20.ppn wire _normal_entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_23 : UInt<34> connect _normal_entries_WIRE_23, superpage_entries[3].data[0] node _normal_entries_T_173 = bits(_normal_entries_WIRE_23, 0, 0) connect _normal_entries_WIRE_22.fragmented_superpage, _normal_entries_T_173 node _normal_entries_T_174 = bits(_normal_entries_WIRE_23, 1, 1) connect _normal_entries_WIRE_22.c, _normal_entries_T_174 node _normal_entries_T_175 = bits(_normal_entries_WIRE_23, 2, 2) connect _normal_entries_WIRE_22.eff, _normal_entries_T_175 node _normal_entries_T_176 = bits(_normal_entries_WIRE_23, 3, 3) connect _normal_entries_WIRE_22.paa, _normal_entries_T_176 node _normal_entries_T_177 = bits(_normal_entries_WIRE_23, 4, 4) connect _normal_entries_WIRE_22.pal, _normal_entries_T_177 node _normal_entries_T_178 = bits(_normal_entries_WIRE_23, 5, 5) connect _normal_entries_WIRE_22.pr, _normal_entries_T_178 node _normal_entries_T_179 = bits(_normal_entries_WIRE_23, 6, 6) connect _normal_entries_WIRE_22.px, _normal_entries_T_179 node _normal_entries_T_180 = bits(_normal_entries_WIRE_23, 7, 7) connect _normal_entries_WIRE_22.pw, _normal_entries_T_180 node _normal_entries_T_181 = bits(_normal_entries_WIRE_23, 8, 8) connect _normal_entries_WIRE_22.sr, _normal_entries_T_181 node _normal_entries_T_182 = bits(_normal_entries_WIRE_23, 9, 9) connect _normal_entries_WIRE_22.sx, _normal_entries_T_182 node _normal_entries_T_183 = bits(_normal_entries_WIRE_23, 10, 10) connect _normal_entries_WIRE_22.sw, _normal_entries_T_183 node _normal_entries_T_184 = bits(_normal_entries_WIRE_23, 11, 11) connect _normal_entries_WIRE_22.ae, _normal_entries_T_184 node _normal_entries_T_185 = bits(_normal_entries_WIRE_23, 12, 12) connect _normal_entries_WIRE_22.g, _normal_entries_T_185 node _normal_entries_T_186 = bits(_normal_entries_WIRE_23, 13, 13) connect _normal_entries_WIRE_22.u, _normal_entries_T_186 node _normal_entries_T_187 = bits(_normal_entries_WIRE_23, 33, 14) connect _normal_entries_WIRE_22.ppn, _normal_entries_T_187 inst normal_entries_barrier_11 of OptimizationBarrier_EntryData_38 connect normal_entries_barrier_11.clock, clock connect normal_entries_barrier_11.reset, reset connect normal_entries_barrier_11.io.x.fragmented_superpage, _normal_entries_WIRE_22.fragmented_superpage connect normal_entries_barrier_11.io.x.c, _normal_entries_WIRE_22.c connect normal_entries_barrier_11.io.x.eff, _normal_entries_WIRE_22.eff connect normal_entries_barrier_11.io.x.paa, _normal_entries_WIRE_22.paa connect normal_entries_barrier_11.io.x.pal, _normal_entries_WIRE_22.pal connect normal_entries_barrier_11.io.x.pr, _normal_entries_WIRE_22.pr connect normal_entries_barrier_11.io.x.px, _normal_entries_WIRE_22.px connect normal_entries_barrier_11.io.x.pw, _normal_entries_WIRE_22.pw connect normal_entries_barrier_11.io.x.sr, _normal_entries_WIRE_22.sr connect normal_entries_barrier_11.io.x.sx, _normal_entries_WIRE_22.sx connect normal_entries_barrier_11.io.x.sw, _normal_entries_WIRE_22.sw connect normal_entries_barrier_11.io.x.ae, _normal_entries_WIRE_22.ae connect normal_entries_barrier_11.io.x.g, _normal_entries_WIRE_22.g connect normal_entries_barrier_11.io.x.u, _normal_entries_WIRE_22.u connect normal_entries_barrier_11.io.x.ppn, _normal_entries_WIRE_22.ppn wire _normal_entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[12] connect _normal_entries_WIRE_24[0], normal_entries_barrier.io.y connect _normal_entries_WIRE_24[1], normal_entries_barrier_1.io.y connect _normal_entries_WIRE_24[2], normal_entries_barrier_2.io.y connect _normal_entries_WIRE_24[3], normal_entries_barrier_3.io.y connect _normal_entries_WIRE_24[4], normal_entries_barrier_4.io.y connect _normal_entries_WIRE_24[5], normal_entries_barrier_5.io.y connect _normal_entries_WIRE_24[6], normal_entries_barrier_6.io.y connect _normal_entries_WIRE_24[7], normal_entries_barrier_7.io.y connect _normal_entries_WIRE_24[8], normal_entries_barrier_8.io.y connect _normal_entries_WIRE_24[9], normal_entries_barrier_9.io.y connect _normal_entries_WIRE_24[10], normal_entries_barrier_10.io.y connect _normal_entries_WIRE_24[11], normal_entries_barrier_11.io.y wire normal_entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[12][1] connect normal_entries[0], _normal_entries_WIRE_24 node ptw_ae_array_lo_lo_hi = cat(entries[0][2].ae, entries[0][1].ae) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries[0][0].ae) node ptw_ae_array_lo_hi_hi = cat(entries[0][5].ae, entries[0][4].ae) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries[0][3].ae) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries[0][8].ae, entries[0][7].ae) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries[0][6].ae) node ptw_ae_array_hi_hi_lo = cat(entries[0][10].ae, entries[0][9].ae) node ptw_ae_array_hi_hi_hi = cat(entries[0][12].ae, entries[0][11].ae) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node _ptw_ae_array_T_1 = cat(UInt<1>(0h0), _ptw_ae_array_T) wire ptw_ae_array : UInt<14>[1] connect ptw_ae_array[0], _ptw_ae_array_T_1 node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, io.ptw.status.sum) node priv_rw_ok_lo_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries[0][0].u) node priv_rw_ok_lo_hi_hi = cat(entries[0][5].u, entries[0][4].u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries[0][3].u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries[0][8].u, entries[0][7].u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries[0][6].u) node priv_rw_ok_hi_hi_lo = cat(entries[0][10].u, entries[0][9].u) node priv_rw_ok_hi_hi_hi = cat(entries[0][12].u, entries[0][11].u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries[0][0].u) node priv_rw_ok_lo_hi_hi_1 = cat(entries[0][5].u, entries[0][4].u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries[0][3].u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries[0][8].u, entries[0][7].u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries[0][6].u) node priv_rw_ok_hi_hi_lo_1 = cat(entries[0][10].u, entries[0][9].u) node priv_rw_ok_hi_hi_hi_1 = cat(entries[0][12].u, entries[0][11].u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node _priv_rw_ok_T_7 = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) wire priv_rw_ok : UInt<13>[1] connect priv_rw_ok[0], _priv_rw_ok_T_7 node priv_x_ok_lo_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries[0][0].u) node priv_x_ok_lo_hi_hi = cat(entries[0][5].u, entries[0][4].u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries[0][3].u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries[0][8].u, entries[0][7].u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries[0][6].u) node priv_x_ok_hi_hi_lo = cat(entries[0][10].u, entries[0][9].u) node priv_x_ok_hi_hi_hi = cat(entries[0][12].u, entries[0][11].u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries[0][0].u) node priv_x_ok_lo_hi_hi_1 = cat(entries[0][5].u, entries[0][4].u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries[0][3].u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries[0][8].u, entries[0][7].u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries[0][6].u) node priv_x_ok_hi_hi_lo_1 = cat(entries[0][10].u, entries[0][9].u) node priv_x_ok_hi_hi_hi_1 = cat(entries[0][12].u, entries[0][11].u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node _priv_x_ok_T_3 = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) wire priv_x_ok : UInt<13>[1] connect priv_x_ok[0], _priv_x_ok_T_3 node r_array_lo_lo_hi = cat(entries[0][2].sr, entries[0][1].sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries[0][0].sr) node r_array_lo_hi_hi = cat(entries[0][5].sr, entries[0][4].sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries[0][3].sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries[0][8].sr, entries[0][7].sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries[0][6].sr) node r_array_hi_hi_lo = cat(entries[0][10].sr, entries[0][9].sr) node r_array_hi_hi_hi = cat(entries[0][12].sr, entries[0][11].sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries[0][2].sx, entries[0][1].sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries[0][0].sx) node r_array_lo_hi_hi_1 = cat(entries[0][5].sx, entries[0][4].sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries[0][3].sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries[0][8].sx, entries[0][7].sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries[0][6].sx) node r_array_hi_hi_lo_1 = cat(entries[0][10].sx, entries[0][9].sx) node r_array_hi_hi_hi_1 = cat(entries[0][12].sx, entries[0][11].sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(io.ptw.status.mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok[0], _r_array_T_3) node _r_array_T_5 = cat(UInt<1>(0h1), _r_array_T_4) wire r_array : UInt<14>[1] connect r_array[0], _r_array_T_5 node w_array_lo_lo_hi = cat(entries[0][2].sw, entries[0][1].sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries[0][0].sw) node w_array_lo_hi_hi = cat(entries[0][5].sw, entries[0][4].sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries[0][3].sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries[0][8].sw, entries[0][7].sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries[0][6].sw) node w_array_hi_hi_lo = cat(entries[0][10].sw, entries[0][9].sw) node w_array_hi_hi_hi = cat(entries[0][12].sw, entries[0][11].sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok[0], _w_array_T) node _w_array_T_2 = cat(UInt<1>(0h1), _w_array_T_1) wire w_array : UInt<14>[1] connect w_array[0], _w_array_T_2 node x_array_lo_lo_hi = cat(entries[0][2].sx, entries[0][1].sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries[0][0].sx) node x_array_lo_hi_hi = cat(entries[0][5].sx, entries[0][4].sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries[0][3].sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries[0][8].sx, entries[0][7].sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries[0][6].sx) node x_array_hi_hi_lo = cat(entries[0][10].sx, entries[0][9].sx) node x_array_hi_hi_hi = cat(entries[0][12].sx, entries[0][11].sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok[0], _x_array_T) node _x_array_T_2 = cat(UInt<1>(0h1), _x_array_T_1) wire x_array : UInt<14>[1] connect x_array[0], _x_array_T_2 node _pr_array_T = mux(prot_r[0], UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(normal_entries[0][2].pr, normal_entries[0][1].pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, normal_entries[0][0].pr) node pr_array_lo_hi_hi = cat(normal_entries[0][5].pr, normal_entries[0][4].pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, normal_entries[0][3].pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(normal_entries[0][8].pr, normal_entries[0][7].pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, normal_entries[0][6].pr) node pr_array_hi_hi_hi = cat(normal_entries[0][11].pr, normal_entries[0][10].pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, normal_entries[0][9].pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = not(ptw_ae_array[0]) node _pr_array_T_4 = and(_pr_array_T_2, _pr_array_T_3) wire pr_array : UInt<14>[1] connect pr_array[0], _pr_array_T_4 node _pw_array_T = mux(prot_w[0], UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(normal_entries[0][2].pw, normal_entries[0][1].pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, normal_entries[0][0].pw) node pw_array_lo_hi_hi = cat(normal_entries[0][5].pw, normal_entries[0][4].pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, normal_entries[0][3].pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(normal_entries[0][8].pw, normal_entries[0][7].pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, normal_entries[0][6].pw) node pw_array_hi_hi_hi = cat(normal_entries[0][11].pw, normal_entries[0][10].pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, normal_entries[0][9].pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = not(ptw_ae_array[0]) node _pw_array_T_4 = and(_pw_array_T_2, _pw_array_T_3) wire pw_array : UInt<14>[1] connect pw_array[0], _pw_array_T_4 node _px_array_T = mux(prot_x[0], UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(normal_entries[0][2].px, normal_entries[0][1].px) node px_array_lo_lo = cat(px_array_lo_lo_hi, normal_entries[0][0].px) node px_array_lo_hi_hi = cat(normal_entries[0][5].px, normal_entries[0][4].px) node px_array_lo_hi = cat(px_array_lo_hi_hi, normal_entries[0][3].px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(normal_entries[0][8].px, normal_entries[0][7].px) node px_array_hi_lo = cat(px_array_hi_lo_hi, normal_entries[0][6].px) node px_array_hi_hi_hi = cat(normal_entries[0][11].px, normal_entries[0][10].px) node px_array_hi_hi = cat(px_array_hi_hi_hi, normal_entries[0][9].px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = not(ptw_ae_array[0]) node _px_array_T_4 = and(_px_array_T_2, _px_array_T_3) wire px_array : UInt<14>[1] connect px_array[0], _px_array_T_4 node _eff_array_T = mux(prot_eff[0], UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(normal_entries[0][2].eff, normal_entries[0][1].eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, normal_entries[0][0].eff) node eff_array_lo_hi_hi = cat(normal_entries[0][5].eff, normal_entries[0][4].eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, normal_entries[0][3].eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(normal_entries[0][8].eff, normal_entries[0][7].eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, normal_entries[0][6].eff) node eff_array_hi_hi_hi = cat(normal_entries[0][11].eff, normal_entries[0][10].eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, normal_entries[0][9].eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node _eff_array_T_2 = cat(_eff_array_T, _eff_array_T_1) wire eff_array : UInt<14>[1] connect eff_array[0], _eff_array_T_2 node _c_array_T = mux(cacheable[0], UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node c_array_lo_lo = cat(c_array_lo_lo_hi, normal_entries[0][0].c) node c_array_lo_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node c_array_lo_hi = cat(c_array_lo_hi_hi, normal_entries[0][3].c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(normal_entries[0][8].c, normal_entries[0][7].c) node c_array_hi_lo = cat(c_array_hi_lo_hi, normal_entries[0][6].c) node c_array_hi_hi_hi = cat(normal_entries[0][11].c, normal_entries[0][10].c) node c_array_hi_hi = cat(c_array_hi_hi_hi, normal_entries[0][9].c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node _c_array_T_2 = cat(_c_array_T, _c_array_T_1) wire c_array : UInt<14>[1] connect c_array[0], _c_array_T_2 node _paa_array_T = mux(prot_aa[0], UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(normal_entries[0][2].paa, normal_entries[0][1].paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, normal_entries[0][0].paa) node paa_array_lo_hi_hi = cat(normal_entries[0][5].paa, normal_entries[0][4].paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, normal_entries[0][3].paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(normal_entries[0][8].paa, normal_entries[0][7].paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, normal_entries[0][6].paa) node paa_array_hi_hi_hi = cat(normal_entries[0][11].paa, normal_entries[0][10].paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, normal_entries[0][9].paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node _paa_array_T_2 = cat(_paa_array_T, _paa_array_T_1) wire paa_array : UInt<14>[1] connect paa_array[0], _paa_array_T_2 node _pal_array_T = mux(prot_al[0], UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(normal_entries[0][2].pal, normal_entries[0][1].pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, normal_entries[0][0].pal) node pal_array_lo_hi_hi = cat(normal_entries[0][5].pal, normal_entries[0][4].pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, normal_entries[0][3].pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(normal_entries[0][8].pal, normal_entries[0][7].pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, normal_entries[0][6].pal) node pal_array_hi_hi_hi = cat(normal_entries[0][11].pal, normal_entries[0][10].pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, normal_entries[0][9].pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node _pal_array_T_2 = cat(_pal_array_T, _pal_array_T_1) wire pal_array : UInt<14>[1] connect pal_array[0], _pal_array_T_2 node _paa_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _paa_array_if_cached_T_1 = or(paa_array[0], _paa_array_if_cached_T) wire paa_array_if_cached : UInt<14>[1] connect paa_array_if_cached[0], _paa_array_if_cached_T_1 node _pal_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _pal_array_if_cached_T_1 = or(pal_array[0], _pal_array_if_cached_T) wire pal_array_if_cached : UInt<14>[1] connect pal_array_if_cached[0], _pal_array_if_cached_T_1 node _prefetchable_array_T = and(cacheable[0], homogeneous[0]) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, normal_entries[0][0].c) node prefetchable_array_lo_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, normal_entries[0][3].c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(normal_entries[0][8].c, normal_entries[0][7].c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, normal_entries[0][6].c) node prefetchable_array_hi_hi_hi = cat(normal_entries[0][11].c, normal_entries[0][10].c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, normal_entries[0][9].c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node _prefetchable_array_T_3 = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) wire prefetchable_array : UInt<14>[1] connect prefetchable_array[0], _prefetchable_array_T_3 node _misaligned_T = dshl(UInt<1>(0h1), io.req[0].bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req[0].bits.vaddr, _misaligned_T_2) node _misaligned_T_4 = orr(_misaligned_T_3) wire misaligned : UInt<1>[1] connect misaligned[0], _misaligned_T_4 wire bad_va : UInt<1>[1] connect bad_va[0], UInt<1>(0h0) node _cmd_lrsc_T = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node _cmd_lrsc_T_3 = and(UInt<1>(0h1), _cmd_lrsc_T_2) wire cmd_lrsc : UInt<1>[1] connect cmd_lrsc[0], _cmd_lrsc_T_3 node _cmd_amo_logical_T = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node _cmd_amo_logical_T_7 = and(UInt<1>(0h1), _cmd_amo_logical_T_6) wire cmd_amo_logical : UInt<1>[1] connect cmd_amo_logical[0], _cmd_amo_logical_T_7 node _cmd_amo_arithmetic_T = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node _cmd_amo_arithmetic_T_9 = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) wire cmd_amo_arithmetic : UInt<1>[1] connect cmd_amo_arithmetic[0], _cmd_amo_arithmetic_T_9 node _cmd_read_T = eq(io.req[0].bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node _cmd_read_T_24 = or(_cmd_read_T_6, _cmd_read_T_23) wire cmd_read : UInt<1>[1] connect cmd_read[0], _cmd_read_T_24 node _cmd_write_T = eq(io.req[0].bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node _cmd_write_T_22 = or(_cmd_write_T_4, _cmd_write_T_21) wire cmd_write : UInt<1>[1] connect cmd_write[0], _cmd_write_T_22 node _cmd_write_perms_T = eq(io.req[0].bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = and(UInt<1>(0h0), _cmd_write_perms_T) node _cmd_write_perms_T_2 = or(cmd_write[0], _cmd_write_perms_T_1) wire cmd_write_perms : UInt<1>[1] connect cmd_write_perms[0], _cmd_write_perms_T_2 node _lrscAllowed_T = mux(UInt<1>(0h0), UInt<1>(0h0), c_array[0]) wire lrscAllowed : UInt<14>[1] connect lrscAllowed[0], _lrscAllowed_T node _ae_array_T = mux(misaligned[0], eff_array[0], UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed[0]) node _ae_array_T_2 = mux(cmd_lrsc[0], _ae_array_T_1, UInt<1>(0h0)) node _ae_array_T_3 = or(_ae_array_T, _ae_array_T_2) wire ae_array : UInt<14>[1] connect ae_array[0], _ae_array_T_3 node _ae_valid_array_T = eq(do_refill, UInt<1>(0h0)) node _ae_valid_array_T_1 = cat(UInt<1>(0h1), _ae_valid_array_T) node _ae_valid_array_T_2 = mux(UInt<1>(0h1), UInt<12>(0hfff), UInt<12>(0h0)) node _ae_valid_array_T_3 = cat(_ae_valid_array_T_1, _ae_valid_array_T_2) wire ae_valid_array : UInt<14>[1] connect ae_valid_array[0], _ae_valid_array_T_3 node _ae_ld_array_T = not(pr_array[0]) node _ae_ld_array_T_1 = or(ae_array[0], _ae_ld_array_T) node _ae_ld_array_T_2 = mux(cmd_read[0], _ae_ld_array_T_1, UInt<1>(0h0)) wire ae_ld_array : UInt<14>[1] connect ae_ld_array[0], _ae_ld_array_T_2 node _ae_st_array_T = not(pw_array[0]) node _ae_st_array_T_1 = or(ae_array[0], _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms[0], _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(pal_array_if_cached[0]) node _ae_st_array_T_4 = mux(cmd_amo_logical[0], _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(paa_array_if_cached[0]) node _ae_st_array_T_7 = mux(cmd_amo_arithmetic[0], _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) wire ae_st_array : UInt<14>[1] connect ae_st_array[0], _ae_st_array_T_8 node _must_alloc_array_T = not(paa_array[0]) node _must_alloc_array_T_1 = mux(cmd_amo_logical[0], _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array[0]) node _must_alloc_array_T_3 = mux(cmd_amo_arithmetic[0], _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(UInt<14>(0h0)) node _must_alloc_array_T_6 = mux(cmd_lrsc[0], _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) wire must_alloc_array : UInt<14>[1] connect must_alloc_array[0], _must_alloc_array_T_7 node _ma_ld_array_T = and(misaligned[0], cmd_read[0]) node _ma_ld_array_T_1 = not(eff_array[0]) node _ma_ld_array_T_2 = mux(_ma_ld_array_T, _ma_ld_array_T_1, UInt<1>(0h0)) wire ma_ld_array : UInt<14>[1] connect ma_ld_array[0], _ma_ld_array_T_2 node _ma_st_array_T = and(misaligned[0], cmd_write[0]) node _ma_st_array_T_1 = not(eff_array[0]) node _ma_st_array_T_2 = mux(_ma_st_array_T, _ma_st_array_T_1, UInt<1>(0h0)) wire ma_st_array : UInt<14>[1] connect ma_st_array[0], _ma_st_array_T_2 node _pf_ld_array_T = or(r_array[0], ptw_ae_array[0]) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = mux(cmd_read[0], _pf_ld_array_T_1, UInt<1>(0h0)) wire pf_ld_array : UInt<14>[1] connect pf_ld_array[0], _pf_ld_array_T_2 node _pf_st_array_T = or(w_array[0], ptw_ae_array[0]) node _pf_st_array_T_1 = not(_pf_st_array_T) node _pf_st_array_T_2 = mux(cmd_write_perms[0], _pf_st_array_T_1, UInt<1>(0h0)) wire pf_st_array : UInt<14>[1] connect pf_st_array[0], _pf_st_array_T_2 node _pf_inst_array_T = or(x_array[0], ptw_ae_array[0]) node _pf_inst_array_T_1 = not(_pf_inst_array_T) wire pf_inst_array : UInt<14>[1] connect pf_inst_array[0], _pf_inst_array_T_1 node _tlb_hit_T = orr(real_hits[0]) wire tlb_hit : UInt<1>[1] connect tlb_hit[0], _tlb_hit_T node _tlb_miss_T = eq(bad_va[0], UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled[0], _tlb_miss_T) node _tlb_miss_T_2 = eq(tlb_hit[0], UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) wire tlb_miss : UInt<1>[1] connect tlb_miss[0], _tlb_miss_T_3 regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req[0].valid, vm_enabled[0]) when _T_23 : node _T_24 = or(sector_hits[0][0], sector_hits[0][1]) node _T_25 = or(_T_24, sector_hits[0][2]) node _T_26 = or(_T_25, sector_hits[0][3]) node _T_27 = or(_T_26, sector_hits[0][4]) node _T_28 = or(_T_27, sector_hits[0][5]) node _T_29 = or(_T_28, sector_hits[0][6]) node _T_30 = or(_T_29, sector_hits[0][7]) when _T_30 : node lo_lo = cat(sector_hits[0][1], sector_hits[0][0]) node lo_hi = cat(sector_hits[0][3], sector_hits[0][2]) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits[0][5], sector_hits[0][4]) node hi_hi = cat(sector_hits[0][7], sector_hits[0][6]) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_reg_touch_way_sized = bits(_T_38, 2, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 5, 3) node state_reg_right_subtree_state = bits(state_reg, 2, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0)) node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3) node _state_reg_T_5 = bits(_state_reg_T, 0, 0) node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0) node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0)) node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1) node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4) node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8) node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9) node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0) node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0) node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0)) node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14) node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0) node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0)) node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2) node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15) node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19) node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state) node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10) node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21) connect state_reg, _state_reg_T_22 node _T_39 = or(superpage_hits[0][0], superpage_hits[0][1]) node _T_40 = or(_T_39, superpage_hits[0][2]) node _T_41 = or(_T_40, superpage_hits[0][3]) when _T_41 : node lo_3 = cat(superpage_hits[0][1], superpage_hits[0][0]) node hi_3 = cat(superpage_hits[0][3], superpage_hits[0][2]) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized_1 = bits(_T_46, 1, 0) node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 1, 1) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state_3 = bits(state_reg_1, 0, 0) node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_25 = eq(_state_reg_T_24, UInt<1>(0h0)) node _state_reg_T_26 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_25) node _state_reg_T_27 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_28 = bits(_state_reg_T_27, 0, 0) node _state_reg_T_29 = eq(_state_reg_T_28, UInt<1>(0h0)) node _state_reg_T_30 = mux(state_reg_set_left_older_3, _state_reg_T_29, state_reg_right_subtree_state_3) node state_reg_hi_3 = cat(state_reg_set_left_older_3, _state_reg_T_26) node _state_reg_T_31 = cat(state_reg_hi_3, _state_reg_T_30) connect state_reg_1, _state_reg_T_31 node _multipleHits_T = bits(real_hits[0], 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits[0], 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_49 = or(_multipleHits_T_47, _multipleHits_T_48) wire multipleHits : UInt<1>[1] connect multipleHits[0], _multipleHits_T_49 node _io_miss_rdy_T = eq(state, UInt<2>(0h0)) connect io.miss_rdy, _io_miss_rdy_T connect io.req[0].ready, UInt<1>(0h1) node _io_resp_0_pf_ld_T = and(bad_va[0], cmd_read[0]) node _io_resp_0_pf_ld_T_1 = and(pf_ld_array[0], hits[0]) node _io_resp_0_pf_ld_T_2 = orr(_io_resp_0_pf_ld_T_1) node _io_resp_0_pf_ld_T_3 = or(_io_resp_0_pf_ld_T, _io_resp_0_pf_ld_T_2) connect io.resp[0].pf.ld, _io_resp_0_pf_ld_T_3 node _io_resp_0_pf_st_T = and(bad_va[0], cmd_write_perms[0]) node _io_resp_0_pf_st_T_1 = and(pf_st_array[0], hits[0]) node _io_resp_0_pf_st_T_2 = orr(_io_resp_0_pf_st_T_1) node _io_resp_0_pf_st_T_3 = or(_io_resp_0_pf_st_T, _io_resp_0_pf_st_T_2) connect io.resp[0].pf.st, _io_resp_0_pf_st_T_3 node _io_resp_0_pf_inst_T = and(pf_inst_array[0], hits[0]) node _io_resp_0_pf_inst_T_1 = orr(_io_resp_0_pf_inst_T) node _io_resp_0_pf_inst_T_2 = or(bad_va[0], _io_resp_0_pf_inst_T_1) connect io.resp[0].pf.inst, _io_resp_0_pf_inst_T_2 node _io_resp_0_ae_ld_T = and(ae_valid_array[0], ae_ld_array[0]) node _io_resp_0_ae_ld_T_1 = and(_io_resp_0_ae_ld_T, hits[0]) node _io_resp_0_ae_ld_T_2 = orr(_io_resp_0_ae_ld_T_1) connect io.resp[0].ae.ld, _io_resp_0_ae_ld_T_2 node _io_resp_0_ae_st_T = and(ae_valid_array[0], ae_st_array[0]) node _io_resp_0_ae_st_T_1 = and(_io_resp_0_ae_st_T, hits[0]) node _io_resp_0_ae_st_T_2 = orr(_io_resp_0_ae_st_T_1) connect io.resp[0].ae.st, _io_resp_0_ae_st_T_2 node _io_resp_0_ae_inst_T = not(px_array[0]) node _io_resp_0_ae_inst_T_1 = and(ae_valid_array[0], _io_resp_0_ae_inst_T) node _io_resp_0_ae_inst_T_2 = and(_io_resp_0_ae_inst_T_1, hits[0]) node _io_resp_0_ae_inst_T_3 = orr(_io_resp_0_ae_inst_T_2) connect io.resp[0].ae.inst, _io_resp_0_ae_inst_T_3 node _io_resp_0_ma_ld_T = and(ma_ld_array[0], hits[0]) node _io_resp_0_ma_ld_T_1 = orr(_io_resp_0_ma_ld_T) connect io.resp[0].ma.ld, _io_resp_0_ma_ld_T_1 node _io_resp_0_ma_st_T = and(ma_st_array[0], hits[0]) node _io_resp_0_ma_st_T_1 = orr(_io_resp_0_ma_st_T) connect io.resp[0].ma.st, _io_resp_0_ma_st_T_1 connect io.resp[0].ma.inst, UInt<1>(0h0) node _io_resp_0_cacheable_T = and(c_array[0], hits[0]) node _io_resp_0_cacheable_T_1 = orr(_io_resp_0_cacheable_T) connect io.resp[0].cacheable, _io_resp_0_cacheable_T_1 node _io_resp_0_must_alloc_T = and(must_alloc_array[0], hits[0]) node _io_resp_0_must_alloc_T_1 = orr(_io_resp_0_must_alloc_T) connect io.resp[0].must_alloc, _io_resp_0_must_alloc_T_1 node _io_resp_0_prefetchable_T = and(prefetchable_array[0], hits[0]) node _io_resp_0_prefetchable_T_1 = orr(_io_resp_0_prefetchable_T) node _io_resp_0_prefetchable_T_2 = and(_io_resp_0_prefetchable_T_1, UInt<1>(0h1)) connect io.resp[0].prefetchable, _io_resp_0_prefetchable_T_2 node _io_resp_0_miss_T = or(do_refill, tlb_miss[0]) node _io_resp_0_miss_T_1 = or(_io_resp_0_miss_T, multipleHits[0]) connect io.resp[0].miss, _io_resp_0_miss_T_1 node _io_resp_0_paddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _io_resp_0_paddr_T_1 = cat(ppn[0], _io_resp_0_paddr_T) connect io.resp[0].paddr, _io_resp_0_paddr_T_1 connect io.resp[0].size, io.req[0].bits.size connect io.resp[0].cmd, io.req[0].bits.cmd node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag
module NBDTLB( // @[tlb.scala:17:7] input clock, // @[tlb.scala:17:7] input reset, // @[tlb.scala:17:7] input io_req_0_valid, // @[tlb.scala:19:14] input [33:0] io_req_0_bits_vaddr, // @[tlb.scala:19:14] input [1:0] io_req_0_bits_size, // @[tlb.scala:19:14] input [4:0] io_req_0_bits_cmd, // @[tlb.scala:19:14] output [31:0] io_resp_0_paddr, // @[tlb.scala:19:14] output io_resp_0_pf_ld, // @[tlb.scala:19:14] output io_resp_0_pf_st, // @[tlb.scala:19:14] output io_resp_0_ae_ld, // @[tlb.scala:19:14] output io_resp_0_ae_st, // @[tlb.scala:19:14] output io_resp_0_ma_ld, // @[tlb.scala:19:14] output io_resp_0_ma_st, // @[tlb.scala:19:14] output io_resp_0_cacheable, // @[tlb.scala:19:14] output [20:0] io_ptw_req_bits_bits_addr, // @[tlb.scala:19:14] input io_ptw_resp_valid, // @[tlb.scala:19:14] input [43:0] io_ptw_resp_bits_pte_ppn // @[tlb.scala:19:14] ); wire _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_11_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_10_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_9_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_8_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_7_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_6_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_5_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_4_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_3_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_2_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_1_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_c; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_eff; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_paa; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_pal; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_pr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_px; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_pw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_sr; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_sx; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_sw; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_ae; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_g; // @[tlb.scala:214:45] wire _normal_entries_WIRE_24_0_u; // @[tlb.scala:214:45] wire [19:0] _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:214:45] wire _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_12_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_12_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_11_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_11_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_10_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_10_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_9_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_9_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_8_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_8_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_7_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_7_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_6_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_6_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_5_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_5_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_4_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_4_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_3_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_3_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_2_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_2_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_1_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_1_ppn; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_c; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_eff; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_paa; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_pal; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_pr; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_px; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_pw; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_sr; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_sx; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_sw; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_ae; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_g; // @[tlb.scala:213:38] wire _entries_WIRE_26_0_u; // @[tlb.scala:213:38] wire [19:0] _entries_WIRE_26_0_ppn; // @[tlb.scala:213:38] wire io_req_0_valid_0 = io_req_0_valid; // @[tlb.scala:17:7] wire [33:0] io_req_0_bits_vaddr_0 = io_req_0_bits_vaddr; // @[tlb.scala:17:7] wire [1:0] io_req_0_bits_size_0 = io_req_0_bits_size; // @[tlb.scala:17:7] wire [4:0] io_req_0_bits_cmd_0 = io_req_0_bits_cmd; // @[tlb.scala:17:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[tlb.scala:17:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[tlb.scala:17:7] wire [20:0] io_ptw_req_bits_bits_addr_0 = 21'h0; // @[tlb.scala:17:7, :124:29] wire [11:0] _ae_valid_array_T_2 = 12'hFFF; // @[tlb.scala:257:46] wire [34:0] _prot_r_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_r_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_w_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_w_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_al_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_al_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_aa_T_2 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _prot_aa_T_3 = 35'h0; // @[Parameters.scala:137:46] wire [13:0] _hits_T_1 = 14'h2000; // @[tlb.scala:121:49, :175:31] wire [13:0] hits_0 = 14'h2000; // @[tlb.scala:121:49, :175:31] wire [19:0] _ppn_T_2 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_3 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_4 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_5 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_6 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_7 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_8 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_9 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_10 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_11 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_12 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_13 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_14 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_16 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_17 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_18 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = 20'h0; // @[Mux.scala:30:73] wire [12:0] _real_hits_T = 13'h0; // @[tlb.scala:174:44] wire [12:0] real_hits_0 = 13'h0; // @[tlb.scala:121:49] wire [12:0] _priv_rw_ok_T_6 = 13'h0; // @[tlb.scala:217:108] wire [12:0] _r_array_T_2 = 13'h0; // @[tlb.scala:219:98] wire [1:0] _ae_valid_array_T_1 = 2'h3; // @[tlb.scala:256:84] wire [13:0] _ae_valid_array_T_3 = 14'h3FFF; // @[tlb.scala:256:41] wire [13:0] ae_valid_array_0 = 14'h3FFF; // @[tlb.scala:121:49] wire [13:0] _must_alloc_array_T_5 = 14'h3FFF; // @[tlb.scala:266:32] wire [6:0] real_hits_hi = 7'h0; // @[tlb.scala:174:44] wire [6:0] _multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[tlb.scala:17:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[tlb.scala:17:7, :19:14] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Misc.scala:181:37] wire [5:0] real_hits_lo = 6'h0; // @[Misc.scala:181:37] wire [5:0] _multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[tlb.scala:17:7, :19:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[tlb.scala:17:7, :19:14] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14] wire [31:0] io_ptw_status_isa = 32'h0; // @[tlb.scala:17:7, :19:14] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[tlb.scala:17:7, :19:14] wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[tlb.scala:17:7, :19:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[tlb.scala:17:7, :19:14] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14] wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[Misc.scala:182:39] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Misc.scala:182:39] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Misc.scala:182:39] wire [3:0] real_hits_hi_hi = 4'h0; // @[Misc.scala:182:39] wire [3:0] _multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[tlb.scala:17:7, :19:14] wire [32:0] io_sfence_bits_addr = 33'h0; // @[tlb.scala:17:7, :19:14] wire [32:0] io_ptw_resp_bits_gpa_bits = 33'h0; // @[tlb.scala:17:7, :19:14] wire [33:0] io_resp_0_gpa = 34'h0; // @[tlb.scala:17:7] wire [33:0] _mpu_ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_3 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_5 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_7 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_9 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_11 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_13 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_15 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_17 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_19 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_21 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_23 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _ppn_data_WIRE_25 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_1 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_3 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_5 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_7 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_9 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_11 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_13 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_15 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_17 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_19 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_21 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_23 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _entries_WIRE_25 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_1 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_3 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_5 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_7 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_9 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_11 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_13 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_15 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_17 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_19 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_21 = 34'h0; // @[tlb.scala:60:79] wire [33:0] _normal_entries_WIRE_23 = 34'h0; // @[tlb.scala:60:79] wire [1:0] io_req_0_bits_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_dprv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_sxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_uxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_fs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_mpp = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] _pmp_0_io_prv_T_2 = 2'h0; // @[tlb.scala:157:25] wire [1:0] real_hits_lo_lo_hi = 2'h0; // @[tlb.scala:174:44] wire [1:0] real_hits_lo_hi_hi = 2'h0; // @[tlb.scala:174:44] wire [1:0] real_hits_hi_lo_hi = 2'h0; // @[tlb.scala:174:44] wire [1:0] real_hits_hi_hi_lo = 2'h0; // @[tlb.scala:174:44] wire [1:0] real_hits_hi_hi_hi = 2'h0; // @[tlb.scala:174:44] wire [1:0] special_entry_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] superpage_entries_0_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] superpage_entries_1_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] superpage_entries_2_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] superpage_entries_3_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_0_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_1_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_2_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_3_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_4_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_5_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_6_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] sectored_entries_7_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26] wire [1:0] _multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] _multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] io_ptw_resp_bits_level = 2'h2; // @[tlb.scala:17:7] wire [1:0] _special_entry_level_T = 2'h2; // @[package.scala:163:13] wire [1:0] special_entry_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] superpage_entries_0_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] superpage_entries_1_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] superpage_entries_2_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] superpage_entries_3_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_0_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_1_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_2_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_3_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_4_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_5_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_6_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [1:0] sectored_entries_7_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26] wire [2:0] real_hits_lo_lo = 3'h0; // @[tlb.scala:174:44] wire [2:0] real_hits_lo_hi = 3'h0; // @[tlb.scala:174:44] wire [2:0] real_hits_hi_lo = 3'h0; // @[tlb.scala:174:44] wire [2:0] waddr = 3'h0; // @[tlb.scala:205:22] wire [2:0] state_reg_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] _multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] _multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] _multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire io_req_0_ready = 1'h1; // @[tlb.scala:17:7] wire io_miss_rdy = 1'h1; // @[tlb.scala:17:7] wire io_ptw_req_ready = 1'h1; // @[tlb.scala:17:7] wire io_ptw_req_bits_valid = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_d = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_a = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_u = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_w = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_r = 1'h1; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_v = 1'h1; // @[tlb.scala:17:7] wire priv_uses_vm = 1'h1; // @[tlb.scala:140:27] wire _vm_enabled_T_3 = 1'h1; // @[tlb.scala:141:112] wire _homogeneous_T_24 = 1'h1; // @[TLBPermissions.scala:87:22] wire _homogeneous_T_25 = 1'h1; // @[TLBPermissions.scala:87:22] wire _homogeneous_T_39 = 1'h1; // @[TLBPermissions.scala:87:22] wire _homogeneous_T_40 = 1'h1; // @[TLBPermissions.scala:87:22] wire _prot_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _prot_w_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _prot_al_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _prot_aa_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _hits_T = 1'h1; // @[tlb.scala:175:32] wire _ppn_T = 1'h1; // @[tlb.scala:176:47] wire newEntry_u = 1'h1; // @[tlb.scala:181:24] wire newEntry_sw = 1'h1; // @[tlb.scala:181:24] wire newEntry_sr = 1'h1; // @[tlb.scala:181:24] wire _newEntry_sr_T_2 = 1'h1; // @[PTW.scala:141:38] wire _newEntry_sr_T_3 = 1'h1; // @[PTW.scala:141:32] wire _newEntry_sr_T_4 = 1'h1; // @[PTW.scala:141:52] wire _newEntry_sr_T_5 = 1'h1; // @[PTW.scala:149:35] wire _newEntry_sw_T_2 = 1'h1; // @[PTW.scala:141:38] wire _newEntry_sw_T_3 = 1'h1; // @[PTW.scala:141:32] wire _newEntry_sw_T_4 = 1'h1; // @[PTW.scala:141:52] wire _newEntry_sw_T_5 = 1'h1; // @[PTW.scala:151:35] wire _newEntry_sw_T_6 = 1'h1; // @[PTW.scala:151:40] wire _newEntry_sx_T_2 = 1'h1; // @[PTW.scala:141:38] wire _newEntry_sx_T_3 = 1'h1; // @[PTW.scala:141:32] wire _newEntry_sx_T_4 = 1'h1; // @[PTW.scala:141:52] wire _priv_rw_ok_T = 1'h1; // @[tlb.scala:217:40] wire _priv_rw_ok_T_1 = 1'h1; // @[tlb.scala:217:48] wire _ae_valid_array_T = 1'h1; // @[tlb.scala:256:118] wire _tlb_miss_T = 1'h1; // @[tlb.scala:274:49] wire _tlb_miss_T_2 = 1'h1; // @[tlb.scala:274:63] wire _io_miss_rdy_T = 1'h1; // @[tlb.scala:292:24] wire _io_ptw_req_bits_valid_T = 1'h1; // @[tlb.scala:314:28] wire io_req_0_bits_passthrough = 1'h0; // @[tlb.scala:17:7] wire io_req_0_bits_v = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_miss = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gpa_is_pte = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_ld = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_st = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_inst = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_ma_inst = 1'h0; // @[tlb.scala:17:7] wire io_sfence_valid = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_rs1 = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_rs2 = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_asid = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_hv = 1'h0; // @[tlb.scala:17:7] wire io_sfence_bits_hg = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_valid = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_ptw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_final = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pf = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gf = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hx = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_g = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_x = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_homogeneous = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_valid = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_debug = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_cease = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_wfi = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_dv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_v = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sd = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mpv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_tsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_tw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_tvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mxr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sum = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mprv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_spp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mpie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_spie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_hu = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spvp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_debug = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_cease = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_wfi = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_dv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_v = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mxr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sum = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mprv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[tlb.scala:17:7] wire io_kill = 1'h0; // @[tlb.scala:17:7] wire priv_s = 1'h0; // @[tlb.scala:139:20] wire _vm_enabled_T = 1'h0; // @[tlb.scala:141:63] wire _vm_enabled_T_1 = 1'h0; // @[tlb.scala:141:44] wire _vm_enabled_T_2 = 1'h0; // @[tlb.scala:141:93] wire _vm_enabled_T_4 = 1'h0; // @[tlb.scala:141:109] wire vm_enabled_0 = 1'h0; // @[tlb.scala:121:49] wire do_refill = 1'h0; // @[tlb.scala:146:29] wire _invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire _invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire _invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire invalidate_refill = 1'h0; // @[tlb.scala:147:88] wire _mpu_ppn_T = 1'h0; // @[tlb.scala:150:35] wire _pmp_0_io_prv_T = 1'h0; // @[tlb.scala:157:50] wire _pmp_0_io_prv_T_1 = 1'h0; // @[tlb.scala:157:36] wire _cacheable_T_10 = 1'h0; // @[Mux.scala:30:73] wire _prot_x_T_23 = 1'h0; // @[Mux.scala:30:73] wire _prot_eff_T_22 = 1'h0; // @[Mux.scala:30:73] wire _sector_hits_T = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_7 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_14 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_21 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_28 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_35 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire _sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire _superpage_hits_T_3 = 1'h0; // @[tlb.scala:74:20] wire _superpage_hits_T_7 = 1'h0; // @[tlb.scala:74:20] wire _superpage_hits_T_11 = 1'h0; // @[tlb.scala:74:20] wire _superpage_hits_T_15 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_3 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_4 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_8 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_9 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_13 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_14 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_18 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_19 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_23 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_24 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_28 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_29 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_33 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_34 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_38 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_39 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_43 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_44 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_48 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_49 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_53 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_54 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_58 = 1'h0; // @[tlb.scala:74:20] wire _hitsVec_T_59 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_T_64 = 1'h0; // @[tlb.scala:173:69] wire _hitsVec_WIRE_0 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_1 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_2 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_3 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_4 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_5 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_6 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_7 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_8 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_9 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_10 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_11 = 1'h0; // @[tlb.scala:173:38] wire _hitsVec_WIRE_12 = 1'h0; // @[tlb.scala:173:38] wire hitsVec_0_0 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_1 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_2 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_3 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_4 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_5 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_6 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_7 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_8 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_9 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_10 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_11 = 1'h0; // @[tlb.scala:121:49] wire hitsVec_0_12 = 1'h0; // @[tlb.scala:121:49] wire newEntry_g = 1'h0; // @[tlb.scala:181:24] wire newEntry_ae = 1'h0; // @[tlb.scala:181:24] wire newEntry_sx = 1'h0; // @[tlb.scala:181:24] wire newEntry_fragmented_superpage = 1'h0; // @[tlb.scala:181:24] wire _newEntry_sr_T = 1'h0; // @[PTW.scala:141:47] wire _newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire _newEntry_sw_T = 1'h0; // @[PTW.scala:141:47] wire _newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire _newEntry_sx_T = 1'h0; // @[PTW.scala:141:47] wire _newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire _newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire _superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire _superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire _superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire _superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire bad_va_0 = 1'h0; // @[tlb.scala:121:49] wire _cmd_write_perms_T_1 = 1'h0; // @[tlb.scala:250:29] wire _tlb_hit_T = 1'h0; // @[tlb.scala:273:44] wire tlb_hit_0 = 1'h0; // @[tlb.scala:121:49] wire _tlb_miss_T_1 = 1'h0; // @[tlb.scala:274:46] wire _tlb_miss_T_3 = 1'h0; // @[tlb.scala:274:60] wire tlb_miss_0 = 1'h0; // @[tlb.scala:121:49] wire state_reg_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire state_reg_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire state_reg_left_subtree_state_3 = 1'h0; // @[package.scala:163:13] wire state_reg_right_subtree_state_3 = 1'h0; // @[Replacement.scala:198:38] wire _multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire _multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire _multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire _multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire _multipleHits_T_49 = 1'h0; // @[Misc.scala:183:49] wire multipleHits_0 = 1'h0; // @[tlb.scala:121:49] wire _io_resp_0_pf_ld_T = 1'h0; // @[tlb.scala:295:38] wire _io_resp_0_pf_st_T = 1'h0; // @[tlb.scala:296:38] wire _io_resp_0_miss_T = 1'h0; // @[tlb.scala:307:35] wire _io_resp_0_miss_T_1 = 1'h0; // @[tlb.scala:307:50] wire _io_ptw_req_valid_T = 1'h0; // @[tlb.scala:313:29] wire [1:0] io_resp_0_size = io_req_0_bits_size_0; // @[tlb.scala:17:7] wire [4:0] io_resp_0_cmd = io_req_0_bits_cmd_0; // @[tlb.scala:17:7] wire [31:0] _io_resp_0_paddr_T_1; // @[tlb.scala:308:28] wire _io_resp_0_pf_ld_T_3; // @[tlb.scala:295:54] wire _io_resp_0_pf_st_T_3; // @[tlb.scala:296:61] wire _io_resp_0_pf_inst_T_2; // @[tlb.scala:297:37] wire _io_resp_0_ae_ld_T_2; // @[tlb.scala:298:74] wire _io_resp_0_ae_st_T_2; // @[tlb.scala:299:74] wire _io_resp_0_ae_inst_T_3; // @[tlb.scala:300:74] wire _io_resp_0_ma_ld_T_1; // @[tlb.scala:301:54] wire _io_resp_0_ma_st_T_1; // @[tlb.scala:302:54] wire _io_resp_0_cacheable_T_1; // @[tlb.scala:304:55] wire _io_resp_0_must_alloc_T_1; // @[tlb.scala:305:64] wire _io_resp_0_prefetchable_T_2; // @[tlb.scala:306:70] wire io_resp_0_pf_ld_0; // @[tlb.scala:17:7] wire io_resp_0_pf_st_0; // @[tlb.scala:17:7] wire io_resp_0_pf_inst; // @[tlb.scala:17:7] wire io_resp_0_ae_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ae_st_0; // @[tlb.scala:17:7] wire io_resp_0_ae_inst; // @[tlb.scala:17:7] wire io_resp_0_ma_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ma_st_0; // @[tlb.scala:17:7] wire [31:0] io_resp_0_paddr_0; // @[tlb.scala:17:7] wire io_resp_0_cacheable_0; // @[tlb.scala:17:7] wire io_resp_0_must_alloc; // @[tlb.scala:17:7] wire io_resp_0_prefetchable; // @[tlb.scala:17:7] wire [20:0] _vpn_T = io_req_0_bits_vaddr_0[32:12]; // @[tlb.scala:17:7, :144:47] wire [20:0] vpn_0 = _vpn_T; // @[tlb.scala:121:49, :144:47] wire [20:0] _sector_hits_T_3 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_10 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_17 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_24 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_31 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_38 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_45 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _sector_hits_T_52 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _superpage_hits_T = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _superpage_hits_T_4 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _superpage_hits_T_8 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _superpage_hits_T_12 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_5 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_10 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_15 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_20 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_25 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_30 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_35 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_40 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_45 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_50 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_55 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [20:0] _hitsVec_T_60 = vpn_0; // @[tlb.scala:62:43, :121:49] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :145:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :145:44, :181:24] wire [19:0] _mpu_ppn_data_T_14; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_13; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_12; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_11; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_10; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_9; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_8; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_7; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_6; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_5; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_4; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_3; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_2; // @[tlb.scala:60:79] wire _mpu_ppn_data_T_1; // @[tlb.scala:60:79] wire _mpu_ppn_data_T; // @[tlb.scala:60:79] assign _mpu_ppn_data_T = _mpu_ppn_data_WIRE_1[0]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_fragmented_superpage = _mpu_ppn_data_T; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_1 = _mpu_ppn_data_WIRE_1[1]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_c = _mpu_ppn_data_T_1; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_2 = _mpu_ppn_data_WIRE_1[2]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_eff = _mpu_ppn_data_T_2; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_3 = _mpu_ppn_data_WIRE_1[3]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_paa = _mpu_ppn_data_T_3; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_4 = _mpu_ppn_data_WIRE_1[4]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_pal = _mpu_ppn_data_T_4; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_5 = _mpu_ppn_data_WIRE_1[5]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_pr = _mpu_ppn_data_T_5; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_6 = _mpu_ppn_data_WIRE_1[6]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_px = _mpu_ppn_data_T_6; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_7 = _mpu_ppn_data_WIRE_1[7]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_pw = _mpu_ppn_data_T_7; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_8 = _mpu_ppn_data_WIRE_1[8]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_sr = _mpu_ppn_data_T_8; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_9 = _mpu_ppn_data_WIRE_1[9]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_sx = _mpu_ppn_data_T_9; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_10 = _mpu_ppn_data_WIRE_1[10]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_sw = _mpu_ppn_data_T_10; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_11 = _mpu_ppn_data_WIRE_1[11]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_ae = _mpu_ppn_data_T_11; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_12 = _mpu_ppn_data_WIRE_1[12]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_g = _mpu_ppn_data_T_12; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_13 = _mpu_ppn_data_WIRE_1[13]; // @[tlb.scala:60:79] wire _mpu_ppn_data_WIRE_u = _mpu_ppn_data_T_13; // @[tlb.scala:60:79] assign _mpu_ppn_data_T_14 = _mpu_ppn_data_WIRE_1[33:14]; // @[tlb.scala:60:79] wire [19:0] _mpu_ppn_data_WIRE_ppn = _mpu_ppn_data_T_14; // @[tlb.scala:60:79] wire [21:0] _mpu_ppn_T_1 = io_req_0_bits_vaddr_0[33:12]; // @[tlb.scala:17:7, :150:134] wire [21:0] _mpu_ppn_T_2 = _mpu_ppn_T_1; // @[tlb.scala:150:{20,134}] wire [21:0] _mpu_ppn_T_3 = _mpu_ppn_T_2; // @[tlb.scala:149:20, :150:20] wire [21:0] mpu_ppn_0 = _mpu_ppn_T_3; // @[tlb.scala:121:49, :149:20] wire [11:0] _mpu_physaddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :151:72] wire [11:0] _io_resp_0_paddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :151:72, :308:57] wire [33:0] _mpu_physaddr_T_1 = {mpu_ppn_0, _mpu_physaddr_T}; // @[tlb.scala:121:49, :151:{39,72}] wire [33:0] mpu_physaddr_0 = _mpu_physaddr_T_1; // @[tlb.scala:121:49, :151:39] wire [33:0] _cacheable_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_26 = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_r_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_w_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_al_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_aa_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [33:0] _GEN = {mpu_physaddr_0[33:14], mpu_physaddr_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T; // @[Parameters.scala:137:31] assign _legal_address_T = _GEN; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T; // @[Parameters.scala:137:31] assign _homogeneous_T = _GEN; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_2 = _legal_address_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [33:0] _GEN_0 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T_16; // @[Parameters.scala:137:31] assign _prot_x_T_16 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T_16; // @[Parameters.scala:137:31] assign _prot_eff_T_16 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_7 = _legal_address_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [33:0] _legal_address_T_10 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_12 = _legal_address_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [33:0] _GEN_1 = {mpu_physaddr_0[33:26], mpu_physaddr_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_17 = _legal_address_T_16 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [33:0] _GEN_2 = {mpu_physaddr_0[33:32], mpu_physaddr_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [33:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _cacheable_T_5; // @[Parameters.scala:137:31] assign _cacheable_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_15; // @[Parameters.scala:137:31] assign _homogeneous_T_15 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _homogeneous_T_33; // @[Parameters.scala:137:31] assign _homogeneous_T_33 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T_5; // @[Parameters.scala:137:31] assign _prot_x_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T_5; // @[Parameters.scala:137:31] assign _prot_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [34:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] _legal_address_T_22 = _legal_address_T_21 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire _legal_address_T_25 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_26 = _legal_address_T_25 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_27 = _legal_address_T_26 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_28 = _legal_address_T_27 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire legal_address_0 = _legal_address_T_28; // @[tlb.scala:121:49, :159:84] wire _prot_r_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22] wire _prot_w_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22] wire _prot_al_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22] wire _prot_aa_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22] wire [34:0] _cacheable_T_1 = {1'h0, _cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _cacheable_T_2 = _cacheable_T_1 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _cacheable_T_3 = _cacheable_T_2; // @[Parameters.scala:137:46] wire _cacheable_T_4 = _cacheable_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _cacheable_T_6 = {1'h0, _cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _cacheable_T_7 = _cacheable_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _cacheable_T_8 = _cacheable_T_7; // @[Parameters.scala:137:46] wire _cacheable_T_9 = _cacheable_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_11 = _cacheable_T_9; // @[Mux.scala:30:73] wire _cacheable_T_12 = _cacheable_T_11; // @[Mux.scala:30:73] wire _cacheable_WIRE = _cacheable_T_12; // @[Mux.scala:30:73] wire _cacheable_T_13 = legal_address_0 & _cacheable_WIRE; // @[Mux.scala:30:73] wire _cacheable_T_14 = _cacheable_T_13; // @[tlb.scala:161:22, :162:66] wire cacheable_0 = _cacheable_T_14; // @[tlb.scala:121:49, :162:66] wire newEntry_c = cacheable_0; // @[tlb.scala:121:49, :181:24] wire [34:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_2 = _homogeneous_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_20 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [34:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_7 = _homogeneous_T_6 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_12 = _homogeneous_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_17 = _homogeneous_T_16 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_21 = _homogeneous_T_20 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_22 = _homogeneous_T_21 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_23 = _homogeneous_T_22 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire homogeneous_0 = _homogeneous_T_23; // @[TLBPermissions.scala:101:65] wire [34:0] _homogeneous_T_27 = {1'h0, _homogeneous_T_26}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_28 = _homogeneous_T_27 & 35'h80002000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_29 = _homogeneous_T_28; // @[Parameters.scala:137:46] wire _homogeneous_T_30 = _homogeneous_T_29 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_31 = _homogeneous_T_30; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_32 = ~_homogeneous_T_31; // @[TLBPermissions.scala:87:{22,66}] wire [34:0] _homogeneous_T_34 = {1'h0, _homogeneous_T_33}; // @[Parameters.scala:137:{31,41}] wire [34:0] _homogeneous_T_35 = _homogeneous_T_34 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _homogeneous_T_36 = _homogeneous_T_35; // @[Parameters.scala:137:46] wire _homogeneous_T_37 = _homogeneous_T_36 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_38 = _homogeneous_T_37; // @[TLBPermissions.scala:85:66] wire [34:0] _prot_r_T_1 = {1'h0, _prot_r_T}; // @[Parameters.scala:137:{31,41}] wire _prot_r_T_6 = _prot_r_T_5; // @[tlb.scala:161:22, :164:60] wire prot_r_0 = _prot_r_T_6; // @[tlb.scala:121:49, :164:60] wire newEntry_pr = prot_r_0; // @[tlb.scala:121:49, :181:24] wire [34:0] _prot_w_T_1 = {1'h0, _prot_w_T}; // @[Parameters.scala:137:{31,41}] wire _prot_w_T_6 = _prot_w_T_5; // @[tlb.scala:161:22, :165:64] wire prot_w_0 = _prot_w_T_6; // @[tlb.scala:121:49, :165:64] wire newEntry_pw = prot_w_0; // @[tlb.scala:121:49, :181:24] wire [34:0] _prot_al_T_1 = {1'h0, _prot_al_T}; // @[Parameters.scala:137:{31,41}] wire prot_al_0 = _prot_al_T_5; // @[tlb.scala:121:49, :161:22] wire newEntry_pal = prot_al_0; // @[tlb.scala:121:49, :181:24] wire [34:0] _prot_aa_T_1 = {1'h0, _prot_aa_T}; // @[Parameters.scala:137:{31,41}] wire prot_aa_0 = _prot_aa_T_5; // @[tlb.scala:121:49, :161:22] wire newEntry_paa = prot_aa_0; // @[tlb.scala:121:49, :181:24] wire [34:0] _prot_x_T_1 = {1'h0, _prot_x_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_2 = _prot_x_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_3 = _prot_x_T_2; // @[Parameters.scala:137:46] wire _prot_x_T_4 = _prot_x_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_x_T_6 = {1'h0, _prot_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_7 = _prot_x_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_8 = _prot_x_T_7; // @[Parameters.scala:137:46] wire _prot_x_T_9 = _prot_x_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_10 = _prot_x_T_4 | _prot_x_T_9; // @[Parameters.scala:629:89] wire _prot_x_T_22 = _prot_x_T_10; // @[Mux.scala:30:73] wire [33:0] _GEN_3 = {mpu_physaddr_0[33:17], mpu_physaddr_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [33:0] _prot_x_T_11; // @[Parameters.scala:137:31] assign _prot_x_T_11 = _GEN_3; // @[Parameters.scala:137:31] wire [33:0] _prot_eff_T_11; // @[Parameters.scala:137:31] assign _prot_eff_T_11 = _GEN_3; // @[Parameters.scala:137:31] wire [34:0] _prot_x_T_12 = {1'h0, _prot_x_T_11}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_13 = _prot_x_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_14 = _prot_x_T_13; // @[Parameters.scala:137:46] wire _prot_x_T_15 = _prot_x_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_x_T_17 = {1'h0, _prot_x_T_16}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_x_T_18 = _prot_x_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_x_T_19 = _prot_x_T_18; // @[Parameters.scala:137:46] wire _prot_x_T_20 = _prot_x_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_21 = _prot_x_T_15 | _prot_x_T_20; // @[Parameters.scala:629:89] wire _prot_x_T_24 = _prot_x_T_22; // @[Mux.scala:30:73] wire _prot_x_WIRE = _prot_x_T_24; // @[Mux.scala:30:73] wire _prot_x_T_25 = legal_address_0 & _prot_x_WIRE; // @[Mux.scala:30:73] wire _prot_x_T_26 = _prot_x_T_25; // @[tlb.scala:161:22, :168:59] wire prot_x_0 = _prot_x_T_26; // @[tlb.scala:121:49, :168:59] wire newEntry_px = prot_x_0; // @[tlb.scala:121:49, :181:24] wire [34:0] _prot_eff_T_1 = {1'h0, _prot_eff_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_2 = _prot_eff_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_3 = _prot_eff_T_2; // @[Parameters.scala:137:46] wire _prot_eff_T_4 = _prot_eff_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_eff_T_6 = {1'h0, _prot_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_7 = _prot_eff_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_8 = _prot_eff_T_7; // @[Parameters.scala:137:46] wire _prot_eff_T_9 = _prot_eff_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_10 = _prot_eff_T_4 | _prot_eff_T_9; // @[Parameters.scala:629:89] wire [34:0] _prot_eff_T_12 = {1'h0, _prot_eff_T_11}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_13 = _prot_eff_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_14 = _prot_eff_T_13; // @[Parameters.scala:137:46] wire _prot_eff_T_15 = _prot_eff_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _prot_eff_T_17 = {1'h0, _prot_eff_T_16}; // @[Parameters.scala:137:{31,41}] wire [34:0] _prot_eff_T_18 = _prot_eff_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _prot_eff_T_19 = _prot_eff_T_18; // @[Parameters.scala:137:46] wire _prot_eff_T_20 = _prot_eff_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_21 = _prot_eff_T_15 | _prot_eff_T_20; // @[Parameters.scala:629:89] wire _prot_eff_T_23 = _prot_eff_T_21; // @[Mux.scala:30:73] wire _prot_eff_T_24 = _prot_eff_T_23; // @[Mux.scala:30:73] wire _prot_eff_WIRE = _prot_eff_T_24; // @[Mux.scala:30:73] wire _prot_eff_T_25 = legal_address_0 & _prot_eff_WIRE; // @[Mux.scala:30:73] wire prot_eff_0 = _prot_eff_T_25; // @[tlb.scala:121:49, :161:22] wire newEntry_eff = prot_eff_0; // @[tlb.scala:121:49, :181:24] wire _sector_hits_T_1 = _sector_hits_T; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1; // @[package.scala:81:59] wire [18:0] _sector_hits_T_4 = _sector_hits_T_3[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_5 = _sector_hits_T_4 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_6 = _sector_hits_T_2 & _sector_hits_T_5; // @[package.scala:81:59] wire _sector_hits_WIRE_0 = _sector_hits_T_6; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_8 = _sector_hits_T_7; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8; // @[package.scala:81:59] wire [18:0] _sector_hits_T_11 = _sector_hits_T_10[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_12 = _sector_hits_T_11 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_13 = _sector_hits_T_9 & _sector_hits_T_12; // @[package.scala:81:59] wire _sector_hits_WIRE_1 = _sector_hits_T_13; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_15 = _sector_hits_T_14; // @[package.scala:81:59] wire _sector_hits_T_16 = _sector_hits_T_15; // @[package.scala:81:59] wire [18:0] _sector_hits_T_18 = _sector_hits_T_17[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_19 = _sector_hits_T_18 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_20 = _sector_hits_T_16 & _sector_hits_T_19; // @[package.scala:81:59] wire _sector_hits_WIRE_2 = _sector_hits_T_20; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_22 = _sector_hits_T_21; // @[package.scala:81:59] wire _sector_hits_T_23 = _sector_hits_T_22; // @[package.scala:81:59] wire [18:0] _sector_hits_T_25 = _sector_hits_T_24[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_26 = _sector_hits_T_25 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_27 = _sector_hits_T_23 & _sector_hits_T_26; // @[package.scala:81:59] wire _sector_hits_WIRE_3 = _sector_hits_T_27; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_29 = _sector_hits_T_28; // @[package.scala:81:59] wire _sector_hits_T_30 = _sector_hits_T_29; // @[package.scala:81:59] wire [18:0] _sector_hits_T_32 = _sector_hits_T_31[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_33 = _sector_hits_T_32 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_34 = _sector_hits_T_30 & _sector_hits_T_33; // @[package.scala:81:59] wire _sector_hits_WIRE_4 = _sector_hits_T_34; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_36 = _sector_hits_T_35; // @[package.scala:81:59] wire _sector_hits_T_37 = _sector_hits_T_36; // @[package.scala:81:59] wire [18:0] _sector_hits_T_39 = _sector_hits_T_38[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_40 = _sector_hits_T_39 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_41 = _sector_hits_T_37 & _sector_hits_T_40; // @[package.scala:81:59] wire _sector_hits_WIRE_5 = _sector_hits_T_41; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_43 = _sector_hits_T_42; // @[package.scala:81:59] wire _sector_hits_T_44 = _sector_hits_T_43; // @[package.scala:81:59] wire [18:0] _sector_hits_T_46 = _sector_hits_T_45[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_47 = _sector_hits_T_46 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_48 = _sector_hits_T_44 & _sector_hits_T_47; // @[package.scala:81:59] wire _sector_hits_WIRE_6 = _sector_hits_T_48; // @[tlb.scala:61:42, :171:42] wire _sector_hits_T_50 = _sector_hits_T_49; // @[package.scala:81:59] wire _sector_hits_T_51 = _sector_hits_T_50; // @[package.scala:81:59] wire [18:0] _sector_hits_T_53 = _sector_hits_T_52[20:2]; // @[tlb.scala:62:{43,50}] wire _sector_hits_T_54 = _sector_hits_T_53 == 19'h0; // @[tlb.scala:62:{50,73}] wire _sector_hits_T_55 = _sector_hits_T_51 & _sector_hits_T_54; // @[package.scala:81:59] wire _sector_hits_WIRE_7 = _sector_hits_T_55; // @[tlb.scala:61:42, :171:42] wire sector_hits_0_0 = _sector_hits_WIRE_0; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_1 = _sector_hits_WIRE_1; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_2 = _sector_hits_WIRE_2; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_3 = _sector_hits_WIRE_3; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_4 = _sector_hits_WIRE_4; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_5 = _sector_hits_WIRE_5; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_6 = _sector_hits_WIRE_6; // @[tlb.scala:121:49, :171:42] wire sector_hits_0_7 = _sector_hits_WIRE_7; // @[tlb.scala:121:49, :171:42] wire [20:0] _superpage_hits_T_1 = _superpage_hits_T; // @[tlb.scala:62:{43,50}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire _superpage_hits_WIRE_0 = _superpage_hits_T_3; // @[tlb.scala:74:20, :172:45] wire [20:0] _superpage_hits_T_5 = _superpage_hits_T_4; // @[tlb.scala:62:{43,50}] wire _superpage_hits_T_6 = _superpage_hits_T_5 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire _superpage_hits_WIRE_1 = _superpage_hits_T_7; // @[tlb.scala:74:20, :172:45] wire [20:0] _superpage_hits_T_9 = _superpage_hits_T_8; // @[tlb.scala:62:{43,50}] wire _superpage_hits_T_10 = _superpage_hits_T_9 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire _superpage_hits_WIRE_2 = _superpage_hits_T_11; // @[tlb.scala:74:20, :172:45] wire [20:0] _superpage_hits_T_13 = _superpage_hits_T_12; // @[tlb.scala:62:{43,50}] wire _superpage_hits_T_14 = _superpage_hits_T_13 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire _superpage_hits_WIRE_3 = _superpage_hits_T_15; // @[tlb.scala:74:20, :172:45] wire superpage_hits_0_0 = _superpage_hits_WIRE_0; // @[tlb.scala:121:49, :172:45] wire superpage_hits_0_1 = _superpage_hits_WIRE_1; // @[tlb.scala:121:49, :172:45] wire superpage_hits_0_2 = _superpage_hits_WIRE_2; // @[tlb.scala:121:49, :172:45] wire superpage_hits_0_3 = _superpage_hits_WIRE_3; // @[tlb.scala:121:49, :172:45] wire [1:0] hitsVec_idx = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_32 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_48 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_64 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_80 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_96 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_112 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13] wire [18:0] _hitsVec_T_1 = _hitsVec_T[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_2 = _hitsVec_T_1 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_6 = _hitsVec_T_5[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_7 = _hitsVec_T_6 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_11 = _hitsVec_T_10[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_12 = _hitsVec_T_11 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_16 = _hitsVec_T_15[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_17 = _hitsVec_T_16 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_21 = _hitsVec_T_20[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_22 = _hitsVec_T_21 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_26 = _hitsVec_T_25[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_27 = _hitsVec_T_26 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_31 = _hitsVec_T_30[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_32 = _hitsVec_T_31 == 19'h0; // @[tlb.scala:62:{50,73}] wire [18:0] _hitsVec_T_36 = _hitsVec_T_35[20:2]; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_37 = _hitsVec_T_36 == 19'h0; // @[tlb.scala:62:{50,73}] wire [20:0] _hitsVec_T_41 = _hitsVec_T_40; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_42 = _hitsVec_T_41 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire [20:0] _hitsVec_T_46 = _hitsVec_T_45; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_47 = _hitsVec_T_46 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire [20:0] _hitsVec_T_51 = _hitsVec_T_50; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_52 = _hitsVec_T_51 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire [20:0] _hitsVec_T_56 = _hitsVec_T_55; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_57 = _hitsVec_T_56 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire [20:0] _hitsVec_T_61 = _hitsVec_T_60; // @[tlb.scala:62:{43,50}] wire _hitsVec_T_62 = _hitsVec_T_61 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29] wire _hitsVec_T_63 = _hitsVec_T_62; // @[tlb.scala:62:73, :74:20] wire [19:0] _ppn_data_T_15; // @[tlb.scala:60:79] wire _ppn_data_T_14; // @[tlb.scala:60:79] wire _ppn_data_T_13; // @[tlb.scala:60:79] wire _ppn_data_T_12; // @[tlb.scala:60:79] wire _ppn_data_T_11; // @[tlb.scala:60:79] wire _ppn_data_T_10; // @[tlb.scala:60:79] wire _ppn_data_T_9; // @[tlb.scala:60:79] wire _ppn_data_T_8; // @[tlb.scala:60:79] wire _ppn_data_T_7; // @[tlb.scala:60:79] wire _ppn_data_T_6; // @[tlb.scala:60:79] wire _ppn_data_T_5; // @[tlb.scala:60:79] wire _ppn_data_T_4; // @[tlb.scala:60:79] wire _ppn_data_T_3; // @[tlb.scala:60:79] wire _ppn_data_T_2; // @[tlb.scala:60:79] wire _ppn_data_T_1; // @[tlb.scala:60:79] assign _ppn_data_T_1 = _ppn_data_WIRE_1[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_fragmented_superpage = _ppn_data_T_1; // @[tlb.scala:60:79] assign _ppn_data_T_2 = _ppn_data_WIRE_1[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_c = _ppn_data_T_2; // @[tlb.scala:60:79] assign _ppn_data_T_3 = _ppn_data_WIRE_1[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_eff = _ppn_data_T_3; // @[tlb.scala:60:79] assign _ppn_data_T_4 = _ppn_data_WIRE_1[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_paa = _ppn_data_T_4; // @[tlb.scala:60:79] assign _ppn_data_T_5 = _ppn_data_WIRE_1[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_pal = _ppn_data_T_5; // @[tlb.scala:60:79] assign _ppn_data_T_6 = _ppn_data_WIRE_1[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_pr = _ppn_data_T_6; // @[tlb.scala:60:79] assign _ppn_data_T_7 = _ppn_data_WIRE_1[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_px = _ppn_data_T_7; // @[tlb.scala:60:79] assign _ppn_data_T_8 = _ppn_data_WIRE_1[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_pw = _ppn_data_T_8; // @[tlb.scala:60:79] assign _ppn_data_T_9 = _ppn_data_WIRE_1[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_sr = _ppn_data_T_9; // @[tlb.scala:60:79] assign _ppn_data_T_10 = _ppn_data_WIRE_1[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_sx = _ppn_data_T_10; // @[tlb.scala:60:79] assign _ppn_data_T_11 = _ppn_data_WIRE_1[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_sw = _ppn_data_T_11; // @[tlb.scala:60:79] assign _ppn_data_T_12 = _ppn_data_WIRE_1[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_ae = _ppn_data_T_12; // @[tlb.scala:60:79] assign _ppn_data_T_13 = _ppn_data_WIRE_1[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_g = _ppn_data_T_13; // @[tlb.scala:60:79] assign _ppn_data_T_14 = _ppn_data_WIRE_1[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_u = _ppn_data_T_14; // @[tlb.scala:60:79] assign _ppn_data_T_15 = _ppn_data_WIRE_1[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_ppn = _ppn_data_T_15; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_31; // @[tlb.scala:60:79] wire _ppn_data_T_30; // @[tlb.scala:60:79] wire _ppn_data_T_29; // @[tlb.scala:60:79] wire _ppn_data_T_28; // @[tlb.scala:60:79] wire _ppn_data_T_27; // @[tlb.scala:60:79] wire _ppn_data_T_26; // @[tlb.scala:60:79] wire _ppn_data_T_25; // @[tlb.scala:60:79] wire _ppn_data_T_24; // @[tlb.scala:60:79] wire _ppn_data_T_23; // @[tlb.scala:60:79] wire _ppn_data_T_22; // @[tlb.scala:60:79] wire _ppn_data_T_21; // @[tlb.scala:60:79] wire _ppn_data_T_20; // @[tlb.scala:60:79] wire _ppn_data_T_19; // @[tlb.scala:60:79] wire _ppn_data_T_18; // @[tlb.scala:60:79] wire _ppn_data_T_17; // @[tlb.scala:60:79] assign _ppn_data_T_17 = _ppn_data_WIRE_3[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_fragmented_superpage = _ppn_data_T_17; // @[tlb.scala:60:79] assign _ppn_data_T_18 = _ppn_data_WIRE_3[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_c = _ppn_data_T_18; // @[tlb.scala:60:79] assign _ppn_data_T_19 = _ppn_data_WIRE_3[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_eff = _ppn_data_T_19; // @[tlb.scala:60:79] assign _ppn_data_T_20 = _ppn_data_WIRE_3[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_paa = _ppn_data_T_20; // @[tlb.scala:60:79] assign _ppn_data_T_21 = _ppn_data_WIRE_3[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_pal = _ppn_data_T_21; // @[tlb.scala:60:79] assign _ppn_data_T_22 = _ppn_data_WIRE_3[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_pr = _ppn_data_T_22; // @[tlb.scala:60:79] assign _ppn_data_T_23 = _ppn_data_WIRE_3[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_px = _ppn_data_T_23; // @[tlb.scala:60:79] assign _ppn_data_T_24 = _ppn_data_WIRE_3[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_pw = _ppn_data_T_24; // @[tlb.scala:60:79] assign _ppn_data_T_25 = _ppn_data_WIRE_3[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_sr = _ppn_data_T_25; // @[tlb.scala:60:79] assign _ppn_data_T_26 = _ppn_data_WIRE_3[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_sx = _ppn_data_T_26; // @[tlb.scala:60:79] assign _ppn_data_T_27 = _ppn_data_WIRE_3[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_sw = _ppn_data_T_27; // @[tlb.scala:60:79] assign _ppn_data_T_28 = _ppn_data_WIRE_3[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_ae = _ppn_data_T_28; // @[tlb.scala:60:79] assign _ppn_data_T_29 = _ppn_data_WIRE_3[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_g = _ppn_data_T_29; // @[tlb.scala:60:79] assign _ppn_data_T_30 = _ppn_data_WIRE_3[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_2_u = _ppn_data_T_30; // @[tlb.scala:60:79] assign _ppn_data_T_31 = _ppn_data_WIRE_3[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_2_ppn = _ppn_data_T_31; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_47; // @[tlb.scala:60:79] wire _ppn_data_T_46; // @[tlb.scala:60:79] wire _ppn_data_T_45; // @[tlb.scala:60:79] wire _ppn_data_T_44; // @[tlb.scala:60:79] wire _ppn_data_T_43; // @[tlb.scala:60:79] wire _ppn_data_T_42; // @[tlb.scala:60:79] wire _ppn_data_T_41; // @[tlb.scala:60:79] wire _ppn_data_T_40; // @[tlb.scala:60:79] wire _ppn_data_T_39; // @[tlb.scala:60:79] wire _ppn_data_T_38; // @[tlb.scala:60:79] wire _ppn_data_T_37; // @[tlb.scala:60:79] wire _ppn_data_T_36; // @[tlb.scala:60:79] wire _ppn_data_T_35; // @[tlb.scala:60:79] wire _ppn_data_T_34; // @[tlb.scala:60:79] wire _ppn_data_T_33; // @[tlb.scala:60:79] assign _ppn_data_T_33 = _ppn_data_WIRE_5[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_fragmented_superpage = _ppn_data_T_33; // @[tlb.scala:60:79] assign _ppn_data_T_34 = _ppn_data_WIRE_5[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_c = _ppn_data_T_34; // @[tlb.scala:60:79] assign _ppn_data_T_35 = _ppn_data_WIRE_5[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_eff = _ppn_data_T_35; // @[tlb.scala:60:79] assign _ppn_data_T_36 = _ppn_data_WIRE_5[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_paa = _ppn_data_T_36; // @[tlb.scala:60:79] assign _ppn_data_T_37 = _ppn_data_WIRE_5[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_pal = _ppn_data_T_37; // @[tlb.scala:60:79] assign _ppn_data_T_38 = _ppn_data_WIRE_5[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_pr = _ppn_data_T_38; // @[tlb.scala:60:79] assign _ppn_data_T_39 = _ppn_data_WIRE_5[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_px = _ppn_data_T_39; // @[tlb.scala:60:79] assign _ppn_data_T_40 = _ppn_data_WIRE_5[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_pw = _ppn_data_T_40; // @[tlb.scala:60:79] assign _ppn_data_T_41 = _ppn_data_WIRE_5[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_sr = _ppn_data_T_41; // @[tlb.scala:60:79] assign _ppn_data_T_42 = _ppn_data_WIRE_5[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_sx = _ppn_data_T_42; // @[tlb.scala:60:79] assign _ppn_data_T_43 = _ppn_data_WIRE_5[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_sw = _ppn_data_T_43; // @[tlb.scala:60:79] assign _ppn_data_T_44 = _ppn_data_WIRE_5[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_ae = _ppn_data_T_44; // @[tlb.scala:60:79] assign _ppn_data_T_45 = _ppn_data_WIRE_5[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_g = _ppn_data_T_45; // @[tlb.scala:60:79] assign _ppn_data_T_46 = _ppn_data_WIRE_5[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_4_u = _ppn_data_T_46; // @[tlb.scala:60:79] assign _ppn_data_T_47 = _ppn_data_WIRE_5[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_4_ppn = _ppn_data_T_47; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_63; // @[tlb.scala:60:79] wire _ppn_data_T_62; // @[tlb.scala:60:79] wire _ppn_data_T_61; // @[tlb.scala:60:79] wire _ppn_data_T_60; // @[tlb.scala:60:79] wire _ppn_data_T_59; // @[tlb.scala:60:79] wire _ppn_data_T_58; // @[tlb.scala:60:79] wire _ppn_data_T_57; // @[tlb.scala:60:79] wire _ppn_data_T_56; // @[tlb.scala:60:79] wire _ppn_data_T_55; // @[tlb.scala:60:79] wire _ppn_data_T_54; // @[tlb.scala:60:79] wire _ppn_data_T_53; // @[tlb.scala:60:79] wire _ppn_data_T_52; // @[tlb.scala:60:79] wire _ppn_data_T_51; // @[tlb.scala:60:79] wire _ppn_data_T_50; // @[tlb.scala:60:79] wire _ppn_data_T_49; // @[tlb.scala:60:79] assign _ppn_data_T_49 = _ppn_data_WIRE_7[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_fragmented_superpage = _ppn_data_T_49; // @[tlb.scala:60:79] assign _ppn_data_T_50 = _ppn_data_WIRE_7[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_c = _ppn_data_T_50; // @[tlb.scala:60:79] assign _ppn_data_T_51 = _ppn_data_WIRE_7[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_eff = _ppn_data_T_51; // @[tlb.scala:60:79] assign _ppn_data_T_52 = _ppn_data_WIRE_7[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_paa = _ppn_data_T_52; // @[tlb.scala:60:79] assign _ppn_data_T_53 = _ppn_data_WIRE_7[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_pal = _ppn_data_T_53; // @[tlb.scala:60:79] assign _ppn_data_T_54 = _ppn_data_WIRE_7[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_pr = _ppn_data_T_54; // @[tlb.scala:60:79] assign _ppn_data_T_55 = _ppn_data_WIRE_7[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_px = _ppn_data_T_55; // @[tlb.scala:60:79] assign _ppn_data_T_56 = _ppn_data_WIRE_7[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_pw = _ppn_data_T_56; // @[tlb.scala:60:79] assign _ppn_data_T_57 = _ppn_data_WIRE_7[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_sr = _ppn_data_T_57; // @[tlb.scala:60:79] assign _ppn_data_T_58 = _ppn_data_WIRE_7[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_sx = _ppn_data_T_58; // @[tlb.scala:60:79] assign _ppn_data_T_59 = _ppn_data_WIRE_7[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_sw = _ppn_data_T_59; // @[tlb.scala:60:79] assign _ppn_data_T_60 = _ppn_data_WIRE_7[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_ae = _ppn_data_T_60; // @[tlb.scala:60:79] assign _ppn_data_T_61 = _ppn_data_WIRE_7[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_g = _ppn_data_T_61; // @[tlb.scala:60:79] assign _ppn_data_T_62 = _ppn_data_WIRE_7[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_6_u = _ppn_data_T_62; // @[tlb.scala:60:79] assign _ppn_data_T_63 = _ppn_data_WIRE_7[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_6_ppn = _ppn_data_T_63; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_79; // @[tlb.scala:60:79] wire _ppn_data_T_78; // @[tlb.scala:60:79] wire _ppn_data_T_77; // @[tlb.scala:60:79] wire _ppn_data_T_76; // @[tlb.scala:60:79] wire _ppn_data_T_75; // @[tlb.scala:60:79] wire _ppn_data_T_74; // @[tlb.scala:60:79] wire _ppn_data_T_73; // @[tlb.scala:60:79] wire _ppn_data_T_72; // @[tlb.scala:60:79] wire _ppn_data_T_71; // @[tlb.scala:60:79] wire _ppn_data_T_70; // @[tlb.scala:60:79] wire _ppn_data_T_69; // @[tlb.scala:60:79] wire _ppn_data_T_68; // @[tlb.scala:60:79] wire _ppn_data_T_67; // @[tlb.scala:60:79] wire _ppn_data_T_66; // @[tlb.scala:60:79] wire _ppn_data_T_65; // @[tlb.scala:60:79] assign _ppn_data_T_65 = _ppn_data_WIRE_9[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_fragmented_superpage = _ppn_data_T_65; // @[tlb.scala:60:79] assign _ppn_data_T_66 = _ppn_data_WIRE_9[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_c = _ppn_data_T_66; // @[tlb.scala:60:79] assign _ppn_data_T_67 = _ppn_data_WIRE_9[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_eff = _ppn_data_T_67; // @[tlb.scala:60:79] assign _ppn_data_T_68 = _ppn_data_WIRE_9[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_paa = _ppn_data_T_68; // @[tlb.scala:60:79] assign _ppn_data_T_69 = _ppn_data_WIRE_9[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_pal = _ppn_data_T_69; // @[tlb.scala:60:79] assign _ppn_data_T_70 = _ppn_data_WIRE_9[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_pr = _ppn_data_T_70; // @[tlb.scala:60:79] assign _ppn_data_T_71 = _ppn_data_WIRE_9[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_px = _ppn_data_T_71; // @[tlb.scala:60:79] assign _ppn_data_T_72 = _ppn_data_WIRE_9[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_pw = _ppn_data_T_72; // @[tlb.scala:60:79] assign _ppn_data_T_73 = _ppn_data_WIRE_9[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_sr = _ppn_data_T_73; // @[tlb.scala:60:79] assign _ppn_data_T_74 = _ppn_data_WIRE_9[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_sx = _ppn_data_T_74; // @[tlb.scala:60:79] assign _ppn_data_T_75 = _ppn_data_WIRE_9[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_sw = _ppn_data_T_75; // @[tlb.scala:60:79] assign _ppn_data_T_76 = _ppn_data_WIRE_9[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_ae = _ppn_data_T_76; // @[tlb.scala:60:79] assign _ppn_data_T_77 = _ppn_data_WIRE_9[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_g = _ppn_data_T_77; // @[tlb.scala:60:79] assign _ppn_data_T_78 = _ppn_data_WIRE_9[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_8_u = _ppn_data_T_78; // @[tlb.scala:60:79] assign _ppn_data_T_79 = _ppn_data_WIRE_9[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_8_ppn = _ppn_data_T_79; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_95; // @[tlb.scala:60:79] wire _ppn_data_T_94; // @[tlb.scala:60:79] wire _ppn_data_T_93; // @[tlb.scala:60:79] wire _ppn_data_T_92; // @[tlb.scala:60:79] wire _ppn_data_T_91; // @[tlb.scala:60:79] wire _ppn_data_T_90; // @[tlb.scala:60:79] wire _ppn_data_T_89; // @[tlb.scala:60:79] wire _ppn_data_T_88; // @[tlb.scala:60:79] wire _ppn_data_T_87; // @[tlb.scala:60:79] wire _ppn_data_T_86; // @[tlb.scala:60:79] wire _ppn_data_T_85; // @[tlb.scala:60:79] wire _ppn_data_T_84; // @[tlb.scala:60:79] wire _ppn_data_T_83; // @[tlb.scala:60:79] wire _ppn_data_T_82; // @[tlb.scala:60:79] wire _ppn_data_T_81; // @[tlb.scala:60:79] assign _ppn_data_T_81 = _ppn_data_WIRE_11[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_fragmented_superpage = _ppn_data_T_81; // @[tlb.scala:60:79] assign _ppn_data_T_82 = _ppn_data_WIRE_11[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_c = _ppn_data_T_82; // @[tlb.scala:60:79] assign _ppn_data_T_83 = _ppn_data_WIRE_11[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_eff = _ppn_data_T_83; // @[tlb.scala:60:79] assign _ppn_data_T_84 = _ppn_data_WIRE_11[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_paa = _ppn_data_T_84; // @[tlb.scala:60:79] assign _ppn_data_T_85 = _ppn_data_WIRE_11[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_pal = _ppn_data_T_85; // @[tlb.scala:60:79] assign _ppn_data_T_86 = _ppn_data_WIRE_11[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_pr = _ppn_data_T_86; // @[tlb.scala:60:79] assign _ppn_data_T_87 = _ppn_data_WIRE_11[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_px = _ppn_data_T_87; // @[tlb.scala:60:79] assign _ppn_data_T_88 = _ppn_data_WIRE_11[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_pw = _ppn_data_T_88; // @[tlb.scala:60:79] assign _ppn_data_T_89 = _ppn_data_WIRE_11[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_sr = _ppn_data_T_89; // @[tlb.scala:60:79] assign _ppn_data_T_90 = _ppn_data_WIRE_11[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_sx = _ppn_data_T_90; // @[tlb.scala:60:79] assign _ppn_data_T_91 = _ppn_data_WIRE_11[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_sw = _ppn_data_T_91; // @[tlb.scala:60:79] assign _ppn_data_T_92 = _ppn_data_WIRE_11[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_ae = _ppn_data_T_92; // @[tlb.scala:60:79] assign _ppn_data_T_93 = _ppn_data_WIRE_11[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_g = _ppn_data_T_93; // @[tlb.scala:60:79] assign _ppn_data_T_94 = _ppn_data_WIRE_11[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_10_u = _ppn_data_T_94; // @[tlb.scala:60:79] assign _ppn_data_T_95 = _ppn_data_WIRE_11[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_10_ppn = _ppn_data_T_95; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_111; // @[tlb.scala:60:79] wire _ppn_data_T_110; // @[tlb.scala:60:79] wire _ppn_data_T_109; // @[tlb.scala:60:79] wire _ppn_data_T_108; // @[tlb.scala:60:79] wire _ppn_data_T_107; // @[tlb.scala:60:79] wire _ppn_data_T_106; // @[tlb.scala:60:79] wire _ppn_data_T_105; // @[tlb.scala:60:79] wire _ppn_data_T_104; // @[tlb.scala:60:79] wire _ppn_data_T_103; // @[tlb.scala:60:79] wire _ppn_data_T_102; // @[tlb.scala:60:79] wire _ppn_data_T_101; // @[tlb.scala:60:79] wire _ppn_data_T_100; // @[tlb.scala:60:79] wire _ppn_data_T_99; // @[tlb.scala:60:79] wire _ppn_data_T_98; // @[tlb.scala:60:79] wire _ppn_data_T_97; // @[tlb.scala:60:79] assign _ppn_data_T_97 = _ppn_data_WIRE_13[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_fragmented_superpage = _ppn_data_T_97; // @[tlb.scala:60:79] assign _ppn_data_T_98 = _ppn_data_WIRE_13[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_c = _ppn_data_T_98; // @[tlb.scala:60:79] assign _ppn_data_T_99 = _ppn_data_WIRE_13[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_eff = _ppn_data_T_99; // @[tlb.scala:60:79] assign _ppn_data_T_100 = _ppn_data_WIRE_13[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_paa = _ppn_data_T_100; // @[tlb.scala:60:79] assign _ppn_data_T_101 = _ppn_data_WIRE_13[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_pal = _ppn_data_T_101; // @[tlb.scala:60:79] assign _ppn_data_T_102 = _ppn_data_WIRE_13[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_pr = _ppn_data_T_102; // @[tlb.scala:60:79] assign _ppn_data_T_103 = _ppn_data_WIRE_13[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_px = _ppn_data_T_103; // @[tlb.scala:60:79] assign _ppn_data_T_104 = _ppn_data_WIRE_13[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_pw = _ppn_data_T_104; // @[tlb.scala:60:79] assign _ppn_data_T_105 = _ppn_data_WIRE_13[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_sr = _ppn_data_T_105; // @[tlb.scala:60:79] assign _ppn_data_T_106 = _ppn_data_WIRE_13[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_sx = _ppn_data_T_106; // @[tlb.scala:60:79] assign _ppn_data_T_107 = _ppn_data_WIRE_13[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_sw = _ppn_data_T_107; // @[tlb.scala:60:79] assign _ppn_data_T_108 = _ppn_data_WIRE_13[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_ae = _ppn_data_T_108; // @[tlb.scala:60:79] assign _ppn_data_T_109 = _ppn_data_WIRE_13[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_g = _ppn_data_T_109; // @[tlb.scala:60:79] assign _ppn_data_T_110 = _ppn_data_WIRE_13[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_12_u = _ppn_data_T_110; // @[tlb.scala:60:79] assign _ppn_data_T_111 = _ppn_data_WIRE_13[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_12_ppn = _ppn_data_T_111; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_127; // @[tlb.scala:60:79] wire _ppn_data_T_126; // @[tlb.scala:60:79] wire _ppn_data_T_125; // @[tlb.scala:60:79] wire _ppn_data_T_124; // @[tlb.scala:60:79] wire _ppn_data_T_123; // @[tlb.scala:60:79] wire _ppn_data_T_122; // @[tlb.scala:60:79] wire _ppn_data_T_121; // @[tlb.scala:60:79] wire _ppn_data_T_120; // @[tlb.scala:60:79] wire _ppn_data_T_119; // @[tlb.scala:60:79] wire _ppn_data_T_118; // @[tlb.scala:60:79] wire _ppn_data_T_117; // @[tlb.scala:60:79] wire _ppn_data_T_116; // @[tlb.scala:60:79] wire _ppn_data_T_115; // @[tlb.scala:60:79] wire _ppn_data_T_114; // @[tlb.scala:60:79] wire _ppn_data_T_113; // @[tlb.scala:60:79] assign _ppn_data_T_113 = _ppn_data_WIRE_15[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_fragmented_superpage = _ppn_data_T_113; // @[tlb.scala:60:79] assign _ppn_data_T_114 = _ppn_data_WIRE_15[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_c = _ppn_data_T_114; // @[tlb.scala:60:79] assign _ppn_data_T_115 = _ppn_data_WIRE_15[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_eff = _ppn_data_T_115; // @[tlb.scala:60:79] assign _ppn_data_T_116 = _ppn_data_WIRE_15[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_paa = _ppn_data_T_116; // @[tlb.scala:60:79] assign _ppn_data_T_117 = _ppn_data_WIRE_15[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_pal = _ppn_data_T_117; // @[tlb.scala:60:79] assign _ppn_data_T_118 = _ppn_data_WIRE_15[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_pr = _ppn_data_T_118; // @[tlb.scala:60:79] assign _ppn_data_T_119 = _ppn_data_WIRE_15[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_px = _ppn_data_T_119; // @[tlb.scala:60:79] assign _ppn_data_T_120 = _ppn_data_WIRE_15[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_pw = _ppn_data_T_120; // @[tlb.scala:60:79] assign _ppn_data_T_121 = _ppn_data_WIRE_15[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_sr = _ppn_data_T_121; // @[tlb.scala:60:79] assign _ppn_data_T_122 = _ppn_data_WIRE_15[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_sx = _ppn_data_T_122; // @[tlb.scala:60:79] assign _ppn_data_T_123 = _ppn_data_WIRE_15[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_sw = _ppn_data_T_123; // @[tlb.scala:60:79] assign _ppn_data_T_124 = _ppn_data_WIRE_15[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_ae = _ppn_data_T_124; // @[tlb.scala:60:79] assign _ppn_data_T_125 = _ppn_data_WIRE_15[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_g = _ppn_data_T_125; // @[tlb.scala:60:79] assign _ppn_data_T_126 = _ppn_data_WIRE_15[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_14_u = _ppn_data_T_126; // @[tlb.scala:60:79] assign _ppn_data_T_127 = _ppn_data_WIRE_15[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_14_ppn = _ppn_data_T_127; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_142; // @[tlb.scala:60:79] wire _ppn_data_T_141; // @[tlb.scala:60:79] wire _ppn_data_T_140; // @[tlb.scala:60:79] wire _ppn_data_T_139; // @[tlb.scala:60:79] wire _ppn_data_T_138; // @[tlb.scala:60:79] wire _ppn_data_T_137; // @[tlb.scala:60:79] wire _ppn_data_T_136; // @[tlb.scala:60:79] wire _ppn_data_T_135; // @[tlb.scala:60:79] wire _ppn_data_T_134; // @[tlb.scala:60:79] wire _ppn_data_T_133; // @[tlb.scala:60:79] wire _ppn_data_T_132; // @[tlb.scala:60:79] wire _ppn_data_T_131; // @[tlb.scala:60:79] wire _ppn_data_T_130; // @[tlb.scala:60:79] wire _ppn_data_T_129; // @[tlb.scala:60:79] wire _ppn_data_T_128; // @[tlb.scala:60:79] assign _ppn_data_T_128 = _ppn_data_WIRE_17[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_fragmented_superpage = _ppn_data_T_128; // @[tlb.scala:60:79] assign _ppn_data_T_129 = _ppn_data_WIRE_17[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_c = _ppn_data_T_129; // @[tlb.scala:60:79] assign _ppn_data_T_130 = _ppn_data_WIRE_17[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_eff = _ppn_data_T_130; // @[tlb.scala:60:79] assign _ppn_data_T_131 = _ppn_data_WIRE_17[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_paa = _ppn_data_T_131; // @[tlb.scala:60:79] assign _ppn_data_T_132 = _ppn_data_WIRE_17[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_pal = _ppn_data_T_132; // @[tlb.scala:60:79] assign _ppn_data_T_133 = _ppn_data_WIRE_17[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_pr = _ppn_data_T_133; // @[tlb.scala:60:79] assign _ppn_data_T_134 = _ppn_data_WIRE_17[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_px = _ppn_data_T_134; // @[tlb.scala:60:79] assign _ppn_data_T_135 = _ppn_data_WIRE_17[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_pw = _ppn_data_T_135; // @[tlb.scala:60:79] assign _ppn_data_T_136 = _ppn_data_WIRE_17[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_sr = _ppn_data_T_136; // @[tlb.scala:60:79] assign _ppn_data_T_137 = _ppn_data_WIRE_17[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_sx = _ppn_data_T_137; // @[tlb.scala:60:79] assign _ppn_data_T_138 = _ppn_data_WIRE_17[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_sw = _ppn_data_T_138; // @[tlb.scala:60:79] assign _ppn_data_T_139 = _ppn_data_WIRE_17[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_ae = _ppn_data_T_139; // @[tlb.scala:60:79] assign _ppn_data_T_140 = _ppn_data_WIRE_17[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_g = _ppn_data_T_140; // @[tlb.scala:60:79] assign _ppn_data_T_141 = _ppn_data_WIRE_17[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_16_u = _ppn_data_T_141; // @[tlb.scala:60:79] assign _ppn_data_T_142 = _ppn_data_WIRE_17[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_16_ppn = _ppn_data_T_142; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_157; // @[tlb.scala:60:79] wire _ppn_data_T_156; // @[tlb.scala:60:79] wire _ppn_data_T_155; // @[tlb.scala:60:79] wire _ppn_data_T_154; // @[tlb.scala:60:79] wire _ppn_data_T_153; // @[tlb.scala:60:79] wire _ppn_data_T_152; // @[tlb.scala:60:79] wire _ppn_data_T_151; // @[tlb.scala:60:79] wire _ppn_data_T_150; // @[tlb.scala:60:79] wire _ppn_data_T_149; // @[tlb.scala:60:79] wire _ppn_data_T_148; // @[tlb.scala:60:79] wire _ppn_data_T_147; // @[tlb.scala:60:79] wire _ppn_data_T_146; // @[tlb.scala:60:79] wire _ppn_data_T_145; // @[tlb.scala:60:79] wire _ppn_data_T_144; // @[tlb.scala:60:79] wire _ppn_data_T_143; // @[tlb.scala:60:79] assign _ppn_data_T_143 = _ppn_data_WIRE_19[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_fragmented_superpage = _ppn_data_T_143; // @[tlb.scala:60:79] assign _ppn_data_T_144 = _ppn_data_WIRE_19[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_c = _ppn_data_T_144; // @[tlb.scala:60:79] assign _ppn_data_T_145 = _ppn_data_WIRE_19[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_eff = _ppn_data_T_145; // @[tlb.scala:60:79] assign _ppn_data_T_146 = _ppn_data_WIRE_19[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_paa = _ppn_data_T_146; // @[tlb.scala:60:79] assign _ppn_data_T_147 = _ppn_data_WIRE_19[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_pal = _ppn_data_T_147; // @[tlb.scala:60:79] assign _ppn_data_T_148 = _ppn_data_WIRE_19[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_pr = _ppn_data_T_148; // @[tlb.scala:60:79] assign _ppn_data_T_149 = _ppn_data_WIRE_19[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_px = _ppn_data_T_149; // @[tlb.scala:60:79] assign _ppn_data_T_150 = _ppn_data_WIRE_19[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_pw = _ppn_data_T_150; // @[tlb.scala:60:79] assign _ppn_data_T_151 = _ppn_data_WIRE_19[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_sr = _ppn_data_T_151; // @[tlb.scala:60:79] assign _ppn_data_T_152 = _ppn_data_WIRE_19[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_sx = _ppn_data_T_152; // @[tlb.scala:60:79] assign _ppn_data_T_153 = _ppn_data_WIRE_19[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_sw = _ppn_data_T_153; // @[tlb.scala:60:79] assign _ppn_data_T_154 = _ppn_data_WIRE_19[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_ae = _ppn_data_T_154; // @[tlb.scala:60:79] assign _ppn_data_T_155 = _ppn_data_WIRE_19[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_g = _ppn_data_T_155; // @[tlb.scala:60:79] assign _ppn_data_T_156 = _ppn_data_WIRE_19[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_18_u = _ppn_data_T_156; // @[tlb.scala:60:79] assign _ppn_data_T_157 = _ppn_data_WIRE_19[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_18_ppn = _ppn_data_T_157; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_172; // @[tlb.scala:60:79] wire _ppn_data_T_171; // @[tlb.scala:60:79] wire _ppn_data_T_170; // @[tlb.scala:60:79] wire _ppn_data_T_169; // @[tlb.scala:60:79] wire _ppn_data_T_168; // @[tlb.scala:60:79] wire _ppn_data_T_167; // @[tlb.scala:60:79] wire _ppn_data_T_166; // @[tlb.scala:60:79] wire _ppn_data_T_165; // @[tlb.scala:60:79] wire _ppn_data_T_164; // @[tlb.scala:60:79] wire _ppn_data_T_163; // @[tlb.scala:60:79] wire _ppn_data_T_162; // @[tlb.scala:60:79] wire _ppn_data_T_161; // @[tlb.scala:60:79] wire _ppn_data_T_160; // @[tlb.scala:60:79] wire _ppn_data_T_159; // @[tlb.scala:60:79] wire _ppn_data_T_158; // @[tlb.scala:60:79] assign _ppn_data_T_158 = _ppn_data_WIRE_21[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_fragmented_superpage = _ppn_data_T_158; // @[tlb.scala:60:79] assign _ppn_data_T_159 = _ppn_data_WIRE_21[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_c = _ppn_data_T_159; // @[tlb.scala:60:79] assign _ppn_data_T_160 = _ppn_data_WIRE_21[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_eff = _ppn_data_T_160; // @[tlb.scala:60:79] assign _ppn_data_T_161 = _ppn_data_WIRE_21[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_paa = _ppn_data_T_161; // @[tlb.scala:60:79] assign _ppn_data_T_162 = _ppn_data_WIRE_21[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_pal = _ppn_data_T_162; // @[tlb.scala:60:79] assign _ppn_data_T_163 = _ppn_data_WIRE_21[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_pr = _ppn_data_T_163; // @[tlb.scala:60:79] assign _ppn_data_T_164 = _ppn_data_WIRE_21[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_px = _ppn_data_T_164; // @[tlb.scala:60:79] assign _ppn_data_T_165 = _ppn_data_WIRE_21[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_pw = _ppn_data_T_165; // @[tlb.scala:60:79] assign _ppn_data_T_166 = _ppn_data_WIRE_21[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_sr = _ppn_data_T_166; // @[tlb.scala:60:79] assign _ppn_data_T_167 = _ppn_data_WIRE_21[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_sx = _ppn_data_T_167; // @[tlb.scala:60:79] assign _ppn_data_T_168 = _ppn_data_WIRE_21[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_sw = _ppn_data_T_168; // @[tlb.scala:60:79] assign _ppn_data_T_169 = _ppn_data_WIRE_21[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_ae = _ppn_data_T_169; // @[tlb.scala:60:79] assign _ppn_data_T_170 = _ppn_data_WIRE_21[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_g = _ppn_data_T_170; // @[tlb.scala:60:79] assign _ppn_data_T_171 = _ppn_data_WIRE_21[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_20_u = _ppn_data_T_171; // @[tlb.scala:60:79] assign _ppn_data_T_172 = _ppn_data_WIRE_21[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_20_ppn = _ppn_data_T_172; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_187; // @[tlb.scala:60:79] wire _ppn_data_T_186; // @[tlb.scala:60:79] wire _ppn_data_T_185; // @[tlb.scala:60:79] wire _ppn_data_T_184; // @[tlb.scala:60:79] wire _ppn_data_T_183; // @[tlb.scala:60:79] wire _ppn_data_T_182; // @[tlb.scala:60:79] wire _ppn_data_T_181; // @[tlb.scala:60:79] wire _ppn_data_T_180; // @[tlb.scala:60:79] wire _ppn_data_T_179; // @[tlb.scala:60:79] wire _ppn_data_T_178; // @[tlb.scala:60:79] wire _ppn_data_T_177; // @[tlb.scala:60:79] wire _ppn_data_T_176; // @[tlb.scala:60:79] wire _ppn_data_T_175; // @[tlb.scala:60:79] wire _ppn_data_T_174; // @[tlb.scala:60:79] wire _ppn_data_T_173; // @[tlb.scala:60:79] assign _ppn_data_T_173 = _ppn_data_WIRE_23[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_fragmented_superpage = _ppn_data_T_173; // @[tlb.scala:60:79] assign _ppn_data_T_174 = _ppn_data_WIRE_23[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_c = _ppn_data_T_174; // @[tlb.scala:60:79] assign _ppn_data_T_175 = _ppn_data_WIRE_23[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_eff = _ppn_data_T_175; // @[tlb.scala:60:79] assign _ppn_data_T_176 = _ppn_data_WIRE_23[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_paa = _ppn_data_T_176; // @[tlb.scala:60:79] assign _ppn_data_T_177 = _ppn_data_WIRE_23[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_pal = _ppn_data_T_177; // @[tlb.scala:60:79] assign _ppn_data_T_178 = _ppn_data_WIRE_23[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_pr = _ppn_data_T_178; // @[tlb.scala:60:79] assign _ppn_data_T_179 = _ppn_data_WIRE_23[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_px = _ppn_data_T_179; // @[tlb.scala:60:79] assign _ppn_data_T_180 = _ppn_data_WIRE_23[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_pw = _ppn_data_T_180; // @[tlb.scala:60:79] assign _ppn_data_T_181 = _ppn_data_WIRE_23[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_sr = _ppn_data_T_181; // @[tlb.scala:60:79] assign _ppn_data_T_182 = _ppn_data_WIRE_23[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_sx = _ppn_data_T_182; // @[tlb.scala:60:79] assign _ppn_data_T_183 = _ppn_data_WIRE_23[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_sw = _ppn_data_T_183; // @[tlb.scala:60:79] assign _ppn_data_T_184 = _ppn_data_WIRE_23[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_ae = _ppn_data_T_184; // @[tlb.scala:60:79] assign _ppn_data_T_185 = _ppn_data_WIRE_23[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_g = _ppn_data_T_185; // @[tlb.scala:60:79] assign _ppn_data_T_186 = _ppn_data_WIRE_23[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_22_u = _ppn_data_T_186; // @[tlb.scala:60:79] assign _ppn_data_T_187 = _ppn_data_WIRE_23[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_22_ppn = _ppn_data_T_187; // @[tlb.scala:60:79] wire [19:0] _ppn_data_T_202; // @[tlb.scala:60:79] wire _ppn_data_T_201; // @[tlb.scala:60:79] wire _ppn_data_T_200; // @[tlb.scala:60:79] wire _ppn_data_T_199; // @[tlb.scala:60:79] wire _ppn_data_T_198; // @[tlb.scala:60:79] wire _ppn_data_T_197; // @[tlb.scala:60:79] wire _ppn_data_T_196; // @[tlb.scala:60:79] wire _ppn_data_T_195; // @[tlb.scala:60:79] wire _ppn_data_T_194; // @[tlb.scala:60:79] wire _ppn_data_T_193; // @[tlb.scala:60:79] wire _ppn_data_T_192; // @[tlb.scala:60:79] wire _ppn_data_T_191; // @[tlb.scala:60:79] wire _ppn_data_T_190; // @[tlb.scala:60:79] wire _ppn_data_T_189; // @[tlb.scala:60:79] wire _ppn_data_T_188; // @[tlb.scala:60:79] assign _ppn_data_T_188 = _ppn_data_WIRE_25[0]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_fragmented_superpage = _ppn_data_T_188; // @[tlb.scala:60:79] assign _ppn_data_T_189 = _ppn_data_WIRE_25[1]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_c = _ppn_data_T_189; // @[tlb.scala:60:79] assign _ppn_data_T_190 = _ppn_data_WIRE_25[2]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_eff = _ppn_data_T_190; // @[tlb.scala:60:79] assign _ppn_data_T_191 = _ppn_data_WIRE_25[3]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_paa = _ppn_data_T_191; // @[tlb.scala:60:79] assign _ppn_data_T_192 = _ppn_data_WIRE_25[4]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_pal = _ppn_data_T_192; // @[tlb.scala:60:79] assign _ppn_data_T_193 = _ppn_data_WIRE_25[5]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_pr = _ppn_data_T_193; // @[tlb.scala:60:79] assign _ppn_data_T_194 = _ppn_data_WIRE_25[6]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_px = _ppn_data_T_194; // @[tlb.scala:60:79] assign _ppn_data_T_195 = _ppn_data_WIRE_25[7]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_pw = _ppn_data_T_195; // @[tlb.scala:60:79] assign _ppn_data_T_196 = _ppn_data_WIRE_25[8]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_sr = _ppn_data_T_196; // @[tlb.scala:60:79] assign _ppn_data_T_197 = _ppn_data_WIRE_25[9]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_sx = _ppn_data_T_197; // @[tlb.scala:60:79] assign _ppn_data_T_198 = _ppn_data_WIRE_25[10]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_sw = _ppn_data_T_198; // @[tlb.scala:60:79] assign _ppn_data_T_199 = _ppn_data_WIRE_25[11]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_ae = _ppn_data_T_199; // @[tlb.scala:60:79] assign _ppn_data_T_200 = _ppn_data_WIRE_25[12]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_g = _ppn_data_T_200; // @[tlb.scala:60:79] assign _ppn_data_T_201 = _ppn_data_WIRE_25[13]; // @[tlb.scala:60:79] wire _ppn_data_WIRE_24_u = _ppn_data_T_201; // @[tlb.scala:60:79] assign _ppn_data_T_202 = _ppn_data_WIRE_25[33:14]; // @[tlb.scala:60:79] wire [19:0] _ppn_data_WIRE_24_ppn = _ppn_data_T_202; // @[tlb.scala:60:79] wire [19:0] _ppn_T_1 = vpn_0[19:0]; // @[tlb.scala:121:49, :176:103] wire [19:0] _ppn_T_15 = _ppn_T_1; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_15; // @[Mux.scala:30:73] wire [19:0] _ppn_WIRE = _ppn_T_28; // @[Mux.scala:30:73] wire [19:0] ppn_0 = _ppn_WIRE; // @[Mux.scala:30:73] wire [1:0] _GEN_4 = {newEntry_eff, newEntry_c}; // @[tlb.scala:97:26, :181:24] wire [1:0] special_entry_data_0_lo_lo_hi; // @[tlb.scala:97:26] assign special_entry_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] superpage_entries_0_data_0_lo_lo_hi; // @[tlb.scala:97:26] assign superpage_entries_0_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] superpage_entries_1_data_0_lo_lo_hi; // @[tlb.scala:97:26] assign superpage_entries_1_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] superpage_entries_2_data_0_lo_lo_hi; // @[tlb.scala:97:26] assign superpage_entries_2_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] superpage_entries_3_data_0_lo_lo_hi; // @[tlb.scala:97:26] assign superpage_entries_3_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_0_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_0_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_1_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_1_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_2_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_2_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_3_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_3_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_4_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_4_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_5_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_5_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_6_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_6_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [1:0] sectored_entries_7_data_lo_lo_hi; // @[tlb.scala:97:26] assign sectored_entries_7_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26] wire [2:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [1:0] _GEN_5 = {newEntry_pal, newEntry_paa}; // @[tlb.scala:97:26, :181:24] wire [1:0] special_entry_data_0_lo_hi_lo; // @[tlb.scala:97:26] assign special_entry_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] superpage_entries_0_data_0_lo_hi_lo; // @[tlb.scala:97:26] assign superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] superpage_entries_1_data_0_lo_hi_lo; // @[tlb.scala:97:26] assign superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] superpage_entries_2_data_0_lo_hi_lo; // @[tlb.scala:97:26] assign superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] superpage_entries_3_data_0_lo_hi_lo; // @[tlb.scala:97:26] assign superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_0_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_0_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_1_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_1_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_2_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_2_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_3_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_3_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_4_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_4_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_5_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_5_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_6_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_6_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] sectored_entries_7_data_lo_hi_lo; // @[tlb.scala:97:26] assign sectored_entries_7_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26] wire [1:0] _GEN_6 = {newEntry_px, newEntry_pr}; // @[tlb.scala:97:26, :181:24] wire [1:0] special_entry_data_0_lo_hi_hi; // @[tlb.scala:97:26] assign special_entry_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] superpage_entries_0_data_0_lo_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_0_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] superpage_entries_1_data_0_lo_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_1_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] superpage_entries_2_data_0_lo_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_2_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] superpage_entries_3_data_0_lo_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_3_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_0_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_0_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_1_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_1_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_2_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_2_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_3_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_3_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_4_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_4_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_5_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_5_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_6_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_6_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [1:0] sectored_entries_7_data_lo_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_7_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26] wire [3:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[tlb.scala:97:26] wire [1:0] _GEN_7 = {1'h1, newEntry_pw}; // @[tlb.scala:97:26, :181:24] wire [1:0] special_entry_data_0_hi_lo_lo; // @[tlb.scala:97:26] assign special_entry_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] superpage_entries_0_data_0_hi_lo_lo; // @[tlb.scala:97:26] assign superpage_entries_0_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] superpage_entries_1_data_0_hi_lo_lo; // @[tlb.scala:97:26] assign superpage_entries_1_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] superpage_entries_2_data_0_hi_lo_lo; // @[tlb.scala:97:26] assign superpage_entries_2_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] superpage_entries_3_data_0_hi_lo_lo; // @[tlb.scala:97:26] assign superpage_entries_3_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_0_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_0_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_1_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_1_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_2_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_2_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_3_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_3_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_4_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_4_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_5_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_5_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_6_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_6_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [1:0] sectored_entries_7_data_hi_lo_lo; // @[tlb.scala:97:26] assign sectored_entries_7_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26] wire [3:0] special_entry_data_0_hi_lo = {2'h2, special_entry_data_0_hi_lo_lo}; // @[tlb.scala:97:26] wire [20:0] _GEN_8 = {newEntry_ppn, 1'h1}; // @[tlb.scala:97:26, :181:24] wire [20:0] special_entry_data_0_hi_hi_hi; // @[tlb.scala:97:26] assign special_entry_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] superpage_entries_0_data_0_hi_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_0_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] superpage_entries_1_data_0_hi_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_1_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] superpage_entries_2_data_0_hi_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_2_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] superpage_entries_3_data_0_hi_hi_hi; // @[tlb.scala:97:26] assign superpage_entries_3_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_0_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_0_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_1_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_1_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_2_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_2_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_3_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_3_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_4_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_4_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_5_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_5_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_6_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_6_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [20:0] sectored_entries_7_data_hi_hi_hi; // @[tlb.scala:97:26] assign sectored_entries_7_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26] wire [22:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[tlb.scala:97:26] wire [2:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_0_data_0_hi_lo = {2'h2, superpage_entries_0_data_0_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[tlb.scala:97:26] wire [2:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_1_data_0_hi_lo = {2'h2, superpage_entries_1_data_0_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[tlb.scala:97:26] wire [2:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_2_data_0_hi_lo = {2'h2, superpage_entries_2_data_0_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[tlb.scala:97:26] wire [2:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[tlb.scala:97:26] wire [3:0] superpage_entries_3_data_0_hi_lo = {2'h2, superpage_entries_3_data_0_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_0_data_lo_lo = {sectored_entries_0_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_0_data_lo_hi = {sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_0_data_lo = {sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_0_data_hi_lo = {2'h2, sectored_entries_0_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_0_data_hi_hi = {sectored_entries_0_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_0_data_hi = {sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_0_data_T = {sectored_entries_0_data_hi, sectored_entries_0_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_1_data_lo_lo = {sectored_entries_1_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_1_data_lo_hi = {sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_1_data_lo = {sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_1_data_hi_lo = {2'h2, sectored_entries_1_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_1_data_hi_hi = {sectored_entries_1_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_1_data_hi = {sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_1_data_T = {sectored_entries_1_data_hi, sectored_entries_1_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_2_data_lo_lo = {sectored_entries_2_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_2_data_lo_hi = {sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_2_data_lo = {sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_2_data_hi_lo = {2'h2, sectored_entries_2_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_2_data_hi_hi = {sectored_entries_2_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_2_data_hi = {sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_2_data_T = {sectored_entries_2_data_hi, sectored_entries_2_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_3_data_lo_lo = {sectored_entries_3_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_3_data_lo_hi = {sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_3_data_lo = {sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_3_data_hi_lo = {2'h2, sectored_entries_3_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_3_data_hi_hi = {sectored_entries_3_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_3_data_hi = {sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_3_data_T = {sectored_entries_3_data_hi, sectored_entries_3_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_4_data_lo_lo = {sectored_entries_4_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_4_data_lo_hi = {sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_4_data_lo = {sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_4_data_hi_lo = {2'h2, sectored_entries_4_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_4_data_hi_hi = {sectored_entries_4_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_4_data_hi = {sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_4_data_T = {sectored_entries_4_data_hi, sectored_entries_4_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_5_data_lo_lo = {sectored_entries_5_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_5_data_lo_hi = {sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_5_data_lo = {sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_5_data_hi_lo = {2'h2, sectored_entries_5_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_5_data_hi_hi = {sectored_entries_5_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_5_data_hi = {sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_5_data_T = {sectored_entries_5_data_hi, sectored_entries_5_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_6_data_lo_lo = {sectored_entries_6_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_6_data_lo_hi = {sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_6_data_lo = {sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_6_data_hi_lo = {2'h2, sectored_entries_6_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_6_data_hi_hi = {sectored_entries_6_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_6_data_hi = {sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_6_data_T = {sectored_entries_6_data_hi, sectored_entries_6_data_lo}; // @[tlb.scala:97:26] wire [2:0] sectored_entries_7_data_lo_lo = {sectored_entries_7_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_7_data_lo_hi = {sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo}; // @[tlb.scala:97:26] wire [6:0] sectored_entries_7_data_lo = {sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo}; // @[tlb.scala:97:26] wire [3:0] sectored_entries_7_data_hi_lo = {2'h2, sectored_entries_7_data_hi_lo_lo}; // @[tlb.scala:97:26] wire [22:0] sectored_entries_7_data_hi_hi = {sectored_entries_7_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26] wire [26:0] sectored_entries_7_data_hi = {sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo}; // @[tlb.scala:97:26] wire [33:0] _sectored_entries_7_data_T = {sectored_entries_7_data_hi, sectored_entries_7_data_lo}; // @[tlb.scala:97:26] wire [19:0] _entries_T_15; // @[tlb.scala:60:79] wire _entries_T_14; // @[tlb.scala:60:79] wire _entries_T_13; // @[tlb.scala:60:79] wire _entries_T_12; // @[tlb.scala:60:79] wire _entries_T_11; // @[tlb.scala:60:79] wire _entries_T_10; // @[tlb.scala:60:79] wire _entries_T_9; // @[tlb.scala:60:79] wire _entries_T_8; // @[tlb.scala:60:79] wire _entries_T_7; // @[tlb.scala:60:79] wire _entries_T_6; // @[tlb.scala:60:79] wire _entries_T_5; // @[tlb.scala:60:79] wire _entries_T_4; // @[tlb.scala:60:79] wire _entries_T_3; // @[tlb.scala:60:79] wire _entries_T_2; // @[tlb.scala:60:79] wire _entries_T_1; // @[tlb.scala:60:79] assign _entries_T_1 = _entries_WIRE_1[0]; // @[tlb.scala:60:79] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[tlb.scala:60:79] assign _entries_T_2 = _entries_WIRE_1[1]; // @[tlb.scala:60:79] wire _entries_WIRE_c = _entries_T_2; // @[tlb.scala:60:79] assign _entries_T_3 = _entries_WIRE_1[2]; // @[tlb.scala:60:79] wire _entries_WIRE_eff = _entries_T_3; // @[tlb.scala:60:79] assign _entries_T_4 = _entries_WIRE_1[3]; // @[tlb.scala:60:79] wire _entries_WIRE_paa = _entries_T_4; // @[tlb.scala:60:79] assign _entries_T_5 = _entries_WIRE_1[4]; // @[tlb.scala:60:79] wire _entries_WIRE_pal = _entries_T_5; // @[tlb.scala:60:79] assign _entries_T_6 = _entries_WIRE_1[5]; // @[tlb.scala:60:79] wire _entries_WIRE_pr = _entries_T_6; // @[tlb.scala:60:79] assign _entries_T_7 = _entries_WIRE_1[6]; // @[tlb.scala:60:79] wire _entries_WIRE_px = _entries_T_7; // @[tlb.scala:60:79] assign _entries_T_8 = _entries_WIRE_1[7]; // @[tlb.scala:60:79] wire _entries_WIRE_pw = _entries_T_8; // @[tlb.scala:60:79] assign _entries_T_9 = _entries_WIRE_1[8]; // @[tlb.scala:60:79] wire _entries_WIRE_sr = _entries_T_9; // @[tlb.scala:60:79] assign _entries_T_10 = _entries_WIRE_1[9]; // @[tlb.scala:60:79] wire _entries_WIRE_sx = _entries_T_10; // @[tlb.scala:60:79] assign _entries_T_11 = _entries_WIRE_1[10]; // @[tlb.scala:60:79] wire _entries_WIRE_sw = _entries_T_11; // @[tlb.scala:60:79] assign _entries_T_12 = _entries_WIRE_1[11]; // @[tlb.scala:60:79] wire _entries_WIRE_ae = _entries_T_12; // @[tlb.scala:60:79] assign _entries_T_13 = _entries_WIRE_1[12]; // @[tlb.scala:60:79] wire _entries_WIRE_g = _entries_T_13; // @[tlb.scala:60:79] assign _entries_T_14 = _entries_WIRE_1[13]; // @[tlb.scala:60:79] wire _entries_WIRE_u = _entries_T_14; // @[tlb.scala:60:79] assign _entries_T_15 = _entries_WIRE_1[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_ppn = _entries_T_15; // @[tlb.scala:60:79] wire [19:0] _entries_T_31; // @[tlb.scala:60:79] wire _entries_T_30; // @[tlb.scala:60:79] wire _entries_T_29; // @[tlb.scala:60:79] wire _entries_T_28; // @[tlb.scala:60:79] wire _entries_T_27; // @[tlb.scala:60:79] wire _entries_T_26; // @[tlb.scala:60:79] wire _entries_T_25; // @[tlb.scala:60:79] wire _entries_T_24; // @[tlb.scala:60:79] wire _entries_T_23; // @[tlb.scala:60:79] wire _entries_T_22; // @[tlb.scala:60:79] wire _entries_T_21; // @[tlb.scala:60:79] wire _entries_T_20; // @[tlb.scala:60:79] wire _entries_T_19; // @[tlb.scala:60:79] wire _entries_T_18; // @[tlb.scala:60:79] wire _entries_T_17; // @[tlb.scala:60:79] assign _entries_T_17 = _entries_WIRE_3[0]; // @[tlb.scala:60:79] wire _entries_WIRE_2_fragmented_superpage = _entries_T_17; // @[tlb.scala:60:79] assign _entries_T_18 = _entries_WIRE_3[1]; // @[tlb.scala:60:79] wire _entries_WIRE_2_c = _entries_T_18; // @[tlb.scala:60:79] assign _entries_T_19 = _entries_WIRE_3[2]; // @[tlb.scala:60:79] wire _entries_WIRE_2_eff = _entries_T_19; // @[tlb.scala:60:79] assign _entries_T_20 = _entries_WIRE_3[3]; // @[tlb.scala:60:79] wire _entries_WIRE_2_paa = _entries_T_20; // @[tlb.scala:60:79] assign _entries_T_21 = _entries_WIRE_3[4]; // @[tlb.scala:60:79] wire _entries_WIRE_2_pal = _entries_T_21; // @[tlb.scala:60:79] assign _entries_T_22 = _entries_WIRE_3[5]; // @[tlb.scala:60:79] wire _entries_WIRE_2_pr = _entries_T_22; // @[tlb.scala:60:79] assign _entries_T_23 = _entries_WIRE_3[6]; // @[tlb.scala:60:79] wire _entries_WIRE_2_px = _entries_T_23; // @[tlb.scala:60:79] assign _entries_T_24 = _entries_WIRE_3[7]; // @[tlb.scala:60:79] wire _entries_WIRE_2_pw = _entries_T_24; // @[tlb.scala:60:79] assign _entries_T_25 = _entries_WIRE_3[8]; // @[tlb.scala:60:79] wire _entries_WIRE_2_sr = _entries_T_25; // @[tlb.scala:60:79] assign _entries_T_26 = _entries_WIRE_3[9]; // @[tlb.scala:60:79] wire _entries_WIRE_2_sx = _entries_T_26; // @[tlb.scala:60:79] assign _entries_T_27 = _entries_WIRE_3[10]; // @[tlb.scala:60:79] wire _entries_WIRE_2_sw = _entries_T_27; // @[tlb.scala:60:79] assign _entries_T_28 = _entries_WIRE_3[11]; // @[tlb.scala:60:79] wire _entries_WIRE_2_ae = _entries_T_28; // @[tlb.scala:60:79] assign _entries_T_29 = _entries_WIRE_3[12]; // @[tlb.scala:60:79] wire _entries_WIRE_2_g = _entries_T_29; // @[tlb.scala:60:79] assign _entries_T_30 = _entries_WIRE_3[13]; // @[tlb.scala:60:79] wire _entries_WIRE_2_u = _entries_T_30; // @[tlb.scala:60:79] assign _entries_T_31 = _entries_WIRE_3[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_2_ppn = _entries_T_31; // @[tlb.scala:60:79] wire [19:0] _entries_T_47; // @[tlb.scala:60:79] wire _entries_T_46; // @[tlb.scala:60:79] wire _entries_T_45; // @[tlb.scala:60:79] wire _entries_T_44; // @[tlb.scala:60:79] wire _entries_T_43; // @[tlb.scala:60:79] wire _entries_T_42; // @[tlb.scala:60:79] wire _entries_T_41; // @[tlb.scala:60:79] wire _entries_T_40; // @[tlb.scala:60:79] wire _entries_T_39; // @[tlb.scala:60:79] wire _entries_T_38; // @[tlb.scala:60:79] wire _entries_T_37; // @[tlb.scala:60:79] wire _entries_T_36; // @[tlb.scala:60:79] wire _entries_T_35; // @[tlb.scala:60:79] wire _entries_T_34; // @[tlb.scala:60:79] wire _entries_T_33; // @[tlb.scala:60:79] assign _entries_T_33 = _entries_WIRE_5[0]; // @[tlb.scala:60:79] wire _entries_WIRE_4_fragmented_superpage = _entries_T_33; // @[tlb.scala:60:79] assign _entries_T_34 = _entries_WIRE_5[1]; // @[tlb.scala:60:79] wire _entries_WIRE_4_c = _entries_T_34; // @[tlb.scala:60:79] assign _entries_T_35 = _entries_WIRE_5[2]; // @[tlb.scala:60:79] wire _entries_WIRE_4_eff = _entries_T_35; // @[tlb.scala:60:79] assign _entries_T_36 = _entries_WIRE_5[3]; // @[tlb.scala:60:79] wire _entries_WIRE_4_paa = _entries_T_36; // @[tlb.scala:60:79] assign _entries_T_37 = _entries_WIRE_5[4]; // @[tlb.scala:60:79] wire _entries_WIRE_4_pal = _entries_T_37; // @[tlb.scala:60:79] assign _entries_T_38 = _entries_WIRE_5[5]; // @[tlb.scala:60:79] wire _entries_WIRE_4_pr = _entries_T_38; // @[tlb.scala:60:79] assign _entries_T_39 = _entries_WIRE_5[6]; // @[tlb.scala:60:79] wire _entries_WIRE_4_px = _entries_T_39; // @[tlb.scala:60:79] assign _entries_T_40 = _entries_WIRE_5[7]; // @[tlb.scala:60:79] wire _entries_WIRE_4_pw = _entries_T_40; // @[tlb.scala:60:79] assign _entries_T_41 = _entries_WIRE_5[8]; // @[tlb.scala:60:79] wire _entries_WIRE_4_sr = _entries_T_41; // @[tlb.scala:60:79] assign _entries_T_42 = _entries_WIRE_5[9]; // @[tlb.scala:60:79] wire _entries_WIRE_4_sx = _entries_T_42; // @[tlb.scala:60:79] assign _entries_T_43 = _entries_WIRE_5[10]; // @[tlb.scala:60:79] wire _entries_WIRE_4_sw = _entries_T_43; // @[tlb.scala:60:79] assign _entries_T_44 = _entries_WIRE_5[11]; // @[tlb.scala:60:79] wire _entries_WIRE_4_ae = _entries_T_44; // @[tlb.scala:60:79] assign _entries_T_45 = _entries_WIRE_5[12]; // @[tlb.scala:60:79] wire _entries_WIRE_4_g = _entries_T_45; // @[tlb.scala:60:79] assign _entries_T_46 = _entries_WIRE_5[13]; // @[tlb.scala:60:79] wire _entries_WIRE_4_u = _entries_T_46; // @[tlb.scala:60:79] assign _entries_T_47 = _entries_WIRE_5[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_4_ppn = _entries_T_47; // @[tlb.scala:60:79] wire [19:0] _entries_T_63; // @[tlb.scala:60:79] wire _entries_T_62; // @[tlb.scala:60:79] wire _entries_T_61; // @[tlb.scala:60:79] wire _entries_T_60; // @[tlb.scala:60:79] wire _entries_T_59; // @[tlb.scala:60:79] wire _entries_T_58; // @[tlb.scala:60:79] wire _entries_T_57; // @[tlb.scala:60:79] wire _entries_T_56; // @[tlb.scala:60:79] wire _entries_T_55; // @[tlb.scala:60:79] wire _entries_T_54; // @[tlb.scala:60:79] wire _entries_T_53; // @[tlb.scala:60:79] wire _entries_T_52; // @[tlb.scala:60:79] wire _entries_T_51; // @[tlb.scala:60:79] wire _entries_T_50; // @[tlb.scala:60:79] wire _entries_T_49; // @[tlb.scala:60:79] assign _entries_T_49 = _entries_WIRE_7[0]; // @[tlb.scala:60:79] wire _entries_WIRE_6_fragmented_superpage = _entries_T_49; // @[tlb.scala:60:79] assign _entries_T_50 = _entries_WIRE_7[1]; // @[tlb.scala:60:79] wire _entries_WIRE_6_c = _entries_T_50; // @[tlb.scala:60:79] assign _entries_T_51 = _entries_WIRE_7[2]; // @[tlb.scala:60:79] wire _entries_WIRE_6_eff = _entries_T_51; // @[tlb.scala:60:79] assign _entries_T_52 = _entries_WIRE_7[3]; // @[tlb.scala:60:79] wire _entries_WIRE_6_paa = _entries_T_52; // @[tlb.scala:60:79] assign _entries_T_53 = _entries_WIRE_7[4]; // @[tlb.scala:60:79] wire _entries_WIRE_6_pal = _entries_T_53; // @[tlb.scala:60:79] assign _entries_T_54 = _entries_WIRE_7[5]; // @[tlb.scala:60:79] wire _entries_WIRE_6_pr = _entries_T_54; // @[tlb.scala:60:79] assign _entries_T_55 = _entries_WIRE_7[6]; // @[tlb.scala:60:79] wire _entries_WIRE_6_px = _entries_T_55; // @[tlb.scala:60:79] assign _entries_T_56 = _entries_WIRE_7[7]; // @[tlb.scala:60:79] wire _entries_WIRE_6_pw = _entries_T_56; // @[tlb.scala:60:79] assign _entries_T_57 = _entries_WIRE_7[8]; // @[tlb.scala:60:79] wire _entries_WIRE_6_sr = _entries_T_57; // @[tlb.scala:60:79] assign _entries_T_58 = _entries_WIRE_7[9]; // @[tlb.scala:60:79] wire _entries_WIRE_6_sx = _entries_T_58; // @[tlb.scala:60:79] assign _entries_T_59 = _entries_WIRE_7[10]; // @[tlb.scala:60:79] wire _entries_WIRE_6_sw = _entries_T_59; // @[tlb.scala:60:79] assign _entries_T_60 = _entries_WIRE_7[11]; // @[tlb.scala:60:79] wire _entries_WIRE_6_ae = _entries_T_60; // @[tlb.scala:60:79] assign _entries_T_61 = _entries_WIRE_7[12]; // @[tlb.scala:60:79] wire _entries_WIRE_6_g = _entries_T_61; // @[tlb.scala:60:79] assign _entries_T_62 = _entries_WIRE_7[13]; // @[tlb.scala:60:79] wire _entries_WIRE_6_u = _entries_T_62; // @[tlb.scala:60:79] assign _entries_T_63 = _entries_WIRE_7[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_6_ppn = _entries_T_63; // @[tlb.scala:60:79] wire [19:0] _entries_T_79; // @[tlb.scala:60:79] wire _entries_T_78; // @[tlb.scala:60:79] wire _entries_T_77; // @[tlb.scala:60:79] wire _entries_T_76; // @[tlb.scala:60:79] wire _entries_T_75; // @[tlb.scala:60:79] wire _entries_T_74; // @[tlb.scala:60:79] wire _entries_T_73; // @[tlb.scala:60:79] wire _entries_T_72; // @[tlb.scala:60:79] wire _entries_T_71; // @[tlb.scala:60:79] wire _entries_T_70; // @[tlb.scala:60:79] wire _entries_T_69; // @[tlb.scala:60:79] wire _entries_T_68; // @[tlb.scala:60:79] wire _entries_T_67; // @[tlb.scala:60:79] wire _entries_T_66; // @[tlb.scala:60:79] wire _entries_T_65; // @[tlb.scala:60:79] assign _entries_T_65 = _entries_WIRE_9[0]; // @[tlb.scala:60:79] wire _entries_WIRE_8_fragmented_superpage = _entries_T_65; // @[tlb.scala:60:79] assign _entries_T_66 = _entries_WIRE_9[1]; // @[tlb.scala:60:79] wire _entries_WIRE_8_c = _entries_T_66; // @[tlb.scala:60:79] assign _entries_T_67 = _entries_WIRE_9[2]; // @[tlb.scala:60:79] wire _entries_WIRE_8_eff = _entries_T_67; // @[tlb.scala:60:79] assign _entries_T_68 = _entries_WIRE_9[3]; // @[tlb.scala:60:79] wire _entries_WIRE_8_paa = _entries_T_68; // @[tlb.scala:60:79] assign _entries_T_69 = _entries_WIRE_9[4]; // @[tlb.scala:60:79] wire _entries_WIRE_8_pal = _entries_T_69; // @[tlb.scala:60:79] assign _entries_T_70 = _entries_WIRE_9[5]; // @[tlb.scala:60:79] wire _entries_WIRE_8_pr = _entries_T_70; // @[tlb.scala:60:79] assign _entries_T_71 = _entries_WIRE_9[6]; // @[tlb.scala:60:79] wire _entries_WIRE_8_px = _entries_T_71; // @[tlb.scala:60:79] assign _entries_T_72 = _entries_WIRE_9[7]; // @[tlb.scala:60:79] wire _entries_WIRE_8_pw = _entries_T_72; // @[tlb.scala:60:79] assign _entries_T_73 = _entries_WIRE_9[8]; // @[tlb.scala:60:79] wire _entries_WIRE_8_sr = _entries_T_73; // @[tlb.scala:60:79] assign _entries_T_74 = _entries_WIRE_9[9]; // @[tlb.scala:60:79] wire _entries_WIRE_8_sx = _entries_T_74; // @[tlb.scala:60:79] assign _entries_T_75 = _entries_WIRE_9[10]; // @[tlb.scala:60:79] wire _entries_WIRE_8_sw = _entries_T_75; // @[tlb.scala:60:79] assign _entries_T_76 = _entries_WIRE_9[11]; // @[tlb.scala:60:79] wire _entries_WIRE_8_ae = _entries_T_76; // @[tlb.scala:60:79] assign _entries_T_77 = _entries_WIRE_9[12]; // @[tlb.scala:60:79] wire _entries_WIRE_8_g = _entries_T_77; // @[tlb.scala:60:79] assign _entries_T_78 = _entries_WIRE_9[13]; // @[tlb.scala:60:79] wire _entries_WIRE_8_u = _entries_T_78; // @[tlb.scala:60:79] assign _entries_T_79 = _entries_WIRE_9[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_8_ppn = _entries_T_79; // @[tlb.scala:60:79] wire [19:0] _entries_T_95; // @[tlb.scala:60:79] wire _entries_T_94; // @[tlb.scala:60:79] wire _entries_T_93; // @[tlb.scala:60:79] wire _entries_T_92; // @[tlb.scala:60:79] wire _entries_T_91; // @[tlb.scala:60:79] wire _entries_T_90; // @[tlb.scala:60:79] wire _entries_T_89; // @[tlb.scala:60:79] wire _entries_T_88; // @[tlb.scala:60:79] wire _entries_T_87; // @[tlb.scala:60:79] wire _entries_T_86; // @[tlb.scala:60:79] wire _entries_T_85; // @[tlb.scala:60:79] wire _entries_T_84; // @[tlb.scala:60:79] wire _entries_T_83; // @[tlb.scala:60:79] wire _entries_T_82; // @[tlb.scala:60:79] wire _entries_T_81; // @[tlb.scala:60:79] assign _entries_T_81 = _entries_WIRE_11[0]; // @[tlb.scala:60:79] wire _entries_WIRE_10_fragmented_superpage = _entries_T_81; // @[tlb.scala:60:79] assign _entries_T_82 = _entries_WIRE_11[1]; // @[tlb.scala:60:79] wire _entries_WIRE_10_c = _entries_T_82; // @[tlb.scala:60:79] assign _entries_T_83 = _entries_WIRE_11[2]; // @[tlb.scala:60:79] wire _entries_WIRE_10_eff = _entries_T_83; // @[tlb.scala:60:79] assign _entries_T_84 = _entries_WIRE_11[3]; // @[tlb.scala:60:79] wire _entries_WIRE_10_paa = _entries_T_84; // @[tlb.scala:60:79] assign _entries_T_85 = _entries_WIRE_11[4]; // @[tlb.scala:60:79] wire _entries_WIRE_10_pal = _entries_T_85; // @[tlb.scala:60:79] assign _entries_T_86 = _entries_WIRE_11[5]; // @[tlb.scala:60:79] wire _entries_WIRE_10_pr = _entries_T_86; // @[tlb.scala:60:79] assign _entries_T_87 = _entries_WIRE_11[6]; // @[tlb.scala:60:79] wire _entries_WIRE_10_px = _entries_T_87; // @[tlb.scala:60:79] assign _entries_T_88 = _entries_WIRE_11[7]; // @[tlb.scala:60:79] wire _entries_WIRE_10_pw = _entries_T_88; // @[tlb.scala:60:79] assign _entries_T_89 = _entries_WIRE_11[8]; // @[tlb.scala:60:79] wire _entries_WIRE_10_sr = _entries_T_89; // @[tlb.scala:60:79] assign _entries_T_90 = _entries_WIRE_11[9]; // @[tlb.scala:60:79] wire _entries_WIRE_10_sx = _entries_T_90; // @[tlb.scala:60:79] assign _entries_T_91 = _entries_WIRE_11[10]; // @[tlb.scala:60:79] wire _entries_WIRE_10_sw = _entries_T_91; // @[tlb.scala:60:79] assign _entries_T_92 = _entries_WIRE_11[11]; // @[tlb.scala:60:79] wire _entries_WIRE_10_ae = _entries_T_92; // @[tlb.scala:60:79] assign _entries_T_93 = _entries_WIRE_11[12]; // @[tlb.scala:60:79] wire _entries_WIRE_10_g = _entries_T_93; // @[tlb.scala:60:79] assign _entries_T_94 = _entries_WIRE_11[13]; // @[tlb.scala:60:79] wire _entries_WIRE_10_u = _entries_T_94; // @[tlb.scala:60:79] assign _entries_T_95 = _entries_WIRE_11[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_10_ppn = _entries_T_95; // @[tlb.scala:60:79] wire [19:0] _entries_T_111; // @[tlb.scala:60:79] wire _entries_T_110; // @[tlb.scala:60:79] wire _entries_T_109; // @[tlb.scala:60:79] wire _entries_T_108; // @[tlb.scala:60:79] wire _entries_T_107; // @[tlb.scala:60:79] wire _entries_T_106; // @[tlb.scala:60:79] wire _entries_T_105; // @[tlb.scala:60:79] wire _entries_T_104; // @[tlb.scala:60:79] wire _entries_T_103; // @[tlb.scala:60:79] wire _entries_T_102; // @[tlb.scala:60:79] wire _entries_T_101; // @[tlb.scala:60:79] wire _entries_T_100; // @[tlb.scala:60:79] wire _entries_T_99; // @[tlb.scala:60:79] wire _entries_T_98; // @[tlb.scala:60:79] wire _entries_T_97; // @[tlb.scala:60:79] assign _entries_T_97 = _entries_WIRE_13[0]; // @[tlb.scala:60:79] wire _entries_WIRE_12_fragmented_superpage = _entries_T_97; // @[tlb.scala:60:79] assign _entries_T_98 = _entries_WIRE_13[1]; // @[tlb.scala:60:79] wire _entries_WIRE_12_c = _entries_T_98; // @[tlb.scala:60:79] assign _entries_T_99 = _entries_WIRE_13[2]; // @[tlb.scala:60:79] wire _entries_WIRE_12_eff = _entries_T_99; // @[tlb.scala:60:79] assign _entries_T_100 = _entries_WIRE_13[3]; // @[tlb.scala:60:79] wire _entries_WIRE_12_paa = _entries_T_100; // @[tlb.scala:60:79] assign _entries_T_101 = _entries_WIRE_13[4]; // @[tlb.scala:60:79] wire _entries_WIRE_12_pal = _entries_T_101; // @[tlb.scala:60:79] assign _entries_T_102 = _entries_WIRE_13[5]; // @[tlb.scala:60:79] wire _entries_WIRE_12_pr = _entries_T_102; // @[tlb.scala:60:79] assign _entries_T_103 = _entries_WIRE_13[6]; // @[tlb.scala:60:79] wire _entries_WIRE_12_px = _entries_T_103; // @[tlb.scala:60:79] assign _entries_T_104 = _entries_WIRE_13[7]; // @[tlb.scala:60:79] wire _entries_WIRE_12_pw = _entries_T_104; // @[tlb.scala:60:79] assign _entries_T_105 = _entries_WIRE_13[8]; // @[tlb.scala:60:79] wire _entries_WIRE_12_sr = _entries_T_105; // @[tlb.scala:60:79] assign _entries_T_106 = _entries_WIRE_13[9]; // @[tlb.scala:60:79] wire _entries_WIRE_12_sx = _entries_T_106; // @[tlb.scala:60:79] assign _entries_T_107 = _entries_WIRE_13[10]; // @[tlb.scala:60:79] wire _entries_WIRE_12_sw = _entries_T_107; // @[tlb.scala:60:79] assign _entries_T_108 = _entries_WIRE_13[11]; // @[tlb.scala:60:79] wire _entries_WIRE_12_ae = _entries_T_108; // @[tlb.scala:60:79] assign _entries_T_109 = _entries_WIRE_13[12]; // @[tlb.scala:60:79] wire _entries_WIRE_12_g = _entries_T_109; // @[tlb.scala:60:79] assign _entries_T_110 = _entries_WIRE_13[13]; // @[tlb.scala:60:79] wire _entries_WIRE_12_u = _entries_T_110; // @[tlb.scala:60:79] assign _entries_T_111 = _entries_WIRE_13[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_12_ppn = _entries_T_111; // @[tlb.scala:60:79] wire [19:0] _entries_T_127; // @[tlb.scala:60:79] wire _entries_T_126; // @[tlb.scala:60:79] wire _entries_T_125; // @[tlb.scala:60:79] wire _entries_T_124; // @[tlb.scala:60:79] wire _entries_T_123; // @[tlb.scala:60:79] wire _entries_T_122; // @[tlb.scala:60:79] wire _entries_T_121; // @[tlb.scala:60:79] wire _entries_T_120; // @[tlb.scala:60:79] wire _entries_T_119; // @[tlb.scala:60:79] wire _entries_T_118; // @[tlb.scala:60:79] wire _entries_T_117; // @[tlb.scala:60:79] wire _entries_T_116; // @[tlb.scala:60:79] wire _entries_T_115; // @[tlb.scala:60:79] wire _entries_T_114; // @[tlb.scala:60:79] wire _entries_T_113; // @[tlb.scala:60:79] assign _entries_T_113 = _entries_WIRE_15[0]; // @[tlb.scala:60:79] wire _entries_WIRE_14_fragmented_superpage = _entries_T_113; // @[tlb.scala:60:79] assign _entries_T_114 = _entries_WIRE_15[1]; // @[tlb.scala:60:79] wire _entries_WIRE_14_c = _entries_T_114; // @[tlb.scala:60:79] assign _entries_T_115 = _entries_WIRE_15[2]; // @[tlb.scala:60:79] wire _entries_WIRE_14_eff = _entries_T_115; // @[tlb.scala:60:79] assign _entries_T_116 = _entries_WIRE_15[3]; // @[tlb.scala:60:79] wire _entries_WIRE_14_paa = _entries_T_116; // @[tlb.scala:60:79] assign _entries_T_117 = _entries_WIRE_15[4]; // @[tlb.scala:60:79] wire _entries_WIRE_14_pal = _entries_T_117; // @[tlb.scala:60:79] assign _entries_T_118 = _entries_WIRE_15[5]; // @[tlb.scala:60:79] wire _entries_WIRE_14_pr = _entries_T_118; // @[tlb.scala:60:79] assign _entries_T_119 = _entries_WIRE_15[6]; // @[tlb.scala:60:79] wire _entries_WIRE_14_px = _entries_T_119; // @[tlb.scala:60:79] assign _entries_T_120 = _entries_WIRE_15[7]; // @[tlb.scala:60:79] wire _entries_WIRE_14_pw = _entries_T_120; // @[tlb.scala:60:79] assign _entries_T_121 = _entries_WIRE_15[8]; // @[tlb.scala:60:79] wire _entries_WIRE_14_sr = _entries_T_121; // @[tlb.scala:60:79] assign _entries_T_122 = _entries_WIRE_15[9]; // @[tlb.scala:60:79] wire _entries_WIRE_14_sx = _entries_T_122; // @[tlb.scala:60:79] assign _entries_T_123 = _entries_WIRE_15[10]; // @[tlb.scala:60:79] wire _entries_WIRE_14_sw = _entries_T_123; // @[tlb.scala:60:79] assign _entries_T_124 = _entries_WIRE_15[11]; // @[tlb.scala:60:79] wire _entries_WIRE_14_ae = _entries_T_124; // @[tlb.scala:60:79] assign _entries_T_125 = _entries_WIRE_15[12]; // @[tlb.scala:60:79] wire _entries_WIRE_14_g = _entries_T_125; // @[tlb.scala:60:79] assign _entries_T_126 = _entries_WIRE_15[13]; // @[tlb.scala:60:79] wire _entries_WIRE_14_u = _entries_T_126; // @[tlb.scala:60:79] assign _entries_T_127 = _entries_WIRE_15[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_14_ppn = _entries_T_127; // @[tlb.scala:60:79] wire [19:0] _entries_T_142; // @[tlb.scala:60:79] wire _entries_T_141; // @[tlb.scala:60:79] wire _entries_T_140; // @[tlb.scala:60:79] wire _entries_T_139; // @[tlb.scala:60:79] wire _entries_T_138; // @[tlb.scala:60:79] wire _entries_T_137; // @[tlb.scala:60:79] wire _entries_T_136; // @[tlb.scala:60:79] wire _entries_T_135; // @[tlb.scala:60:79] wire _entries_T_134; // @[tlb.scala:60:79] wire _entries_T_133; // @[tlb.scala:60:79] wire _entries_T_132; // @[tlb.scala:60:79] wire _entries_T_131; // @[tlb.scala:60:79] wire _entries_T_130; // @[tlb.scala:60:79] wire _entries_T_129; // @[tlb.scala:60:79] wire _entries_T_128; // @[tlb.scala:60:79] assign _entries_T_128 = _entries_WIRE_17[0]; // @[tlb.scala:60:79] wire _entries_WIRE_16_fragmented_superpage = _entries_T_128; // @[tlb.scala:60:79] assign _entries_T_129 = _entries_WIRE_17[1]; // @[tlb.scala:60:79] wire _entries_WIRE_16_c = _entries_T_129; // @[tlb.scala:60:79] assign _entries_T_130 = _entries_WIRE_17[2]; // @[tlb.scala:60:79] wire _entries_WIRE_16_eff = _entries_T_130; // @[tlb.scala:60:79] assign _entries_T_131 = _entries_WIRE_17[3]; // @[tlb.scala:60:79] wire _entries_WIRE_16_paa = _entries_T_131; // @[tlb.scala:60:79] assign _entries_T_132 = _entries_WIRE_17[4]; // @[tlb.scala:60:79] wire _entries_WIRE_16_pal = _entries_T_132; // @[tlb.scala:60:79] assign _entries_T_133 = _entries_WIRE_17[5]; // @[tlb.scala:60:79] wire _entries_WIRE_16_pr = _entries_T_133; // @[tlb.scala:60:79] assign _entries_T_134 = _entries_WIRE_17[6]; // @[tlb.scala:60:79] wire _entries_WIRE_16_px = _entries_T_134; // @[tlb.scala:60:79] assign _entries_T_135 = _entries_WIRE_17[7]; // @[tlb.scala:60:79] wire _entries_WIRE_16_pw = _entries_T_135; // @[tlb.scala:60:79] assign _entries_T_136 = _entries_WIRE_17[8]; // @[tlb.scala:60:79] wire _entries_WIRE_16_sr = _entries_T_136; // @[tlb.scala:60:79] assign _entries_T_137 = _entries_WIRE_17[9]; // @[tlb.scala:60:79] wire _entries_WIRE_16_sx = _entries_T_137; // @[tlb.scala:60:79] assign _entries_T_138 = _entries_WIRE_17[10]; // @[tlb.scala:60:79] wire _entries_WIRE_16_sw = _entries_T_138; // @[tlb.scala:60:79] assign _entries_T_139 = _entries_WIRE_17[11]; // @[tlb.scala:60:79] wire _entries_WIRE_16_ae = _entries_T_139; // @[tlb.scala:60:79] assign _entries_T_140 = _entries_WIRE_17[12]; // @[tlb.scala:60:79] wire _entries_WIRE_16_g = _entries_T_140; // @[tlb.scala:60:79] assign _entries_T_141 = _entries_WIRE_17[13]; // @[tlb.scala:60:79] wire _entries_WIRE_16_u = _entries_T_141; // @[tlb.scala:60:79] assign _entries_T_142 = _entries_WIRE_17[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_16_ppn = _entries_T_142; // @[tlb.scala:60:79] wire [19:0] _entries_T_157; // @[tlb.scala:60:79] wire _entries_T_156; // @[tlb.scala:60:79] wire _entries_T_155; // @[tlb.scala:60:79] wire _entries_T_154; // @[tlb.scala:60:79] wire _entries_T_153; // @[tlb.scala:60:79] wire _entries_T_152; // @[tlb.scala:60:79] wire _entries_T_151; // @[tlb.scala:60:79] wire _entries_T_150; // @[tlb.scala:60:79] wire _entries_T_149; // @[tlb.scala:60:79] wire _entries_T_148; // @[tlb.scala:60:79] wire _entries_T_147; // @[tlb.scala:60:79] wire _entries_T_146; // @[tlb.scala:60:79] wire _entries_T_145; // @[tlb.scala:60:79] wire _entries_T_144; // @[tlb.scala:60:79] wire _entries_T_143; // @[tlb.scala:60:79] assign _entries_T_143 = _entries_WIRE_19[0]; // @[tlb.scala:60:79] wire _entries_WIRE_18_fragmented_superpage = _entries_T_143; // @[tlb.scala:60:79] assign _entries_T_144 = _entries_WIRE_19[1]; // @[tlb.scala:60:79] wire _entries_WIRE_18_c = _entries_T_144; // @[tlb.scala:60:79] assign _entries_T_145 = _entries_WIRE_19[2]; // @[tlb.scala:60:79] wire _entries_WIRE_18_eff = _entries_T_145; // @[tlb.scala:60:79] assign _entries_T_146 = _entries_WIRE_19[3]; // @[tlb.scala:60:79] wire _entries_WIRE_18_paa = _entries_T_146; // @[tlb.scala:60:79] assign _entries_T_147 = _entries_WIRE_19[4]; // @[tlb.scala:60:79] wire _entries_WIRE_18_pal = _entries_T_147; // @[tlb.scala:60:79] assign _entries_T_148 = _entries_WIRE_19[5]; // @[tlb.scala:60:79] wire _entries_WIRE_18_pr = _entries_T_148; // @[tlb.scala:60:79] assign _entries_T_149 = _entries_WIRE_19[6]; // @[tlb.scala:60:79] wire _entries_WIRE_18_px = _entries_T_149; // @[tlb.scala:60:79] assign _entries_T_150 = _entries_WIRE_19[7]; // @[tlb.scala:60:79] wire _entries_WIRE_18_pw = _entries_T_150; // @[tlb.scala:60:79] assign _entries_T_151 = _entries_WIRE_19[8]; // @[tlb.scala:60:79] wire _entries_WIRE_18_sr = _entries_T_151; // @[tlb.scala:60:79] assign _entries_T_152 = _entries_WIRE_19[9]; // @[tlb.scala:60:79] wire _entries_WIRE_18_sx = _entries_T_152; // @[tlb.scala:60:79] assign _entries_T_153 = _entries_WIRE_19[10]; // @[tlb.scala:60:79] wire _entries_WIRE_18_sw = _entries_T_153; // @[tlb.scala:60:79] assign _entries_T_154 = _entries_WIRE_19[11]; // @[tlb.scala:60:79] wire _entries_WIRE_18_ae = _entries_T_154; // @[tlb.scala:60:79] assign _entries_T_155 = _entries_WIRE_19[12]; // @[tlb.scala:60:79] wire _entries_WIRE_18_g = _entries_T_155; // @[tlb.scala:60:79] assign _entries_T_156 = _entries_WIRE_19[13]; // @[tlb.scala:60:79] wire _entries_WIRE_18_u = _entries_T_156; // @[tlb.scala:60:79] assign _entries_T_157 = _entries_WIRE_19[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_18_ppn = _entries_T_157; // @[tlb.scala:60:79] wire [19:0] _entries_T_172; // @[tlb.scala:60:79] wire _entries_T_171; // @[tlb.scala:60:79] wire _entries_T_170; // @[tlb.scala:60:79] wire _entries_T_169; // @[tlb.scala:60:79] wire _entries_T_168; // @[tlb.scala:60:79] wire _entries_T_167; // @[tlb.scala:60:79] wire _entries_T_166; // @[tlb.scala:60:79] wire _entries_T_165; // @[tlb.scala:60:79] wire _entries_T_164; // @[tlb.scala:60:79] wire _entries_T_163; // @[tlb.scala:60:79] wire _entries_T_162; // @[tlb.scala:60:79] wire _entries_T_161; // @[tlb.scala:60:79] wire _entries_T_160; // @[tlb.scala:60:79] wire _entries_T_159; // @[tlb.scala:60:79] wire _entries_T_158; // @[tlb.scala:60:79] assign _entries_T_158 = _entries_WIRE_21[0]; // @[tlb.scala:60:79] wire _entries_WIRE_20_fragmented_superpage = _entries_T_158; // @[tlb.scala:60:79] assign _entries_T_159 = _entries_WIRE_21[1]; // @[tlb.scala:60:79] wire _entries_WIRE_20_c = _entries_T_159; // @[tlb.scala:60:79] assign _entries_T_160 = _entries_WIRE_21[2]; // @[tlb.scala:60:79] wire _entries_WIRE_20_eff = _entries_T_160; // @[tlb.scala:60:79] assign _entries_T_161 = _entries_WIRE_21[3]; // @[tlb.scala:60:79] wire _entries_WIRE_20_paa = _entries_T_161; // @[tlb.scala:60:79] assign _entries_T_162 = _entries_WIRE_21[4]; // @[tlb.scala:60:79] wire _entries_WIRE_20_pal = _entries_T_162; // @[tlb.scala:60:79] assign _entries_T_163 = _entries_WIRE_21[5]; // @[tlb.scala:60:79] wire _entries_WIRE_20_pr = _entries_T_163; // @[tlb.scala:60:79] assign _entries_T_164 = _entries_WIRE_21[6]; // @[tlb.scala:60:79] wire _entries_WIRE_20_px = _entries_T_164; // @[tlb.scala:60:79] assign _entries_T_165 = _entries_WIRE_21[7]; // @[tlb.scala:60:79] wire _entries_WIRE_20_pw = _entries_T_165; // @[tlb.scala:60:79] assign _entries_T_166 = _entries_WIRE_21[8]; // @[tlb.scala:60:79] wire _entries_WIRE_20_sr = _entries_T_166; // @[tlb.scala:60:79] assign _entries_T_167 = _entries_WIRE_21[9]; // @[tlb.scala:60:79] wire _entries_WIRE_20_sx = _entries_T_167; // @[tlb.scala:60:79] assign _entries_T_168 = _entries_WIRE_21[10]; // @[tlb.scala:60:79] wire _entries_WIRE_20_sw = _entries_T_168; // @[tlb.scala:60:79] assign _entries_T_169 = _entries_WIRE_21[11]; // @[tlb.scala:60:79] wire _entries_WIRE_20_ae = _entries_T_169; // @[tlb.scala:60:79] assign _entries_T_170 = _entries_WIRE_21[12]; // @[tlb.scala:60:79] wire _entries_WIRE_20_g = _entries_T_170; // @[tlb.scala:60:79] assign _entries_T_171 = _entries_WIRE_21[13]; // @[tlb.scala:60:79] wire _entries_WIRE_20_u = _entries_T_171; // @[tlb.scala:60:79] assign _entries_T_172 = _entries_WIRE_21[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_20_ppn = _entries_T_172; // @[tlb.scala:60:79] wire [19:0] _entries_T_187; // @[tlb.scala:60:79] wire _entries_T_186; // @[tlb.scala:60:79] wire _entries_T_185; // @[tlb.scala:60:79] wire _entries_T_184; // @[tlb.scala:60:79] wire _entries_T_183; // @[tlb.scala:60:79] wire _entries_T_182; // @[tlb.scala:60:79] wire _entries_T_181; // @[tlb.scala:60:79] wire _entries_T_180; // @[tlb.scala:60:79] wire _entries_T_179; // @[tlb.scala:60:79] wire _entries_T_178; // @[tlb.scala:60:79] wire _entries_T_177; // @[tlb.scala:60:79] wire _entries_T_176; // @[tlb.scala:60:79] wire _entries_T_175; // @[tlb.scala:60:79] wire _entries_T_174; // @[tlb.scala:60:79] wire _entries_T_173; // @[tlb.scala:60:79] assign _entries_T_173 = _entries_WIRE_23[0]; // @[tlb.scala:60:79] wire _entries_WIRE_22_fragmented_superpage = _entries_T_173; // @[tlb.scala:60:79] assign _entries_T_174 = _entries_WIRE_23[1]; // @[tlb.scala:60:79] wire _entries_WIRE_22_c = _entries_T_174; // @[tlb.scala:60:79] assign _entries_T_175 = _entries_WIRE_23[2]; // @[tlb.scala:60:79] wire _entries_WIRE_22_eff = _entries_T_175; // @[tlb.scala:60:79] assign _entries_T_176 = _entries_WIRE_23[3]; // @[tlb.scala:60:79] wire _entries_WIRE_22_paa = _entries_T_176; // @[tlb.scala:60:79] assign _entries_T_177 = _entries_WIRE_23[4]; // @[tlb.scala:60:79] wire _entries_WIRE_22_pal = _entries_T_177; // @[tlb.scala:60:79] assign _entries_T_178 = _entries_WIRE_23[5]; // @[tlb.scala:60:79] wire _entries_WIRE_22_pr = _entries_T_178; // @[tlb.scala:60:79] assign _entries_T_179 = _entries_WIRE_23[6]; // @[tlb.scala:60:79] wire _entries_WIRE_22_px = _entries_T_179; // @[tlb.scala:60:79] assign _entries_T_180 = _entries_WIRE_23[7]; // @[tlb.scala:60:79] wire _entries_WIRE_22_pw = _entries_T_180; // @[tlb.scala:60:79] assign _entries_T_181 = _entries_WIRE_23[8]; // @[tlb.scala:60:79] wire _entries_WIRE_22_sr = _entries_T_181; // @[tlb.scala:60:79] assign _entries_T_182 = _entries_WIRE_23[9]; // @[tlb.scala:60:79] wire _entries_WIRE_22_sx = _entries_T_182; // @[tlb.scala:60:79] assign _entries_T_183 = _entries_WIRE_23[10]; // @[tlb.scala:60:79] wire _entries_WIRE_22_sw = _entries_T_183; // @[tlb.scala:60:79] assign _entries_T_184 = _entries_WIRE_23[11]; // @[tlb.scala:60:79] wire _entries_WIRE_22_ae = _entries_T_184; // @[tlb.scala:60:79] assign _entries_T_185 = _entries_WIRE_23[12]; // @[tlb.scala:60:79] wire _entries_WIRE_22_g = _entries_T_185; // @[tlb.scala:60:79] assign _entries_T_186 = _entries_WIRE_23[13]; // @[tlb.scala:60:79] wire _entries_WIRE_22_u = _entries_T_186; // @[tlb.scala:60:79] assign _entries_T_187 = _entries_WIRE_23[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_22_ppn = _entries_T_187; // @[tlb.scala:60:79] wire [19:0] _entries_T_202; // @[tlb.scala:60:79] wire _entries_T_201; // @[tlb.scala:60:79] wire _entries_T_200; // @[tlb.scala:60:79] wire _entries_T_199; // @[tlb.scala:60:79] wire _entries_T_198; // @[tlb.scala:60:79] wire _entries_T_197; // @[tlb.scala:60:79] wire _entries_T_196; // @[tlb.scala:60:79] wire _entries_T_195; // @[tlb.scala:60:79] wire _entries_T_194; // @[tlb.scala:60:79] wire _entries_T_193; // @[tlb.scala:60:79] wire _entries_T_192; // @[tlb.scala:60:79] wire _entries_T_191; // @[tlb.scala:60:79] wire _entries_T_190; // @[tlb.scala:60:79] wire _entries_T_189; // @[tlb.scala:60:79] wire _entries_T_188; // @[tlb.scala:60:79] assign _entries_T_188 = _entries_WIRE_25[0]; // @[tlb.scala:60:79] wire _entries_WIRE_24_fragmented_superpage = _entries_T_188; // @[tlb.scala:60:79] assign _entries_T_189 = _entries_WIRE_25[1]; // @[tlb.scala:60:79] wire _entries_WIRE_24_c = _entries_T_189; // @[tlb.scala:60:79] assign _entries_T_190 = _entries_WIRE_25[2]; // @[tlb.scala:60:79] wire _entries_WIRE_24_eff = _entries_T_190; // @[tlb.scala:60:79] assign _entries_T_191 = _entries_WIRE_25[3]; // @[tlb.scala:60:79] wire _entries_WIRE_24_paa = _entries_T_191; // @[tlb.scala:60:79] assign _entries_T_192 = _entries_WIRE_25[4]; // @[tlb.scala:60:79] wire _entries_WIRE_24_pal = _entries_T_192; // @[tlb.scala:60:79] assign _entries_T_193 = _entries_WIRE_25[5]; // @[tlb.scala:60:79] wire _entries_WIRE_24_pr = _entries_T_193; // @[tlb.scala:60:79] assign _entries_T_194 = _entries_WIRE_25[6]; // @[tlb.scala:60:79] wire _entries_WIRE_24_px = _entries_T_194; // @[tlb.scala:60:79] assign _entries_T_195 = _entries_WIRE_25[7]; // @[tlb.scala:60:79] wire _entries_WIRE_24_pw = _entries_T_195; // @[tlb.scala:60:79] assign _entries_T_196 = _entries_WIRE_25[8]; // @[tlb.scala:60:79] wire _entries_WIRE_24_sr = _entries_T_196; // @[tlb.scala:60:79] assign _entries_T_197 = _entries_WIRE_25[9]; // @[tlb.scala:60:79] wire _entries_WIRE_24_sx = _entries_T_197; // @[tlb.scala:60:79] assign _entries_T_198 = _entries_WIRE_25[10]; // @[tlb.scala:60:79] wire _entries_WIRE_24_sw = _entries_T_198; // @[tlb.scala:60:79] assign _entries_T_199 = _entries_WIRE_25[11]; // @[tlb.scala:60:79] wire _entries_WIRE_24_ae = _entries_T_199; // @[tlb.scala:60:79] assign _entries_T_200 = _entries_WIRE_25[12]; // @[tlb.scala:60:79] wire _entries_WIRE_24_g = _entries_T_200; // @[tlb.scala:60:79] assign _entries_T_201 = _entries_WIRE_25[13]; // @[tlb.scala:60:79] wire _entries_WIRE_24_u = _entries_T_201; // @[tlb.scala:60:79] assign _entries_T_202 = _entries_WIRE_25[33:14]; // @[tlb.scala:60:79] wire [19:0] _entries_WIRE_24_ppn = _entries_T_202; // @[tlb.scala:60:79] wire [19:0] entries_0_0_ppn = _entries_WIRE_26_0_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_0_u = _entries_WIRE_26_0_u; // @[tlb.scala:121:49, :213:38] wire entries_0_0_g = _entries_WIRE_26_0_g; // @[tlb.scala:121:49, :213:38] wire entries_0_0_ae = _entries_WIRE_26_0_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_0_sw = _entries_WIRE_26_0_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_0_sx = _entries_WIRE_26_0_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_0_sr = _entries_WIRE_26_0_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_0_pw = _entries_WIRE_26_0_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_0_px = _entries_WIRE_26_0_px; // @[tlb.scala:121:49, :213:38] wire entries_0_0_pr = _entries_WIRE_26_0_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_0_pal = _entries_WIRE_26_0_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_0_paa = _entries_WIRE_26_0_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_0_eff = _entries_WIRE_26_0_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_0_c = _entries_WIRE_26_0_c; // @[tlb.scala:121:49, :213:38] wire entries_0_0_fragmented_superpage = _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_1_ppn = _entries_WIRE_26_1_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_1_u = _entries_WIRE_26_1_u; // @[tlb.scala:121:49, :213:38] wire entries_0_1_g = _entries_WIRE_26_1_g; // @[tlb.scala:121:49, :213:38] wire entries_0_1_ae = _entries_WIRE_26_1_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_1_sw = _entries_WIRE_26_1_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_1_sx = _entries_WIRE_26_1_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_1_sr = _entries_WIRE_26_1_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_1_pw = _entries_WIRE_26_1_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_1_px = _entries_WIRE_26_1_px; // @[tlb.scala:121:49, :213:38] wire entries_0_1_pr = _entries_WIRE_26_1_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_1_pal = _entries_WIRE_26_1_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_1_paa = _entries_WIRE_26_1_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_1_eff = _entries_WIRE_26_1_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_1_c = _entries_WIRE_26_1_c; // @[tlb.scala:121:49, :213:38] wire entries_0_1_fragmented_superpage = _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_2_ppn = _entries_WIRE_26_2_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_2_u = _entries_WIRE_26_2_u; // @[tlb.scala:121:49, :213:38] wire entries_0_2_g = _entries_WIRE_26_2_g; // @[tlb.scala:121:49, :213:38] wire entries_0_2_ae = _entries_WIRE_26_2_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_2_sw = _entries_WIRE_26_2_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_2_sx = _entries_WIRE_26_2_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_2_sr = _entries_WIRE_26_2_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_2_pw = _entries_WIRE_26_2_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_2_px = _entries_WIRE_26_2_px; // @[tlb.scala:121:49, :213:38] wire entries_0_2_pr = _entries_WIRE_26_2_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_2_pal = _entries_WIRE_26_2_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_2_paa = _entries_WIRE_26_2_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_2_eff = _entries_WIRE_26_2_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_2_c = _entries_WIRE_26_2_c; // @[tlb.scala:121:49, :213:38] wire entries_0_2_fragmented_superpage = _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_3_ppn = _entries_WIRE_26_3_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_3_u = _entries_WIRE_26_3_u; // @[tlb.scala:121:49, :213:38] wire entries_0_3_g = _entries_WIRE_26_3_g; // @[tlb.scala:121:49, :213:38] wire entries_0_3_ae = _entries_WIRE_26_3_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_3_sw = _entries_WIRE_26_3_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_3_sx = _entries_WIRE_26_3_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_3_sr = _entries_WIRE_26_3_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_3_pw = _entries_WIRE_26_3_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_3_px = _entries_WIRE_26_3_px; // @[tlb.scala:121:49, :213:38] wire entries_0_3_pr = _entries_WIRE_26_3_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_3_pal = _entries_WIRE_26_3_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_3_paa = _entries_WIRE_26_3_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_3_eff = _entries_WIRE_26_3_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_3_c = _entries_WIRE_26_3_c; // @[tlb.scala:121:49, :213:38] wire entries_0_3_fragmented_superpage = _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_4_ppn = _entries_WIRE_26_4_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_4_u = _entries_WIRE_26_4_u; // @[tlb.scala:121:49, :213:38] wire entries_0_4_g = _entries_WIRE_26_4_g; // @[tlb.scala:121:49, :213:38] wire entries_0_4_ae = _entries_WIRE_26_4_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_4_sw = _entries_WIRE_26_4_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_4_sx = _entries_WIRE_26_4_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_4_sr = _entries_WIRE_26_4_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_4_pw = _entries_WIRE_26_4_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_4_px = _entries_WIRE_26_4_px; // @[tlb.scala:121:49, :213:38] wire entries_0_4_pr = _entries_WIRE_26_4_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_4_pal = _entries_WIRE_26_4_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_4_paa = _entries_WIRE_26_4_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_4_eff = _entries_WIRE_26_4_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_4_c = _entries_WIRE_26_4_c; // @[tlb.scala:121:49, :213:38] wire entries_0_4_fragmented_superpage = _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_5_ppn = _entries_WIRE_26_5_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_5_u = _entries_WIRE_26_5_u; // @[tlb.scala:121:49, :213:38] wire entries_0_5_g = _entries_WIRE_26_5_g; // @[tlb.scala:121:49, :213:38] wire entries_0_5_ae = _entries_WIRE_26_5_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_5_sw = _entries_WIRE_26_5_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_5_sx = _entries_WIRE_26_5_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_5_sr = _entries_WIRE_26_5_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_5_pw = _entries_WIRE_26_5_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_5_px = _entries_WIRE_26_5_px; // @[tlb.scala:121:49, :213:38] wire entries_0_5_pr = _entries_WIRE_26_5_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_5_pal = _entries_WIRE_26_5_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_5_paa = _entries_WIRE_26_5_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_5_eff = _entries_WIRE_26_5_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_5_c = _entries_WIRE_26_5_c; // @[tlb.scala:121:49, :213:38] wire entries_0_5_fragmented_superpage = _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_6_ppn = _entries_WIRE_26_6_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_6_u = _entries_WIRE_26_6_u; // @[tlb.scala:121:49, :213:38] wire entries_0_6_g = _entries_WIRE_26_6_g; // @[tlb.scala:121:49, :213:38] wire entries_0_6_ae = _entries_WIRE_26_6_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_6_sw = _entries_WIRE_26_6_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_6_sx = _entries_WIRE_26_6_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_6_sr = _entries_WIRE_26_6_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_6_pw = _entries_WIRE_26_6_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_6_px = _entries_WIRE_26_6_px; // @[tlb.scala:121:49, :213:38] wire entries_0_6_pr = _entries_WIRE_26_6_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_6_pal = _entries_WIRE_26_6_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_6_paa = _entries_WIRE_26_6_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_6_eff = _entries_WIRE_26_6_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_6_c = _entries_WIRE_26_6_c; // @[tlb.scala:121:49, :213:38] wire entries_0_6_fragmented_superpage = _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_7_ppn = _entries_WIRE_26_7_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_7_u = _entries_WIRE_26_7_u; // @[tlb.scala:121:49, :213:38] wire entries_0_7_g = _entries_WIRE_26_7_g; // @[tlb.scala:121:49, :213:38] wire entries_0_7_ae = _entries_WIRE_26_7_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_7_sw = _entries_WIRE_26_7_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_7_sx = _entries_WIRE_26_7_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_7_sr = _entries_WIRE_26_7_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_7_pw = _entries_WIRE_26_7_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_7_px = _entries_WIRE_26_7_px; // @[tlb.scala:121:49, :213:38] wire entries_0_7_pr = _entries_WIRE_26_7_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_7_pal = _entries_WIRE_26_7_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_7_paa = _entries_WIRE_26_7_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_7_eff = _entries_WIRE_26_7_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_7_c = _entries_WIRE_26_7_c; // @[tlb.scala:121:49, :213:38] wire entries_0_7_fragmented_superpage = _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_8_ppn = _entries_WIRE_26_8_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_8_u = _entries_WIRE_26_8_u; // @[tlb.scala:121:49, :213:38] wire entries_0_8_g = _entries_WIRE_26_8_g; // @[tlb.scala:121:49, :213:38] wire entries_0_8_ae = _entries_WIRE_26_8_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_8_sw = _entries_WIRE_26_8_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_8_sx = _entries_WIRE_26_8_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_8_sr = _entries_WIRE_26_8_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_8_pw = _entries_WIRE_26_8_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_8_px = _entries_WIRE_26_8_px; // @[tlb.scala:121:49, :213:38] wire entries_0_8_pr = _entries_WIRE_26_8_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_8_pal = _entries_WIRE_26_8_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_8_paa = _entries_WIRE_26_8_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_8_eff = _entries_WIRE_26_8_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_8_c = _entries_WIRE_26_8_c; // @[tlb.scala:121:49, :213:38] wire entries_0_8_fragmented_superpage = _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_9_ppn = _entries_WIRE_26_9_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_9_u = _entries_WIRE_26_9_u; // @[tlb.scala:121:49, :213:38] wire entries_0_9_g = _entries_WIRE_26_9_g; // @[tlb.scala:121:49, :213:38] wire entries_0_9_ae = _entries_WIRE_26_9_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_9_sw = _entries_WIRE_26_9_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_9_sx = _entries_WIRE_26_9_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_9_sr = _entries_WIRE_26_9_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_9_pw = _entries_WIRE_26_9_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_9_px = _entries_WIRE_26_9_px; // @[tlb.scala:121:49, :213:38] wire entries_0_9_pr = _entries_WIRE_26_9_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_9_pal = _entries_WIRE_26_9_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_9_paa = _entries_WIRE_26_9_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_9_eff = _entries_WIRE_26_9_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_9_c = _entries_WIRE_26_9_c; // @[tlb.scala:121:49, :213:38] wire entries_0_9_fragmented_superpage = _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_10_ppn = _entries_WIRE_26_10_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_10_u = _entries_WIRE_26_10_u; // @[tlb.scala:121:49, :213:38] wire entries_0_10_g = _entries_WIRE_26_10_g; // @[tlb.scala:121:49, :213:38] wire entries_0_10_ae = _entries_WIRE_26_10_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_10_sw = _entries_WIRE_26_10_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_10_sx = _entries_WIRE_26_10_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_10_sr = _entries_WIRE_26_10_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_10_pw = _entries_WIRE_26_10_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_10_px = _entries_WIRE_26_10_px; // @[tlb.scala:121:49, :213:38] wire entries_0_10_pr = _entries_WIRE_26_10_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_10_pal = _entries_WIRE_26_10_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_10_paa = _entries_WIRE_26_10_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_10_eff = _entries_WIRE_26_10_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_10_c = _entries_WIRE_26_10_c; // @[tlb.scala:121:49, :213:38] wire entries_0_10_fragmented_superpage = _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_11_ppn = _entries_WIRE_26_11_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_11_u = _entries_WIRE_26_11_u; // @[tlb.scala:121:49, :213:38] wire entries_0_11_g = _entries_WIRE_26_11_g; // @[tlb.scala:121:49, :213:38] wire entries_0_11_ae = _entries_WIRE_26_11_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_11_sw = _entries_WIRE_26_11_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_11_sx = _entries_WIRE_26_11_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_11_sr = _entries_WIRE_26_11_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_11_pw = _entries_WIRE_26_11_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_11_px = _entries_WIRE_26_11_px; // @[tlb.scala:121:49, :213:38] wire entries_0_11_pr = _entries_WIRE_26_11_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_11_pal = _entries_WIRE_26_11_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_11_paa = _entries_WIRE_26_11_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_11_eff = _entries_WIRE_26_11_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_11_c = _entries_WIRE_26_11_c; // @[tlb.scala:121:49, :213:38] wire entries_0_11_fragmented_superpage = _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] entries_0_12_ppn = _entries_WIRE_26_12_ppn; // @[tlb.scala:121:49, :213:38] wire entries_0_12_u = _entries_WIRE_26_12_u; // @[tlb.scala:121:49, :213:38] wire entries_0_12_g = _entries_WIRE_26_12_g; // @[tlb.scala:121:49, :213:38] wire entries_0_12_ae = _entries_WIRE_26_12_ae; // @[tlb.scala:121:49, :213:38] wire entries_0_12_sw = _entries_WIRE_26_12_sw; // @[tlb.scala:121:49, :213:38] wire entries_0_12_sx = _entries_WIRE_26_12_sx; // @[tlb.scala:121:49, :213:38] wire entries_0_12_sr = _entries_WIRE_26_12_sr; // @[tlb.scala:121:49, :213:38] wire entries_0_12_pw = _entries_WIRE_26_12_pw; // @[tlb.scala:121:49, :213:38] wire entries_0_12_px = _entries_WIRE_26_12_px; // @[tlb.scala:121:49, :213:38] wire entries_0_12_pr = _entries_WIRE_26_12_pr; // @[tlb.scala:121:49, :213:38] wire entries_0_12_pal = _entries_WIRE_26_12_pal; // @[tlb.scala:121:49, :213:38] wire entries_0_12_paa = _entries_WIRE_26_12_paa; // @[tlb.scala:121:49, :213:38] wire entries_0_12_eff = _entries_WIRE_26_12_eff; // @[tlb.scala:121:49, :213:38] wire entries_0_12_c = _entries_WIRE_26_12_c; // @[tlb.scala:121:49, :213:38] wire entries_0_12_fragmented_superpage = _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:121:49, :213:38] wire [19:0] _normal_entries_T_15; // @[tlb.scala:60:79] wire _normal_entries_T_14; // @[tlb.scala:60:79] wire _normal_entries_T_13; // @[tlb.scala:60:79] wire _normal_entries_T_12; // @[tlb.scala:60:79] wire _normal_entries_T_11; // @[tlb.scala:60:79] wire _normal_entries_T_10; // @[tlb.scala:60:79] wire _normal_entries_T_9; // @[tlb.scala:60:79] wire _normal_entries_T_8; // @[tlb.scala:60:79] wire _normal_entries_T_7; // @[tlb.scala:60:79] wire _normal_entries_T_6; // @[tlb.scala:60:79] wire _normal_entries_T_5; // @[tlb.scala:60:79] wire _normal_entries_T_4; // @[tlb.scala:60:79] wire _normal_entries_T_3; // @[tlb.scala:60:79] wire _normal_entries_T_2; // @[tlb.scala:60:79] wire _normal_entries_T_1; // @[tlb.scala:60:79] assign _normal_entries_T_1 = _normal_entries_WIRE_1[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_fragmented_superpage = _normal_entries_T_1; // @[tlb.scala:60:79] assign _normal_entries_T_2 = _normal_entries_WIRE_1[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_c = _normal_entries_T_2; // @[tlb.scala:60:79] assign _normal_entries_T_3 = _normal_entries_WIRE_1[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_eff = _normal_entries_T_3; // @[tlb.scala:60:79] assign _normal_entries_T_4 = _normal_entries_WIRE_1[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_paa = _normal_entries_T_4; // @[tlb.scala:60:79] assign _normal_entries_T_5 = _normal_entries_WIRE_1[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_pal = _normal_entries_T_5; // @[tlb.scala:60:79] assign _normal_entries_T_6 = _normal_entries_WIRE_1[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_pr = _normal_entries_T_6; // @[tlb.scala:60:79] assign _normal_entries_T_7 = _normal_entries_WIRE_1[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_px = _normal_entries_T_7; // @[tlb.scala:60:79] assign _normal_entries_T_8 = _normal_entries_WIRE_1[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_pw = _normal_entries_T_8; // @[tlb.scala:60:79] assign _normal_entries_T_9 = _normal_entries_WIRE_1[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_sr = _normal_entries_T_9; // @[tlb.scala:60:79] assign _normal_entries_T_10 = _normal_entries_WIRE_1[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_sx = _normal_entries_T_10; // @[tlb.scala:60:79] assign _normal_entries_T_11 = _normal_entries_WIRE_1[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_sw = _normal_entries_T_11; // @[tlb.scala:60:79] assign _normal_entries_T_12 = _normal_entries_WIRE_1[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_ae = _normal_entries_T_12; // @[tlb.scala:60:79] assign _normal_entries_T_13 = _normal_entries_WIRE_1[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_g = _normal_entries_T_13; // @[tlb.scala:60:79] assign _normal_entries_T_14 = _normal_entries_WIRE_1[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_u = _normal_entries_T_14; // @[tlb.scala:60:79] assign _normal_entries_T_15 = _normal_entries_WIRE_1[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_ppn = _normal_entries_T_15; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_31; // @[tlb.scala:60:79] wire _normal_entries_T_30; // @[tlb.scala:60:79] wire _normal_entries_T_29; // @[tlb.scala:60:79] wire _normal_entries_T_28; // @[tlb.scala:60:79] wire _normal_entries_T_27; // @[tlb.scala:60:79] wire _normal_entries_T_26; // @[tlb.scala:60:79] wire _normal_entries_T_25; // @[tlb.scala:60:79] wire _normal_entries_T_24; // @[tlb.scala:60:79] wire _normal_entries_T_23; // @[tlb.scala:60:79] wire _normal_entries_T_22; // @[tlb.scala:60:79] wire _normal_entries_T_21; // @[tlb.scala:60:79] wire _normal_entries_T_20; // @[tlb.scala:60:79] wire _normal_entries_T_19; // @[tlb.scala:60:79] wire _normal_entries_T_18; // @[tlb.scala:60:79] wire _normal_entries_T_17; // @[tlb.scala:60:79] assign _normal_entries_T_17 = _normal_entries_WIRE_3[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_fragmented_superpage = _normal_entries_T_17; // @[tlb.scala:60:79] assign _normal_entries_T_18 = _normal_entries_WIRE_3[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_c = _normal_entries_T_18; // @[tlb.scala:60:79] assign _normal_entries_T_19 = _normal_entries_WIRE_3[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_eff = _normal_entries_T_19; // @[tlb.scala:60:79] assign _normal_entries_T_20 = _normal_entries_WIRE_3[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_paa = _normal_entries_T_20; // @[tlb.scala:60:79] assign _normal_entries_T_21 = _normal_entries_WIRE_3[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_pal = _normal_entries_T_21; // @[tlb.scala:60:79] assign _normal_entries_T_22 = _normal_entries_WIRE_3[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_pr = _normal_entries_T_22; // @[tlb.scala:60:79] assign _normal_entries_T_23 = _normal_entries_WIRE_3[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_px = _normal_entries_T_23; // @[tlb.scala:60:79] assign _normal_entries_T_24 = _normal_entries_WIRE_3[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_pw = _normal_entries_T_24; // @[tlb.scala:60:79] assign _normal_entries_T_25 = _normal_entries_WIRE_3[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_sr = _normal_entries_T_25; // @[tlb.scala:60:79] assign _normal_entries_T_26 = _normal_entries_WIRE_3[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_sx = _normal_entries_T_26; // @[tlb.scala:60:79] assign _normal_entries_T_27 = _normal_entries_WIRE_3[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_sw = _normal_entries_T_27; // @[tlb.scala:60:79] assign _normal_entries_T_28 = _normal_entries_WIRE_3[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_ae = _normal_entries_T_28; // @[tlb.scala:60:79] assign _normal_entries_T_29 = _normal_entries_WIRE_3[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_g = _normal_entries_T_29; // @[tlb.scala:60:79] assign _normal_entries_T_30 = _normal_entries_WIRE_3[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_2_u = _normal_entries_T_30; // @[tlb.scala:60:79] assign _normal_entries_T_31 = _normal_entries_WIRE_3[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_2_ppn = _normal_entries_T_31; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_47; // @[tlb.scala:60:79] wire _normal_entries_T_46; // @[tlb.scala:60:79] wire _normal_entries_T_45; // @[tlb.scala:60:79] wire _normal_entries_T_44; // @[tlb.scala:60:79] wire _normal_entries_T_43; // @[tlb.scala:60:79] wire _normal_entries_T_42; // @[tlb.scala:60:79] wire _normal_entries_T_41; // @[tlb.scala:60:79] wire _normal_entries_T_40; // @[tlb.scala:60:79] wire _normal_entries_T_39; // @[tlb.scala:60:79] wire _normal_entries_T_38; // @[tlb.scala:60:79] wire _normal_entries_T_37; // @[tlb.scala:60:79] wire _normal_entries_T_36; // @[tlb.scala:60:79] wire _normal_entries_T_35; // @[tlb.scala:60:79] wire _normal_entries_T_34; // @[tlb.scala:60:79] wire _normal_entries_T_33; // @[tlb.scala:60:79] assign _normal_entries_T_33 = _normal_entries_WIRE_5[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_fragmented_superpage = _normal_entries_T_33; // @[tlb.scala:60:79] assign _normal_entries_T_34 = _normal_entries_WIRE_5[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_c = _normal_entries_T_34; // @[tlb.scala:60:79] assign _normal_entries_T_35 = _normal_entries_WIRE_5[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_eff = _normal_entries_T_35; // @[tlb.scala:60:79] assign _normal_entries_T_36 = _normal_entries_WIRE_5[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_paa = _normal_entries_T_36; // @[tlb.scala:60:79] assign _normal_entries_T_37 = _normal_entries_WIRE_5[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_pal = _normal_entries_T_37; // @[tlb.scala:60:79] assign _normal_entries_T_38 = _normal_entries_WIRE_5[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_pr = _normal_entries_T_38; // @[tlb.scala:60:79] assign _normal_entries_T_39 = _normal_entries_WIRE_5[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_px = _normal_entries_T_39; // @[tlb.scala:60:79] assign _normal_entries_T_40 = _normal_entries_WIRE_5[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_pw = _normal_entries_T_40; // @[tlb.scala:60:79] assign _normal_entries_T_41 = _normal_entries_WIRE_5[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_sr = _normal_entries_T_41; // @[tlb.scala:60:79] assign _normal_entries_T_42 = _normal_entries_WIRE_5[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_sx = _normal_entries_T_42; // @[tlb.scala:60:79] assign _normal_entries_T_43 = _normal_entries_WIRE_5[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_sw = _normal_entries_T_43; // @[tlb.scala:60:79] assign _normal_entries_T_44 = _normal_entries_WIRE_5[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_ae = _normal_entries_T_44; // @[tlb.scala:60:79] assign _normal_entries_T_45 = _normal_entries_WIRE_5[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_g = _normal_entries_T_45; // @[tlb.scala:60:79] assign _normal_entries_T_46 = _normal_entries_WIRE_5[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_4_u = _normal_entries_T_46; // @[tlb.scala:60:79] assign _normal_entries_T_47 = _normal_entries_WIRE_5[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_4_ppn = _normal_entries_T_47; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_63; // @[tlb.scala:60:79] wire _normal_entries_T_62; // @[tlb.scala:60:79] wire _normal_entries_T_61; // @[tlb.scala:60:79] wire _normal_entries_T_60; // @[tlb.scala:60:79] wire _normal_entries_T_59; // @[tlb.scala:60:79] wire _normal_entries_T_58; // @[tlb.scala:60:79] wire _normal_entries_T_57; // @[tlb.scala:60:79] wire _normal_entries_T_56; // @[tlb.scala:60:79] wire _normal_entries_T_55; // @[tlb.scala:60:79] wire _normal_entries_T_54; // @[tlb.scala:60:79] wire _normal_entries_T_53; // @[tlb.scala:60:79] wire _normal_entries_T_52; // @[tlb.scala:60:79] wire _normal_entries_T_51; // @[tlb.scala:60:79] wire _normal_entries_T_50; // @[tlb.scala:60:79] wire _normal_entries_T_49; // @[tlb.scala:60:79] assign _normal_entries_T_49 = _normal_entries_WIRE_7[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_fragmented_superpage = _normal_entries_T_49; // @[tlb.scala:60:79] assign _normal_entries_T_50 = _normal_entries_WIRE_7[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_c = _normal_entries_T_50; // @[tlb.scala:60:79] assign _normal_entries_T_51 = _normal_entries_WIRE_7[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_eff = _normal_entries_T_51; // @[tlb.scala:60:79] assign _normal_entries_T_52 = _normal_entries_WIRE_7[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_paa = _normal_entries_T_52; // @[tlb.scala:60:79] assign _normal_entries_T_53 = _normal_entries_WIRE_7[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_pal = _normal_entries_T_53; // @[tlb.scala:60:79] assign _normal_entries_T_54 = _normal_entries_WIRE_7[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_pr = _normal_entries_T_54; // @[tlb.scala:60:79] assign _normal_entries_T_55 = _normal_entries_WIRE_7[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_px = _normal_entries_T_55; // @[tlb.scala:60:79] assign _normal_entries_T_56 = _normal_entries_WIRE_7[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_pw = _normal_entries_T_56; // @[tlb.scala:60:79] assign _normal_entries_T_57 = _normal_entries_WIRE_7[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_sr = _normal_entries_T_57; // @[tlb.scala:60:79] assign _normal_entries_T_58 = _normal_entries_WIRE_7[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_sx = _normal_entries_T_58; // @[tlb.scala:60:79] assign _normal_entries_T_59 = _normal_entries_WIRE_7[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_sw = _normal_entries_T_59; // @[tlb.scala:60:79] assign _normal_entries_T_60 = _normal_entries_WIRE_7[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_ae = _normal_entries_T_60; // @[tlb.scala:60:79] assign _normal_entries_T_61 = _normal_entries_WIRE_7[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_g = _normal_entries_T_61; // @[tlb.scala:60:79] assign _normal_entries_T_62 = _normal_entries_WIRE_7[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_6_u = _normal_entries_T_62; // @[tlb.scala:60:79] assign _normal_entries_T_63 = _normal_entries_WIRE_7[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_6_ppn = _normal_entries_T_63; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_79; // @[tlb.scala:60:79] wire _normal_entries_T_78; // @[tlb.scala:60:79] wire _normal_entries_T_77; // @[tlb.scala:60:79] wire _normal_entries_T_76; // @[tlb.scala:60:79] wire _normal_entries_T_75; // @[tlb.scala:60:79] wire _normal_entries_T_74; // @[tlb.scala:60:79] wire _normal_entries_T_73; // @[tlb.scala:60:79] wire _normal_entries_T_72; // @[tlb.scala:60:79] wire _normal_entries_T_71; // @[tlb.scala:60:79] wire _normal_entries_T_70; // @[tlb.scala:60:79] wire _normal_entries_T_69; // @[tlb.scala:60:79] wire _normal_entries_T_68; // @[tlb.scala:60:79] wire _normal_entries_T_67; // @[tlb.scala:60:79] wire _normal_entries_T_66; // @[tlb.scala:60:79] wire _normal_entries_T_65; // @[tlb.scala:60:79] assign _normal_entries_T_65 = _normal_entries_WIRE_9[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_fragmented_superpage = _normal_entries_T_65; // @[tlb.scala:60:79] assign _normal_entries_T_66 = _normal_entries_WIRE_9[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_c = _normal_entries_T_66; // @[tlb.scala:60:79] assign _normal_entries_T_67 = _normal_entries_WIRE_9[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_eff = _normal_entries_T_67; // @[tlb.scala:60:79] assign _normal_entries_T_68 = _normal_entries_WIRE_9[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_paa = _normal_entries_T_68; // @[tlb.scala:60:79] assign _normal_entries_T_69 = _normal_entries_WIRE_9[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_pal = _normal_entries_T_69; // @[tlb.scala:60:79] assign _normal_entries_T_70 = _normal_entries_WIRE_9[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_pr = _normal_entries_T_70; // @[tlb.scala:60:79] assign _normal_entries_T_71 = _normal_entries_WIRE_9[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_px = _normal_entries_T_71; // @[tlb.scala:60:79] assign _normal_entries_T_72 = _normal_entries_WIRE_9[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_pw = _normal_entries_T_72; // @[tlb.scala:60:79] assign _normal_entries_T_73 = _normal_entries_WIRE_9[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_sr = _normal_entries_T_73; // @[tlb.scala:60:79] assign _normal_entries_T_74 = _normal_entries_WIRE_9[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_sx = _normal_entries_T_74; // @[tlb.scala:60:79] assign _normal_entries_T_75 = _normal_entries_WIRE_9[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_sw = _normal_entries_T_75; // @[tlb.scala:60:79] assign _normal_entries_T_76 = _normal_entries_WIRE_9[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_ae = _normal_entries_T_76; // @[tlb.scala:60:79] assign _normal_entries_T_77 = _normal_entries_WIRE_9[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_g = _normal_entries_T_77; // @[tlb.scala:60:79] assign _normal_entries_T_78 = _normal_entries_WIRE_9[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_8_u = _normal_entries_T_78; // @[tlb.scala:60:79] assign _normal_entries_T_79 = _normal_entries_WIRE_9[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_8_ppn = _normal_entries_T_79; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_95; // @[tlb.scala:60:79] wire _normal_entries_T_94; // @[tlb.scala:60:79] wire _normal_entries_T_93; // @[tlb.scala:60:79] wire _normal_entries_T_92; // @[tlb.scala:60:79] wire _normal_entries_T_91; // @[tlb.scala:60:79] wire _normal_entries_T_90; // @[tlb.scala:60:79] wire _normal_entries_T_89; // @[tlb.scala:60:79] wire _normal_entries_T_88; // @[tlb.scala:60:79] wire _normal_entries_T_87; // @[tlb.scala:60:79] wire _normal_entries_T_86; // @[tlb.scala:60:79] wire _normal_entries_T_85; // @[tlb.scala:60:79] wire _normal_entries_T_84; // @[tlb.scala:60:79] wire _normal_entries_T_83; // @[tlb.scala:60:79] wire _normal_entries_T_82; // @[tlb.scala:60:79] wire _normal_entries_T_81; // @[tlb.scala:60:79] assign _normal_entries_T_81 = _normal_entries_WIRE_11[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_fragmented_superpage = _normal_entries_T_81; // @[tlb.scala:60:79] assign _normal_entries_T_82 = _normal_entries_WIRE_11[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_c = _normal_entries_T_82; // @[tlb.scala:60:79] assign _normal_entries_T_83 = _normal_entries_WIRE_11[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_eff = _normal_entries_T_83; // @[tlb.scala:60:79] assign _normal_entries_T_84 = _normal_entries_WIRE_11[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_paa = _normal_entries_T_84; // @[tlb.scala:60:79] assign _normal_entries_T_85 = _normal_entries_WIRE_11[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_pal = _normal_entries_T_85; // @[tlb.scala:60:79] assign _normal_entries_T_86 = _normal_entries_WIRE_11[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_pr = _normal_entries_T_86; // @[tlb.scala:60:79] assign _normal_entries_T_87 = _normal_entries_WIRE_11[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_px = _normal_entries_T_87; // @[tlb.scala:60:79] assign _normal_entries_T_88 = _normal_entries_WIRE_11[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_pw = _normal_entries_T_88; // @[tlb.scala:60:79] assign _normal_entries_T_89 = _normal_entries_WIRE_11[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_sr = _normal_entries_T_89; // @[tlb.scala:60:79] assign _normal_entries_T_90 = _normal_entries_WIRE_11[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_sx = _normal_entries_T_90; // @[tlb.scala:60:79] assign _normal_entries_T_91 = _normal_entries_WIRE_11[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_sw = _normal_entries_T_91; // @[tlb.scala:60:79] assign _normal_entries_T_92 = _normal_entries_WIRE_11[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_ae = _normal_entries_T_92; // @[tlb.scala:60:79] assign _normal_entries_T_93 = _normal_entries_WIRE_11[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_g = _normal_entries_T_93; // @[tlb.scala:60:79] assign _normal_entries_T_94 = _normal_entries_WIRE_11[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_10_u = _normal_entries_T_94; // @[tlb.scala:60:79] assign _normal_entries_T_95 = _normal_entries_WIRE_11[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_10_ppn = _normal_entries_T_95; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_111; // @[tlb.scala:60:79] wire _normal_entries_T_110; // @[tlb.scala:60:79] wire _normal_entries_T_109; // @[tlb.scala:60:79] wire _normal_entries_T_108; // @[tlb.scala:60:79] wire _normal_entries_T_107; // @[tlb.scala:60:79] wire _normal_entries_T_106; // @[tlb.scala:60:79] wire _normal_entries_T_105; // @[tlb.scala:60:79] wire _normal_entries_T_104; // @[tlb.scala:60:79] wire _normal_entries_T_103; // @[tlb.scala:60:79] wire _normal_entries_T_102; // @[tlb.scala:60:79] wire _normal_entries_T_101; // @[tlb.scala:60:79] wire _normal_entries_T_100; // @[tlb.scala:60:79] wire _normal_entries_T_99; // @[tlb.scala:60:79] wire _normal_entries_T_98; // @[tlb.scala:60:79] wire _normal_entries_T_97; // @[tlb.scala:60:79] assign _normal_entries_T_97 = _normal_entries_WIRE_13[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_fragmented_superpage = _normal_entries_T_97; // @[tlb.scala:60:79] assign _normal_entries_T_98 = _normal_entries_WIRE_13[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_c = _normal_entries_T_98; // @[tlb.scala:60:79] assign _normal_entries_T_99 = _normal_entries_WIRE_13[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_eff = _normal_entries_T_99; // @[tlb.scala:60:79] assign _normal_entries_T_100 = _normal_entries_WIRE_13[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_paa = _normal_entries_T_100; // @[tlb.scala:60:79] assign _normal_entries_T_101 = _normal_entries_WIRE_13[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_pal = _normal_entries_T_101; // @[tlb.scala:60:79] assign _normal_entries_T_102 = _normal_entries_WIRE_13[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_pr = _normal_entries_T_102; // @[tlb.scala:60:79] assign _normal_entries_T_103 = _normal_entries_WIRE_13[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_px = _normal_entries_T_103; // @[tlb.scala:60:79] assign _normal_entries_T_104 = _normal_entries_WIRE_13[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_pw = _normal_entries_T_104; // @[tlb.scala:60:79] assign _normal_entries_T_105 = _normal_entries_WIRE_13[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_sr = _normal_entries_T_105; // @[tlb.scala:60:79] assign _normal_entries_T_106 = _normal_entries_WIRE_13[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_sx = _normal_entries_T_106; // @[tlb.scala:60:79] assign _normal_entries_T_107 = _normal_entries_WIRE_13[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_sw = _normal_entries_T_107; // @[tlb.scala:60:79] assign _normal_entries_T_108 = _normal_entries_WIRE_13[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_ae = _normal_entries_T_108; // @[tlb.scala:60:79] assign _normal_entries_T_109 = _normal_entries_WIRE_13[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_g = _normal_entries_T_109; // @[tlb.scala:60:79] assign _normal_entries_T_110 = _normal_entries_WIRE_13[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_12_u = _normal_entries_T_110; // @[tlb.scala:60:79] assign _normal_entries_T_111 = _normal_entries_WIRE_13[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_12_ppn = _normal_entries_T_111; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_127; // @[tlb.scala:60:79] wire _normal_entries_T_126; // @[tlb.scala:60:79] wire _normal_entries_T_125; // @[tlb.scala:60:79] wire _normal_entries_T_124; // @[tlb.scala:60:79] wire _normal_entries_T_123; // @[tlb.scala:60:79] wire _normal_entries_T_122; // @[tlb.scala:60:79] wire _normal_entries_T_121; // @[tlb.scala:60:79] wire _normal_entries_T_120; // @[tlb.scala:60:79] wire _normal_entries_T_119; // @[tlb.scala:60:79] wire _normal_entries_T_118; // @[tlb.scala:60:79] wire _normal_entries_T_117; // @[tlb.scala:60:79] wire _normal_entries_T_116; // @[tlb.scala:60:79] wire _normal_entries_T_115; // @[tlb.scala:60:79] wire _normal_entries_T_114; // @[tlb.scala:60:79] wire _normal_entries_T_113; // @[tlb.scala:60:79] assign _normal_entries_T_113 = _normal_entries_WIRE_15[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_fragmented_superpage = _normal_entries_T_113; // @[tlb.scala:60:79] assign _normal_entries_T_114 = _normal_entries_WIRE_15[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_c = _normal_entries_T_114; // @[tlb.scala:60:79] assign _normal_entries_T_115 = _normal_entries_WIRE_15[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_eff = _normal_entries_T_115; // @[tlb.scala:60:79] assign _normal_entries_T_116 = _normal_entries_WIRE_15[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_paa = _normal_entries_T_116; // @[tlb.scala:60:79] assign _normal_entries_T_117 = _normal_entries_WIRE_15[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_pal = _normal_entries_T_117; // @[tlb.scala:60:79] assign _normal_entries_T_118 = _normal_entries_WIRE_15[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_pr = _normal_entries_T_118; // @[tlb.scala:60:79] assign _normal_entries_T_119 = _normal_entries_WIRE_15[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_px = _normal_entries_T_119; // @[tlb.scala:60:79] assign _normal_entries_T_120 = _normal_entries_WIRE_15[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_pw = _normal_entries_T_120; // @[tlb.scala:60:79] assign _normal_entries_T_121 = _normal_entries_WIRE_15[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_sr = _normal_entries_T_121; // @[tlb.scala:60:79] assign _normal_entries_T_122 = _normal_entries_WIRE_15[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_sx = _normal_entries_T_122; // @[tlb.scala:60:79] assign _normal_entries_T_123 = _normal_entries_WIRE_15[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_sw = _normal_entries_T_123; // @[tlb.scala:60:79] assign _normal_entries_T_124 = _normal_entries_WIRE_15[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_ae = _normal_entries_T_124; // @[tlb.scala:60:79] assign _normal_entries_T_125 = _normal_entries_WIRE_15[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_g = _normal_entries_T_125; // @[tlb.scala:60:79] assign _normal_entries_T_126 = _normal_entries_WIRE_15[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_14_u = _normal_entries_T_126; // @[tlb.scala:60:79] assign _normal_entries_T_127 = _normal_entries_WIRE_15[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_14_ppn = _normal_entries_T_127; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_142; // @[tlb.scala:60:79] wire _normal_entries_T_141; // @[tlb.scala:60:79] wire _normal_entries_T_140; // @[tlb.scala:60:79] wire _normal_entries_T_139; // @[tlb.scala:60:79] wire _normal_entries_T_138; // @[tlb.scala:60:79] wire _normal_entries_T_137; // @[tlb.scala:60:79] wire _normal_entries_T_136; // @[tlb.scala:60:79] wire _normal_entries_T_135; // @[tlb.scala:60:79] wire _normal_entries_T_134; // @[tlb.scala:60:79] wire _normal_entries_T_133; // @[tlb.scala:60:79] wire _normal_entries_T_132; // @[tlb.scala:60:79] wire _normal_entries_T_131; // @[tlb.scala:60:79] wire _normal_entries_T_130; // @[tlb.scala:60:79] wire _normal_entries_T_129; // @[tlb.scala:60:79] wire _normal_entries_T_128; // @[tlb.scala:60:79] assign _normal_entries_T_128 = _normal_entries_WIRE_17[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_fragmented_superpage = _normal_entries_T_128; // @[tlb.scala:60:79] assign _normal_entries_T_129 = _normal_entries_WIRE_17[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_c = _normal_entries_T_129; // @[tlb.scala:60:79] assign _normal_entries_T_130 = _normal_entries_WIRE_17[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_eff = _normal_entries_T_130; // @[tlb.scala:60:79] assign _normal_entries_T_131 = _normal_entries_WIRE_17[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_paa = _normal_entries_T_131; // @[tlb.scala:60:79] assign _normal_entries_T_132 = _normal_entries_WIRE_17[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_pal = _normal_entries_T_132; // @[tlb.scala:60:79] assign _normal_entries_T_133 = _normal_entries_WIRE_17[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_pr = _normal_entries_T_133; // @[tlb.scala:60:79] assign _normal_entries_T_134 = _normal_entries_WIRE_17[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_px = _normal_entries_T_134; // @[tlb.scala:60:79] assign _normal_entries_T_135 = _normal_entries_WIRE_17[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_pw = _normal_entries_T_135; // @[tlb.scala:60:79] assign _normal_entries_T_136 = _normal_entries_WIRE_17[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_sr = _normal_entries_T_136; // @[tlb.scala:60:79] assign _normal_entries_T_137 = _normal_entries_WIRE_17[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_sx = _normal_entries_T_137; // @[tlb.scala:60:79] assign _normal_entries_T_138 = _normal_entries_WIRE_17[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_sw = _normal_entries_T_138; // @[tlb.scala:60:79] assign _normal_entries_T_139 = _normal_entries_WIRE_17[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_ae = _normal_entries_T_139; // @[tlb.scala:60:79] assign _normal_entries_T_140 = _normal_entries_WIRE_17[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_g = _normal_entries_T_140; // @[tlb.scala:60:79] assign _normal_entries_T_141 = _normal_entries_WIRE_17[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_16_u = _normal_entries_T_141; // @[tlb.scala:60:79] assign _normal_entries_T_142 = _normal_entries_WIRE_17[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_16_ppn = _normal_entries_T_142; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_157; // @[tlb.scala:60:79] wire _normal_entries_T_156; // @[tlb.scala:60:79] wire _normal_entries_T_155; // @[tlb.scala:60:79] wire _normal_entries_T_154; // @[tlb.scala:60:79] wire _normal_entries_T_153; // @[tlb.scala:60:79] wire _normal_entries_T_152; // @[tlb.scala:60:79] wire _normal_entries_T_151; // @[tlb.scala:60:79] wire _normal_entries_T_150; // @[tlb.scala:60:79] wire _normal_entries_T_149; // @[tlb.scala:60:79] wire _normal_entries_T_148; // @[tlb.scala:60:79] wire _normal_entries_T_147; // @[tlb.scala:60:79] wire _normal_entries_T_146; // @[tlb.scala:60:79] wire _normal_entries_T_145; // @[tlb.scala:60:79] wire _normal_entries_T_144; // @[tlb.scala:60:79] wire _normal_entries_T_143; // @[tlb.scala:60:79] assign _normal_entries_T_143 = _normal_entries_WIRE_19[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_fragmented_superpage = _normal_entries_T_143; // @[tlb.scala:60:79] assign _normal_entries_T_144 = _normal_entries_WIRE_19[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_c = _normal_entries_T_144; // @[tlb.scala:60:79] assign _normal_entries_T_145 = _normal_entries_WIRE_19[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_eff = _normal_entries_T_145; // @[tlb.scala:60:79] assign _normal_entries_T_146 = _normal_entries_WIRE_19[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_paa = _normal_entries_T_146; // @[tlb.scala:60:79] assign _normal_entries_T_147 = _normal_entries_WIRE_19[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_pal = _normal_entries_T_147; // @[tlb.scala:60:79] assign _normal_entries_T_148 = _normal_entries_WIRE_19[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_pr = _normal_entries_T_148; // @[tlb.scala:60:79] assign _normal_entries_T_149 = _normal_entries_WIRE_19[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_px = _normal_entries_T_149; // @[tlb.scala:60:79] assign _normal_entries_T_150 = _normal_entries_WIRE_19[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_pw = _normal_entries_T_150; // @[tlb.scala:60:79] assign _normal_entries_T_151 = _normal_entries_WIRE_19[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_sr = _normal_entries_T_151; // @[tlb.scala:60:79] assign _normal_entries_T_152 = _normal_entries_WIRE_19[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_sx = _normal_entries_T_152; // @[tlb.scala:60:79] assign _normal_entries_T_153 = _normal_entries_WIRE_19[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_sw = _normal_entries_T_153; // @[tlb.scala:60:79] assign _normal_entries_T_154 = _normal_entries_WIRE_19[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_ae = _normal_entries_T_154; // @[tlb.scala:60:79] assign _normal_entries_T_155 = _normal_entries_WIRE_19[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_g = _normal_entries_T_155; // @[tlb.scala:60:79] assign _normal_entries_T_156 = _normal_entries_WIRE_19[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_18_u = _normal_entries_T_156; // @[tlb.scala:60:79] assign _normal_entries_T_157 = _normal_entries_WIRE_19[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_18_ppn = _normal_entries_T_157; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_172; // @[tlb.scala:60:79] wire _normal_entries_T_171; // @[tlb.scala:60:79] wire _normal_entries_T_170; // @[tlb.scala:60:79] wire _normal_entries_T_169; // @[tlb.scala:60:79] wire _normal_entries_T_168; // @[tlb.scala:60:79] wire _normal_entries_T_167; // @[tlb.scala:60:79] wire _normal_entries_T_166; // @[tlb.scala:60:79] wire _normal_entries_T_165; // @[tlb.scala:60:79] wire _normal_entries_T_164; // @[tlb.scala:60:79] wire _normal_entries_T_163; // @[tlb.scala:60:79] wire _normal_entries_T_162; // @[tlb.scala:60:79] wire _normal_entries_T_161; // @[tlb.scala:60:79] wire _normal_entries_T_160; // @[tlb.scala:60:79] wire _normal_entries_T_159; // @[tlb.scala:60:79] wire _normal_entries_T_158; // @[tlb.scala:60:79] assign _normal_entries_T_158 = _normal_entries_WIRE_21[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_fragmented_superpage = _normal_entries_T_158; // @[tlb.scala:60:79] assign _normal_entries_T_159 = _normal_entries_WIRE_21[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_c = _normal_entries_T_159; // @[tlb.scala:60:79] assign _normal_entries_T_160 = _normal_entries_WIRE_21[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_eff = _normal_entries_T_160; // @[tlb.scala:60:79] assign _normal_entries_T_161 = _normal_entries_WIRE_21[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_paa = _normal_entries_T_161; // @[tlb.scala:60:79] assign _normal_entries_T_162 = _normal_entries_WIRE_21[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_pal = _normal_entries_T_162; // @[tlb.scala:60:79] assign _normal_entries_T_163 = _normal_entries_WIRE_21[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_pr = _normal_entries_T_163; // @[tlb.scala:60:79] assign _normal_entries_T_164 = _normal_entries_WIRE_21[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_px = _normal_entries_T_164; // @[tlb.scala:60:79] assign _normal_entries_T_165 = _normal_entries_WIRE_21[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_pw = _normal_entries_T_165; // @[tlb.scala:60:79] assign _normal_entries_T_166 = _normal_entries_WIRE_21[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_sr = _normal_entries_T_166; // @[tlb.scala:60:79] assign _normal_entries_T_167 = _normal_entries_WIRE_21[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_sx = _normal_entries_T_167; // @[tlb.scala:60:79] assign _normal_entries_T_168 = _normal_entries_WIRE_21[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_sw = _normal_entries_T_168; // @[tlb.scala:60:79] assign _normal_entries_T_169 = _normal_entries_WIRE_21[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_ae = _normal_entries_T_169; // @[tlb.scala:60:79] assign _normal_entries_T_170 = _normal_entries_WIRE_21[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_g = _normal_entries_T_170; // @[tlb.scala:60:79] assign _normal_entries_T_171 = _normal_entries_WIRE_21[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_20_u = _normal_entries_T_171; // @[tlb.scala:60:79] assign _normal_entries_T_172 = _normal_entries_WIRE_21[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_20_ppn = _normal_entries_T_172; // @[tlb.scala:60:79] wire [19:0] _normal_entries_T_187; // @[tlb.scala:60:79] wire _normal_entries_T_186; // @[tlb.scala:60:79] wire _normal_entries_T_185; // @[tlb.scala:60:79] wire _normal_entries_T_184; // @[tlb.scala:60:79] wire _normal_entries_T_183; // @[tlb.scala:60:79] wire _normal_entries_T_182; // @[tlb.scala:60:79] wire _normal_entries_T_181; // @[tlb.scala:60:79] wire _normal_entries_T_180; // @[tlb.scala:60:79] wire _normal_entries_T_179; // @[tlb.scala:60:79] wire _normal_entries_T_178; // @[tlb.scala:60:79] wire _normal_entries_T_177; // @[tlb.scala:60:79] wire _normal_entries_T_176; // @[tlb.scala:60:79] wire _normal_entries_T_175; // @[tlb.scala:60:79] wire _normal_entries_T_174; // @[tlb.scala:60:79] wire _normal_entries_T_173; // @[tlb.scala:60:79] assign _normal_entries_T_173 = _normal_entries_WIRE_23[0]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_fragmented_superpage = _normal_entries_T_173; // @[tlb.scala:60:79] assign _normal_entries_T_174 = _normal_entries_WIRE_23[1]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_c = _normal_entries_T_174; // @[tlb.scala:60:79] assign _normal_entries_T_175 = _normal_entries_WIRE_23[2]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_eff = _normal_entries_T_175; // @[tlb.scala:60:79] assign _normal_entries_T_176 = _normal_entries_WIRE_23[3]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_paa = _normal_entries_T_176; // @[tlb.scala:60:79] assign _normal_entries_T_177 = _normal_entries_WIRE_23[4]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_pal = _normal_entries_T_177; // @[tlb.scala:60:79] assign _normal_entries_T_178 = _normal_entries_WIRE_23[5]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_pr = _normal_entries_T_178; // @[tlb.scala:60:79] assign _normal_entries_T_179 = _normal_entries_WIRE_23[6]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_px = _normal_entries_T_179; // @[tlb.scala:60:79] assign _normal_entries_T_180 = _normal_entries_WIRE_23[7]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_pw = _normal_entries_T_180; // @[tlb.scala:60:79] assign _normal_entries_T_181 = _normal_entries_WIRE_23[8]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_sr = _normal_entries_T_181; // @[tlb.scala:60:79] assign _normal_entries_T_182 = _normal_entries_WIRE_23[9]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_sx = _normal_entries_T_182; // @[tlb.scala:60:79] assign _normal_entries_T_183 = _normal_entries_WIRE_23[10]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_sw = _normal_entries_T_183; // @[tlb.scala:60:79] assign _normal_entries_T_184 = _normal_entries_WIRE_23[11]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_ae = _normal_entries_T_184; // @[tlb.scala:60:79] assign _normal_entries_T_185 = _normal_entries_WIRE_23[12]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_g = _normal_entries_T_185; // @[tlb.scala:60:79] assign _normal_entries_T_186 = _normal_entries_WIRE_23[13]; // @[tlb.scala:60:79] wire _normal_entries_WIRE_22_u = _normal_entries_T_186; // @[tlb.scala:60:79] assign _normal_entries_T_187 = _normal_entries_WIRE_23[33:14]; // @[tlb.scala:60:79] wire [19:0] _normal_entries_WIRE_22_ppn = _normal_entries_T_187; // @[tlb.scala:60:79] wire [19:0] normal_entries_0_0_ppn = _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_u = _normal_entries_WIRE_24_0_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_g = _normal_entries_WIRE_24_0_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_ae = _normal_entries_WIRE_24_0_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_sw = _normal_entries_WIRE_24_0_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_sx = _normal_entries_WIRE_24_0_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_sr = _normal_entries_WIRE_24_0_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_pw = _normal_entries_WIRE_24_0_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_px = _normal_entries_WIRE_24_0_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_pr = _normal_entries_WIRE_24_0_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_pal = _normal_entries_WIRE_24_0_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_paa = _normal_entries_WIRE_24_0_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_eff = _normal_entries_WIRE_24_0_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_c = _normal_entries_WIRE_24_0_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_0_fragmented_superpage = _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_1_ppn = _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_u = _normal_entries_WIRE_24_1_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_g = _normal_entries_WIRE_24_1_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_ae = _normal_entries_WIRE_24_1_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_sw = _normal_entries_WIRE_24_1_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_sx = _normal_entries_WIRE_24_1_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_sr = _normal_entries_WIRE_24_1_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_pw = _normal_entries_WIRE_24_1_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_px = _normal_entries_WIRE_24_1_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_pr = _normal_entries_WIRE_24_1_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_pal = _normal_entries_WIRE_24_1_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_paa = _normal_entries_WIRE_24_1_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_eff = _normal_entries_WIRE_24_1_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_c = _normal_entries_WIRE_24_1_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_1_fragmented_superpage = _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_2_ppn = _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_u = _normal_entries_WIRE_24_2_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_g = _normal_entries_WIRE_24_2_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_ae = _normal_entries_WIRE_24_2_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_sw = _normal_entries_WIRE_24_2_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_sx = _normal_entries_WIRE_24_2_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_sr = _normal_entries_WIRE_24_2_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_pw = _normal_entries_WIRE_24_2_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_px = _normal_entries_WIRE_24_2_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_pr = _normal_entries_WIRE_24_2_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_pal = _normal_entries_WIRE_24_2_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_paa = _normal_entries_WIRE_24_2_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_eff = _normal_entries_WIRE_24_2_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_c = _normal_entries_WIRE_24_2_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_2_fragmented_superpage = _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_3_ppn = _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_u = _normal_entries_WIRE_24_3_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_g = _normal_entries_WIRE_24_3_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_ae = _normal_entries_WIRE_24_3_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_sw = _normal_entries_WIRE_24_3_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_sx = _normal_entries_WIRE_24_3_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_sr = _normal_entries_WIRE_24_3_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_pw = _normal_entries_WIRE_24_3_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_px = _normal_entries_WIRE_24_3_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_pr = _normal_entries_WIRE_24_3_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_pal = _normal_entries_WIRE_24_3_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_paa = _normal_entries_WIRE_24_3_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_eff = _normal_entries_WIRE_24_3_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_c = _normal_entries_WIRE_24_3_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_3_fragmented_superpage = _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_4_ppn = _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_u = _normal_entries_WIRE_24_4_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_g = _normal_entries_WIRE_24_4_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_ae = _normal_entries_WIRE_24_4_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_sw = _normal_entries_WIRE_24_4_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_sx = _normal_entries_WIRE_24_4_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_sr = _normal_entries_WIRE_24_4_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_pw = _normal_entries_WIRE_24_4_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_px = _normal_entries_WIRE_24_4_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_pr = _normal_entries_WIRE_24_4_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_pal = _normal_entries_WIRE_24_4_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_paa = _normal_entries_WIRE_24_4_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_eff = _normal_entries_WIRE_24_4_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_c = _normal_entries_WIRE_24_4_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_4_fragmented_superpage = _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_5_ppn = _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_u = _normal_entries_WIRE_24_5_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_g = _normal_entries_WIRE_24_5_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_ae = _normal_entries_WIRE_24_5_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_sw = _normal_entries_WIRE_24_5_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_sx = _normal_entries_WIRE_24_5_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_sr = _normal_entries_WIRE_24_5_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_pw = _normal_entries_WIRE_24_5_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_px = _normal_entries_WIRE_24_5_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_pr = _normal_entries_WIRE_24_5_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_pal = _normal_entries_WIRE_24_5_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_paa = _normal_entries_WIRE_24_5_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_eff = _normal_entries_WIRE_24_5_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_c = _normal_entries_WIRE_24_5_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_5_fragmented_superpage = _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_6_ppn = _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_u = _normal_entries_WIRE_24_6_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_g = _normal_entries_WIRE_24_6_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_ae = _normal_entries_WIRE_24_6_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_sw = _normal_entries_WIRE_24_6_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_sx = _normal_entries_WIRE_24_6_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_sr = _normal_entries_WIRE_24_6_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_pw = _normal_entries_WIRE_24_6_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_px = _normal_entries_WIRE_24_6_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_pr = _normal_entries_WIRE_24_6_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_pal = _normal_entries_WIRE_24_6_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_paa = _normal_entries_WIRE_24_6_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_eff = _normal_entries_WIRE_24_6_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_c = _normal_entries_WIRE_24_6_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_6_fragmented_superpage = _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_7_ppn = _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_u = _normal_entries_WIRE_24_7_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_g = _normal_entries_WIRE_24_7_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_ae = _normal_entries_WIRE_24_7_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_sw = _normal_entries_WIRE_24_7_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_sx = _normal_entries_WIRE_24_7_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_sr = _normal_entries_WIRE_24_7_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_pw = _normal_entries_WIRE_24_7_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_px = _normal_entries_WIRE_24_7_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_pr = _normal_entries_WIRE_24_7_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_pal = _normal_entries_WIRE_24_7_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_paa = _normal_entries_WIRE_24_7_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_eff = _normal_entries_WIRE_24_7_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_c = _normal_entries_WIRE_24_7_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_7_fragmented_superpage = _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_8_ppn = _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_u = _normal_entries_WIRE_24_8_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_g = _normal_entries_WIRE_24_8_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_ae = _normal_entries_WIRE_24_8_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_sw = _normal_entries_WIRE_24_8_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_sx = _normal_entries_WIRE_24_8_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_sr = _normal_entries_WIRE_24_8_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_pw = _normal_entries_WIRE_24_8_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_px = _normal_entries_WIRE_24_8_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_pr = _normal_entries_WIRE_24_8_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_pal = _normal_entries_WIRE_24_8_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_paa = _normal_entries_WIRE_24_8_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_eff = _normal_entries_WIRE_24_8_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_c = _normal_entries_WIRE_24_8_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_8_fragmented_superpage = _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_9_ppn = _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_u = _normal_entries_WIRE_24_9_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_g = _normal_entries_WIRE_24_9_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_ae = _normal_entries_WIRE_24_9_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_sw = _normal_entries_WIRE_24_9_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_sx = _normal_entries_WIRE_24_9_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_sr = _normal_entries_WIRE_24_9_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_pw = _normal_entries_WIRE_24_9_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_px = _normal_entries_WIRE_24_9_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_pr = _normal_entries_WIRE_24_9_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_pal = _normal_entries_WIRE_24_9_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_paa = _normal_entries_WIRE_24_9_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_eff = _normal_entries_WIRE_24_9_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_c = _normal_entries_WIRE_24_9_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_9_fragmented_superpage = _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_10_ppn = _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_u = _normal_entries_WIRE_24_10_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_g = _normal_entries_WIRE_24_10_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_ae = _normal_entries_WIRE_24_10_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_sw = _normal_entries_WIRE_24_10_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_sx = _normal_entries_WIRE_24_10_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_sr = _normal_entries_WIRE_24_10_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_pw = _normal_entries_WIRE_24_10_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_px = _normal_entries_WIRE_24_10_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_pr = _normal_entries_WIRE_24_10_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_pal = _normal_entries_WIRE_24_10_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_paa = _normal_entries_WIRE_24_10_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_eff = _normal_entries_WIRE_24_10_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_c = _normal_entries_WIRE_24_10_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_10_fragmented_superpage = _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [19:0] normal_entries_0_11_ppn = _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_u = _normal_entries_WIRE_24_11_u; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_g = _normal_entries_WIRE_24_11_g; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_ae = _normal_entries_WIRE_24_11_ae; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_sw = _normal_entries_WIRE_24_11_sw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_sx = _normal_entries_WIRE_24_11_sx; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_sr = _normal_entries_WIRE_24_11_sr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_pw = _normal_entries_WIRE_24_11_pw; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_px = _normal_entries_WIRE_24_11_px; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_pr = _normal_entries_WIRE_24_11_pr; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_pal = _normal_entries_WIRE_24_11_pal; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_paa = _normal_entries_WIRE_24_11_paa; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_eff = _normal_entries_WIRE_24_11_eff; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_c = _normal_entries_WIRE_24_11_c; // @[tlb.scala:121:49, :214:45] wire normal_entries_0_11_fragmented_superpage = _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:121:49, :214:45] wire [1:0] ptw_ae_array_lo_lo_hi = {entries_0_2_ae, entries_0_1_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, entries_0_0_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_lo_hi_hi = {entries_0_5_ae, entries_0_4_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, entries_0_3_ae}; // @[package.scala:45:27] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {entries_0_8_ae, entries_0_7_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, entries_0_6_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_hi_lo = {entries_0_10_ae, entries_0_9_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_hi_hi = {entries_0_12_ae, entries_0_11_ae}; // @[package.scala:45:27] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] _ptw_ae_array_T_1 = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [13:0] ptw_ae_array_0 = _ptw_ae_array_T_1; // @[tlb.scala:121:49, :216:39] wire [1:0] _GEN_9 = {entries_0_2_u, entries_0_1_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [1:0] _GEN_10 = {entries_0_5_u, entries_0_4_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_11 = {entries_0_8_u, entries_0_7_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27] wire [1:0] _GEN_12 = {entries_0_10_u, entries_0_9_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] _GEN_13 = {entries_0_12_u, entries_0_11_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_7 = _priv_rw_ok_T_3; // @[tlb.scala:217:{39,103}] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] priv_rw_ok_0 = _priv_rw_ok_T_7; // @[tlb.scala:121:49, :217:103] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_3 = _priv_x_ok_T_2; // @[package.scala:45:27] wire [12:0] priv_x_ok_0 = _priv_x_ok_T_3; // @[tlb.scala:121:49, :218:39] wire [1:0] r_array_lo_lo_hi = {entries_0_2_sr, entries_0_1_sr}; // @[package.scala:45:27] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, entries_0_0_sr}; // @[package.scala:45:27] wire [1:0] r_array_lo_hi_hi = {entries_0_5_sr, entries_0_4_sr}; // @[package.scala:45:27] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, entries_0_3_sr}; // @[package.scala:45:27] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {entries_0_8_sr, entries_0_7_sr}; // @[package.scala:45:27] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, entries_0_6_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_lo = {entries_0_10_sr, entries_0_9_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_hi = {entries_0_12_sr, entries_0_11_sr}; // @[package.scala:45:27] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_14 = {entries_0_2_sx, entries_0_1_sx}; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_14; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, entries_0_0_sx}; // @[package.scala:45:27] wire [1:0] _GEN_15 = {entries_0_5_sx, entries_0_4_sx}; // @[package.scala:45:27] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_15; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, entries_0_3_sx}; // @[package.scala:45:27] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_16 = {entries_0_8_sx, entries_0_7_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, entries_0_6_sx}; // @[package.scala:45:27] wire [1:0] _GEN_17 = {entries_0_10_sx, entries_0_9_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_17; // @[package.scala:45:27] wire [1:0] _GEN_18 = {entries_0_12_sx, entries_0_11_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_18; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok_0 & _r_array_T_3; // @[tlb.scala:121:49, :219:{62,93}] wire [13:0] _r_array_T_5 = {1'h1, _r_array_T_4}; // @[tlb.scala:219:{39,62}] wire [13:0] r_array_0 = _r_array_T_5; // @[tlb.scala:121:49, :219:39] wire [1:0] w_array_lo_lo_hi = {entries_0_2_sw, entries_0_1_sw}; // @[package.scala:45:27] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, entries_0_0_sw}; // @[package.scala:45:27] wire [1:0] w_array_lo_hi_hi = {entries_0_5_sw, entries_0_4_sw}; // @[package.scala:45:27] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, entries_0_3_sw}; // @[package.scala:45:27] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {entries_0_8_sw, entries_0_7_sw}; // @[package.scala:45:27] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, entries_0_6_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_hi_lo = {entries_0_10_sw, entries_0_9_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_hi_hi = {entries_0_12_sw, entries_0_11_sw}; // @[package.scala:45:27] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok_0 & _w_array_T; // @[package.scala:45:27] wire [13:0] _w_array_T_2 = {1'h1, _w_array_T_1}; // @[tlb.scala:220:{39,62}] wire [13:0] w_array_0 = _w_array_T_2; // @[tlb.scala:121:49, :220:39] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, entries_0_0_sx}; // @[package.scala:45:27] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, entries_0_3_sx}; // @[package.scala:45:27] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, entries_0_6_sx}; // @[package.scala:45:27] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok_0 & _x_array_T; // @[package.scala:45:27] wire [13:0] _x_array_T_2 = {1'h1, _x_array_T_1}; // @[tlb.scala:221:{39,62}] wire [13:0] x_array_0 = _x_array_T_2; // @[tlb.scala:121:49, :221:39] wire [1:0] _pr_array_T = {2{prot_r_0}}; // @[tlb.scala:121:49, :222:44] wire [1:0] pr_array_lo_lo_hi = {normal_entries_0_2_pr, normal_entries_0_1_pr}; // @[package.scala:45:27] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, normal_entries_0_0_pr}; // @[package.scala:45:27] wire [1:0] pr_array_lo_hi_hi = {normal_entries_0_5_pr, normal_entries_0_4_pr}; // @[package.scala:45:27] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, normal_entries_0_3_pr}; // @[package.scala:45:27] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {normal_entries_0_8_pr, normal_entries_0_7_pr}; // @[package.scala:45:27] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, normal_entries_0_6_pr}; // @[package.scala:45:27] wire [1:0] pr_array_hi_hi_hi = {normal_entries_0_11_pr, normal_entries_0_10_pr}; // @[package.scala:45:27] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, normal_entries_0_9_pr}; // @[package.scala:45:27] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _pr_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:121:49, :222:116] wire [13:0] _pr_array_T_4 = _pr_array_T_2 & _pr_array_T_3; // @[tlb.scala:222:{39,114,116}] wire [13:0] pr_array_0 = _pr_array_T_4; // @[tlb.scala:121:49, :222:114] wire [1:0] _pw_array_T = {2{prot_w_0}}; // @[tlb.scala:121:49, :223:44] wire [1:0] pw_array_lo_lo_hi = {normal_entries_0_2_pw, normal_entries_0_1_pw}; // @[package.scala:45:27] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, normal_entries_0_0_pw}; // @[package.scala:45:27] wire [1:0] pw_array_lo_hi_hi = {normal_entries_0_5_pw, normal_entries_0_4_pw}; // @[package.scala:45:27] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, normal_entries_0_3_pw}; // @[package.scala:45:27] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {normal_entries_0_8_pw, normal_entries_0_7_pw}; // @[package.scala:45:27] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, normal_entries_0_6_pw}; // @[package.scala:45:27] wire [1:0] pw_array_hi_hi_hi = {normal_entries_0_11_pw, normal_entries_0_10_pw}; // @[package.scala:45:27] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, normal_entries_0_9_pw}; // @[package.scala:45:27] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:121:49, :222:116, :223:116] wire [13:0] _pw_array_T_4 = _pw_array_T_2 & _pw_array_T_3; // @[tlb.scala:223:{39,114,116}] wire [13:0] pw_array_0 = _pw_array_T_4; // @[tlb.scala:121:49, :223:114] wire [1:0] _px_array_T = {2{prot_x_0}}; // @[tlb.scala:121:49, :224:44] wire [1:0] px_array_lo_lo_hi = {normal_entries_0_2_px, normal_entries_0_1_px}; // @[package.scala:45:27] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, normal_entries_0_0_px}; // @[package.scala:45:27] wire [1:0] px_array_lo_hi_hi = {normal_entries_0_5_px, normal_entries_0_4_px}; // @[package.scala:45:27] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, normal_entries_0_3_px}; // @[package.scala:45:27] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {normal_entries_0_8_px, normal_entries_0_7_px}; // @[package.scala:45:27] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, normal_entries_0_6_px}; // @[package.scala:45:27] wire [1:0] px_array_hi_hi_hi = {normal_entries_0_11_px, normal_entries_0_10_px}; // @[package.scala:45:27] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, normal_entries_0_9_px}; // @[package.scala:45:27] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:121:49, :222:116, :224:116] wire [13:0] _px_array_T_4 = _px_array_T_2 & _px_array_T_3; // @[tlb.scala:224:{39,114,116}] wire [13:0] px_array_0 = _px_array_T_4; // @[tlb.scala:121:49, :224:114] wire [1:0] _eff_array_T = {2{prot_eff_0}}; // @[tlb.scala:121:49, :225:44] wire [1:0] eff_array_lo_lo_hi = {normal_entries_0_2_eff, normal_entries_0_1_eff}; // @[package.scala:45:27] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, normal_entries_0_0_eff}; // @[package.scala:45:27] wire [1:0] eff_array_lo_hi_hi = {normal_entries_0_5_eff, normal_entries_0_4_eff}; // @[package.scala:45:27] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, normal_entries_0_3_eff}; // @[package.scala:45:27] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {normal_entries_0_8_eff, normal_entries_0_7_eff}; // @[package.scala:45:27] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, normal_entries_0_6_eff}; // @[package.scala:45:27] wire [1:0] eff_array_hi_hi_hi = {normal_entries_0_11_eff, normal_entries_0_10_eff}; // @[package.scala:45:27] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, normal_entries_0_9_eff}; // @[package.scala:45:27] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] _eff_array_T_2 = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [13:0] eff_array_0 = _eff_array_T_2; // @[tlb.scala:121:49, :225:39] wire [1:0] _c_array_T = {2{cacheable_0}}; // @[tlb.scala:121:49, :226:44] wire [1:0] _GEN_19 = {normal_entries_0_2_c, normal_entries_0_1_c}; // @[package.scala:45:27] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [1:0] _GEN_20 = {normal_entries_0_5_c, normal_entries_0_4_c}; // @[package.scala:45:27] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_21 = {normal_entries_0_8_c, normal_entries_0_7_c}; // @[package.scala:45:27] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27] wire [1:0] _GEN_22 = {normal_entries_0_11_c, normal_entries_0_10_c}; // @[package.scala:45:27] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] _c_array_T_2 = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] c_array_0 = _c_array_T_2; // @[tlb.scala:121:49, :226:39] wire [13:0] _paa_array_if_cached_T = c_array_0; // @[tlb.scala:121:49, :229:61] wire [13:0] _pal_array_if_cached_T = c_array_0; // @[tlb.scala:121:49, :230:61] wire [13:0] _lrscAllowed_T = c_array_0; // @[tlb.scala:121:49, :252:38] wire [1:0] _paa_array_T = {2{prot_aa_0}}; // @[tlb.scala:121:49, :227:44] wire [1:0] paa_array_lo_lo_hi = {normal_entries_0_2_paa, normal_entries_0_1_paa}; // @[package.scala:45:27] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, normal_entries_0_0_paa}; // @[package.scala:45:27] wire [1:0] paa_array_lo_hi_hi = {normal_entries_0_5_paa, normal_entries_0_4_paa}; // @[package.scala:45:27] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, normal_entries_0_3_paa}; // @[package.scala:45:27] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {normal_entries_0_8_paa, normal_entries_0_7_paa}; // @[package.scala:45:27] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, normal_entries_0_6_paa}; // @[package.scala:45:27] wire [1:0] paa_array_hi_hi_hi = {normal_entries_0_11_paa, normal_entries_0_10_paa}; // @[package.scala:45:27] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, normal_entries_0_9_paa}; // @[package.scala:45:27] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] _paa_array_T_2 = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [13:0] paa_array_0 = _paa_array_T_2; // @[tlb.scala:121:49, :227:39] wire [1:0] _pal_array_T = {2{prot_al_0}}; // @[tlb.scala:121:49, :228:44] wire [1:0] pal_array_lo_lo_hi = {normal_entries_0_2_pal, normal_entries_0_1_pal}; // @[package.scala:45:27] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, normal_entries_0_0_pal}; // @[package.scala:45:27] wire [1:0] pal_array_lo_hi_hi = {normal_entries_0_5_pal, normal_entries_0_4_pal}; // @[package.scala:45:27] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, normal_entries_0_3_pal}; // @[package.scala:45:27] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {normal_entries_0_8_pal, normal_entries_0_7_pal}; // @[package.scala:45:27] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, normal_entries_0_6_pal}; // @[package.scala:45:27] wire [1:0] pal_array_hi_hi_hi = {normal_entries_0_11_pal, normal_entries_0_10_pal}; // @[package.scala:45:27] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, normal_entries_0_9_pal}; // @[package.scala:45:27] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] _pal_array_T_2 = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pal_array_0 = _pal_array_T_2; // @[tlb.scala:121:49, :228:39] wire [13:0] _paa_array_if_cached_T_1 = paa_array_0 | _paa_array_if_cached_T; // @[tlb.scala:121:49, :229:{56,61}] wire [13:0] paa_array_if_cached_0 = _paa_array_if_cached_T_1; // @[tlb.scala:121:49, :229:56] wire [13:0] _pal_array_if_cached_T_1 = pal_array_0 | _pal_array_if_cached_T; // @[tlb.scala:121:49, :230:{56,61}] wire [13:0] pal_array_if_cached_0 = _pal_array_if_cached_T_1; // @[tlb.scala:121:49, :230:56] wire _prefetchable_array_T = cacheable_0 & homogeneous_0; // @[tlb.scala:121:49, :231:61] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[tlb.scala:231:{61,80}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] _prefetchable_array_T_3 = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [13:0] prefetchable_array_0 = _prefetchable_array_T_3; // @[tlb.scala:121:49, :231:46] wire [3:0] _misaligned_T = 4'h1 << io_req_0_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[tlb.scala:233:89] wire [33:0] _misaligned_T_3 = {30'h0, io_req_0_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[tlb.scala:17:7, :19:14, :233:{56,89}] wire _misaligned_T_4 = |_misaligned_T_3; // @[tlb.scala:233:{56,97}] wire misaligned_0 = _misaligned_T_4; // @[tlb.scala:121:49, :233:97] wire _GEN_23 = io_req_0_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_23; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_0_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_24; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_24; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_24; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _cmd_lrsc_T_3 = _cmd_lrsc_T_2; // @[package.scala:81:59] wire cmd_lrsc_0 = _cmd_lrsc_T_3; // @[tlb.scala:121:49, :244:57] wire _GEN_25 = io_req_0_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_25; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_25; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_25; // @[package.scala:16:47] wire _GEN_26 = io_req_0_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_26; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_26; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = io_req_0_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_27; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_27; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_27; // @[package.scala:16:47] wire _GEN_28 = io_req_0_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_28; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_28; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_28; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_7 = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire cmd_amo_logical_0 = _cmd_amo_logical_T_7; // @[tlb.scala:121:49, :245:57] wire _GEN_29 = io_req_0_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_29; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_29; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = io_req_0_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_30; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_30; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = io_req_0_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_31; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_31; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_31; // @[package.scala:16:47] wire _GEN_32 = io_req_0_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_32; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_32; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = io_req_0_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_33; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_33; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_33; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_9 = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire cmd_amo_arithmetic_0 = _cmd_amo_arithmetic_T_9; // @[tlb.scala:121:49, :246:57] wire _cmd_read_T = io_req_0_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _cmd_read_T_1 = io_req_0_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire _cmd_read_T_24 = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire cmd_read_0 = _cmd_read_T_24; // @[Consts.scala:89:68] wire _cmd_write_T = io_req_0_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _cmd_write_T_1 = io_req_0_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire _cmd_write_T_22 = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire cmd_write_0 = _cmd_write_T_22; // @[Consts.scala:90:76] wire _cmd_write_perms_T_2 = cmd_write_0; // @[tlb.scala:121:49, :249:55] wire _cmd_write_perms_T = io_req_0_bits_cmd_0 == 5'h5; // @[tlb.scala:17:7, :250:51] wire cmd_write_perms_0 = _cmd_write_perms_T_2; // @[tlb.scala:121:49, :249:55] wire [13:0] lrscAllowed_0 = _lrscAllowed_T; // @[tlb.scala:121:49, :252:38] wire [13:0] _ae_array_T = misaligned_0 ? eff_array_0 : 14'h0; // @[tlb.scala:121:49, :254:8] wire [13:0] _ae_array_T_1 = ~lrscAllowed_0; // @[tlb.scala:121:49, :255:24] wire [13:0] _ae_array_T_2 = cmd_lrsc_0 ? _ae_array_T_1 : 14'h0; // @[tlb.scala:121:49, :255:{8,24}] wire [13:0] _ae_array_T_3 = _ae_array_T | _ae_array_T_2; // @[tlb.scala:254:{8,43}, :255:8] wire [13:0] ae_array_0 = _ae_array_T_3; // @[tlb.scala:121:49, :254:43] wire [13:0] _ae_ld_array_T = ~pr_array_0; // @[tlb.scala:121:49, :258:66] wire [13:0] _ae_ld_array_T_1 = ae_array_0 | _ae_ld_array_T; // @[tlb.scala:121:49, :258:{64,66}] wire [13:0] _ae_ld_array_T_2 = cmd_read_0 ? _ae_ld_array_T_1 : 14'h0; // @[tlb.scala:121:49, :258:{38,64}] wire [13:0] ae_ld_array_0 = _ae_ld_array_T_2; // @[tlb.scala:121:49, :258:38] wire [13:0] _io_resp_0_ae_ld_T = ae_ld_array_0; // @[tlb.scala:121:49, :298:46] wire [13:0] _ae_st_array_T = ~pw_array_0; // @[tlb.scala:121:49, :260:46] wire [13:0] _ae_st_array_T_1 = ae_array_0 | _ae_st_array_T; // @[tlb.scala:121:49, :260:{44,46}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms_0 ? _ae_st_array_T_1 : 14'h0; // @[tlb.scala:121:49, :260:{8,44}] wire [13:0] _ae_st_array_T_3 = ~pal_array_if_cached_0; // @[tlb.scala:121:49, :261:32] wire [13:0] _ae_st_array_T_4 = cmd_amo_logical_0 ? _ae_st_array_T_3 : 14'h0; // @[tlb.scala:121:49, :261:{8,32}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[tlb.scala:260:{8,65}, :261:8] wire [13:0] _ae_st_array_T_6 = ~paa_array_if_cached_0; // @[tlb.scala:121:49, :262:32] wire [13:0] _ae_st_array_T_7 = cmd_amo_arithmetic_0 ? _ae_st_array_T_6 : 14'h0; // @[tlb.scala:121:49, :262:{8,32}] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[tlb.scala:260:65, :261:62, :262:8] wire [13:0] ae_st_array_0 = _ae_st_array_T_8; // @[tlb.scala:121:49, :261:62] wire [13:0] _io_resp_0_ae_st_T = ae_st_array_0; // @[tlb.scala:121:49, :299:46] wire [13:0] _must_alloc_array_T = ~paa_array_0; // @[tlb.scala:121:49, :264:32] wire [13:0] _must_alloc_array_T_1 = cmd_amo_logical_0 ? _must_alloc_array_T : 14'h0; // @[tlb.scala:121:49, :264:{8,32}] wire [13:0] _must_alloc_array_T_2 = ~pal_array_0; // @[tlb.scala:121:49, :265:32] wire [13:0] _must_alloc_array_T_3 = cmd_amo_arithmetic_0 ? _must_alloc_array_T_2 : 14'h0; // @[tlb.scala:121:49, :265:{8,32}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[tlb.scala:264:{8,52}, :265:8] wire [13:0] _must_alloc_array_T_6 = {14{cmd_lrsc_0}}; // @[tlb.scala:121:49, :266:8] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[tlb.scala:264:52, :265:52, :266:8] wire [13:0] must_alloc_array_0 = _must_alloc_array_T_7; // @[tlb.scala:121:49, :265:52] wire _ma_ld_array_T = misaligned_0 & cmd_read_0; // @[tlb.scala:121:49, :267:53] wire [13:0] _ma_ld_array_T_1 = ~eff_array_0; // @[tlb.scala:121:49, :267:70] wire [13:0] _ma_ld_array_T_2 = _ma_ld_array_T ? _ma_ld_array_T_1 : 14'h0; // @[tlb.scala:267:{38,53,70}] wire [13:0] ma_ld_array_0 = _ma_ld_array_T_2; // @[tlb.scala:121:49, :267:38] wire _ma_st_array_T = misaligned_0 & cmd_write_0; // @[tlb.scala:121:49, :268:53] wire [13:0] _ma_st_array_T_1 = ~eff_array_0; // @[tlb.scala:121:49, :267:70, :268:70] wire [13:0] _ma_st_array_T_2 = _ma_st_array_T ? _ma_st_array_T_1 : 14'h0; // @[tlb.scala:268:{38,53,70}] wire [13:0] ma_st_array_0 = _ma_st_array_T_2; // @[tlb.scala:121:49, :268:38] wire [13:0] _pf_ld_array_T = r_array_0 | ptw_ae_array_0; // @[tlb.scala:121:49, :269:72] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[tlb.scala:269:{59,72}] wire [13:0] _pf_ld_array_T_2 = cmd_read_0 ? _pf_ld_array_T_1 : 14'h0; // @[tlb.scala:121:49, :269:{38,59}] wire [13:0] pf_ld_array_0 = _pf_ld_array_T_2; // @[tlb.scala:121:49, :269:38] wire [13:0] _pf_st_array_T = w_array_0 | ptw_ae_array_0; // @[tlb.scala:121:49, :270:72] wire [13:0] _pf_st_array_T_1 = ~_pf_st_array_T; // @[tlb.scala:270:{59,72}] wire [13:0] _pf_st_array_T_2 = cmd_write_perms_0 ? _pf_st_array_T_1 : 14'h0; // @[tlb.scala:121:49, :270:{38,59}] wire [13:0] pf_st_array_0 = _pf_st_array_T_2; // @[tlb.scala:121:49, :270:38] wire [13:0] _pf_inst_array_T = x_array_0 | ptw_ae_array_0; // @[tlb.scala:121:49, :271:50] wire [13:0] _pf_inst_array_T_1 = ~_pf_inst_array_T; // @[tlb.scala:271:{37,50}] wire [13:0] pf_inst_array_0 = _pf_inst_array_T_1; // @[tlb.scala:121:49, :271:37] wire [1:0] lo_lo = {sector_hits_0_1, sector_hits_0_0}; // @[OneHot.scala:22:45] wire [1:0] lo_hi = {sector_hits_0_3, sector_hits_0_2}; // @[OneHot.scala:22:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:22:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:22:45, :31:18] wire [1:0] hi_lo = {sector_hits_0_5, sector_hits_0_4}; // @[OneHot.scala:22:45] wire [1:0] hi_hi = {sector_hits_0_7, sector_hits_0_6}; // @[OneHot.scala:22:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:22:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:22:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = ~state_reg_set_left_older_1 & _state_reg_T_3; // @[Replacement.scala:196:33, :203:16, :218:7] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 & _state_reg_T_7; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? 3'h0 : _state_reg_T_9; // @[Replacement.scala:196:33, :202:12, :203:16] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = ~state_reg_set_left_older_2 & _state_reg_T_14; // @[Replacement.scala:196:33, :203:16, :218:7] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 & _state_reg_T_18; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] lo_3 = {superpage_hits_0_1, superpage_hits_0_0}; // @[OneHot.scala:22:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:22:45, :31:18] wire [1:0] hi_3 = {superpage_hits_0_3, superpage_hits_0_2}; // @[OneHot.scala:22:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:22:45, :30:18] wire [1:0] state_reg_touch_way_sized_1 = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire _state_reg_T_23 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_27 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23; // @[package.scala:163:13] wire _state_reg_T_25 = ~_state_reg_T_24; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_26 = ~state_reg_set_left_older_3 & _state_reg_T_25; // @[Replacement.scala:196:33, :203:16, :218:7] wire _state_reg_T_28 = _state_reg_T_27; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_29 = ~_state_reg_T_28; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_30 = state_reg_set_left_older_3 & _state_reg_T_29; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_26}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_31 = {state_reg_hi_3, _state_reg_T_30}; // @[Replacement.scala:202:12, :206:16] wire [13:0] _io_resp_0_pf_ld_T_1 = pf_ld_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :295:73] wire _io_resp_0_pf_ld_T_2 = |_io_resp_0_pf_ld_T_1; // @[tlb.scala:295:{73,84}] assign _io_resp_0_pf_ld_T_3 = _io_resp_0_pf_ld_T_2; // @[tlb.scala:295:{54,84}] assign io_resp_0_pf_ld_0 = _io_resp_0_pf_ld_T_3; // @[tlb.scala:17:7, :295:54] wire [13:0] _io_resp_0_pf_st_T_1 = pf_st_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :296:80] wire _io_resp_0_pf_st_T_2 = |_io_resp_0_pf_st_T_1; // @[tlb.scala:296:{80,91}] assign _io_resp_0_pf_st_T_3 = _io_resp_0_pf_st_T_2; // @[tlb.scala:296:{61,91}] assign io_resp_0_pf_st_0 = _io_resp_0_pf_st_T_3; // @[tlb.scala:17:7, :296:61] wire [13:0] _io_resp_0_pf_inst_T = pf_inst_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :297:58] wire _io_resp_0_pf_inst_T_1 = |_io_resp_0_pf_inst_T; // @[tlb.scala:297:{58,69}] assign _io_resp_0_pf_inst_T_2 = _io_resp_0_pf_inst_T_1; // @[tlb.scala:297:{37,69}] assign io_resp_0_pf_inst = _io_resp_0_pf_inst_T_2; // @[tlb.scala:17:7, :297:37] wire [13:0] _io_resp_0_ae_ld_T_1 = _io_resp_0_ae_ld_T & 14'h2000; // @[tlb.scala:121:49, :175:31, :298:{46,63}] assign _io_resp_0_ae_ld_T_2 = |_io_resp_0_ae_ld_T_1; // @[tlb.scala:298:{63,74}] assign io_resp_0_ae_ld_0 = _io_resp_0_ae_ld_T_2; // @[tlb.scala:17:7, :298:74] wire [13:0] _io_resp_0_ae_st_T_1 = _io_resp_0_ae_st_T & 14'h2000; // @[tlb.scala:121:49, :175:31, :299:{46,63}] assign _io_resp_0_ae_st_T_2 = |_io_resp_0_ae_st_T_1; // @[tlb.scala:299:{63,74}] assign io_resp_0_ae_st_0 = _io_resp_0_ae_st_T_2; // @[tlb.scala:17:7, :299:74] wire [13:0] _io_resp_0_ae_inst_T = ~px_array_0; // @[tlb.scala:121:49, :300:48] wire [13:0] _io_resp_0_ae_inst_T_1 = _io_resp_0_ae_inst_T; // @[tlb.scala:300:{46,48}] wire [13:0] _io_resp_0_ae_inst_T_2 = _io_resp_0_ae_inst_T_1 & 14'h2000; // @[tlb.scala:121:49, :175:31, :300:{46,63}] assign _io_resp_0_ae_inst_T_3 = |_io_resp_0_ae_inst_T_2; // @[tlb.scala:300:{63,74}] assign io_resp_0_ae_inst = _io_resp_0_ae_inst_T_3; // @[tlb.scala:17:7, :300:74] wire [13:0] _io_resp_0_ma_ld_T = ma_ld_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :301:43] assign _io_resp_0_ma_ld_T_1 = |_io_resp_0_ma_ld_T; // @[tlb.scala:301:{43,54}] assign io_resp_0_ma_ld_0 = _io_resp_0_ma_ld_T_1; // @[tlb.scala:17:7, :301:54] wire [13:0] _io_resp_0_ma_st_T = ma_st_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :302:43] assign _io_resp_0_ma_st_T_1 = |_io_resp_0_ma_st_T; // @[tlb.scala:302:{43,54}] assign io_resp_0_ma_st_0 = _io_resp_0_ma_st_T_1; // @[tlb.scala:17:7, :302:54] wire [13:0] _io_resp_0_cacheable_T = c_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :304:44] assign _io_resp_0_cacheable_T_1 = |_io_resp_0_cacheable_T; // @[tlb.scala:304:{44,55}] assign io_resp_0_cacheable_0 = _io_resp_0_cacheable_T_1; // @[tlb.scala:17:7, :304:55] wire [13:0] _io_resp_0_must_alloc_T = must_alloc_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :305:53] assign _io_resp_0_must_alloc_T_1 = |_io_resp_0_must_alloc_T; // @[tlb.scala:305:{53,64}] assign io_resp_0_must_alloc = _io_resp_0_must_alloc_T_1; // @[tlb.scala:17:7, :305:64] wire [13:0] _io_resp_0_prefetchable_T = prefetchable_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :306:55] wire _io_resp_0_prefetchable_T_1 = |_io_resp_0_prefetchable_T; // @[tlb.scala:306:{55,66}] assign _io_resp_0_prefetchable_T_2 = _io_resp_0_prefetchable_T_1; // @[tlb.scala:306:{66,70}] assign io_resp_0_prefetchable = _io_resp_0_prefetchable_T_2; // @[tlb.scala:17:7, :306:70] assign _io_resp_0_paddr_T_1 = {ppn_0, _io_resp_0_paddr_T}; // @[tlb.scala:121:49, :308:{28,57}] assign io_resp_0_paddr_0 = _io_resp_0_paddr_T_1; // @[tlb.scala:17:7, :308:28] OptimizationBarrier_EntryData mpu_ppn_data_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_data_WIRE_ppn), // @[tlb.scala:60:79] .io_x_u (_mpu_ppn_data_WIRE_u), // @[tlb.scala:60:79] .io_x_g (_mpu_ppn_data_WIRE_g), // @[tlb.scala:60:79] .io_x_ae (_mpu_ppn_data_WIRE_ae), // @[tlb.scala:60:79] .io_x_sw (_mpu_ppn_data_WIRE_sw), // @[tlb.scala:60:79] .io_x_sx (_mpu_ppn_data_WIRE_sx), // @[tlb.scala:60:79] .io_x_sr (_mpu_ppn_data_WIRE_sr), // @[tlb.scala:60:79] .io_x_pw (_mpu_ppn_data_WIRE_pw), // @[tlb.scala:60:79] .io_x_px (_mpu_ppn_data_WIRE_px), // @[tlb.scala:60:79] .io_x_pr (_mpu_ppn_data_WIRE_pr), // @[tlb.scala:60:79] .io_x_pal (_mpu_ppn_data_WIRE_pal), // @[tlb.scala:60:79] .io_x_paa (_mpu_ppn_data_WIRE_paa), // @[tlb.scala:60:79] .io_x_eff (_mpu_ppn_data_WIRE_eff), // @[tlb.scala:60:79] .io_x_c (_mpu_ppn_data_WIRE_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_mpu_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] PMPChecker_s3 pmp_0 ( // @[tlb.scala:152:40] .clock (clock), .reset (reset), .io_addr (mpu_physaddr_0[31:0]), // @[tlb.scala:121:49, :154:20] .io_size (io_req_0_bits_size_0) // @[tlb.scala:17:7] ); // @[tlb.scala:152:40] OptimizationBarrier_EntryData_1 ppn_data_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_2 ppn_data_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_2_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_2_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_2_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_2_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_2_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_2_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_2_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_2_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_2_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_2_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_2_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_2_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_2_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_2_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_2_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_3 ppn_data_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_4_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_4_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_4_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_4_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_4_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_4_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_4_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_4_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_4_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_4_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_4_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_4_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_4_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_4_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_4_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_4 ppn_data_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_6_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_6_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_6_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_6_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_6_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_6_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_6_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_6_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_6_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_6_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_6_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_6_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_6_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_6_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_6_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_5 ppn_data_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_8_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_8_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_8_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_8_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_8_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_8_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_8_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_8_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_8_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_8_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_8_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_8_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_8_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_8_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_8_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_6 ppn_data_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_10_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_10_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_10_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_10_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_10_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_10_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_10_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_10_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_10_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_10_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_10_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_10_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_10_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_10_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_10_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_7 ppn_data_barrier_6 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_12_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_12_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_12_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_12_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_12_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_12_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_12_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_12_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_12_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_12_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_12_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_12_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_12_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_12_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_12_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_8 ppn_data_barrier_7 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_14_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_14_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_14_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_14_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_14_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_14_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_14_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_14_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_14_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_14_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_14_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_14_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_14_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_14_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_14_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_9 ppn_data_barrier_8 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_16_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_16_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_16_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_16_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_16_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_16_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_16_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_16_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_16_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_16_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_16_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_16_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_16_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_16_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_16_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_10 ppn_data_barrier_9 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_18_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_18_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_18_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_18_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_18_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_18_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_18_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_18_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_18_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_18_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_18_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_18_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_18_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_18_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_18_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_11 ppn_data_barrier_10 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_20_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_20_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_20_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_20_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_20_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_20_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_20_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_20_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_20_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_20_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_20_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_20_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_20_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_20_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_20_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_12 ppn_data_barrier_11 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_22_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_22_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_22_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_22_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_22_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_22_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_22_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_22_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_22_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_22_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_22_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_22_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_22_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_22_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_22_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_13 ppn_data_barrier_12 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_ppn_data_WIRE_24_ppn), // @[tlb.scala:60:79] .io_x_u (_ppn_data_WIRE_24_u), // @[tlb.scala:60:79] .io_x_g (_ppn_data_WIRE_24_g), // @[tlb.scala:60:79] .io_x_ae (_ppn_data_WIRE_24_ae), // @[tlb.scala:60:79] .io_x_sw (_ppn_data_WIRE_24_sw), // @[tlb.scala:60:79] .io_x_sx (_ppn_data_WIRE_24_sx), // @[tlb.scala:60:79] .io_x_sr (_ppn_data_WIRE_24_sr), // @[tlb.scala:60:79] .io_x_pw (_ppn_data_WIRE_24_pw), // @[tlb.scala:60:79] .io_x_px (_ppn_data_WIRE_24_px), // @[tlb.scala:60:79] .io_x_pr (_ppn_data_WIRE_24_pr), // @[tlb.scala:60:79] .io_x_pal (_ppn_data_WIRE_24_pal), // @[tlb.scala:60:79] .io_x_paa (_ppn_data_WIRE_24_paa), // @[tlb.scala:60:79] .io_x_eff (_ppn_data_WIRE_24_eff), // @[tlb.scala:60:79] .io_x_c (_ppn_data_WIRE_24_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_ppn_data_WIRE_24_fragmented_superpage) // @[tlb.scala:60:79] ); // @[package.scala:267:25] OptimizationBarrier_EntryData_14 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_0_ppn), .io_y_u (_entries_WIRE_26_0_u), .io_y_g (_entries_WIRE_26_0_g), .io_y_ae (_entries_WIRE_26_0_ae), .io_y_sw (_entries_WIRE_26_0_sw), .io_y_sx (_entries_WIRE_26_0_sx), .io_y_sr (_entries_WIRE_26_0_sr), .io_y_pw (_entries_WIRE_26_0_pw), .io_y_px (_entries_WIRE_26_0_px), .io_y_pr (_entries_WIRE_26_0_pr), .io_y_pal (_entries_WIRE_26_0_pal), .io_y_paa (_entries_WIRE_26_0_paa), .io_y_eff (_entries_WIRE_26_0_eff), .io_y_c (_entries_WIRE_26_0_c), .io_y_fragmented_superpage (_entries_WIRE_26_0_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_15 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_2_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_2_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_2_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_2_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_2_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_2_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_2_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_2_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_2_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_2_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_2_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_2_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_2_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_1_ppn), .io_y_u (_entries_WIRE_26_1_u), .io_y_g (_entries_WIRE_26_1_g), .io_y_ae (_entries_WIRE_26_1_ae), .io_y_sw (_entries_WIRE_26_1_sw), .io_y_sx (_entries_WIRE_26_1_sx), .io_y_sr (_entries_WIRE_26_1_sr), .io_y_pw (_entries_WIRE_26_1_pw), .io_y_px (_entries_WIRE_26_1_px), .io_y_pr (_entries_WIRE_26_1_pr), .io_y_pal (_entries_WIRE_26_1_pal), .io_y_paa (_entries_WIRE_26_1_paa), .io_y_eff (_entries_WIRE_26_1_eff), .io_y_c (_entries_WIRE_26_1_c), .io_y_fragmented_superpage (_entries_WIRE_26_1_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_16 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_4_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_4_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_4_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_4_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_4_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_4_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_4_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_4_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_4_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_4_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_4_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_4_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_4_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_2_ppn), .io_y_u (_entries_WIRE_26_2_u), .io_y_g (_entries_WIRE_26_2_g), .io_y_ae (_entries_WIRE_26_2_ae), .io_y_sw (_entries_WIRE_26_2_sw), .io_y_sx (_entries_WIRE_26_2_sx), .io_y_sr (_entries_WIRE_26_2_sr), .io_y_pw (_entries_WIRE_26_2_pw), .io_y_px (_entries_WIRE_26_2_px), .io_y_pr (_entries_WIRE_26_2_pr), .io_y_pal (_entries_WIRE_26_2_pal), .io_y_paa (_entries_WIRE_26_2_paa), .io_y_eff (_entries_WIRE_26_2_eff), .io_y_c (_entries_WIRE_26_2_c), .io_y_fragmented_superpage (_entries_WIRE_26_2_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_17 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_6_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_6_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_6_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_6_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_6_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_6_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_6_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_6_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_6_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_6_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_6_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_6_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_6_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_3_ppn), .io_y_u (_entries_WIRE_26_3_u), .io_y_g (_entries_WIRE_26_3_g), .io_y_ae (_entries_WIRE_26_3_ae), .io_y_sw (_entries_WIRE_26_3_sw), .io_y_sx (_entries_WIRE_26_3_sx), .io_y_sr (_entries_WIRE_26_3_sr), .io_y_pw (_entries_WIRE_26_3_pw), .io_y_px (_entries_WIRE_26_3_px), .io_y_pr (_entries_WIRE_26_3_pr), .io_y_pal (_entries_WIRE_26_3_pal), .io_y_paa (_entries_WIRE_26_3_paa), .io_y_eff (_entries_WIRE_26_3_eff), .io_y_c (_entries_WIRE_26_3_c), .io_y_fragmented_superpage (_entries_WIRE_26_3_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_18 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_8_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_8_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_8_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_8_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_8_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_8_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_8_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_8_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_8_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_8_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_8_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_8_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_8_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_4_ppn), .io_y_u (_entries_WIRE_26_4_u), .io_y_g (_entries_WIRE_26_4_g), .io_y_ae (_entries_WIRE_26_4_ae), .io_y_sw (_entries_WIRE_26_4_sw), .io_y_sx (_entries_WIRE_26_4_sx), .io_y_sr (_entries_WIRE_26_4_sr), .io_y_pw (_entries_WIRE_26_4_pw), .io_y_px (_entries_WIRE_26_4_px), .io_y_pr (_entries_WIRE_26_4_pr), .io_y_pal (_entries_WIRE_26_4_pal), .io_y_paa (_entries_WIRE_26_4_paa), .io_y_eff (_entries_WIRE_26_4_eff), .io_y_c (_entries_WIRE_26_4_c), .io_y_fragmented_superpage (_entries_WIRE_26_4_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_19 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_10_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_10_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_10_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_10_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_10_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_10_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_10_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_10_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_10_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_10_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_10_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_10_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_10_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_5_ppn), .io_y_u (_entries_WIRE_26_5_u), .io_y_g (_entries_WIRE_26_5_g), .io_y_ae (_entries_WIRE_26_5_ae), .io_y_sw (_entries_WIRE_26_5_sw), .io_y_sx (_entries_WIRE_26_5_sx), .io_y_sr (_entries_WIRE_26_5_sr), .io_y_pw (_entries_WIRE_26_5_pw), .io_y_px (_entries_WIRE_26_5_px), .io_y_pr (_entries_WIRE_26_5_pr), .io_y_pal (_entries_WIRE_26_5_pal), .io_y_paa (_entries_WIRE_26_5_paa), .io_y_eff (_entries_WIRE_26_5_eff), .io_y_c (_entries_WIRE_26_5_c), .io_y_fragmented_superpage (_entries_WIRE_26_5_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_20 entries_barrier_6 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_12_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_12_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_12_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_12_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_12_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_12_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_12_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_12_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_12_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_12_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_12_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_12_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_12_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_12_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_6_ppn), .io_y_u (_entries_WIRE_26_6_u), .io_y_g (_entries_WIRE_26_6_g), .io_y_ae (_entries_WIRE_26_6_ae), .io_y_sw (_entries_WIRE_26_6_sw), .io_y_sx (_entries_WIRE_26_6_sx), .io_y_sr (_entries_WIRE_26_6_sr), .io_y_pw (_entries_WIRE_26_6_pw), .io_y_px (_entries_WIRE_26_6_px), .io_y_pr (_entries_WIRE_26_6_pr), .io_y_pal (_entries_WIRE_26_6_pal), .io_y_paa (_entries_WIRE_26_6_paa), .io_y_eff (_entries_WIRE_26_6_eff), .io_y_c (_entries_WIRE_26_6_c), .io_y_fragmented_superpage (_entries_WIRE_26_6_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_21 entries_barrier_7 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_14_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_14_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_14_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_14_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_14_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_14_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_14_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_14_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_14_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_14_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_14_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_14_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_14_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_14_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_7_ppn), .io_y_u (_entries_WIRE_26_7_u), .io_y_g (_entries_WIRE_26_7_g), .io_y_ae (_entries_WIRE_26_7_ae), .io_y_sw (_entries_WIRE_26_7_sw), .io_y_sx (_entries_WIRE_26_7_sx), .io_y_sr (_entries_WIRE_26_7_sr), .io_y_pw (_entries_WIRE_26_7_pw), .io_y_px (_entries_WIRE_26_7_px), .io_y_pr (_entries_WIRE_26_7_pr), .io_y_pal (_entries_WIRE_26_7_pal), .io_y_paa (_entries_WIRE_26_7_paa), .io_y_eff (_entries_WIRE_26_7_eff), .io_y_c (_entries_WIRE_26_7_c), .io_y_fragmented_superpage (_entries_WIRE_26_7_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_22 entries_barrier_8 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_16_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_16_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_16_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_16_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_16_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_16_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_16_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_16_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_16_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_16_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_16_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_16_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_16_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_16_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_8_ppn), .io_y_u (_entries_WIRE_26_8_u), .io_y_g (_entries_WIRE_26_8_g), .io_y_ae (_entries_WIRE_26_8_ae), .io_y_sw (_entries_WIRE_26_8_sw), .io_y_sx (_entries_WIRE_26_8_sx), .io_y_sr (_entries_WIRE_26_8_sr), .io_y_pw (_entries_WIRE_26_8_pw), .io_y_px (_entries_WIRE_26_8_px), .io_y_pr (_entries_WIRE_26_8_pr), .io_y_pal (_entries_WIRE_26_8_pal), .io_y_paa (_entries_WIRE_26_8_paa), .io_y_eff (_entries_WIRE_26_8_eff), .io_y_c (_entries_WIRE_26_8_c), .io_y_fragmented_superpage (_entries_WIRE_26_8_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_23 entries_barrier_9 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_18_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_18_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_18_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_18_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_18_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_18_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_18_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_18_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_18_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_18_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_18_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_18_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_18_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_18_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_9_ppn), .io_y_u (_entries_WIRE_26_9_u), .io_y_g (_entries_WIRE_26_9_g), .io_y_ae (_entries_WIRE_26_9_ae), .io_y_sw (_entries_WIRE_26_9_sw), .io_y_sx (_entries_WIRE_26_9_sx), .io_y_sr (_entries_WIRE_26_9_sr), .io_y_pw (_entries_WIRE_26_9_pw), .io_y_px (_entries_WIRE_26_9_px), .io_y_pr (_entries_WIRE_26_9_pr), .io_y_pal (_entries_WIRE_26_9_pal), .io_y_paa (_entries_WIRE_26_9_paa), .io_y_eff (_entries_WIRE_26_9_eff), .io_y_c (_entries_WIRE_26_9_c), .io_y_fragmented_superpage (_entries_WIRE_26_9_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_24 entries_barrier_10 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_20_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_20_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_20_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_20_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_20_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_20_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_20_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_20_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_20_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_20_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_20_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_20_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_20_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_20_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_10_ppn), .io_y_u (_entries_WIRE_26_10_u), .io_y_g (_entries_WIRE_26_10_g), .io_y_ae (_entries_WIRE_26_10_ae), .io_y_sw (_entries_WIRE_26_10_sw), .io_y_sx (_entries_WIRE_26_10_sx), .io_y_sr (_entries_WIRE_26_10_sr), .io_y_pw (_entries_WIRE_26_10_pw), .io_y_px (_entries_WIRE_26_10_px), .io_y_pr (_entries_WIRE_26_10_pr), .io_y_pal (_entries_WIRE_26_10_pal), .io_y_paa (_entries_WIRE_26_10_paa), .io_y_eff (_entries_WIRE_26_10_eff), .io_y_c (_entries_WIRE_26_10_c), .io_y_fragmented_superpage (_entries_WIRE_26_10_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_25 entries_barrier_11 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_22_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_22_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_22_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_22_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_22_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_22_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_22_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_22_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_22_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_22_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_22_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_22_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_22_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_22_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_11_ppn), .io_y_u (_entries_WIRE_26_11_u), .io_y_g (_entries_WIRE_26_11_g), .io_y_ae (_entries_WIRE_26_11_ae), .io_y_sw (_entries_WIRE_26_11_sw), .io_y_sx (_entries_WIRE_26_11_sx), .io_y_sr (_entries_WIRE_26_11_sr), .io_y_pw (_entries_WIRE_26_11_pw), .io_y_px (_entries_WIRE_26_11_px), .io_y_pr (_entries_WIRE_26_11_pr), .io_y_pal (_entries_WIRE_26_11_pal), .io_y_paa (_entries_WIRE_26_11_paa), .io_y_eff (_entries_WIRE_26_11_eff), .io_y_c (_entries_WIRE_26_11_c), .io_y_fragmented_superpage (_entries_WIRE_26_11_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_26 entries_barrier_12 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_24_ppn), // @[tlb.scala:60:79] .io_x_u (_entries_WIRE_24_u), // @[tlb.scala:60:79] .io_x_g (_entries_WIRE_24_g), // @[tlb.scala:60:79] .io_x_ae (_entries_WIRE_24_ae), // @[tlb.scala:60:79] .io_x_sw (_entries_WIRE_24_sw), // @[tlb.scala:60:79] .io_x_sx (_entries_WIRE_24_sx), // @[tlb.scala:60:79] .io_x_sr (_entries_WIRE_24_sr), // @[tlb.scala:60:79] .io_x_pw (_entries_WIRE_24_pw), // @[tlb.scala:60:79] .io_x_px (_entries_WIRE_24_px), // @[tlb.scala:60:79] .io_x_pr (_entries_WIRE_24_pr), // @[tlb.scala:60:79] .io_x_pal (_entries_WIRE_24_pal), // @[tlb.scala:60:79] .io_x_paa (_entries_WIRE_24_paa), // @[tlb.scala:60:79] .io_x_eff (_entries_WIRE_24_eff), // @[tlb.scala:60:79] .io_x_c (_entries_WIRE_24_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_entries_WIRE_24_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_entries_WIRE_26_12_ppn), .io_y_u (_entries_WIRE_26_12_u), .io_y_g (_entries_WIRE_26_12_g), .io_y_ae (_entries_WIRE_26_12_ae), .io_y_sw (_entries_WIRE_26_12_sw), .io_y_sx (_entries_WIRE_26_12_sx), .io_y_sr (_entries_WIRE_26_12_sr), .io_y_pw (_entries_WIRE_26_12_pw), .io_y_px (_entries_WIRE_26_12_px), .io_y_pr (_entries_WIRE_26_12_pr), .io_y_pal (_entries_WIRE_26_12_pal), .io_y_paa (_entries_WIRE_26_12_paa), .io_y_eff (_entries_WIRE_26_12_eff), .io_y_c (_entries_WIRE_26_12_c), .io_y_fragmented_superpage (_entries_WIRE_26_12_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_27 normal_entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_0_ppn), .io_y_u (_normal_entries_WIRE_24_0_u), .io_y_g (_normal_entries_WIRE_24_0_g), .io_y_ae (_normal_entries_WIRE_24_0_ae), .io_y_sw (_normal_entries_WIRE_24_0_sw), .io_y_sx (_normal_entries_WIRE_24_0_sx), .io_y_sr (_normal_entries_WIRE_24_0_sr), .io_y_pw (_normal_entries_WIRE_24_0_pw), .io_y_px (_normal_entries_WIRE_24_0_px), .io_y_pr (_normal_entries_WIRE_24_0_pr), .io_y_pal (_normal_entries_WIRE_24_0_pal), .io_y_paa (_normal_entries_WIRE_24_0_paa), .io_y_eff (_normal_entries_WIRE_24_0_eff), .io_y_c (_normal_entries_WIRE_24_0_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_0_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_28 normal_entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_2_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_2_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_2_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_2_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_2_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_2_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_2_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_2_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_2_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_2_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_2_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_2_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_2_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_2_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_1_ppn), .io_y_u (_normal_entries_WIRE_24_1_u), .io_y_g (_normal_entries_WIRE_24_1_g), .io_y_ae (_normal_entries_WIRE_24_1_ae), .io_y_sw (_normal_entries_WIRE_24_1_sw), .io_y_sx (_normal_entries_WIRE_24_1_sx), .io_y_sr (_normal_entries_WIRE_24_1_sr), .io_y_pw (_normal_entries_WIRE_24_1_pw), .io_y_px (_normal_entries_WIRE_24_1_px), .io_y_pr (_normal_entries_WIRE_24_1_pr), .io_y_pal (_normal_entries_WIRE_24_1_pal), .io_y_paa (_normal_entries_WIRE_24_1_paa), .io_y_eff (_normal_entries_WIRE_24_1_eff), .io_y_c (_normal_entries_WIRE_24_1_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_1_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_29 normal_entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_4_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_4_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_4_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_4_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_4_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_4_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_4_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_4_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_4_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_4_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_4_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_4_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_4_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_4_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_2_ppn), .io_y_u (_normal_entries_WIRE_24_2_u), .io_y_g (_normal_entries_WIRE_24_2_g), .io_y_ae (_normal_entries_WIRE_24_2_ae), .io_y_sw (_normal_entries_WIRE_24_2_sw), .io_y_sx (_normal_entries_WIRE_24_2_sx), .io_y_sr (_normal_entries_WIRE_24_2_sr), .io_y_pw (_normal_entries_WIRE_24_2_pw), .io_y_px (_normal_entries_WIRE_24_2_px), .io_y_pr (_normal_entries_WIRE_24_2_pr), .io_y_pal (_normal_entries_WIRE_24_2_pal), .io_y_paa (_normal_entries_WIRE_24_2_paa), .io_y_eff (_normal_entries_WIRE_24_2_eff), .io_y_c (_normal_entries_WIRE_24_2_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_2_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_30 normal_entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_6_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_6_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_6_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_6_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_6_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_6_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_6_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_6_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_6_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_6_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_6_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_6_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_6_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_6_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_3_ppn), .io_y_u (_normal_entries_WIRE_24_3_u), .io_y_g (_normal_entries_WIRE_24_3_g), .io_y_ae (_normal_entries_WIRE_24_3_ae), .io_y_sw (_normal_entries_WIRE_24_3_sw), .io_y_sx (_normal_entries_WIRE_24_3_sx), .io_y_sr (_normal_entries_WIRE_24_3_sr), .io_y_pw (_normal_entries_WIRE_24_3_pw), .io_y_px (_normal_entries_WIRE_24_3_px), .io_y_pr (_normal_entries_WIRE_24_3_pr), .io_y_pal (_normal_entries_WIRE_24_3_pal), .io_y_paa (_normal_entries_WIRE_24_3_paa), .io_y_eff (_normal_entries_WIRE_24_3_eff), .io_y_c (_normal_entries_WIRE_24_3_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_3_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_31 normal_entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_8_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_8_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_8_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_8_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_8_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_8_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_8_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_8_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_8_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_8_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_8_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_8_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_8_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_8_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_4_ppn), .io_y_u (_normal_entries_WIRE_24_4_u), .io_y_g (_normal_entries_WIRE_24_4_g), .io_y_ae (_normal_entries_WIRE_24_4_ae), .io_y_sw (_normal_entries_WIRE_24_4_sw), .io_y_sx (_normal_entries_WIRE_24_4_sx), .io_y_sr (_normal_entries_WIRE_24_4_sr), .io_y_pw (_normal_entries_WIRE_24_4_pw), .io_y_px (_normal_entries_WIRE_24_4_px), .io_y_pr (_normal_entries_WIRE_24_4_pr), .io_y_pal (_normal_entries_WIRE_24_4_pal), .io_y_paa (_normal_entries_WIRE_24_4_paa), .io_y_eff (_normal_entries_WIRE_24_4_eff), .io_y_c (_normal_entries_WIRE_24_4_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_4_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_32 normal_entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_10_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_10_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_10_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_10_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_10_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_10_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_10_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_10_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_10_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_10_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_10_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_10_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_10_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_10_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_5_ppn), .io_y_u (_normal_entries_WIRE_24_5_u), .io_y_g (_normal_entries_WIRE_24_5_g), .io_y_ae (_normal_entries_WIRE_24_5_ae), .io_y_sw (_normal_entries_WIRE_24_5_sw), .io_y_sx (_normal_entries_WIRE_24_5_sx), .io_y_sr (_normal_entries_WIRE_24_5_sr), .io_y_pw (_normal_entries_WIRE_24_5_pw), .io_y_px (_normal_entries_WIRE_24_5_px), .io_y_pr (_normal_entries_WIRE_24_5_pr), .io_y_pal (_normal_entries_WIRE_24_5_pal), .io_y_paa (_normal_entries_WIRE_24_5_paa), .io_y_eff (_normal_entries_WIRE_24_5_eff), .io_y_c (_normal_entries_WIRE_24_5_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_5_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_33 normal_entries_barrier_6 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_12_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_12_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_12_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_12_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_12_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_12_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_12_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_12_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_12_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_12_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_12_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_12_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_12_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_12_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_6_ppn), .io_y_u (_normal_entries_WIRE_24_6_u), .io_y_g (_normal_entries_WIRE_24_6_g), .io_y_ae (_normal_entries_WIRE_24_6_ae), .io_y_sw (_normal_entries_WIRE_24_6_sw), .io_y_sx (_normal_entries_WIRE_24_6_sx), .io_y_sr (_normal_entries_WIRE_24_6_sr), .io_y_pw (_normal_entries_WIRE_24_6_pw), .io_y_px (_normal_entries_WIRE_24_6_px), .io_y_pr (_normal_entries_WIRE_24_6_pr), .io_y_pal (_normal_entries_WIRE_24_6_pal), .io_y_paa (_normal_entries_WIRE_24_6_paa), .io_y_eff (_normal_entries_WIRE_24_6_eff), .io_y_c (_normal_entries_WIRE_24_6_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_6_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_34 normal_entries_barrier_7 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_14_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_14_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_14_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_14_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_14_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_14_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_14_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_14_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_14_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_14_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_14_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_14_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_14_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_14_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_7_ppn), .io_y_u (_normal_entries_WIRE_24_7_u), .io_y_g (_normal_entries_WIRE_24_7_g), .io_y_ae (_normal_entries_WIRE_24_7_ae), .io_y_sw (_normal_entries_WIRE_24_7_sw), .io_y_sx (_normal_entries_WIRE_24_7_sx), .io_y_sr (_normal_entries_WIRE_24_7_sr), .io_y_pw (_normal_entries_WIRE_24_7_pw), .io_y_px (_normal_entries_WIRE_24_7_px), .io_y_pr (_normal_entries_WIRE_24_7_pr), .io_y_pal (_normal_entries_WIRE_24_7_pal), .io_y_paa (_normal_entries_WIRE_24_7_paa), .io_y_eff (_normal_entries_WIRE_24_7_eff), .io_y_c (_normal_entries_WIRE_24_7_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_7_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_35 normal_entries_barrier_8 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_16_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_16_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_16_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_16_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_16_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_16_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_16_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_16_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_16_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_16_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_16_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_16_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_16_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_16_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_8_ppn), .io_y_u (_normal_entries_WIRE_24_8_u), .io_y_g (_normal_entries_WIRE_24_8_g), .io_y_ae (_normal_entries_WIRE_24_8_ae), .io_y_sw (_normal_entries_WIRE_24_8_sw), .io_y_sx (_normal_entries_WIRE_24_8_sx), .io_y_sr (_normal_entries_WIRE_24_8_sr), .io_y_pw (_normal_entries_WIRE_24_8_pw), .io_y_px (_normal_entries_WIRE_24_8_px), .io_y_pr (_normal_entries_WIRE_24_8_pr), .io_y_pal (_normal_entries_WIRE_24_8_pal), .io_y_paa (_normal_entries_WIRE_24_8_paa), .io_y_eff (_normal_entries_WIRE_24_8_eff), .io_y_c (_normal_entries_WIRE_24_8_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_8_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_36 normal_entries_barrier_9 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_18_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_18_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_18_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_18_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_18_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_18_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_18_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_18_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_18_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_18_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_18_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_18_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_18_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_18_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_9_ppn), .io_y_u (_normal_entries_WIRE_24_9_u), .io_y_g (_normal_entries_WIRE_24_9_g), .io_y_ae (_normal_entries_WIRE_24_9_ae), .io_y_sw (_normal_entries_WIRE_24_9_sw), .io_y_sx (_normal_entries_WIRE_24_9_sx), .io_y_sr (_normal_entries_WIRE_24_9_sr), .io_y_pw (_normal_entries_WIRE_24_9_pw), .io_y_px (_normal_entries_WIRE_24_9_px), .io_y_pr (_normal_entries_WIRE_24_9_pr), .io_y_pal (_normal_entries_WIRE_24_9_pal), .io_y_paa (_normal_entries_WIRE_24_9_paa), .io_y_eff (_normal_entries_WIRE_24_9_eff), .io_y_c (_normal_entries_WIRE_24_9_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_9_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_37 normal_entries_barrier_10 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_20_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_20_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_20_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_20_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_20_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_20_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_20_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_20_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_20_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_20_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_20_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_20_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_20_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_20_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_10_ppn), .io_y_u (_normal_entries_WIRE_24_10_u), .io_y_g (_normal_entries_WIRE_24_10_g), .io_y_ae (_normal_entries_WIRE_24_10_ae), .io_y_sw (_normal_entries_WIRE_24_10_sw), .io_y_sx (_normal_entries_WIRE_24_10_sx), .io_y_sr (_normal_entries_WIRE_24_10_sr), .io_y_pw (_normal_entries_WIRE_24_10_pw), .io_y_px (_normal_entries_WIRE_24_10_px), .io_y_pr (_normal_entries_WIRE_24_10_pr), .io_y_pal (_normal_entries_WIRE_24_10_pal), .io_y_paa (_normal_entries_WIRE_24_10_paa), .io_y_eff (_normal_entries_WIRE_24_10_eff), .io_y_c (_normal_entries_WIRE_24_10_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_10_fragmented_superpage) ); // @[package.scala:267:25] OptimizationBarrier_EntryData_38 normal_entries_barrier_11 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_normal_entries_WIRE_22_ppn), // @[tlb.scala:60:79] .io_x_u (_normal_entries_WIRE_22_u), // @[tlb.scala:60:79] .io_x_g (_normal_entries_WIRE_22_g), // @[tlb.scala:60:79] .io_x_ae (_normal_entries_WIRE_22_ae), // @[tlb.scala:60:79] .io_x_sw (_normal_entries_WIRE_22_sw), // @[tlb.scala:60:79] .io_x_sx (_normal_entries_WIRE_22_sx), // @[tlb.scala:60:79] .io_x_sr (_normal_entries_WIRE_22_sr), // @[tlb.scala:60:79] .io_x_pw (_normal_entries_WIRE_22_pw), // @[tlb.scala:60:79] .io_x_px (_normal_entries_WIRE_22_px), // @[tlb.scala:60:79] .io_x_pr (_normal_entries_WIRE_22_pr), // @[tlb.scala:60:79] .io_x_pal (_normal_entries_WIRE_22_pal), // @[tlb.scala:60:79] .io_x_paa (_normal_entries_WIRE_22_paa), // @[tlb.scala:60:79] .io_x_eff (_normal_entries_WIRE_22_eff), // @[tlb.scala:60:79] .io_x_c (_normal_entries_WIRE_22_c), // @[tlb.scala:60:79] .io_x_fragmented_superpage (_normal_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:60:79] .io_y_ppn (_normal_entries_WIRE_24_11_ppn), .io_y_u (_normal_entries_WIRE_24_11_u), .io_y_g (_normal_entries_WIRE_24_11_g), .io_y_ae (_normal_entries_WIRE_24_11_ae), .io_y_sw (_normal_entries_WIRE_24_11_sw), .io_y_sx (_normal_entries_WIRE_24_11_sx), .io_y_sr (_normal_entries_WIRE_24_11_sr), .io_y_pw (_normal_entries_WIRE_24_11_pw), .io_y_px (_normal_entries_WIRE_24_11_px), .io_y_pr (_normal_entries_WIRE_24_11_pr), .io_y_pal (_normal_entries_WIRE_24_11_pal), .io_y_paa (_normal_entries_WIRE_24_11_paa), .io_y_eff (_normal_entries_WIRE_24_11_eff), .io_y_c (_normal_entries_WIRE_24_11_c), .io_y_fragmented_superpage (_normal_entries_WIRE_24_11_fragmented_superpage) ); // @[package.scala:267:25] assign io_resp_0_paddr = io_resp_0_paddr_0; // @[tlb.scala:17:7] assign io_resp_0_pf_ld = io_resp_0_pf_ld_0; // @[tlb.scala:17:7] assign io_resp_0_pf_st = io_resp_0_pf_st_0; // @[tlb.scala:17:7] assign io_resp_0_ae_ld = io_resp_0_ae_ld_0; // @[tlb.scala:17:7] assign io_resp_0_ae_st = io_resp_0_ae_st_0; // @[tlb.scala:17:7] assign io_resp_0_ma_ld = io_resp_0_ma_ld_0; // @[tlb.scala:17:7] assign io_resp_0_ma_st = io_resp_0_ma_st_0; // @[tlb.scala:17:7] assign io_resp_0_cacheable = io_resp_0_cacheable_0; // @[tlb.scala:17:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[tlb.scala:17:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_58 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} inst input_buffer of InputBuffer_58 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) inst route_arbiter of Arbiter2_RouteComputerReq_12 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _T_12 = and(io.router_req.ready, io.router_req.valid) when _T_12 : node _T_13 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_13, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_17 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_17 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_18 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_18 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2] wire vcalloc_vals : UInt<1>[2] node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0)) node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11) node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_19 = and(io.router_req.ready, io.router_req.valid) when _T_19 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1]) when _T_20 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = bits(vcalloc_sel, 0, 0) node _mask_T_6 = bits(vcalloc_sel, 1, 1) node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_7, _mask_T_8) wire _mask_WIRE : UInt<2> connect _mask_WIRE, _mask_T_9 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}} wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2] node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10 connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2] node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[2] node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1] node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16 wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_34 connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_19 : UInt<4> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) wire _io_vcalloc_req_bits_WIRE_20 : UInt<2> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) wire _io_vcalloc_req_bits_WIRE_21 : UInt<4> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_43 connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_46 connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].flow, states[0].flow node _T_21 = bits(vcalloc_sel, 0, 0) node _T_22 = and(vcalloc_vals[0], _T_21) node _T_23 = and(_T_22, io.vcalloc_req.ready) when _T_23 : connect states[0].g, UInt<3>(0h3) node _T_24 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_24 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, io.router_resp.vc_sel.`4` node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].flow, states[1].flow node _T_25 = bits(vcalloc_sel, 1, 1) node _T_26 = and(vcalloc_vals[1], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[1].g, UInt<3>(0h3) node _T_28 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_28 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, io.router_resp.vc_sel.`4` node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready) node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1) connect io.debug.va_stall, _io_debug_va_stall_T_3 node _T_29 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_29 : node _T_30 = bits(vcalloc_sel, 0, 0) when _T_30 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].g, UInt<3>(0h3) node _T_31 = bits(vcalloc_sel, 1, 1) when _T_31 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_143 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node _credit_available_T = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node _credit_available_T_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0]) node _credit_available_T_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0]) node _credit_available_T_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_hi = cat(states[0].vc_sel.`4`[0], _credit_available_T_3) node credit_available_hi = cat(credit_available_hi_hi, _credit_available_T_2) node _credit_available_T_4 = cat(credit_available_hi, credit_available_lo) node _credit_available_T_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node _credit_available_T_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node _credit_available_T_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_1 = cat(_credit_available_T_6, _credit_available_T_5) node credit_available_hi_hi_1 = cat(io.out_credit_available.`4`[0], _credit_available_T_8) node credit_available_hi_1 = cat(credit_available_hi_hi_1, _credit_available_T_7) node _credit_available_T_9 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_32 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_33 = and(_T_32, input_buffer.io.deq[0].bits.tail) when _T_33 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node _credit_available_T_11 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node _credit_available_T_12 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node _credit_available_T_13 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node _credit_available_T_14 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_2 = cat(_credit_available_T_12, _credit_available_T_11) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`4`[0], _credit_available_T_14) node credit_available_hi_2 = cat(credit_available_hi_hi_2, _credit_available_T_13) node _credit_available_T_15 = cat(credit_available_hi_2, credit_available_lo_2) node _credit_available_T_16 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_17 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node _credit_available_T_18 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node _credit_available_T_19 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_3 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_hi_3 = cat(io.out_credit_available.`4`[0], _credit_available_T_19) node credit_available_hi_3 = cat(credit_available_hi_hi_3, _credit_available_T_18) node _credit_available_T_20 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_34 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_35 = and(_T_34, input_buffer.io.deq[1].bits.tail) when _T_35 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_5 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5 node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_7 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1) connect salloc_outs[0].vid, _salloc_outs_0_vid_T node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _vc_sel_WIRE : UInt<1>[2] node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_4 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_7 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_3 : UInt<1>[2] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_10 connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4 node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_13 connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5 connect vc_sel.`1`, _vc_sel_WIRE_3 wire _vc_sel_WIRE_6 : UInt<1>[2] node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_16 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_19 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 connect vc_sel.`2`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_9 : UInt<1>[2] node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_22 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_25 = or(_vc_sel_T_23, _vc_sel_T_24) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_25 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 connect vc_sel.`3`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_12 : UInt<1>[1] node _vc_sel_T_26 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_26, _vc_sel_T_27) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_28 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 connect vc_sel.`4`, _vc_sel_WIRE_12 node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_3 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1) node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0)) node _virt_channel_T_9 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0)) node _virt_channel_T_10 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0)) node _virt_channel_T_11 = mux(channel_oh_3, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_12 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_13 = or(_virt_channel_T_8, _virt_channel_T_9) node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_10) node _virt_channel_T_15 = or(_virt_channel_T_14, _virt_channel_T_11) node _virt_channel_T_16 = or(_virt_channel_T_15, _virt_channel_T_12) wire virt_channel : UInt<1> connect virt_channel, _virt_channel_T_16 node _T_36 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_36 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3) wire _salloc_outs_0_flit_payload_WIRE : UInt<37> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[0], UInt<1>(0h0) connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) node _T_37 = asUInt(reset) when _T_37 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0)
module InputUnit_58( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_1_1; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_3_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_2 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_169 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_184 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_169( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_184 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_150 = or(UInt<1>(0h0), _T_149) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_148, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_10) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_11) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_12) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_13) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_193 = shr(io.in.a.bits.source, 3) node _T_194 = eq(_T_193, UInt<3>(0h4)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_14) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0)) node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = or(_T_202, _T_203) node _T_211 = or(_T_210, _T_204) node _T_212 = or(_T_211, _T_205) node _T_213 = or(_T_212, _T_206) node _T_214 = or(_T_213, _T_207) node _T_215 = or(_T_214, _T_208) node _T_216 = or(_T_215, _T_209) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_15) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_16) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_17) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_18) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_290 = shr(io.in.a.bits.source, 3) node _T_291 = eq(_T_290, UInt<3>(0h4)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_19) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_298 = or(_T_265, _T_271) node _T_299 = or(_T_298, _T_277) node _T_300 = or(_T_299, _T_283) node _T_301 = or(_T_300, _T_289) node _T_302 = or(_T_301, _T_295) node _T_303 = or(_T_302, _T_296) node _T_304 = or(_T_303, _T_297) node _T_305 = and(_T_264, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = and(_T_308, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = and(_T_306, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_322, UInt<1>(0h1), "") : assert_10 node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_20) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<1>(0h1)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_21) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h2)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_22) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<2>(0h3)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_23) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_351 = shr(io.in.a.bits.source, 3) node _T_352 = eq(_T_351, UInt<3>(0h4)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_24) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_326 connect _WIRE_2[1], _T_332 connect _WIRE_2[2], _T_338 connect _WIRE_2[3], _T_344 connect _WIRE_2[4], _T_350 connect _WIRE_2[5], _T_356 connect _WIRE_2[6], _T_357 connect _WIRE_2[7], _T_358 node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0)) node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = or(_T_360, _T_361) node _T_369 = or(_T_368, _T_362) node _T_370 = or(_T_369, _T_363) node _T_371 = or(_T_370, _T_364) node _T_372 = or(_T_371, _T_365) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_374 node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = or(_T_383, _T_388) node _T_390 = and(_T_378, _T_389) node _T_391 = or(UInt<1>(0h0), _T_390) node _T_392 = and(_WIRE_3, _T_391) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_392, UInt<1>(0h1), "") : assert_11 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(source_ok, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_399, UInt<1>(0h1), "") : assert_13 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(is_aligned, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_406, UInt<1>(0h1), "") : assert_15 node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_410, UInt<1>(0h1), "") : assert_16 node _T_414 = not(io.in.a.bits.mask) node _T_415 = eq(_T_414, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_415, UInt<1>(0h1), "") : assert_17 node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_419, UInt<1>(0h1), "") : assert_18 node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_423 : node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_25) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_433 = and(_T_431, _T_432) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_434 = shr(io.in.a.bits.source, 2) node _T_435 = eq(_T_434, UInt<1>(0h1)) node _T_436 = leq(UInt<1>(0h0), uncommonBits_26) node _T_437 = and(_T_435, _T_436) node _T_438 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_439 = and(_T_437, _T_438) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<2>(0h2)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_27) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<2>(0h3)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_28) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<3>(0h4)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_29) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_460 = or(_T_427, _T_433) node _T_461 = or(_T_460, _T_439) node _T_462 = or(_T_461, _T_445) node _T_463 = or(_T_462, _T_451) node _T_464 = or(_T_463, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = and(_T_426, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_468, UInt<1>(0h1), "") : assert_19 node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_474 = and(_T_472, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = or(_T_480, _T_485) node _T_487 = and(_T_475, _T_486) node _T_488 = or(UInt<1>(0h0), _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_488, UInt<1>(0h1), "") : assert_20 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(source_ok, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_498, UInt<1>(0h1), "") : assert_23 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_502, UInt<1>(0h1), "") : assert_24 node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_T_506, UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_506, UInt<1>(0h1), "") : assert_25 node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_510 : node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_30) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<1>(0h1)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_31) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h2)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_32) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_533 = shr(io.in.a.bits.source, 2) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_33) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<3>(0h4)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_34) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_547 = or(_T_514, _T_520) node _T_548 = or(_T_547, _T_526) node _T_549 = or(_T_548, _T_532) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_544) node _T_552 = or(_T_551, _T_545) node _T_553 = or(_T_552, _T_546) node _T_554 = and(_T_513, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = or(_T_564, _T_569) node _T_571 = and(_T_559, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = and(_T_555, _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_573, UInt<1>(0h1), "") : assert_26 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_583, UInt<1>(0h1), "") : assert_29 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_587, UInt<1>(0h1), "") : assert_30 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_35) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_620 = shr(io.in.a.bits.source, 3) node _T_621 = eq(_T_620, UInt<3>(0h4)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_625) node _T_633 = or(_T_632, _T_626) node _T_634 = or(_T_633, _T_627) node _T_635 = and(_T_594, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_639 = and(_T_637, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_642 = cvt(_T_641) node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0))) node _T_644 = asSInt(_T_643) node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0))) node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = or(_T_645, _T_650) node _T_652 = and(_T_640, _T_651) node _T_653 = or(UInt<1>(0h0), _T_652) node _T_654 = and(_T_636, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_654, UInt<1>(0h1), "") : assert_31 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(source_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(is_aligned, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_664, UInt<1>(0h1), "") : assert_34 node _T_668 = not(mask) node _T_669 = and(io.in.a.bits.mask, _T_668) node _T_670 = eq(_T_669, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_670, UInt<1>(0h1), "") : assert_35 node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_674 : node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_679 = shr(io.in.a.bits.source, 2) node _T_680 = eq(_T_679, UInt<1>(0h0)) node _T_681 = leq(UInt<1>(0h0), uncommonBits_40) node _T_682 = and(_T_680, _T_681) node _T_683 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_684 = and(_T_682, _T_683) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_41) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<2>(0h2)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_42) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h3)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_43) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_703 = shr(io.in.a.bits.source, 3) node _T_704 = eq(_T_703, UInt<3>(0h4)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_44) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_711 = or(_T_678, _T_684) node _T_712 = or(_T_711, _T_690) node _T_713 = or(_T_712, _T_696) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = and(_T_677, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_722 = and(_T_720, _T_721) node _T_723 = or(UInt<1>(0h0), _T_722) node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = or(_T_728, _T_733) node _T_735 = and(_T_723, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = and(_T_719, _T_736) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_737, UInt<1>(0h1), "") : assert_36 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(source_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(is_aligned, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_747, UInt<1>(0h1), "") : assert_39 node _T_751 = eq(io.in.a.bits.mask, mask) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_751, UInt<1>(0h1), "") : assert_40 node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_755 : node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_45) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<1>(0h1)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_46) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h2)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_47) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<2>(0h3)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_48) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_784 = shr(io.in.a.bits.source, 3) node _T_785 = eq(_T_784, UInt<3>(0h4)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_49) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_792 = or(_T_759, _T_765) node _T_793 = or(_T_792, _T_771) node _T_794 = or(_T_793, _T_777) node _T_795 = or(_T_794, _T_783) node _T_796 = or(_T_795, _T_789) node _T_797 = or(_T_796, _T_790) node _T_798 = or(_T_797, _T_791) node _T_799 = and(_T_758, _T_798) node _T_800 = or(UInt<1>(0h0), _T_799) node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_803 = and(_T_801, _T_802) node _T_804 = or(UInt<1>(0h0), _T_803) node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = or(_T_809, _T_814) node _T_816 = and(_T_804, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = and(_T_800, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(source_ok, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<1>(0h0)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_50) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h1)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_51) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<2>(0h2)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_52) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h3)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_53) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_865 = shr(io.in.a.bits.source, 3) node _T_866 = eq(_T_865, UInt<3>(0h4)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_54) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_873 = or(_T_840, _T_846) node _T_874 = or(_T_873, _T_852) node _T_875 = or(_T_874, _T_858) node _T_876 = or(_T_875, _T_864) node _T_877 = or(_T_876, _T_870) node _T_878 = or(_T_877, _T_871) node _T_879 = or(_T_878, _T_872) node _T_880 = and(_T_839, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_884 = and(_T_882, _T_883) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = or(_T_890, _T_895) node _T_897 = and(_T_885, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_881, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h1), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h1), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h1), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h1), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h1), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1061 = cvt(_T_1060) node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = asSInt(_T_1062) node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0))) node _T_1065 = or(_T_1059, _T_1064) node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1066 = shr(io.in.b.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1072, _T_1077) node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1079 = shr(io.in.b.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h1)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1085, _T_1090) node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1092 = shr(io.in.b.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = or(_T_1098, _T_1103) node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1105 = shr(io.in.b.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = or(_T_1111, _T_1116) node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1118 = shr(io.in.b.bits.source, 3) node _T_1119 = eq(_T_1118, UInt<3>(0h4)) node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1124, _T_1129) node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = or(_T_1132, _T_1137) node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = or(_T_1140, _T_1145) node _T_1147 = and(_T_1065, _T_1078) node _T_1148 = and(_T_1147, _T_1091) node _T_1149 = and(_T_1148, _T_1104) node _T_1150 = and(_T_1149, _T_1117) node _T_1151 = and(_T_1150, _T_1130) node _T_1152 = and(_T_1151, _T_1138) node _T_1153 = and(_T_1152, _T_1146) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 3) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _legal_source_WIRE : UInt<1>[8] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_31 connect _legal_source_WIRE[7], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38) node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_47 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1157 : node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1165 = shr(io.in.b.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1171 = shr(io.in.b.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1177 = shr(io.in.b.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1183 = shr(io.in.b.bits.source, 3) node _T_1184 = eq(_T_1183, UInt<3>(0h4)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _WIRE_4 : UInt<1>[8] connect _WIRE_4[0], _T_1158 connect _WIRE_4[1], _T_1164 connect _WIRE_4[2], _T_1170 connect _WIRE_4[3], _T_1176 connect _WIRE_4[4], _T_1182 connect _WIRE_4[5], _T_1188 connect _WIRE_4[6], _T_1189 connect _WIRE_4[7], _T_1190 node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0)) node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1200 = or(_T_1192, _T_1193) node _T_1201 = or(_T_1200, _T_1194) node _T_1202 = or(_T_1201, _T_1195) node _T_1203 = or(_T_1202, _T_1196) node _T_1204 = or(_T_1203, _T_1197) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = or(_T_1205, _T_1199) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1206 node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = or(UInt<1>(0h0), _T_1209) node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1212 = cvt(_T_1211) node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0))) node _T_1214 = asSInt(_T_1213) node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0))) node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = or(_T_1215, _T_1220) node _T_1222 = and(_T_1210, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = and(_WIRE_5, _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86 node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(address_ok, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(legal_source, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90 node _T_1241 = eq(io.in.b.bits.mask, mask_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91 node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92 node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1249 : node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = or(UInt<1>(0h0), _T_1252) node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1260 = cvt(_T_1259) node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0))) node _T_1262 = asSInt(_T_1261) node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0))) node _T_1264 = or(_T_1258, _T_1263) node _T_1265 = and(_T_1253, _T_1264) node _T_1266 = or(UInt<1>(0h0), _T_1265) node _T_1267 = and(UInt<1>(0h0), _T_1266) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93 node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(address_ok, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(legal_source, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97 node _T_1284 = eq(io.in.b.bits.mask, mask_1) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98 node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99 node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1292 : node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = or(_T_1301, _T_1306) node _T_1308 = and(_T_1296, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = and(UInt<1>(0h0), _T_1309) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100 node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(address_ok, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(legal_source, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104 node _T_1327 = eq(io.in.b.bits.mask, mask_1) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105 node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1331 : node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1337 = cvt(_T_1336) node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0))) node _T_1339 = asSInt(_T_1338) node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0))) node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = or(_T_1340, _T_1345) node _T_1347 = and(_T_1335, _T_1346) node _T_1348 = or(UInt<1>(0h0), _T_1347) node _T_1349 = and(UInt<1>(0h0), _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106 node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(address_ok, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(legal_source, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110 node _T_1366 = not(mask_1) node _T_1367 = and(io.in.b.bits.mask, _T_1366) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111 node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1372 : node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1375 = and(_T_1373, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1375) node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = or(_T_1381, _T_1386) node _T_1388 = and(_T_1376, _T_1387) node _T_1389 = or(UInt<1>(0h0), _T_1388) node _T_1390 = and(UInt<1>(0h0), _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(address_ok, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(legal_source, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116 node _T_1407 = eq(io.in.b.bits.mask, mask_1) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117 node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1411 : node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = or(UInt<1>(0h0), _T_1414) node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = or(_T_1420, _T_1425) node _T_1427 = and(_T_1415, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1427) node _T_1429 = and(UInt<1>(0h0), _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(address_ok, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(legal_source, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122 node _T_1446 = eq(io.in.b.bits.mask, mask_1) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123 node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1450 : node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1456 = cvt(_T_1455) node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0))) node _T_1458 = asSInt(_T_1457) node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0))) node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1461 = cvt(_T_1460) node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0))) node _T_1463 = asSInt(_T_1462) node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0))) node _T_1465 = or(_T_1459, _T_1464) node _T_1466 = and(_T_1454, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1466) node _T_1468 = and(UInt<1>(0h0), _T_1467) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124 node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(address_ok, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(legal_source, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1481 = eq(io.in.b.bits.mask, mask_1) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128 node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130 node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_97 = shr(io.in.c.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0) node _source_ok_T_103 = shr(io.in.c.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_2 : UInt<1>[8] connect _source_ok_WIRE_2[0], _source_ok_T_78 connect _source_ok_WIRE_2[1], _source_ok_T_84 connect _source_ok_WIRE_2[2], _source_ok_T_90 connect _source_ok_WIRE_2[3], _source_ok_T_96 connect _source_ok_WIRE_2[4], _source_ok_T_102 connect _source_ok_WIRE_2[5], _source_ok_T_108 connect _source_ok_WIRE_2[6], _source_ok_T_109 connect _source_ok_WIRE_2[7], _source_ok_T_110 node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6]) node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = or(_T_1494, _T_1499) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1501 = shr(io.in.c.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = or(_T_1507, _T_1512) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1514 = shr(io.in.c.bits.source, 2) node _T_1515 = eq(_T_1514, UInt<1>(0h1)) node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1519 = and(_T_1517, _T_1518) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1520, _T_1525) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1527 = shr(io.in.c.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h2)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = or(_T_1533, _T_1538) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1540 = shr(io.in.c.bits.source, 2) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1553 = shr(io.in.c.bits.source, 3) node _T_1554 = eq(_T_1553, UInt<3>(0h4)) node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1556 = and(_T_1554, _T_1555) node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = or(_T_1567, _T_1572) node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1577 = cvt(_T_1576) node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = asSInt(_T_1578) node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = or(_T_1575, _T_1580) node _T_1582 = and(_T_1500, _T_1513) node _T_1583 = and(_T_1582, _T_1526) node _T_1584 = and(_T_1583, _T_1539) node _T_1585 = and(_T_1584, _T_1552) node _T_1586 = and(_T_1585, _T_1565) node _T_1587 = and(_T_1586, _T_1573) node _T_1588 = and(_T_1587, _T_1581) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131 node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1592 : node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(address_ok_1, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(source_ok_2, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136 node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137 node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1614 : node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(address_ok_1, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_2, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140 node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1629 = asUInt(reset) node _T_1630 = eq(_T_1629, UInt<1>(0h0)) when _T_1630 : node _T_1631 = eq(_T_1628, UInt<1>(0h0)) when _T_1631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142 node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1632 : node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1637 = shr(io.in.c.bits.source, 2) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1640 = and(_T_1638, _T_1639) node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1642 = and(_T_1640, _T_1641) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1643 = shr(io.in.c.bits.source, 2) node _T_1644 = eq(_T_1643, UInt<1>(0h1)) node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1646 = and(_T_1644, _T_1645) node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1648 = and(_T_1646, _T_1647) node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1649 = shr(io.in.c.bits.source, 2) node _T_1650 = eq(_T_1649, UInt<2>(0h2)) node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1652 = and(_T_1650, _T_1651) node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1654 = and(_T_1652, _T_1653) node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1655 = shr(io.in.c.bits.source, 2) node _T_1656 = eq(_T_1655, UInt<2>(0h3)) node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1658 = and(_T_1656, _T_1657) node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1660 = and(_T_1658, _T_1659) node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1661 = shr(io.in.c.bits.source, 3) node _T_1662 = eq(_T_1661, UInt<3>(0h4)) node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1664 = and(_T_1662, _T_1663) node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1666 = and(_T_1664, _T_1665) node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1669 = or(_T_1636, _T_1642) node _T_1670 = or(_T_1669, _T_1648) node _T_1671 = or(_T_1670, _T_1654) node _T_1672 = or(_T_1671, _T_1660) node _T_1673 = or(_T_1672, _T_1666) node _T_1674 = or(_T_1673, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = and(_T_1635, _T_1675) node _T_1677 = or(UInt<1>(0h0), _T_1676) node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1679 = or(UInt<1>(0h0), _T_1678) node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1686 = cvt(_T_1685) node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0))) node _T_1688 = asSInt(_T_1687) node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0))) node _T_1690 = or(_T_1684, _T_1689) node _T_1691 = and(_T_1679, _T_1690) node _T_1692 = or(UInt<1>(0h0), _T_1691) node _T_1693 = and(_T_1677, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143 node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0) node _T_1704 = shr(io.in.c.bits.source, 2) node _T_1705 = eq(_T_1704, UInt<1>(0h1)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0) node _T_1710 = shr(io.in.c.bits.source, 2) node _T_1711 = eq(_T_1710, UInt<2>(0h2)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_1716 = shr(io.in.c.bits.source, 2) node _T_1717 = eq(_T_1716, UInt<2>(0h3)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_1721 = and(_T_1719, _T_1720) node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0) node _T_1722 = shr(io.in.c.bits.source, 3) node _T_1723 = eq(_T_1722, UInt<3>(0h4)) node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1725 = and(_T_1723, _T_1724) node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7)) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_6 : UInt<1>[8] connect _WIRE_6[0], _T_1697 connect _WIRE_6[1], _T_1703 connect _WIRE_6[2], _T_1709 connect _WIRE_6[3], _T_1715 connect _WIRE_6[4], _T_1721 connect _WIRE_6[5], _T_1727 connect _WIRE_6[6], _T_1728 connect _WIRE_6[7], _T_1729 node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0)) node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1739 = or(_T_1731, _T_1732) node _T_1740 = or(_T_1739, _T_1733) node _T_1741 = or(_T_1740, _T_1734) node _T_1742 = or(_T_1741, _T_1735) node _T_1743 = or(_T_1742, _T_1736) node _T_1744 = or(_T_1743, _T_1737) node _T_1745 = or(_T_1744, _T_1738) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1745 node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1748 = and(_T_1746, _T_1747) node _T_1749 = or(UInt<1>(0h0), _T_1748) node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = or(_T_1754, _T_1759) node _T_1761 = and(_T_1749, _T_1760) node _T_1762 = or(UInt<1>(0h0), _T_1761) node _T_1763 = and(_WIRE_7, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144 node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(source_ok_2, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1771 = asUInt(reset) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) when _T_1772 : node _T_1773 = eq(_T_1770, UInt<1>(0h0)) when _T_1773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146 node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148 node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149 node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0) node _T_1790 = shr(io.in.c.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0) node _T_1796 = shr(io.in.c.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<1>(0h1)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0) node _T_1802 = shr(io.in.c.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<2>(0h2)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0) node _T_1808 = shr(io.in.c.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<2>(0h3)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0) node _T_1814 = shr(io.in.c.bits.source, 3) node _T_1815 = eq(_T_1814, UInt<3>(0h4)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7)) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1822 = or(_T_1789, _T_1795) node _T_1823 = or(_T_1822, _T_1801) node _T_1824 = or(_T_1823, _T_1807) node _T_1825 = or(_T_1824, _T_1813) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = and(_T_1788, _T_1828) node _T_1830 = or(UInt<1>(0h0), _T_1829) node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1832 = or(UInt<1>(0h0), _T_1831) node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1834 = cvt(_T_1833) node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0))) node _T_1836 = asSInt(_T_1835) node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0))) node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1839 = cvt(_T_1838) node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0))) node _T_1841 = asSInt(_T_1840) node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = or(_T_1837, _T_1842) node _T_1844 = and(_T_1832, _T_1843) node _T_1845 = or(UInt<1>(0h0), _T_1844) node _T_1846 = and(_T_1830, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150 node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1851 = shr(io.in.c.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1857 = shr(io.in.c.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<1>(0h1)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1863 = shr(io.in.c.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<2>(0h2)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_1869 = shr(io.in.c.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<2>(0h3)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0) node _T_1875 = shr(io.in.c.bits.source, 3) node _T_1876 = eq(_T_1875, UInt<3>(0h4)) node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7)) node _T_1880 = and(_T_1878, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_8 : UInt<1>[8] connect _WIRE_8[0], _T_1850 connect _WIRE_8[1], _T_1856 connect _WIRE_8[2], _T_1862 connect _WIRE_8[3], _T_1868 connect _WIRE_8[4], _T_1874 connect _WIRE_8[5], _T_1880 connect _WIRE_8[6], _T_1881 connect _WIRE_8[7], _T_1882 node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0)) node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1892 = or(_T_1884, _T_1885) node _T_1893 = or(_T_1892, _T_1886) node _T_1894 = or(_T_1893, _T_1887) node _T_1895 = or(_T_1894, _T_1888) node _T_1896 = or(_T_1895, _T_1889) node _T_1897 = or(_T_1896, _T_1890) node _T_1898 = or(_T_1897, _T_1891) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1898 node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = or(_T_1907, _T_1912) node _T_1914 = and(_T_1902, _T_1913) node _T_1915 = or(UInt<1>(0h0), _T_1914) node _T_1916 = and(_WIRE_9, _T_1915) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151 node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(source_ok_2, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155 node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1941 = asUInt(reset) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) when _T_1942 : node _T_1943 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159 node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160 node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(address_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_2, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164 node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1966 : node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(address_ok_1, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_2, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168 node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1987 = eq(a_first, UInt<1>(0h0)) node _T_1988 = and(io.in.a.valid, _T_1987) when _T_1988 : node _T_1989 = eq(io.in.a.bits.opcode, opcode) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171 node _T_1993 = eq(io.in.a.bits.param, param) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172 node _T_1997 = eq(io.in.a.bits.size, size) node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(_T_1997, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173 node _T_2001 = eq(io.in.a.bits.source, source) node _T_2002 = asUInt(reset) node _T_2003 = eq(_T_2002, UInt<1>(0h0)) when _T_2003 : node _T_2004 = eq(_T_2001, UInt<1>(0h0)) when _T_2004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174 node _T_2005 = eq(io.in.a.bits.address, address) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175 node _T_2009 = and(io.in.a.ready, io.in.a.valid) node _T_2010 = and(_T_2009, a_first) when _T_2010 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2011 = eq(d_first, UInt<1>(0h0)) node _T_2012 = and(io.in.d.valid, _T_2011) when _T_2012 : node _T_2013 = eq(io.in.d.bits.opcode, opcode_1) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176 node _T_2017 = eq(io.in.d.bits.param, param_1) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177 node _T_2021 = eq(io.in.d.bits.size, size_1) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178 node _T_2025 = eq(io.in.d.bits.source, source_1) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179 node _T_2029 = eq(io.in.d.bits.sink, sink) node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(_T_2029, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180 node _T_2033 = eq(io.in.d.bits.denied, denied) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181 node _T_2037 = and(io.in.d.ready, io.in.d.valid) node _T_2038 = and(_T_2037, d_first) when _T_2038 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2039 = eq(b_first, UInt<1>(0h0)) node _T_2040 = and(io.in.b.valid, _T_2039) when _T_2040 : node _T_2041 = eq(io.in.b.bits.opcode, opcode_2) node _T_2042 = asUInt(reset) node _T_2043 = eq(_T_2042, UInt<1>(0h0)) when _T_2043 : node _T_2044 = eq(_T_2041, UInt<1>(0h0)) when _T_2044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182 node _T_2045 = eq(io.in.b.bits.param, param_2) node _T_2046 = asUInt(reset) node _T_2047 = eq(_T_2046, UInt<1>(0h0)) when _T_2047 : node _T_2048 = eq(_T_2045, UInt<1>(0h0)) when _T_2048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183 node _T_2049 = eq(io.in.b.bits.size, size_2) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184 node _T_2053 = eq(io.in.b.bits.source, source_2) node _T_2054 = asUInt(reset) node _T_2055 = eq(_T_2054, UInt<1>(0h0)) when _T_2055 : node _T_2056 = eq(_T_2053, UInt<1>(0h0)) when _T_2056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185 node _T_2057 = eq(io.in.b.bits.address, address_1) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186 node _T_2061 = and(io.in.b.ready, io.in.b.valid) node _T_2062 = and(_T_2061, b_first) when _T_2062 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2063 = eq(c_first, UInt<1>(0h0)) node _T_2064 = and(io.in.c.valid, _T_2063) when _T_2064 : node _T_2065 = eq(io.in.c.bits.opcode, opcode_3) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187 node _T_2069 = eq(io.in.c.bits.param, param_3) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188 node _T_2073 = eq(io.in.c.bits.size, size_3) node _T_2074 = asUInt(reset) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) when _T_2075 : node _T_2076 = eq(_T_2073, UInt<1>(0h0)) when _T_2076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189 node _T_2077 = eq(io.in.c.bits.source, source_3) node _T_2078 = asUInt(reset) node _T_2079 = eq(_T_2078, UInt<1>(0h0)) when _T_2079 : node _T_2080 = eq(_T_2077, UInt<1>(0h0)) when _T_2080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190 node _T_2081 = eq(io.in.c.bits.address, address_2) node _T_2082 = asUInt(reset) node _T_2083 = eq(_T_2082, UInt<1>(0h0)) when _T_2083 : node _T_2084 = eq(_T_2081, UInt<1>(0h0)) when _T_2084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191 node _T_2085 = and(io.in.c.ready, io.in.c.valid) node _T_2086 = and(_T_2085, c_first) when _T_2086 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<43> connect a_set, UInt<43>(0h0) wire a_set_wo_ready : UInt<43> connect a_set_wo_ready, UInt<43>(0h0) wire a_opcodes_set : UInt<172> connect a_opcodes_set, UInt<172>(0h0) wire a_sizes_set : UInt<172> connect a_sizes_set, UInt<172>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2087 = and(io.in.a.valid, a_first_1) node _T_2088 = and(_T_2087, UInt<1>(0h1)) when _T_2088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2089 = and(io.in.a.ready, io.in.a.valid) node _T_2090 = and(_T_2089, a_first_1) node _T_2091 = and(_T_2090, UInt<1>(0h1)) when _T_2091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2092 = dshr(inflight, io.in.a.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<43> connect d_clr, UInt<43>(0h0) wire d_clr_wo_ready : UInt<43> connect d_clr_wo_ready, UInt<43>(0h0) wire d_opcodes_clr : UInt<172> connect d_opcodes_clr, UInt<172>(0h0) wire d_sizes_clr : UInt<172> connect d_sizes_clr, UInt<172>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2098 = and(io.in.d.valid, d_first_1) node _T_2099 = and(_T_2098, UInt<1>(0h1)) node _T_2100 = eq(d_release_ack, UInt<1>(0h0)) node _T_2101 = and(_T_2099, _T_2100) when _T_2101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2102 = and(io.in.d.ready, io.in.d.valid) node _T_2103 = and(_T_2102, d_first_1) node _T_2104 = and(_T_2103, UInt<1>(0h1)) node _T_2105 = eq(d_release_ack, UInt<1>(0h0)) node _T_2106 = and(_T_2104, _T_2105) when _T_2106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2107 = and(io.in.d.valid, d_first_1) node _T_2108 = and(_T_2107, UInt<1>(0h1)) node _T_2109 = eq(d_release_ack, UInt<1>(0h0)) node _T_2110 = and(_T_2108, _T_2109) when _T_2110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2111 = dshr(inflight, io.in.d.bits.source) node _T_2112 = bits(_T_2111, 0, 0) node _T_2113 = or(_T_2112, same_cycle_resp) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2119 = or(_T_2117, _T_2118) node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(_T_2119, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194 node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195 else : node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196 node _T_2133 = eq(io.in.d.bits.size, a_size_lookup) node _T_2134 = asUInt(reset) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) when _T_2135 : node _T_2136 = eq(_T_2133, UInt<1>(0h0)) when _T_2136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197 node _T_2137 = and(io.in.d.valid, d_first_1) node _T_2138 = and(_T_2137, a_first_1) node _T_2139 = and(_T_2138, io.in.a.valid) node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2141 = and(_T_2139, _T_2140) node _T_2142 = eq(d_release_ack, UInt<1>(0h0)) node _T_2143 = and(_T_2141, _T_2142) when _T_2143 : node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2145 = or(_T_2144, io.in.a.ready) node _T_2146 = asUInt(reset) node _T_2147 = eq(_T_2146, UInt<1>(0h0)) when _T_2147 : node _T_2148 = eq(_T_2145, UInt<1>(0h0)) when _T_2148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198 node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2150 = orr(a_set_wo_ready) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) node _T_2152 = or(_T_2149, _T_2151) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_128 node _T_2156 = orr(inflight) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2159 = or(_T_2157, _T_2158) node _T_2160 = lt(watchdog, plusarg_reader.out) node _T_2161 = or(_T_2159, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2165 = and(io.in.a.ready, io.in.a.valid) node _T_2166 = and(io.in.d.ready, io.in.d.valid) node _T_2167 = or(_T_2165, _T_2166) when _T_2167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<43> connect c_set, UInt<43>(0h0) wire c_set_wo_ready : UInt<43> connect c_set_wo_ready, UInt<43>(0h0) wire c_opcodes_set : UInt<172> connect c_opcodes_set, UInt<172>(0h0) wire c_sizes_set : UInt<172> connect c_sizes_set, UInt<172>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2168 = and(io.in.c.valid, c_first_1) node _T_2169 = bits(io.in.c.bits.opcode, 2, 2) node _T_2170 = bits(io.in.c.bits.opcode, 1, 1) node _T_2171 = and(_T_2169, _T_2170) node _T_2172 = and(_T_2168, _T_2171) when _T_2172 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2173 = and(io.in.c.ready, io.in.c.valid) node _T_2174 = and(_T_2173, c_first_1) node _T_2175 = bits(io.in.c.bits.opcode, 2, 2) node _T_2176 = bits(io.in.c.bits.opcode, 1, 1) node _T_2177 = and(_T_2175, _T_2176) node _T_2178 = and(_T_2174, _T_2177) when _T_2178 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2179 = dshr(inflight_1, io.in.c.bits.source) node _T_2180 = bits(_T_2179, 0, 0) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = asUInt(reset) node _T_2183 = eq(_T_2182, UInt<1>(0h0)) when _T_2183 : node _T_2184 = eq(_T_2181, UInt<1>(0h0)) when _T_2184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<43> connect d_clr_1, UInt<43>(0h0) wire d_clr_wo_ready_1 : UInt<43> connect d_clr_wo_ready_1, UInt<43>(0h0) wire d_opcodes_clr_1 : UInt<172> connect d_opcodes_clr_1, UInt<172>(0h0) wire d_sizes_clr_1 : UInt<172> connect d_sizes_clr_1, UInt<172>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2185 = and(io.in.d.valid, d_first_2) node _T_2186 = and(_T_2185, UInt<1>(0h1)) node _T_2187 = and(_T_2186, d_release_ack_1) when _T_2187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2188 = and(io.in.d.ready, io.in.d.valid) node _T_2189 = and(_T_2188, d_first_2) node _T_2190 = and(_T_2189, UInt<1>(0h1)) node _T_2191 = and(_T_2190, d_release_ack_1) when _T_2191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2192 = and(io.in.d.valid, d_first_2) node _T_2193 = and(_T_2192, UInt<1>(0h1)) node _T_2194 = and(_T_2193, d_release_ack_1) when _T_2194 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2195 = dshr(inflight_1, io.in.d.bits.source) node _T_2196 = bits(_T_2195, 0, 0) node _T_2197 = or(_T_2196, same_cycle_resp_1) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203 else : node _T_2205 = eq(io.in.d.bits.size, c_size_lookup) node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(_T_2205, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204 node _T_2209 = and(io.in.d.valid, d_first_2) node _T_2210 = and(_T_2209, c_first_1) node _T_2211 = and(_T_2210, io.in.c.valid) node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = and(_T_2213, d_release_ack_1) node _T_2215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2216 = and(_T_2214, _T_2215) when _T_2216 : node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2218 = or(_T_2217, io.in.c.ready) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(_T_2218, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205 node _T_2222 = orr(c_set_wo_ready) when _T_2222 : node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(_T_2223, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_129 node _T_2227 = orr(inflight_1) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2230 = or(_T_2228, _T_2229) node _T_2231 = lt(watchdog_1, plusarg_reader_1.out) node _T_2232 = or(_T_2230, _T_2231) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2236 = and(io.in.c.ready, io.in.c.valid) node _T_2237 = and(io.in.d.ready, io.in.d.valid) node _T_2238 = or(_T_2236, _T_2237) when _T_2238 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<12> connect d_set, UInt<12>(0h0) node _T_2239 = and(io.in.d.ready, io.in.d.valid) node _T_2240 = and(_T_2239, d_first_3) node _T_2241 = bits(io.in.d.bits.opcode, 2, 2) node _T_2242 = bits(io.in.d.bits.opcode, 1, 1) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) node _T_2244 = and(_T_2241, _T_2243) node _T_2245 = and(_T_2240, _T_2244) when _T_2245 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2246 = dshr(inflight_2, io.in.d.bits.sink) node _T_2247 = bits(_T_2246, 0, 0) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<12> connect e_clr, UInt<12>(0h0) node _T_2252 = and(io.in.e.ready, io.in.e.valid) node _T_2253 = and(_T_2252, UInt<1>(0h1)) node _T_2254 = and(_T_2253, UInt<1>(0h1)) when _T_2254 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2255 = or(d_set, inflight_2) node _T_2256 = dshr(_T_2255, io.in.e.bits.sink) node _T_2257 = bits(_T_2256, 0, 0) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_131 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000180; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000180; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_116 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000180; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000180; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31] wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [1:0] b_first_counter; // @[Edges.scala:229:27] wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [42:0] inflight; // @[Monitor.scala:614:27] reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [171:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] a_set; // @[Monitor.scala:626:34] wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [171:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [42:0] d_clr; // @[Monitor.scala:664:34] wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [42:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [171:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [171:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [42:0] inflight_1; // @[Monitor.scala:726:35] reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] c_set; // @[Monitor.scala:738:34] wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [171:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [42:0] d_clr_1; // @[Monitor.scala:774:34] wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [42:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [11:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_set; // @[Monitor.scala:833:25] wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] wire [11:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_12 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_131 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_132 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_134 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_12( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_131 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_132 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_134 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_6 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<13>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_12 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<13>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_13 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<13>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k3z4c_3 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_18 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k3z4c_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k3z4c_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s4k3z4c_1 connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s4k3z4c_1 connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s4k3z4c_1 connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready
module TLBuffer_a32d64s4k3z4c_3( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_18 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s4k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s4k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s4k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_36 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_EntryData_36( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_29 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1]}, credit_alloc : { `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[5]}, switch_sel : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_178 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_179 connect arbs_1.clock, clock connect arbs_1.reset, reset inst arbs_2 of SwitchArbiter_180 connect arbs_2.clock, clock connect arbs_2.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) connect arbs_2.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[3] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_0_valid_T_3 = or(_arbs_0_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_0_valid_T_4 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_3) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_4 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) connect fires[2], _fires_2_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T_1 wire fires_1 : UInt<1>[3] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_1_valid_T_3 = or(_arbs_0_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_1_valid_T_4 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_3) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_4 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) connect fires_1[2], _fires_2_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T_1 wire fires_2 : UInt<1>[3] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_2_valid_T_3 = or(_arbs_0_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_2_valid_T_4 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_3) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_4 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) connect fires_2[2], _fires_2_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T_1 wire fires_3 : UInt<1>[3] node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_3_valid_T_1 = or(_arbs_0_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_3_valid_T_2 = or(_arbs_0_io_in_3_valid_T_1, io.req.`3`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_3_valid_T_3 = or(_arbs_0_io_in_3_valid_T_2, io.req.`3`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_3_valid_T_4 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T_3) connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_4 connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid) connect fires_3[0], _fires_0_T_3 node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid) connect fires_3[1], _fires_1_T_3 node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid) connect fires_3[2], _fires_2_T_3 node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1]) node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2]) connect io.req.`3`[0].ready, _io_req_3_0_ready_T_1 node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3) node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T) node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3) node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T) node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2 node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3) node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T) node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[4].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) when _T_2 : connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3]) when _T_3 : connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail node _T_4 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[4]) when _T_4 : connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[4].tail, arbs_0.io.out[0].bits.tail node _T_5 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_5 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail node _T_6 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) when _T_6 : connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail
module SwitchAllocator_29( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 | io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2 | io_req_1_0_bits_vc_sel_0_3 | io_req_1_0_bits_vc_sel_0_4); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_178 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (/* unused */), .io_in_0_valid (1'h0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4), .io_out_0_bits_tail (/* unused */), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_178 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_178 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_2_io_in_1_ready), .io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid | _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_82 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_82( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24 : output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 31, 31) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f)) node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32) node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33) node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34) node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35) node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36) node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37) node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38) node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39) node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40) node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41) node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42) node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43) node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44) node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45) node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46) node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47) node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48) node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49) node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50) node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51) node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52) node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53) node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54) node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55) node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56) node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57) node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58) node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59) node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module INToRecFN_i32_e8_s24( // @[INToRecFN.scala:43:7] input [31:0] io_in, // @[INToRecFN.scala:46:16] output [32:0] io_out // @[INToRecFN.scala:46:16] ); wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [32:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31] wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70] wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie6_is32_oe8_os24 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_112 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 13, 0) node _source_ok_T = shr(io.in.a.bits.source, 14) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<14>(0h200f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits = bits(_uncommonBits_T, 13, 0) node _T_4 = shr(io.in.a.bits.source, 14) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<14>(0h200f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 13, 0) node _T_24 = shr(io.in.a.bits.source, 14) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<14>(0h200f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 13, 0) node _T_86 = shr(io.in.a.bits.source, 14) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<14>(0h200f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 13, 0) node _T_152 = shr(io.in.a.bits.source, 14) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<14>(0h200f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 13, 0) node _T_199 = shr(io.in.a.bits.source, 14) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<14>(0h200f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 13, 0) node _T_240 = shr(io.in.a.bits.source, 14) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<14>(0h200f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 13, 0) node _T_283 = shr(io.in.a.bits.source, 14) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<14>(0h200f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 13, 0) node _T_321 = shr(io.in.a.bits.source, 14) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<14>(0h200f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 13, 0) node _T_359 = shr(io.in.a.bits.source, 14) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<14>(0h200f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 13, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 14) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<14>(0h200f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes : UInt<32832>, clock, reset, UInt<32832>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<8208> connect a_set, UInt<8208>(0h0) wire a_set_wo_ready : UInt<8208> connect a_set_wo_ready, UInt<8208>(0h0) wire a_opcodes_set : UInt<32832> connect a_opcodes_set, UInt<32832>(0h0) wire a_sizes_set : UInt<32832> connect a_sizes_set, UInt<32832>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<8208> connect d_clr, UInt<8208>(0h0) wire d_clr_wo_ready : UInt<8208> connect d_clr_wo_ready, UInt<8208>(0h0) wire d_opcodes_clr : UInt<32832> connect d_opcodes_clr, UInt<32832>(0h0) wire d_sizes_clr : UInt<32832> connect d_sizes_clr, UInt<32832>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_227 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<14>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<14>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<8208> connect c_set, UInt<8208>(0h0) wire c_set_wo_ready : UInt<8208> connect c_set_wo_ready, UInt<8208>(0h0) wire c_opcodes_set : UInt<32832> connect c_opcodes_set, UInt<32832>(0h0) wire c_sizes_set : UInt<32832> connect c_sizes_set, UInt<32832>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<14>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<14>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<14>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<14>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<14>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<14>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<8208> connect d_clr_1, UInt<8208>(0h0) wire d_clr_wo_ready_1 : UInt<8208> connect d_clr_wo_ready_1, UInt<8208>(0h0) wire d_opcodes_clr_1 : UInt<32832> connect d_opcodes_clr_1, UInt<32832>(0h0) wire d_sizes_clr_1 : UInt<32832> connect d_sizes_clr_1, UInt<32832>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<14>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<14>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<14>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<14>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_228 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<14>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_112( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52] wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79] wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77] wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35] wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35] wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34] wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34] wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34] wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [8207:0] a_set; // @[Monitor.scala:626:34] wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [16383:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8207:0] d_clr; // @[Monitor.scala:664:34] wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8207:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [32831:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [32831:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [8207:0] d_clr_1; // @[Monitor.scala:774:34] wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113] wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SinkX_7 : input clock : Clock input reset : Reset output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}, flip x : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}} inst x_q of Queue1_SinkXRequest_7 connect x_q.clock, clock connect x_q.reset, reset connect x_q.io.enq.valid, io.x.valid connect x_q.io.enq.bits.address, io.x.bits.address connect io.x.ready, x_q.io.enq.ready node _offset_T = bits(x_q.io.deq.bits.address, 0, 0) node _offset_T_1 = bits(x_q.io.deq.bits.address, 1, 1) node _offset_T_2 = bits(x_q.io.deq.bits.address, 2, 2) node _offset_T_3 = bits(x_q.io.deq.bits.address, 3, 3) node _offset_T_4 = bits(x_q.io.deq.bits.address, 4, 4) node _offset_T_5 = bits(x_q.io.deq.bits.address, 5, 5) node _offset_T_6 = bits(x_q.io.deq.bits.address, 9, 9) node _offset_T_7 = bits(x_q.io.deq.bits.address, 10, 10) node _offset_T_8 = bits(x_q.io.deq.bits.address, 11, 11) node _offset_T_9 = bits(x_q.io.deq.bits.address, 12, 12) node _offset_T_10 = bits(x_q.io.deq.bits.address, 13, 13) node _offset_T_11 = bits(x_q.io.deq.bits.address, 14, 14) node _offset_T_12 = bits(x_q.io.deq.bits.address, 15, 15) node _offset_T_13 = bits(x_q.io.deq.bits.address, 16, 16) node _offset_T_14 = bits(x_q.io.deq.bits.address, 17, 17) node _offset_T_15 = bits(x_q.io.deq.bits.address, 18, 18) node _offset_T_16 = bits(x_q.io.deq.bits.address, 19, 19) node _offset_T_17 = bits(x_q.io.deq.bits.address, 20, 20) node _offset_T_18 = bits(x_q.io.deq.bits.address, 21, 21) node _offset_T_19 = bits(x_q.io.deq.bits.address, 22, 22) node _offset_T_20 = bits(x_q.io.deq.bits.address, 23, 23) node _offset_T_21 = bits(x_q.io.deq.bits.address, 24, 24) node _offset_T_22 = bits(x_q.io.deq.bits.address, 25, 25) node _offset_T_23 = bits(x_q.io.deq.bits.address, 26, 26) node _offset_T_24 = bits(x_q.io.deq.bits.address, 27, 27) node _offset_T_25 = bits(x_q.io.deq.bits.address, 31, 31) node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1) node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T) node offset_lo_lo_hi_hi = cat(_offset_T_5, _offset_T_4) node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, _offset_T_3) node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo) node offset_lo_hi_lo_hi = cat(_offset_T_8, _offset_T_7) node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_6) node offset_lo_hi_hi_lo = cat(_offset_T_10, _offset_T_9) node offset_lo_hi_hi_hi = cat(_offset_T_12, _offset_T_11) node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo) node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo) node offset_lo = cat(offset_lo_hi, offset_lo_lo) node offset_hi_lo_lo_hi = cat(_offset_T_15, _offset_T_14) node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_13) node offset_hi_lo_hi_hi = cat(_offset_T_18, _offset_T_17) node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, _offset_T_16) node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo) node offset_hi_hi_lo_hi = cat(_offset_T_21, _offset_T_20) node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_19) node offset_hi_hi_hi_lo = cat(_offset_T_23, _offset_T_22) node offset_hi_hi_hi_hi = cat(_offset_T_25, _offset_T_24) node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo) node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo) node offset_hi = cat(offset_hi_hi, offset_hi_lo) node offset = cat(offset_hi, offset_lo) node set = shr(offset, 6) node tag = shr(set, 11) node tag_1 = bits(tag, 8, 0) node set_1 = bits(set, 10, 0) node offset_1 = bits(offset, 5, 0) connect x_q.io.deq.ready, io.req.ready connect io.req.valid, x_q.io.deq.valid node _T = eq(x_q.io.deq.ready, UInt<1>(0h0)) node _T_1 = and(x_q.io.deq.valid, _T) wire _WIRE : UInt<1>[3] connect _WIRE[0], UInt<1>(0h1) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect io.req.bits.prio, _WIRE connect io.req.bits.control, UInt<1>(0h1) connect io.req.bits.opcode, UInt<1>(0h0) connect io.req.bits.param, UInt<1>(0h0) connect io.req.bits.size, UInt<3>(0h6) connect io.req.bits.source, UInt<1>(0h0) connect io.req.bits.offset, UInt<1>(0h0) connect io.req.bits.set, set_1 connect io.req.bits.tag, tag_1 connect io.req.bits.put, UInt<1>(0h0)
module SinkX_7( // @[SinkX.scala:28:7] input clock, // @[SinkX.scala:28:7] input reset, // @[SinkX.scala:28:7] input io_req_ready, // @[SinkX.scala:30:14] output io_req_valid, // @[SinkX.scala:30:14] output [8:0] io_req_bits_tag, // @[SinkX.scala:30:14] output [10:0] io_req_bits_set, // @[SinkX.scala:30:14] output io_x_ready, // @[SinkX.scala:30:14] input io_x_valid, // @[SinkX.scala:30:14] input [31:0] io_x_bits_address // @[SinkX.scala:30:14] ); wire [31:0] _x_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire io_req_ready_0 = io_req_ready; // @[SinkX.scala:28:7] wire io_x_valid_0 = io_x_valid; // @[SinkX.scala:28:7] wire [31:0] io_x_bits_address_0 = io_x_bits_address; // @[SinkX.scala:28:7] wire [5:0] io_req_bits_source = 6'h0; // @[SinkX.scala:28:7] wire [5:0] io_req_bits_offset = 6'h0; // @[SinkX.scala:28:7] wire [5:0] io_req_bits_put = 6'h0; // @[SinkX.scala:28:7] wire [2:0] io_req_bits_size = 3'h6; // @[SinkX.scala:28:7] wire [2:0] io_req_bits_opcode = 3'h0; // @[SinkX.scala:28:7] wire [2:0] io_req_bits_param = 3'h0; // @[SinkX.scala:28:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkX.scala:28:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkX.scala:28:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkX.scala:28:7] wire io_req_bits_control = 1'h1; // @[SinkX.scala:28:7] wire [8:0] tag_1; // @[Parameters.scala:217:9] wire [10:0] set_1; // @[Parameters.scala:217:28] wire [8:0] io_req_bits_tag_0; // @[SinkX.scala:28:7] wire [10:0] io_req_bits_set_0; // @[SinkX.scala:28:7] wire io_req_valid_0; // @[SinkX.scala:28:7] wire io_x_ready_0; // @[SinkX.scala:28:7] wire _offset_T = _x_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21] wire _offset_T_1 = _x_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21] wire _offset_T_2 = _x_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21] wire _offset_T_3 = _x_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21] wire _offset_T_4 = _x_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21] wire _offset_T_5 = _x_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21] wire _offset_T_6 = _x_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21] wire _offset_T_7 = _x_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21] wire _offset_T_8 = _x_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21] wire _offset_T_9 = _x_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21] wire _offset_T_10 = _x_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21] wire _offset_T_11 = _x_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21] wire _offset_T_12 = _x_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21] wire _offset_T_13 = _x_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21] wire _offset_T_14 = _x_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21] wire _offset_T_15 = _x_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21] wire _offset_T_16 = _x_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21] wire _offset_T_17 = _x_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21] wire _offset_T_18 = _x_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21] wire _offset_T_19 = _x_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21] wire _offset_T_20 = _x_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21] wire _offset_T_21 = _x_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21] wire _offset_T_22 = _x_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21] wire _offset_T_23 = _x_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21] wire _offset_T_24 = _x_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21] wire _offset_T_25 = _x_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_5, _offset_T_4}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [5:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_8, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_6}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_10, _offset_T_9}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_12, _offset_T_11}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [12:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_15, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_13}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, _offset_T_16}; // @[Parameters.scala:214:{21,47}] wire [5:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_21, _offset_T_20}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [12:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [25:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [19:0] set = offset[25:6]; // @[Parameters.scala:214:21, :215:22] wire [8:0] tag = set[19:11]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkX.scala:28:7] assign set_1 = set[10:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkX.scala:28:7] wire [5:0] offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] Queue1_SinkXRequest_7 x_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (io_x_ready_0), .io_enq_valid (io_x_valid_0), // @[SinkX.scala:28:7] .io_enq_bits_address (io_x_bits_address_0), // @[SinkX.scala:28:7] .io_deq_ready (io_req_ready_0), // @[SinkX.scala:28:7] .io_deq_valid (io_req_valid_0), .io_deq_bits_address (_x_q_io_deq_bits_address) ); // @[Decoupled.scala:362:21] assign io_req_valid = io_req_valid_0; // @[SinkX.scala:28:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkX.scala:28:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkX.scala:28:7] assign io_x_ready = io_x_ready_0; // @[SinkX.scala:28:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_96 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_352 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_96( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_352 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s5k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_34 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s5k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s5k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a28d64s5k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_34 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s5k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s5k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_82 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_82( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_61 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_529 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_530 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_531 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_532 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_61( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_529 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_530 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_531 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_532 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_68 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_78 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_68( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_78 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_70 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_326 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_70( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_326 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e8_s24( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_81 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_81( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCache : input clock : Clock input reset : Reset output auto : { flip ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} inst ctrls of InclusiveCacheControl connect ctrls.clock, clock connect ctrls.reset, reset wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_49 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect ctrls.auto.ctrl_in, auto.ctrls_ctrl_in inst inclusive_cache_bank_sched of InclusiveCacheBankScheduler connect inclusive_cache_bank_sched.clock, clock connect inclusive_cache_bank_sched.reset, reset connect inclusive_cache_bank_sched.io.in, nodeIn connect nodeOut.e.bits, inclusive_cache_bank_sched.io.out.e.bits connect nodeOut.e.valid, inclusive_cache_bank_sched.io.out.e.valid connect inclusive_cache_bank_sched.io.out.e.ready, nodeOut.e.ready connect inclusive_cache_bank_sched.io.out.d, nodeOut.d connect nodeOut.c.bits, inclusive_cache_bank_sched.io.out.c.bits connect nodeOut.c.valid, inclusive_cache_bank_sched.io.out.c.valid connect inclusive_cache_bank_sched.io.out.c.ready, nodeOut.c.ready connect inclusive_cache_bank_sched.io.out.b, nodeOut.b connect nodeOut.a.bits, inclusive_cache_bank_sched.io.out.a.bits connect nodeOut.a.valid, inclusive_cache_bank_sched.io.out.a.valid connect inclusive_cache_bank_sched.io.out.a.ready, nodeOut.a.ready invalidate inclusive_cache_bank_sched.io.ways[0] invalidate inclusive_cache_bank_sched.io.ways[1] invalidate inclusive_cache_bank_sched.io.ways[2] invalidate inclusive_cache_bank_sched.io.ways[3] invalidate inclusive_cache_bank_sched.io.ways[4] invalidate inclusive_cache_bank_sched.io.ways[5] invalidate inclusive_cache_bank_sched.io.ways[6] invalidate inclusive_cache_bank_sched.io.ways[7] invalidate inclusive_cache_bank_sched.io.ways[8] invalidate inclusive_cache_bank_sched.io.ways[9] invalidate inclusive_cache_bank_sched.io.ways[10] invalidate inclusive_cache_bank_sched.io.ways[11] invalidate inclusive_cache_bank_sched.io.ways[12] invalidate inclusive_cache_bank_sched.io.divs[0] invalidate inclusive_cache_bank_sched.io.divs[1] invalidate inclusive_cache_bank_sched.io.divs[2] invalidate inclusive_cache_bank_sched.io.divs[3] invalidate inclusive_cache_bank_sched.io.divs[4] invalidate inclusive_cache_bank_sched.io.divs[5] invalidate inclusive_cache_bank_sched.io.divs[6] invalidate inclusive_cache_bank_sched.io.divs[7] invalidate inclusive_cache_bank_sched.io.divs[8] invalidate inclusive_cache_bank_sched.io.divs[9] invalidate inclusive_cache_bank_sched.io.divs[10] invalidate inclusive_cache_bank_sched.io.divs[11] invalidate inclusive_cache_bank_sched.io.divs[12] connect inclusive_cache_bank_sched.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_1 = cvt(_nodeOut_a_bits_address_mux_matches_T) node _nodeOut_a_bits_address_mux_matches_T_2 = and(_nodeOut_a_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_3 = asSInt(_nodeOut_a_bits_address_mux_matches_T_2) node nodeOut_a_bits_address_mux_0_1 = eq(_nodeOut_a_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T = or(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T node _nodeIn_b_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_1 = cvt(_nodeIn_b_bits_address_mux_matches_T) node _nodeIn_b_bits_address_mux_matches_T_2 = and(_nodeIn_b_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_3 = asSInt(_nodeIn_b_bits_address_mux_matches_T_2) node nodeIn_b_bits_address_mux_0_1 = eq(_nodeIn_b_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T = or(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) connect nodeIn.b.bits.address, _nodeIn_b_bits_address_T node _nodeOut_c_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_1 = cvt(_nodeOut_c_bits_address_mux_matches_T) node _nodeOut_c_bits_address_mux_matches_T_2 = and(_nodeOut_c_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_3 = asSInt(_nodeOut_c_bits_address_mux_matches_T_2) node nodeOut_c_bits_address_mux_0_1 = eq(_nodeOut_c_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T = or(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) connect nodeOut.c.bits.address, _nodeOut_c_bits_address_T connect ctrls.io.flush_req.ready, UInt<1>(0h0) connect ctrls.io.flush_resp, UInt<1>(0h0) connect ctrls.io.flush_match, UInt<1>(0h0) node _contained_T = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000000)) node _contained_T_1 = cvt(_contained_T) node _contained_T_2 = and(_contained_T_1, asSInt(UInt<29>(0h10000000))) node _contained_T_3 = asSInt(_contained_T_2) node _contained_T_4 = eq(_contained_T_3, asSInt(UInt<1>(0h0))) node _contained_T_5 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000000)) node _contained_T_6 = cvt(_contained_T_5) node _contained_T_7 = and(_contained_T_6, asSInt(UInt<17>(0h10000))) node _contained_T_8 = asSInt(_contained_T_7) node _contained_T_9 = eq(_contained_T_8, asSInt(UInt<1>(0h0))) node contained = or(_contained_T_4, _contained_T_9) when contained : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T = and(contained, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T connect inclusive_cache_bank_sched.io.req.bits.address, ctrls.io.flush_req.bits node _T = and(contained, inclusive_cache_bank_sched.io.req.ready) when _T : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1)
module InclusiveCache( // @[InclusiveCache.scala:108:9] input clock, // @[InclusiveCache.scala:108:9] input reset, // @[InclusiveCache.scala:108:9] output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_out_a_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_out_c_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43] wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43] wire auto_ctrls_ctrl_in_a_valid_0 = auto_ctrls_ctrl_in_a_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_a_bits_opcode_0 = auto_ctrls_ctrl_in_a_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_a_bits_param_0 = auto_ctrls_ctrl_in_a_bits_param; // @[InclusiveCache.scala:108:9] wire [1:0] auto_ctrls_ctrl_in_a_bits_size_0 = auto_ctrls_ctrl_in_a_bits_size; // @[InclusiveCache.scala:108:9] wire [10:0] auto_ctrls_ctrl_in_a_bits_source_0 = auto_ctrls_ctrl_in_a_bits_source; // @[InclusiveCache.scala:108:9] wire [25:0] auto_ctrls_ctrl_in_a_bits_address_0 = auto_ctrls_ctrl_in_a_bits_address; // @[InclusiveCache.scala:108:9] wire [7:0] auto_ctrls_ctrl_in_a_bits_mask_0 = auto_ctrls_ctrl_in_a_bits_mask; // @[InclusiveCache.scala:108:9] wire [63:0] auto_ctrls_ctrl_in_a_bits_data_0 = auto_ctrls_ctrl_in_a_bits_data; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_a_bits_corrupt_0 = auto_ctrls_ctrl_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_d_ready_0 = auto_ctrls_ctrl_in_d_ready; // @[InclusiveCache.scala:108:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[InclusiveCache.scala:108:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[InclusiveCache.scala:108:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[InclusiveCache.scala:108:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[InclusiveCache.scala:108:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[InclusiveCache.scala:108:9] wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[InclusiveCache.scala:108:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[InclusiveCache.scala:108:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[InclusiveCache.scala:108:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[InclusiveCache.scala:108:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[InclusiveCache.scala:108:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[InclusiveCache.scala:108:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[InclusiveCache.scala:108:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[InclusiveCache.scala:108:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[InclusiveCache.scala:108:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[InclusiveCache.scala:108:9] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [7:0] auto_out_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [7:0] nodeOut_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [31:0] auto_out_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [31:0] nodeOut_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_source = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_source = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_b_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_b_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_a_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_b_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_c_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire [63:0] auto_in_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_valid = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_valid = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_ctrls_ctrl_in_d_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire [1:0] auto_out_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire [1:0] nodeOut_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[InclusiveCache.scala:108:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[InclusiveCache.scala:108:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[InclusiveCache.scala:108:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[InclusiveCache.scala:108:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[InclusiveCache.scala:108:9] wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[InclusiveCache.scala:108:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[InclusiveCache.scala:108:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[InclusiveCache.scala:108:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[InclusiveCache.scala:108:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_c_ready = auto_out_c_ready_0; // @[InclusiveCache.scala:108:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[InclusiveCache.scala:108:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[InclusiveCache.scala:108:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [10:0] auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9] wire auto_in_a_ready_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9] wire [5:0] auto_in_b_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9] wire auto_in_b_valid_0; // @[InclusiveCache.scala:108:9] wire auto_in_c_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [5:0] auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9] wire [7:0] auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_out_a_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_out_c_valid_0; // @[InclusiveCache.scala:108:9] wire auto_out_d_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9] wire auto_out_e_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[InclusiveCache.scala:108:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[InclusiveCache.scala:108:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[InclusiveCache.scala:108:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[InclusiveCache.scala:108:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[InclusiveCache.scala:108:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_a_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_a_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14] wire [31:0] _nodeIn_b_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_1 = {1'h0, _nodeIn_b_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeIn_b_bits_address = _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14] wire [31:0] _nodeOut_c_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_c_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeOut_c_bits_address = _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14] wire [63:0] _contained_T = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [64:0] _contained_T_1 = {1'h0, _contained_T}; // @[Nodes.scala:27:25] wire [64:0] _contained_T_2 = _contained_T_1 & 65'h1FFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [64:0] _contained_T_3 = _contained_T_2; // @[Parameters.scala:137:46] wire _contained_T_4 = _contained_T_3 == 65'h0; // @[Parameters.scala:137:{46,59}] wire [63:0] _contained_T_5 = {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [64:0] _contained_T_6 = {1'h0, _contained_T_5}; // @[Nodes.scala:27:25] wire [64:0] _contained_T_7 = _contained_T_6 & 65'h1FFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [64:0] _contained_T_8 = _contained_T_7; // @[Parameters.scala:137:46] wire _contained_T_9 = _contained_T_8 == 65'h0; // @[Parameters.scala:137:{46,59}] wire contained = _contained_T_4 | _contained_T_9; // @[Parameters.scala:137:59] wire _inclusive_cache_bank_sched_io_req_valid_T = contained & _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43, :169:67, :172:41] InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43] .clock (clock), .reset (reset), .auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready_0), .auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid_0), .auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size_0), .auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source_0), .auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data_0), .io_flush_match (contained), // @[InclusiveCache.scala:169:67] .io_flush_req_ready (contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:25] .io_flush_req_valid (_ctrls_io_flush_req_valid), .io_flush_req_bits (_ctrls_io_flush_req_bits), .io_flush_resp (_inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29] ); // @[InclusiveCache.scala:103:43] TLMonitor_49 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), .io_in_b_bits_param (nodeIn_b_bits_param), .io_in_b_bits_source (nodeIn_b_bits_source), .io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), .io_in_c_ready (nodeIn_c_ready), .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), .io_in_d_bits_opcode (nodeIn_d_bits_opcode), .io_in_d_bits_param (nodeIn_d_bits_param), .io_in_d_bits_size (nodeIn_d_bits_size), .io_in_d_bits_source (nodeIn_d_bits_source), .io_in_d_bits_sink (nodeIn_d_bits_sink), .io_in_d_bits_denied (nodeIn_d_bits_denied), .io_in_d_bits_data (nodeIn_d_bits_data), .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_out_a_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_out_a_valid (nodeOut_a_valid), .io_out_a_bits_opcode (nodeOut_a_bits_opcode), .io_out_a_bits_param (nodeOut_a_bits_param), .io_out_a_bits_size (nodeOut_a_bits_size), .io_out_a_bits_source (nodeOut_a_bits_source), .io_out_a_bits_address (_inclusive_cache_bank_sched_io_out_a_bits_address), .io_out_a_bits_mask (nodeOut_a_bits_mask), .io_out_a_bits_data (nodeOut_a_bits_data), .io_out_a_bits_corrupt (nodeOut_a_bits_corrupt), .io_out_c_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_out_c_valid (nodeOut_c_valid), .io_out_c_bits_opcode (nodeOut_c_bits_opcode), .io_out_c_bits_param (nodeOut_c_bits_param), .io_out_c_bits_size (nodeOut_c_bits_size), .io_out_c_bits_source (nodeOut_c_bits_source), .io_out_c_bits_address (_inclusive_cache_bank_sched_io_out_c_bits_address), .io_out_c_bits_data (nodeOut_c_bits_data), .io_out_c_bits_corrupt (nodeOut_c_bits_corrupt), .io_out_d_ready (nodeOut_d_ready), .io_out_d_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_out_d_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_out_d_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_out_d_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_out_d_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_out_d_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_out_d_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_out_d_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_out_d_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_out_e_valid (nodeOut_e_valid), .io_out_e_bits_sink (nodeOut_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_io_req_ready), .io_req_valid (_inclusive_cache_bank_sched_io_req_valid_T), // @[InclusiveCache.scala:172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid) ); // @[InclusiveCache.scala:137:29] assign _nodeOut_a_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:137:31] assign _nodeOut_a_bits_address_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:248:14] assign _nodeIn_b_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:137:31] assign _nodeIn_b_bits_address_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:248:14] assign _nodeOut_c_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:137:31] assign _nodeOut_c_bits_address_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:248:14] assign auto_ctrls_ctrl_in_a_ready = auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_valid = auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_opcode = auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_size = auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_source = auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_data = auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[InclusiveCache.scala:108:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_2 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_2( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_314 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_314( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s4k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_32 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s4k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s4k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_32 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_118 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_118( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_cbus : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_4 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in wire initval : { state : UInt<2>} connect initval.state, UInt<1>(0h0) wire _cam_s_WIRE : { state : UInt<2>}[1] connect _cam_s_WIRE[0], initval regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1) node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2) node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<14>(0h2000)) node _a_canLogical_T_5 = cvt(_a_canLogical_T_4) node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<15>(0h2000))) node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6) node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0))) node _a_canLogical_T_9 = and(_a_canLogical_T_3, _a_canLogical_T_8) node _a_canLogical_T_10 = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canLogical_T_11 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canLogical_T_12 = cvt(_a_canLogical_T_11) node _a_canLogical_T_13 = and(_a_canLogical_T_12, asSInt(UInt<15>(0h2000))) node _a_canLogical_T_14 = asSInt(_a_canLogical_T_13) node _a_canLogical_T_15 = eq(_a_canLogical_T_14, asSInt(UInt<1>(0h0))) node _a_canLogical_T_16 = and(_a_canLogical_T_10, _a_canLogical_T_15) node _a_canLogical_T_17 = or(UInt<1>(0h0), _a_canLogical_T_9) node _a_canLogical_T_18 = or(_a_canLogical_T_17, _a_canLogical_T_16) node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_18) node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1) node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2) node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<14>(0h2000)) node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4) node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<15>(0h2000))) node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6) node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_9 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_8) node _a_canArithmetic_T_10 = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canArithmetic_T_11 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canArithmetic_T_12 = cvt(_a_canArithmetic_T_11) node _a_canArithmetic_T_13 = and(_a_canArithmetic_T_12, asSInt(UInt<15>(0h2000))) node _a_canArithmetic_T_14 = asSInt(_a_canArithmetic_T_13) node _a_canArithmetic_T_15 = eq(_a_canArithmetic_T_14, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_16 = and(_a_canArithmetic_T_10, _a_canArithmetic_T_15) node _a_canArithmetic_T_17 = or(UInt<1>(0h0), _a_canArithmetic_T_9) node _a_canArithmetic_T_18 = or(_a_canArithmetic_T_17, _a_canArithmetic_T_16) node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_18) node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_fifoId_T_1 = cvt(_a_fifoId_T) node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) node _indexes_T = bits(cam_a[0].bits.data, 0, 0) node _indexes_T_1 = bits(cam_d[0].data, 0, 0) node indexes_0 = cat(_indexes_T, _indexes_T_1) node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) node _indexes_T_3 = bits(cam_d[0].data, 1, 1) node indexes_1 = cat(_indexes_T_2, _indexes_T_3) node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) node _indexes_T_5 = bits(cam_d[0].data, 2, 2) node indexes_2 = cat(_indexes_T_4, _indexes_T_5) node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) node _indexes_T_7 = bits(cam_d[0].data, 3, 3) node indexes_3 = cat(_indexes_T_6, _indexes_T_7) node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) node _indexes_T_9 = bits(cam_d[0].data, 4, 4) node indexes_4 = cat(_indexes_T_8, _indexes_T_9) node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) node _indexes_T_11 = bits(cam_d[0].data, 5, 5) node indexes_5 = cat(_indexes_T_10, _indexes_T_11) node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) node _indexes_T_13 = bits(cam_d[0].data, 6, 6) node indexes_6 = cat(_indexes_T_12, _indexes_T_13) node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) node _indexes_T_15 = bits(cam_d[0].data, 7, 7) node indexes_7 = cat(_indexes_T_14, _indexes_T_15) node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) node _indexes_T_17 = bits(cam_d[0].data, 8, 8) node indexes_8 = cat(_indexes_T_16, _indexes_T_17) node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) node _indexes_T_19 = bits(cam_d[0].data, 9, 9) node indexes_9 = cat(_indexes_T_18, _indexes_T_19) node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) node _indexes_T_21 = bits(cam_d[0].data, 10, 10) node indexes_10 = cat(_indexes_T_20, _indexes_T_21) node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) node _indexes_T_23 = bits(cam_d[0].data, 11, 11) node indexes_11 = cat(_indexes_T_22, _indexes_T_23) node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) node _indexes_T_25 = bits(cam_d[0].data, 12, 12) node indexes_12 = cat(_indexes_T_24, _indexes_T_25) node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) node _indexes_T_27 = bits(cam_d[0].data, 13, 13) node indexes_13 = cat(_indexes_T_26, _indexes_T_27) node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) node _indexes_T_29 = bits(cam_d[0].data, 14, 14) node indexes_14 = cat(_indexes_T_28, _indexes_T_29) node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) node _indexes_T_31 = bits(cam_d[0].data, 15, 15) node indexes_15 = cat(_indexes_T_30, _indexes_T_31) node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) node _indexes_T_33 = bits(cam_d[0].data, 16, 16) node indexes_16 = cat(_indexes_T_32, _indexes_T_33) node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) node _indexes_T_35 = bits(cam_d[0].data, 17, 17) node indexes_17 = cat(_indexes_T_34, _indexes_T_35) node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) node _indexes_T_37 = bits(cam_d[0].data, 18, 18) node indexes_18 = cat(_indexes_T_36, _indexes_T_37) node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) node _indexes_T_39 = bits(cam_d[0].data, 19, 19) node indexes_19 = cat(_indexes_T_38, _indexes_T_39) node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) node _indexes_T_41 = bits(cam_d[0].data, 20, 20) node indexes_20 = cat(_indexes_T_40, _indexes_T_41) node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) node _indexes_T_43 = bits(cam_d[0].data, 21, 21) node indexes_21 = cat(_indexes_T_42, _indexes_T_43) node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) node _indexes_T_45 = bits(cam_d[0].data, 22, 22) node indexes_22 = cat(_indexes_T_44, _indexes_T_45) node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) node _indexes_T_47 = bits(cam_d[0].data, 23, 23) node indexes_23 = cat(_indexes_T_46, _indexes_T_47) node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) node _indexes_T_49 = bits(cam_d[0].data, 24, 24) node indexes_24 = cat(_indexes_T_48, _indexes_T_49) node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) node _indexes_T_51 = bits(cam_d[0].data, 25, 25) node indexes_25 = cat(_indexes_T_50, _indexes_T_51) node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) node _indexes_T_53 = bits(cam_d[0].data, 26, 26) node indexes_26 = cat(_indexes_T_52, _indexes_T_53) node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) node _indexes_T_55 = bits(cam_d[0].data, 27, 27) node indexes_27 = cat(_indexes_T_54, _indexes_T_55) node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) node _indexes_T_57 = bits(cam_d[0].data, 28, 28) node indexes_28 = cat(_indexes_T_56, _indexes_T_57) node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) node _indexes_T_59 = bits(cam_d[0].data, 29, 29) node indexes_29 = cat(_indexes_T_58, _indexes_T_59) node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) node _indexes_T_61 = bits(cam_d[0].data, 30, 30) node indexes_30 = cat(_indexes_T_60, _indexes_T_61) node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) node _indexes_T_63 = bits(cam_d[0].data, 31, 31) node indexes_31 = cat(_indexes_T_62, _indexes_T_63) node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) node _indexes_T_65 = bits(cam_d[0].data, 32, 32) node indexes_32 = cat(_indexes_T_64, _indexes_T_65) node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) node _indexes_T_67 = bits(cam_d[0].data, 33, 33) node indexes_33 = cat(_indexes_T_66, _indexes_T_67) node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) node _indexes_T_69 = bits(cam_d[0].data, 34, 34) node indexes_34 = cat(_indexes_T_68, _indexes_T_69) node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) node _indexes_T_71 = bits(cam_d[0].data, 35, 35) node indexes_35 = cat(_indexes_T_70, _indexes_T_71) node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) node _indexes_T_73 = bits(cam_d[0].data, 36, 36) node indexes_36 = cat(_indexes_T_72, _indexes_T_73) node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) node _indexes_T_75 = bits(cam_d[0].data, 37, 37) node indexes_37 = cat(_indexes_T_74, _indexes_T_75) node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) node _indexes_T_77 = bits(cam_d[0].data, 38, 38) node indexes_38 = cat(_indexes_T_76, _indexes_T_77) node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) node _indexes_T_79 = bits(cam_d[0].data, 39, 39) node indexes_39 = cat(_indexes_T_78, _indexes_T_79) node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) node _indexes_T_81 = bits(cam_d[0].data, 40, 40) node indexes_40 = cat(_indexes_T_80, _indexes_T_81) node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) node _indexes_T_83 = bits(cam_d[0].data, 41, 41) node indexes_41 = cat(_indexes_T_82, _indexes_T_83) node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) node _indexes_T_85 = bits(cam_d[0].data, 42, 42) node indexes_42 = cat(_indexes_T_84, _indexes_T_85) node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) node _indexes_T_87 = bits(cam_d[0].data, 43, 43) node indexes_43 = cat(_indexes_T_86, _indexes_T_87) node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) node _indexes_T_89 = bits(cam_d[0].data, 44, 44) node indexes_44 = cat(_indexes_T_88, _indexes_T_89) node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) node _indexes_T_91 = bits(cam_d[0].data, 45, 45) node indexes_45 = cat(_indexes_T_90, _indexes_T_91) node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) node _indexes_T_93 = bits(cam_d[0].data, 46, 46) node indexes_46 = cat(_indexes_T_92, _indexes_T_93) node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) node _indexes_T_95 = bits(cam_d[0].data, 47, 47) node indexes_47 = cat(_indexes_T_94, _indexes_T_95) node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) node _indexes_T_97 = bits(cam_d[0].data, 48, 48) node indexes_48 = cat(_indexes_T_96, _indexes_T_97) node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) node _indexes_T_99 = bits(cam_d[0].data, 49, 49) node indexes_49 = cat(_indexes_T_98, _indexes_T_99) node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) node _indexes_T_101 = bits(cam_d[0].data, 50, 50) node indexes_50 = cat(_indexes_T_100, _indexes_T_101) node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) node _indexes_T_103 = bits(cam_d[0].data, 51, 51) node indexes_51 = cat(_indexes_T_102, _indexes_T_103) node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) node _indexes_T_105 = bits(cam_d[0].data, 52, 52) node indexes_52 = cat(_indexes_T_104, _indexes_T_105) node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) node _indexes_T_107 = bits(cam_d[0].data, 53, 53) node indexes_53 = cat(_indexes_T_106, _indexes_T_107) node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) node _indexes_T_109 = bits(cam_d[0].data, 54, 54) node indexes_54 = cat(_indexes_T_108, _indexes_T_109) node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) node _indexes_T_111 = bits(cam_d[0].data, 55, 55) node indexes_55 = cat(_indexes_T_110, _indexes_T_111) node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) node _indexes_T_113 = bits(cam_d[0].data, 56, 56) node indexes_56 = cat(_indexes_T_112, _indexes_T_113) node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) node _indexes_T_115 = bits(cam_d[0].data, 57, 57) node indexes_57 = cat(_indexes_T_114, _indexes_T_115) node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) node _indexes_T_117 = bits(cam_d[0].data, 58, 58) node indexes_58 = cat(_indexes_T_116, _indexes_T_117) node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) node _indexes_T_119 = bits(cam_d[0].data, 59, 59) node indexes_59 = cat(_indexes_T_118, _indexes_T_119) node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) node _indexes_T_121 = bits(cam_d[0].data, 60, 60) node indexes_60 = cat(_indexes_T_120, _indexes_T_121) node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) node _indexes_T_123 = bits(cam_d[0].data, 61, 61) node indexes_61 = cat(_indexes_T_122, _indexes_T_123) node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) node _indexes_T_125 = bits(cam_d[0].data, 62, 62) node indexes_62 = cat(_indexes_T_124, _indexes_T_125) node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) node _indexes_T_127 = bits(cam_d[0].data, 63, 63) node indexes_63 = cat(_indexes_T_126, _indexes_T_127) node _logic_out_T = dshr(cam_a[0].lut, indexes_0) node _logic_out_T_1 = bits(_logic_out_T, 0, 0) node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) node logic_out = cat(logic_out_hi, logic_out_lo) node unsigned = bits(cam_a[0].bits.param, 1, 1) node take_max = bits(cam_a[0].bits.param, 0, 0) node adder = bits(cam_a[0].bits.param, 2, 2) node _signSel_T = not(cam_a[0].bits.mask) node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) node _signSel_T_2 = or(_signSel_T, _signSel_T_1) node signSel = not(_signSel_T_2) node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) node signbits_a = cat(signbits_a_hi, signbits_a_lo) node _signbits_d_T = bits(cam_d[0].data, 7, 7) node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) node signbits_d = cat(signbits_d_hi, signbits_d_lo) node _signbit_a_T = and(signbits_a, signSel) node _signbit_a_T_1 = shl(_signbit_a_T, 1) node signbit_a = bits(_signbit_a_T_1, 7, 0) node _signbit_d_T = and(signbits_d, signSel) node _signbit_d_T_1 = shl(_signbit_d_T, 1) node signbit_d = bits(_signbit_d_T_1, 7, 0) node _signext_a_T = shl(signbit_a, 1) node _signext_a_T_1 = bits(_signext_a_T, 7, 0) node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) node _signext_a_T_3 = shl(_signext_a_T_2, 2) node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) node _signext_a_T_6 = shl(_signext_a_T_5, 4) node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) node signext_a = cat(signext_a_hi, signext_a_lo) node _signext_d_T = shl(signbit_d, 1) node _signext_d_T_1 = bits(_signext_d_T, 7, 0) node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) node _signext_d_T_3 = shl(_signext_d_T_2, 2) node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) node _signext_d_T_6 = shl(_signext_d_T_5, 4) node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) node signext_d = cat(signext_d_hi, signext_d_lo) node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) node wide_mask = cat(wide_mask_hi, wide_mask_lo) node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) node a_a_ext = or(_a_a_ext_T, signext_a) node _a_d_ext_T = and(cam_d[0].data, wide_mask) node a_d_ext = or(_a_d_ext_T, signext_d) node _a_d_inv_T = not(a_d_ext) node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) node _adder_out_T = add(a_a_ext, a_d_inv) node adder_out = tail(_adder_out_T, 1) node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) node _a_bigger_T = bits(a_a_ext, 63, 63) node _a_bigger_T_1 = bits(a_d_ext, 63, 63) node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) node _a_bigger_T_3 = bits(adder_out, 63, 63) node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) node pick_a = eq(take_max, a_bigger) node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) node arith_out = mux(adder, adder_out, _arith_out_T) node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) node amo_data = mux(_amo_data_T, logic_out, arith_out) wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) node _a_allow_T_1 = or(a_isSupported, cam_free_0) node a_allow = and(_a_allow_T, _a_allow_T_1) node _nodeIn_a_ready_T = and(source_i.ready, a_allow) connect nodeIn.a.ready, _nodeIn_a_ready_T node _source_i_valid_T = and(nodeIn.a.valid, a_allow) connect source_i.valid, _source_i_valid_T connect source_i.bits, nodeIn.a.bits node _T = eq(a_isSupported, UInt<1>(0h0)) when _T : connect source_i.bits.opcode, UInt<3>(0h4) connect source_i.bits.param, UInt<1>(0h0) wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect source_c.valid, cam_amo_0 node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc)) node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h2000)) node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<15>(0h2000))) node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6)) node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11) node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12) node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0)) node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14) node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<15>(0h2000))) node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16) node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_19 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_18) node _source_c_bits_legal_T_20 = or(UInt<1>(0h0), _source_c_bits_legal_T_9) node source_c_bits_legal = or(_source_c_bits_legal_T_20, _source_c_bits_legal_T_19) wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect source_c_bits_a.opcode, UInt<1>(0h0) connect source_c_bits_a.param, UInt<1>(0h0) connect source_c_bits_a.size, cam_a[0].bits.size connect source_c_bits_a.source, cam_a[0].bits.source connect source_c_bits_a.address, cam_a[0].bits.address node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) connect source_c_bits_a.mask, _source_c_bits_a_mask_T connect source_c_bits_a.data, amo_data connect source_c_bits_a.corrupt, _source_c_bits_T connect source_c.bits, source_c_bits_a node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size) node _decode_T_1 = bits(_decode_T, 11, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_1 = mux(opdata, decode, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, nodeOut.a.ready) node _readys_T = cat(source_i.valid, source_c.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 1, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = bits(_readys_T_3, 1, 0) node _readys_T_5 = shl(_readys_T_4, 1) node _readys_T_6 = bits(_readys_T_5, 1, 0) node _readys_T_7 = not(_readys_T_6) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], source_c.valid) node _winner_T_1 = and(readys[1], source_i.valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_3 = eq(winner[0], UInt<1>(0h0)) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) node _T_6 = eq(winner[1], UInt<1>(0h0)) node _T_7 = or(_T_5, _T_6) node _T_8 = and(_T_4, _T_7) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_8, UInt<1>(0h1), "") : assert node _T_12 = or(source_c.valid, source_i.valid) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = or(winner[0], winner[1]) node _T_15 = or(_T_13, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) connect source_c.ready, _source_c_ready_T node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) connect source_i.ready, _source_i_ready_T node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) wire _nodeOut_a_valid_WIRE : UInt<1> connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) connect nodeOut.a.valid, _nodeOut_a_valid_T_4 wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) wire _nodeOut_a_bits_WIRE_1 : UInt<1> connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) wire _nodeOut_a_bits_WIRE_2 : UInt<64> connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) wire _nodeOut_a_bits_WIRE_3 : UInt<8> connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 wire _nodeOut_a_bits_WIRE_4 : { } connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 wire _nodeOut_a_bits_WIRE_5 : { } connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) wire _nodeOut_a_bits_WIRE_6 : UInt<26> connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11 connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6 node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) wire _nodeOut_a_bits_WIRE_7 : UInt<5> connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14 connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7 node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) wire _nodeOut_a_bits_WIRE_8 : UInt<4> connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17 connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8 node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) wire _nodeOut_a_bits_WIRE_9 : UInt<3> connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20 connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9 node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) wire _nodeOut_a_bits_WIRE_10 : UInt<3> connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23 connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10 connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode node _T_19 = and(source_i.ready, source_i.valid) node _T_20 = eq(a_isSupported, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : when a_cam_sel_free_0 : connect cam_a[0].fifoId, UInt<1>(0h0) connect cam_a[0].bits, nodeIn.a.bits node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) connect cam_a[0].lut, _cam_a_0_lut_T_6 when a_cam_sel_free_0 : connect cam_s[0].state, UInt<2>(0h3) node _T_22 = and(source_c.ready, source_c.valid) when _T_22 : when a_cam_sel_put_0 : connect cam_s[0].state, UInt<1>(0h1) node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0) node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0) node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) node _T_24 = and(_T_23, d_first) when _T_24 : node _T_25 = and(d_cam_sel_0, d_ackd) when _T_25 : connect cam_d[0].data, nodeOut.d.bits.data connect cam_d[0].denied, nodeOut.d.bits.denied connect cam_d[0].corrupt, nodeOut.d.bits.corrupt when d_cam_sel_0 : node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) connect cam_s[0].state, _cam_s_0_state_T node _d_drop_T = and(d_first, d_ackd) node d_drop = and(_d_drop_T, d_cam_sel_any) node _d_replace_T = and(d_first, d_ack) node d_replace = and(_d_replace_T, d_cam_sel_match_0) node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) connect nodeIn.d.valid, _nodeIn_d_valid_T_1 node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) connect nodeOut.d.ready, _nodeOut_d_ready_T connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn.d.bits.data, nodeOut.d.bits.data connect nodeIn.d.bits.denied, nodeOut.d.bits.denied connect nodeIn.d.bits.sink, nodeOut.d.bits.sink connect nodeIn.d.bits.source, nodeOut.d.bits.source connect nodeIn.d.bits.size, nodeOut.d.bits.size connect nodeIn.d.bits.param, nodeOut.d.bits.param connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode when d_replace : connect nodeIn.d.bits.opcode, UInt<1>(0h1) connect nodeIn.d.bits.data, cam_d[0].data node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_10 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_11 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28] wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28] wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83] wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60] wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85] wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _a_canLogical_T_10 = 1'h0; // @[Parameters.scala:684:29] wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:54] wire _a_canArithmetic_T_10 = 1'h0; // @[Parameters.scala:684:29] wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:54] wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [26:0] _a_fifoId_T_2 = 27'h0; // @[Parameters.scala:137:46] wire [26:0] _a_fifoId_T_3 = 27'h0; // @[Parameters.scala:137:46] wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27] wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [4:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [4:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [25:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9] wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9] wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28] wire [4:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28] wire [25:0] _a_canLogical_T_11 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [25:0] _a_canArithmetic_T_11 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [25:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [25:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28] wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28] wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28] wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [4:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [25:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17] wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34] reg [4:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] wire [4:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17] reg [25:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [25:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [25:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44] wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58] wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82] wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire cam_amo_0; // @[AtomicAutomata.scala:87:44] assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44] wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68] assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68] wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56] wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80] wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28] wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49] wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}] wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96] wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49] wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38] wire _a_canLogical_T_1; // @[Parameters.scala:92:38] assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38] wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38] assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38] wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}] wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29] wire [25:0] _GEN_1 = {nodeIn_a_bits_address[25:14], nodeIn_a_bits_address[13:0] ^ 14'h2000}; // @[Parameters.scala:137:31] wire [25:0] _a_canLogical_T_4; // @[Parameters.scala:137:31] assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31] wire [25:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31] wire [26:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}] wire [26:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 27'h2000; // @[Parameters.scala:137:{41,46}] wire [26:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46] wire _a_canLogical_T_8 = _a_canLogical_T_7 == 27'h0; // @[Parameters.scala:137:{46,59}] wire _a_canLogical_T_9 = _a_canLogical_T_3 & _a_canLogical_T_8; // @[Parameters.scala:684:{29,54}] wire _a_canLogical_T_17 = _a_canLogical_T_9; // @[Parameters.scala:684:54, :686:26] wire [26:0] _a_canLogical_T_12 = {1'h0, _a_canLogical_T_11}; // @[Parameters.scala:137:{31,41}] wire [26:0] _a_canLogical_T_13 = _a_canLogical_T_12 & 27'h2000; // @[Parameters.scala:137:{41,46}] wire [26:0] _a_canLogical_T_14 = _a_canLogical_T_13; // @[Parameters.scala:137:46] wire _a_canLogical_T_15 = _a_canLogical_T_14 == 27'h0; // @[Parameters.scala:137:{46,59}] wire _a_canLogical_T_18 = _a_canLogical_T_17; // @[Parameters.scala:686:26] wire a_canLogical = _a_canLogical_T_18; // @[Parameters.scala:686:26] wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}] wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29] wire [26:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}] wire [26:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 27'h2000; // @[Parameters.scala:137:{41,46}] wire [26:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 27'h0; // @[Parameters.scala:137:{46,59}] wire _a_canArithmetic_T_9 = _a_canArithmetic_T_3 & _a_canArithmetic_T_8; // @[Parameters.scala:684:{29,54}] wire _a_canArithmetic_T_17 = _a_canArithmetic_T_9; // @[Parameters.scala:684:54, :686:26] wire [26:0] _a_canArithmetic_T_12 = {1'h0, _a_canArithmetic_T_11}; // @[Parameters.scala:137:{31,41}] wire [26:0] _a_canArithmetic_T_13 = _a_canArithmetic_T_12 & 27'h2000; // @[Parameters.scala:137:{41,46}] wire [26:0] _a_canArithmetic_T_14 = _a_canArithmetic_T_13; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_15 = _a_canArithmetic_T_14 == 27'h0; // @[Parameters.scala:137:{46,59}] wire _a_canArithmetic_T_18 = _a_canArithmetic_T_17; // @[Parameters.scala:686:26] wire a_canArithmetic = _a_canArithmetic_T_18; // @[Parameters.scala:686:26] wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47] wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47] wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63] wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}] wire [26:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}] wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}] wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57] wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28] wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42] wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42] wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39] wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25] wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39] wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}] wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}] wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29] wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29] wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38] wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}] wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}] wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38] wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}] wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}] wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17] wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17] wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17] wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17] wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17] wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17] wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17] wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17] wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40] wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40] wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17] wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17] wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17] wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17] wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17] wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17] wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17] wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17] wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40] wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40] wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40] wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28] wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}] wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28] wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}] wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43] wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}] wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33] wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33] wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49] wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35] wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}] wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50] wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}] wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65] wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}] wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}] wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31] wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50] wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}] wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34] wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}] wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17] wire _source_i_ready_T; // @[Arbiter.scala:94:31] wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38] wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28] wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28] wire source_i_ready; // @[AtomicAutomata.scala:154:28] wire source_i_valid; // @[AtomicAutomata.scala:154:28] wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23] wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53] wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}] assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38] assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32] assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32] wire _source_c_ready_T; // @[Arbiter.scala:94:31] wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17] wire source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28] wire [4:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28] wire [25:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28] wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28] wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28] wire source_c_ready; // @[AtomicAutomata.scala:165:28] wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45] assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17] wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29] wire [25:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[25:14], cam_a_0_bits_address[13:0] ^ 14'h2000}; // @[AtomicAutomata.scala:83:24] wire [26:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [26:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 27'h2000; // @[Parameters.scala:137:{41,46}] wire [26:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 27'h0; // @[Parameters.scala:137:{46,59}] wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}] wire _source_c_bits_legal_T_20 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29] wire [26:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [26:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 27'h2000; // @[Parameters.scala:137:{41,46}] wire [26:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 27'h0; // @[Parameters.scala:137:{46,59}] wire _source_c_bits_legal_T_19 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_18; // @[Parameters.scala:684:{29,54}] wire source_c_bits_legal = _source_c_bits_legal_T_20 | _source_c_bits_legal_T_19; // @[Parameters.scala:684:54, :686:26] assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17] assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17] assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10] assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17] assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17] assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10] assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10] wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71] wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46] wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28]
Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_64 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[1024] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5350300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0hf8140000edfe0dd0) connect rom[25], UInt<64>(0h9812000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0h6012000060020000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000015000000) connect rom[70], UInt<64>(0h722c657669666973) connect rom[71], UInt<64>(0h72003074656b636f) connect rom[72], UInt<64>(0h76637369) connect rom[73], UInt<64>(0h400000003000000) connect rom[74], UInt<64>(0h4000000063000000) connect rom[75], UInt<64>(0h400000003000000) connect rom[76], UInt<64>(0h4000000076000000) connect rom[77], UInt<64>(0h400000003000000) connect rom[78], UInt<64>(0h80000083000000) connect rom[79], UInt<64>(0h400000003000000) connect rom[80], UInt<64>(0h100000090000000) connect rom[81], UInt<64>(0h400000003000000) connect rom[82], UInt<64>(0h200000009b000000) connect rom[83], UInt<64>(0h400000003000000) connect rom[84], UInt<64>(0h757063a6000000) connect rom[85], UInt<64>(0h400000003000000) connect rom[86], UInt<64>(0h1000000b2000000) connect rom[87], UInt<64>(0h400000003000000) connect rom[88], UInt<64>(0h40000000d1000000) connect rom[89], UInt<64>(0h400000003000000) connect rom[90], UInt<64>(0h40000000e4000000) connect rom[91], UInt<64>(0h400000003000000) connect rom[92], UInt<64>(0h800000f1000000) connect rom[93], UInt<64>(0h400000003000000) connect rom[94], UInt<64>(0h1000000fe000000) connect rom[95], UInt<64>(0h400000003000000) connect rom[96], UInt<64>(0h2000000009010000) connect rom[97], UInt<64>(0hb00000003000000) connect rom[98], UInt<64>(0h6373697214010000) connect rom[99], UInt<64>(0h393376732c76) connect rom[100], UInt<64>(0h400000003000000) connect rom[101], UInt<64>(0h10000001d010000) connect rom[102], UInt<64>(0h400000003000000) connect rom[103], UInt<64>(0h2e010000) connect rom[104], UInt<64>(0h3800000003000000) connect rom[105], UInt<64>(0h3436767232010000) connect rom[106], UInt<64>(0h7a62636466616d69) connect rom[107], UInt<64>(0h66697a5f72736369) connect rom[108], UInt<64>(0h697a5f6965636e65) connect rom[109], UInt<64>(0h5f68667a5f6d7068) connect rom[110], UInt<64>(0h5f62627a5f61627a) connect rom[111], UInt<64>(0h636f72785f73627a) connect rom[112], UInt<64>(0h30000000074656b) connect rom[113], UInt<64>(0h3c01000004000000) connect rom[114], UInt<64>(0h300000004000000) connect rom[115], UInt<64>(0h5101000004000000) connect rom[116], UInt<64>(0h300000008000000) connect rom[117], UInt<64>(0h6201000005000000) connect rom[118], UInt<64>(0h79616b6f) connect rom[119], UInt<64>(0h400000003000000) connect rom[120], UInt<64>(0h20a1070040000000) connect rom[121], UInt<64>(0h3000000) connect rom[122], UInt<64>(0h100000069010000) connect rom[123], UInt<64>(0h7075727265746e69) connect rom[124], UInt<64>(0h6f72746e6f632d74) connect rom[125], UInt<64>(0h72656c6c) connect rom[126], UInt<64>(0h400000003000000) connect rom[127], UInt<64>(0h100000073010000) connect rom[128], UInt<64>(0hf00000003000000) connect rom[129], UInt<64>(0h637369721b000000) connect rom[130], UInt<64>(0h6e692d7570632c76) connect rom[131], UInt<64>(0h300000000006374) connect rom[132], UInt<64>(0h8401000000000000) connect rom[133], UInt<64>(0h400000003000000) connect rom[134], UInt<64>(0h400000099010000) connect rom[135], UInt<64>(0h200000002000000) connect rom[136], UInt<64>(0h4075706301000000) connect rom[137], UInt<64>(0h300000000000031) connect rom[138], UInt<64>(0h5300000004000000) connect rom[139], UInt<64>(0h300000000000000) connect rom[140], UInt<64>(0h1b00000015000000) connect rom[141], UInt<64>(0h722c657669666973) connect rom[142], UInt<64>(0h72003074656b636f) connect rom[143], UInt<64>(0h76637369) connect rom[144], UInt<64>(0h400000003000000) connect rom[145], UInt<64>(0h4000000063000000) connect rom[146], UInt<64>(0h400000003000000) connect rom[147], UInt<64>(0h4000000076000000) connect rom[148], UInt<64>(0h400000003000000) connect rom[149], UInt<64>(0h80000083000000) connect rom[150], UInt<64>(0h400000003000000) connect rom[151], UInt<64>(0h100000090000000) connect rom[152], UInt<64>(0h400000003000000) connect rom[153], UInt<64>(0h200000009b000000) connect rom[154], UInt<64>(0h400000003000000) connect rom[155], UInt<64>(0h757063a6000000) connect rom[156], UInt<64>(0h400000003000000) connect rom[157], UInt<64>(0h1000000b2000000) connect rom[158], UInt<64>(0h400000003000000) connect rom[159], UInt<64>(0h40000000d1000000) connect rom[160], UInt<64>(0h400000003000000) connect rom[161], UInt<64>(0h40000000e4000000) connect rom[162], UInt<64>(0h400000003000000) connect rom[163], UInt<64>(0h800000f1000000) connect rom[164], UInt<64>(0h400000003000000) connect rom[165], UInt<64>(0h1000000fe000000) connect rom[166], UInt<64>(0h400000003000000) connect rom[167], UInt<64>(0h2000000009010000) connect rom[168], UInt<64>(0hb00000003000000) connect rom[169], UInt<64>(0h6373697214010000) connect rom[170], UInt<64>(0h393376732c76) connect rom[171], UInt<64>(0h400000003000000) connect rom[172], UInt<64>(0h10000001d010000) connect rom[173], UInt<64>(0h400000003000000) connect rom[174], UInt<64>(0h10000002e010000) connect rom[175], UInt<64>(0h3800000003000000) connect rom[176], UInt<64>(0h3436767232010000) connect rom[177], UInt<64>(0h7a62636466616d69) connect rom[178], UInt<64>(0h66697a5f72736369) connect rom[179], UInt<64>(0h697a5f6965636e65) connect rom[180], UInt<64>(0h5f68667a5f6d7068) connect rom[181], UInt<64>(0h5f62627a5f61627a) connect rom[182], UInt<64>(0h636f72785f73627a) connect rom[183], UInt<64>(0h30000000074656b) connect rom[184], UInt<64>(0h3c01000004000000) connect rom[185], UInt<64>(0h300000004000000) connect rom[186], UInt<64>(0h5101000004000000) connect rom[187], UInt<64>(0h300000008000000) connect rom[188], UInt<64>(0h6201000005000000) connect rom[189], UInt<64>(0h79616b6f) connect rom[190], UInt<64>(0h400000003000000) connect rom[191], UInt<64>(0h20a1070040000000) connect rom[192], UInt<64>(0h3000000) connect rom[193], UInt<64>(0h100000069010000) connect rom[194], UInt<64>(0h7075727265746e69) connect rom[195], UInt<64>(0h6f72746e6f632d74) connect rom[196], UInt<64>(0h72656c6c) connect rom[197], UInt<64>(0h400000003000000) connect rom[198], UInt<64>(0h100000073010000) connect rom[199], UInt<64>(0hf00000003000000) connect rom[200], UInt<64>(0h637369721b000000) connect rom[201], UInt<64>(0h6e692d7570632c76) connect rom[202], UInt<64>(0h300000000006374) connect rom[203], UInt<64>(0h8401000000000000) connect rom[204], UInt<64>(0h400000003000000) connect rom[205], UInt<64>(0h500000099010000) connect rom[206], UInt<64>(0h200000002000000) connect rom[207], UInt<64>(0h4075706301000000) connect rom[208], UInt<64>(0h300000000000032) connect rom[209], UInt<64>(0h5300000004000000) connect rom[210], UInt<64>(0h300000000000000) connect rom[211], UInt<64>(0h1b00000014000000) connect rom[212], UInt<64>(0h2c7261622d626375) connect rom[213], UInt<64>(0h697200306d6f6f62) connect rom[214], UInt<64>(0h300000000766373) connect rom[215], UInt<64>(0h6300000004000000) connect rom[216], UInt<64>(0h300000040000000) connect rom[217], UInt<64>(0h7600000004000000) connect rom[218], UInt<64>(0h300000040000000) connect rom[219], UInt<64>(0h8300000004000000) connect rom[220], UInt<64>(0h300000000800000) connect rom[221], UInt<64>(0h9000000004000000) connect rom[222], UInt<64>(0h300000001000000) connect rom[223], UInt<64>(0h9b00000004000000) connect rom[224], UInt<64>(0h300000010000000) connect rom[225], UInt<64>(0ha600000004000000) connect rom[226], UInt<64>(0h300000000757063) connect rom[227], UInt<64>(0hb200000004000000) connect rom[228], UInt<64>(0h300000000000000) connect rom[229], UInt<64>(0hd100000004000000) connect rom[230], UInt<64>(0h300000040000000) connect rom[231], UInt<64>(0he400000004000000) connect rom[232], UInt<64>(0h300000040000000) connect rom[233], UInt<64>(0hf100000004000000) connect rom[234], UInt<64>(0h300000000800000) connect rom[235], UInt<64>(0hfe00000004000000) connect rom[236], UInt<64>(0h300000001000000) connect rom[237], UInt<64>(0h901000004000000) connect rom[238], UInt<64>(0h300000020000000) connect rom[239], UInt<64>(0h140100000b000000) connect rom[240], UInt<64>(0h76732c7663736972) connect rom[241], UInt<64>(0h300000000003933) connect rom[242], UInt<64>(0h1d01000004000000) connect rom[243], UInt<64>(0h300000001000000) connect rom[244], UInt<64>(0h2e01000004000000) connect rom[245], UInt<64>(0h300000002000000) connect rom[246], UInt<64>(0h320100001f000000) connect rom[247], UInt<64>(0h66616d6934367672) connect rom[248], UInt<64>(0h5f727363697a6364) connect rom[249], UInt<64>(0h6965636e6566697a) connect rom[250], UInt<64>(0h6d7068697a5f) connect rom[251], UInt<64>(0h400000003000000) connect rom[252], UInt<64>(0h40000003c010000) connect rom[253], UInt<64>(0h400000003000000) connect rom[254], UInt<64>(0h800000051010000) connect rom[255], UInt<64>(0h500000003000000) connect rom[256], UInt<64>(0h79616b6f62010000) connect rom[257], UInt<64>(0h300000000000000) connect rom[258], UInt<64>(0h4000000004000000) connect rom[259], UInt<64>(0h300000020a10700) connect rom[260], UInt<64>(0h6901000000000000) connect rom[261], UInt<64>(0h65746e6901000000) connect rom[262], UInt<64>(0h6f632d7470757272) connect rom[263], UInt<64>(0h72656c6c6f72746e) connect rom[264], UInt<64>(0h300000000000000) connect rom[265], UInt<64>(0h7301000004000000) connect rom[266], UInt<64>(0h300000001000000) connect rom[267], UInt<64>(0h1b0000000f000000) connect rom[268], UInt<64>(0h70632c7663736972) connect rom[269], UInt<64>(0h63746e692d75) connect rom[270], UInt<64>(0h3000000) connect rom[271], UInt<64>(0h300000084010000) connect rom[272], UInt<64>(0h9901000004000000) connect rom[273], UInt<64>(0h200000006000000) connect rom[274], UInt<64>(0h100000002000000) connect rom[275], UInt<64>(0h3340757063) connect rom[276], UInt<64>(0h400000003000000) connect rom[277], UInt<64>(0h53000000) connect rom[278], UInt<64>(0h1400000003000000) connect rom[279], UInt<64>(0h2d6263751b000000) connect rom[280], UInt<64>(0h6d6f6f622c726162) connect rom[281], UInt<64>(0h76637369720030) connect rom[282], UInt<64>(0h400000003000000) connect rom[283], UInt<64>(0h4000000063000000) connect rom[284], UInt<64>(0h400000003000000) connect rom[285], UInt<64>(0h4000000076000000) connect rom[286], UInt<64>(0h400000003000000) connect rom[287], UInt<64>(0h80000083000000) connect rom[288], UInt<64>(0h400000003000000) connect rom[289], UInt<64>(0h100000090000000) connect rom[290], UInt<64>(0h400000003000000) connect rom[291], UInt<64>(0h100000009b000000) connect rom[292], UInt<64>(0h400000003000000) connect rom[293], UInt<64>(0h757063a6000000) connect rom[294], UInt<64>(0h400000003000000) connect rom[295], UInt<64>(0hb2000000) connect rom[296], UInt<64>(0h400000003000000) connect rom[297], UInt<64>(0h40000000d1000000) connect rom[298], UInt<64>(0h400000003000000) connect rom[299], UInt<64>(0h40000000e4000000) connect rom[300], UInt<64>(0h400000003000000) connect rom[301], UInt<64>(0h800000f1000000) connect rom[302], UInt<64>(0h400000003000000) connect rom[303], UInt<64>(0h1000000fe000000) connect rom[304], UInt<64>(0h400000003000000) connect rom[305], UInt<64>(0h2000000009010000) connect rom[306], UInt<64>(0hb00000003000000) connect rom[307], UInt<64>(0h6373697214010000) connect rom[308], UInt<64>(0h393376732c76) connect rom[309], UInt<64>(0h400000003000000) connect rom[310], UInt<64>(0h10000001d010000) connect rom[311], UInt<64>(0h400000003000000) connect rom[312], UInt<64>(0h30000002e010000) connect rom[313], UInt<64>(0h1f00000003000000) connect rom[314], UInt<64>(0h3436767232010000) connect rom[315], UInt<64>(0h697a636466616d69) connect rom[316], UInt<64>(0h6566697a5f727363) connect rom[317], UInt<64>(0h68697a5f6965636e) connect rom[318], UInt<64>(0h300000000006d70) connect rom[319], UInt<64>(0h3c01000004000000) connect rom[320], UInt<64>(0h300000004000000) connect rom[321], UInt<64>(0h5101000004000000) connect rom[322], UInt<64>(0h300000008000000) connect rom[323], UInt<64>(0h6201000005000000) connect rom[324], UInt<64>(0h79616b6f) connect rom[325], UInt<64>(0h400000003000000) connect rom[326], UInt<64>(0h20a1070040000000) connect rom[327], UInt<64>(0h3000000) connect rom[328], UInt<64>(0h100000069010000) connect rom[329], UInt<64>(0h7075727265746e69) connect rom[330], UInt<64>(0h6f72746e6f632d74) connect rom[331], UInt<64>(0h72656c6c) connect rom[332], UInt<64>(0h400000003000000) connect rom[333], UInt<64>(0h100000073010000) connect rom[334], UInt<64>(0hf00000003000000) connect rom[335], UInt<64>(0h637369721b000000) connect rom[336], UInt<64>(0h6e692d7570632c76) connect rom[337], UInt<64>(0h300000000006374) connect rom[338], UInt<64>(0h8401000000000000) connect rom[339], UInt<64>(0h400000003000000) connect rom[340], UInt<64>(0h700000099010000) connect rom[341], UInt<64>(0h200000002000000) connect rom[342], UInt<64>(0h100000002000000) connect rom[343], UInt<64>(0h66697468) connect rom[344], UInt<64>(0ha00000003000000) connect rom[345], UInt<64>(0h2c6263751b000000) connect rom[346], UInt<64>(0h3066697468) connect rom[347], UInt<64>(0h100000002000000) connect rom[348], UInt<64>(0h384079726f6d656d) connect rom[349], UInt<64>(0h303030303030) connect rom[350], UInt<64>(0h700000003000000) connect rom[351], UInt<64>(0h6f6d656da6000000) connect rom[352], UInt<64>(0h300000000007972) connect rom[353], UInt<64>(0h2e01000008000000) connect rom[354], UInt<64>(0h10000000008) connect rom[355], UInt<64>(0h900000003000000) connect rom[356], UInt<64>(0h6173696462010000) connect rom[357], UInt<64>(0h64656c62) connect rom[358], UInt<64>(0h400000003000000) connect rom[359], UInt<64>(0h300000099010000) connect rom[360], UInt<64>(0h100000002000000) connect rom[361], UInt<64>(0h384079726f6d656d) connect rom[362], UInt<64>(0h30303030303030) connect rom[363], UInt<64>(0h700000003000000) connect rom[364], UInt<64>(0h6f6d656da6000000) connect rom[365], UInt<64>(0h300000000007972) connect rom[366], UInt<64>(0h2e01000008000000) connect rom[367], UInt<64>(0h1000000080) connect rom[368], UInt<64>(0h400000003000000) connect rom[369], UInt<64>(0h200000099010000) connect rom[370], UInt<64>(0h100000002000000) connect rom[371], UInt<64>(0h300000000636f73) connect rom[372], UInt<64>(0h4000000) connect rom[373], UInt<64>(0h300000001000000) connect rom[374], UInt<64>(0hf00000004000000) connect rom[375], UInt<64>(0h300000001000000) connect rom[376], UInt<64>(0h1b00000020000000) connect rom[377], UInt<64>(0h2c7261622d626375) connect rom[378], UInt<64>(0h6472617970696863) connect rom[379], UInt<64>(0h6d697300636f732d) connect rom[380], UInt<64>(0h7375622d656c70) connect rom[381], UInt<64>(0h3000000) connect rom[382], UInt<64>(0h1000000a1010000) connect rom[383], UInt<64>(0h6464612d746f6f62) connect rom[384], UInt<64>(0h6765722d73736572) connect rom[385], UInt<64>(0h3030303140) connect rom[386], UInt<64>(0h800000003000000) connect rom[387], UInt<64>(0h1000002e010000) connect rom[388], UInt<64>(0h300000000100000) connect rom[389], UInt<64>(0ha801000008000000) connect rom[390], UInt<64>(0h6c6f72746e6f63) connect rom[391], UInt<64>(0h100000002000000) connect rom[392], UInt<64>(0h6f632d6568636163) connect rom[393], UInt<64>(0h72656c6c6f72746e) connect rom[394], UInt<64>(0h3030303031303240) connect rom[395], UInt<64>(0h300000000000000) connect rom[396], UInt<64>(0h6500000004000000) connect rom[397], UInt<64>(0h300000040000000) connect rom[398], UInt<64>(0hb201000004000000) connect rom[399], UInt<64>(0h300000002000000) connect rom[400], UInt<64>(0h7800000004000000) connect rom[401], UInt<64>(0h300000000040000) connect rom[402], UInt<64>(0h8500000004000000) connect rom[403], UInt<64>(0h300000000000800) connect rom[404], UInt<64>(0hbe01000000000000) connect rom[405], UInt<64>(0h1d00000003000000) connect rom[406], UInt<64>(0h696669731b000000) connect rom[407], UInt<64>(0h756c636e692c6576) connect rom[408], UInt<64>(0h6863616365766973) connect rom[409], UInt<64>(0h6568636163003065) connect rom[410], UInt<64>(0h300000000000000) connect rom[411], UInt<64>(0h1d01000008000000) connect rom[412], UInt<64>(0h300000002000000) connect rom[413], UInt<64>(0h800000003000000) connect rom[414], UInt<64>(0h1022e010000) connect rom[415], UInt<64>(0h300000000100000) connect rom[416], UInt<64>(0ha801000008000000) connect rom[417], UInt<64>(0h6c6f72746e6f63) connect rom[418], UInt<64>(0h400000003000000) connect rom[419], UInt<64>(0hc000000cc010000) connect rom[420], UInt<64>(0h400000003000000) connect rom[421], UInt<64>(0h100000099010000) connect rom[422], UInt<64>(0h100000002000000) connect rom[423], UInt<64>(0h6f6c635f73756263) connect rom[424], UInt<64>(0h300000000006b63) connect rom[425], UInt<64>(0hde01000004000000) connect rom[426], UInt<64>(0h300000000000000) connect rom[427], UInt<64>(0h5300000004000000) connect rom[428], UInt<64>(0h30000000065cd1d) connect rom[429], UInt<64>(0heb0100000b000000) connect rom[430], UInt<64>(0h6f6c635f73756263) connect rom[431], UInt<64>(0h300000000006b63) connect rom[432], UInt<64>(0h1b0000000c000000) connect rom[433], UInt<64>(0h6c632d6465786966) connect rom[434], UInt<64>(0h2000000006b636f) connect rom[435], UInt<64>(0h6e696c6301000000) connect rom[436], UInt<64>(0h3030303030324074) connect rom[437], UInt<64>(0h300000000000030) connect rom[438], UInt<64>(0h1b0000000d000000) connect rom[439], UInt<64>(0h6c632c7663736972) connect rom[440], UInt<64>(0h30746e69) connect rom[441], UInt<64>(0h4000000003000000) connect rom[442], UInt<64>(0h4000000fe010000) connect rom[443], UInt<64>(0h400000003000000) connect rom[444], UInt<64>(0h500000007000000) connect rom[445], UInt<64>(0h500000003000000) connect rom[446], UInt<64>(0h600000007000000) connect rom[447], UInt<64>(0h600000003000000) connect rom[448], UInt<64>(0h700000007000000) connect rom[449], UInt<64>(0h700000003000000) connect rom[450], UInt<64>(0h300000007000000) connect rom[451], UInt<64>(0h2e01000008000000) connect rom[452], UInt<64>(0h10000000002) connect rom[453], UInt<64>(0h800000003000000) connect rom[454], UInt<64>(0h746e6f63a8010000) connect rom[455], UInt<64>(0h2000000006c6f72) connect rom[456], UInt<64>(0h636f6c6301000000) connect rom[457], UInt<64>(0h4072657461672d6b) connect rom[458], UInt<64>(0h303030303031) connect rom[459], UInt<64>(0h800000003000000) connect rom[460], UInt<64>(0h10002e010000) connect rom[461], UInt<64>(0h300000000100000) connect rom[462], UInt<64>(0ha801000008000000) connect rom[463], UInt<64>(0h6c6f72746e6f63) connect rom[464], UInt<64>(0h100000002000000) connect rom[465], UInt<64>(0h6f632d6775626564) connect rom[466], UInt<64>(0h72656c6c6f72746e) connect rom[467], UInt<64>(0h300000000003040) connect rom[468], UInt<64>(0h1b00000021000000) connect rom[469], UInt<64>(0h642c657669666973) connect rom[470], UInt<64>(0h3331302d67756265) connect rom[471], UInt<64>(0h642c766373697200) connect rom[472], UInt<64>(0h3331302d67756265) connect rom[473], UInt<64>(0h300000000000000) connect rom[474], UInt<64>(0h1202000005000000) connect rom[475], UInt<64>(0h6761746a) connect rom[476], UInt<64>(0h2000000003000000) connect rom[477], UInt<64>(0h4000000fe010000) connect rom[478], UInt<64>(0h5000000ffff0000) connect rom[479], UInt<64>(0h6000000ffff0000) connect rom[480], UInt<64>(0h7000000ffff0000) connect rom[481], UInt<64>(0h3000000ffff0000) connect rom[482], UInt<64>(0h2e01000008000000) connect rom[483], UInt<64>(0h10000000000000) connect rom[484], UInt<64>(0h800000003000000) connect rom[485], UInt<64>(0h746e6f63a8010000) connect rom[486], UInt<64>(0h2000000006c6f72) connect rom[487], UInt<64>(0h6f72726501000000) connect rom[488], UInt<64>(0h6563697665642d72) connect rom[489], UInt<64>(0h3030303340) connect rom[490], UInt<64>(0he00000003000000) connect rom[491], UInt<64>(0h696669731b000000) connect rom[492], UInt<64>(0h726f7272652c6576) connect rom[493], UInt<64>(0h300000000000030) connect rom[494], UInt<64>(0h2e01000008000000) connect rom[495], UInt<64>(0h10000000300000) connect rom[496], UInt<64>(0h100000002000000) connect rom[497], UInt<64>(0h6f6c635f73756266) connect rom[498], UInt<64>(0h300000000006b63) connect rom[499], UInt<64>(0hde01000004000000) connect rom[500], UInt<64>(0h300000000000000) connect rom[501], UInt<64>(0h5300000004000000) connect rom[502], UInt<64>(0h30000000065cd1d) connect rom[503], UInt<64>(0heb0100000b000000) connect rom[504], UInt<64>(0h6f6c635f73756266) connect rom[505], UInt<64>(0h300000000006b63) connect rom[506], UInt<64>(0h1b0000000c000000) connect rom[507], UInt<64>(0h6c632d6465786966) connect rom[508], UInt<64>(0h2000000006b636f) connect rom[509], UInt<64>(0h65746e6901000000) connect rom[510], UInt<64>(0h6f632d7470757272) connect rom[511], UInt<64>(0h72656c6c6f72746e) connect rom[512], UInt<64>(0h3030303030306340) connect rom[513], UInt<64>(0h300000000000000) connect rom[514], UInt<64>(0h7301000004000000) connect rom[515], UInt<64>(0h300000001000000) connect rom[516], UInt<64>(0h1b0000000c000000) connect rom[517], UInt<64>(0h6c702c7663736972) connect rom[518], UInt<64>(0h300000000306369) connect rom[519], UInt<64>(0h8401000000000000) connect rom[520], UInt<64>(0h4000000003000000) connect rom[521], UInt<64>(0h4000000fe010000) connect rom[522], UInt<64>(0h40000000b000000) connect rom[523], UInt<64>(0h500000009000000) connect rom[524], UInt<64>(0h50000000b000000) connect rom[525], UInt<64>(0h600000009000000) connect rom[526], UInt<64>(0h60000000b000000) connect rom[527], UInt<64>(0h700000009000000) connect rom[528], UInt<64>(0h70000000b000000) connect rom[529], UInt<64>(0h300000009000000) connect rom[530], UInt<64>(0h2e01000008000000) connect rom[531], UInt<64>(0h40000000c) connect rom[532], UInt<64>(0h800000003000000) connect rom[533], UInt<64>(0h746e6f63a8010000) connect rom[534], UInt<64>(0h3000000006c6f72) connect rom[535], UInt<64>(0h1f02000004000000) connect rom[536], UInt<64>(0h300000001000000) connect rom[537], UInt<64>(0h3202000004000000) connect rom[538], UInt<64>(0h300000001000000) connect rom[539], UInt<64>(0h9901000004000000) connect rom[540], UInt<64>(0h200000009000000) connect rom[541], UInt<64>(0h7375626d01000000) connect rom[542], UInt<64>(0h6b636f6c635f) connect rom[543], UInt<64>(0h400000003000000) connect rom[544], UInt<64>(0hde010000) connect rom[545], UInt<64>(0h400000003000000) connect rom[546], UInt<64>(0h65cd1d53000000) connect rom[547], UInt<64>(0hb00000003000000) connect rom[548], UInt<64>(0h7375626deb010000) connect rom[549], UInt<64>(0h6b636f6c635f) connect rom[550], UInt<64>(0hc00000003000000) connect rom[551], UInt<64>(0h657869661b000000) connect rom[552], UInt<64>(0h6b636f6c632d64) connect rom[553], UInt<64>(0h100000002000000) connect rom[554], UInt<64>(0h6f6c635f73756270) connect rom[555], UInt<64>(0h300000000006b63) connect rom[556], UInt<64>(0hde01000004000000) connect rom[557], UInt<64>(0h300000000000000) connect rom[558], UInt<64>(0h5300000004000000) connect rom[559], UInt<64>(0h30000000065cd1d) connect rom[560], UInt<64>(0heb0100000b000000) connect rom[561], UInt<64>(0h6f6c635f73756270) connect rom[562], UInt<64>(0h300000000006b63) connect rom[563], UInt<64>(0h1b0000000c000000) connect rom[564], UInt<64>(0h6c632d6465786966) connect rom[565], UInt<64>(0h3000000006b636f) connect rom[566], UInt<64>(0h9901000004000000) connect rom[567], UInt<64>(0h200000008000000) connect rom[568], UInt<64>(0h406d6f7201000000) connect rom[569], UInt<64>(0h3030303031) connect rom[570], UInt<64>(0hc00000003000000) connect rom[571], UInt<64>(0h696669731b000000) connect rom[572], UInt<64>(0h306d6f722c6576) connect rom[573], UInt<64>(0h800000003000000) connect rom[574], UInt<64>(0h1002e010000) connect rom[575], UInt<64>(0h300000000000100) connect rom[576], UInt<64>(0ha801000004000000) connect rom[577], UInt<64>(0h2000000006d656d) connect rom[578], UInt<64>(0h7375627301000000) connect rom[579], UInt<64>(0h6b636f6c635f) connect rom[580], UInt<64>(0h400000003000000) connect rom[581], UInt<64>(0hde010000) connect rom[582], UInt<64>(0h400000003000000) connect rom[583], UInt<64>(0h65cd1d53000000) connect rom[584], UInt<64>(0hb00000003000000) connect rom[585], UInt<64>(0h73756273eb010000) connect rom[586], UInt<64>(0h6b636f6c635f) connect rom[587], UInt<64>(0hc00000003000000) connect rom[588], UInt<64>(0h657869661b000000) connect rom[589], UInt<64>(0h6b636f6c632d64) connect rom[590], UInt<64>(0h100000002000000) connect rom[591], UInt<64>(0h31406c6169726573) connect rom[592], UInt<64>(0h30303030323030) connect rom[593], UInt<64>(0h400000003000000) connect rom[594], UInt<64>(0h80000003d020000) connect rom[595], UInt<64>(0hd00000003000000) connect rom[596], UInt<64>(0h696669731b000000) connect rom[597], UInt<64>(0h30747261752c6576) connect rom[598], UInt<64>(0h300000000000000) connect rom[599], UInt<64>(0h4402000004000000) connect rom[600], UInt<64>(0h300000009000000) connect rom[601], UInt<64>(0h5502000004000000) connect rom[602], UInt<64>(0h300000001000000) connect rom[603], UInt<64>(0h2e01000008000000) connect rom[604], UInt<64>(0h10000000000210) connect rom[605], UInt<64>(0h800000003000000) connect rom[606], UInt<64>(0h746e6f63a8010000) connect rom[607], UInt<64>(0h2000000006c6f72) connect rom[608], UInt<64>(0h656c697401000000) connect rom[609], UInt<64>(0h732d74657365722d) connect rom[610], UInt<64>(0h3131407265747465) connect rom[611], UInt<64>(0h30303030) connect rom[612], UInt<64>(0h800000003000000) connect rom[613], UInt<64>(0h11002e010000) connect rom[614], UInt<64>(0h300000000100000) connect rom[615], UInt<64>(0ha801000008000000) connect rom[616], UInt<64>(0h6c6f72746e6f63) connect rom[617], UInt<64>(0h200000002000000) connect rom[618], UInt<64>(0h900000002000000) connect rom[619], UInt<64>(0h7373657264646123) connect rom[620], UInt<64>(0h2300736c6c65632d) connect rom[621], UInt<64>(0h6c65632d657a6973) connect rom[622], UInt<64>(0h61706d6f6300736c) connect rom[623], UInt<64>(0h6f6d00656c626974) connect rom[624], UInt<64>(0h69726573006c6564) connect rom[625], UInt<64>(0h6f64747300306c61) connect rom[626], UInt<64>(0h687461702d7475) connect rom[627], UInt<64>(0h65736162656d6974) connect rom[628], UInt<64>(0h6e6575716572662d) connect rom[629], UInt<64>(0h6b636f6c63007963) connect rom[630], UInt<64>(0h6e6575716572662d) connect rom[631], UInt<64>(0h6361632d64007963) connect rom[632], UInt<64>(0h6b636f6c622d6568) connect rom[633], UInt<64>(0h2d6400657a69732d) connect rom[634], UInt<64>(0h65732d6568636163) connect rom[635], UInt<64>(0h6361632d64007374) connect rom[636], UInt<64>(0h657a69732d6568) connect rom[637], UInt<64>(0h65732d626c742d64) connect rom[638], UInt<64>(0h626c742d64007374) connect rom[639], UInt<64>(0h656400657a69732d) connect rom[640], UInt<64>(0h7079745f65636976) connect rom[641], UInt<64>(0h6177647261680065) connect rom[642], UInt<64>(0h2d636578652d6572) connect rom[643], UInt<64>(0h696f706b61657262) connect rom[644], UInt<64>(0h746e756f632d746e) connect rom[645], UInt<64>(0h65686361632d6900) connect rom[646], UInt<64>(0h732d6b636f6c622d) connect rom[647], UInt<64>(0h61632d6900657a69) connect rom[648], UInt<64>(0h737465732d656863) connect rom[649], UInt<64>(0h65686361632d6900) connect rom[650], UInt<64>(0h2d6900657a69732d) connect rom[651], UInt<64>(0h737465732d626c74) connect rom[652], UInt<64>(0h732d626c742d6900) connect rom[653], UInt<64>(0h2d756d6d00657a69) connect rom[654], UInt<64>(0h78656e0065707974) connect rom[655], UInt<64>(0h2d6c6576656c2d74) connect rom[656], UInt<64>(0h6572006568636163) connect rom[657], UInt<64>(0h2c76637369720067) connect rom[658], UInt<64>(0h6373697200617369) connect rom[659], UInt<64>(0h617267706d702c76) connect rom[660], UInt<64>(0h79746972616c756e) connect rom[661], UInt<64>(0h702c766373697200) connect rom[662], UInt<64>(0h6e6f69676572706d) connect rom[663], UInt<64>(0h7375746174730073) connect rom[664], UInt<64>(0h6c70732d626c7400) connect rom[665], UInt<64>(0h65746e6923007469) connect rom[666], UInt<64>(0h65632d7470757272) connect rom[667], UInt<64>(0h65746e6900736c6c) connect rom[668], UInt<64>(0h6f632d7470757272) connect rom[669], UInt<64>(0h72656c6c6f72746e) connect rom[670], UInt<64>(0h656c646e61687000) connect rom[671], UInt<64>(0h7365676e617200) connect rom[672], UInt<64>(0h656d616e2d676572) connect rom[673], UInt<64>(0h2d65686361630073) connect rom[674], UInt<64>(0h6163006c6576656c) connect rom[675], UInt<64>(0h66696e752d656863) connect rom[676], UInt<64>(0h6966697300646569) connect rom[677], UInt<64>(0h2d7268736d2c6576) connect rom[678], UInt<64>(0h632300746e756f63) connect rom[679], UInt<64>(0h6c65632d6b636f6c) connect rom[680], UInt<64>(0h6b636f6c6300736c) connect rom[681], UInt<64>(0h2d74757074756f2d) connect rom[682], UInt<64>(0h6e690073656d616e) connect rom[683], UInt<64>(0h7374707572726574) connect rom[684], UInt<64>(0h65646e657478652d) connect rom[685], UInt<64>(0h2d67756265640064) connect rom[686], UInt<64>(0h7200686361747461) connect rom[687], UInt<64>(0h78616d2c76637369) connect rom[688], UInt<64>(0h7469726f6972702d) connect rom[689], UInt<64>(0h2c76637369720079) connect rom[690], UInt<64>(0h6f6c63007665646e) connect rom[691], UInt<64>(0h65746e6900736b63) connect rom[692], UInt<64>(0h61702d7470757272) connect rom[693], UInt<64>(0h746e6900746e6572) connect rom[694], UInt<64>(0h73747075727265) connect rom[695], UInt<64>(0h0) connect rom[696], UInt<64>(0h0) connect rom[697], UInt<64>(0h0) connect rom[698], UInt<64>(0h0) connect rom[699], UInt<64>(0h0) connect rom[700], UInt<64>(0h0) connect rom[701], UInt<64>(0h0) connect rom[702], UInt<64>(0h0) connect rom[703], UInt<64>(0h0) connect rom[704], UInt<64>(0h0) connect rom[705], UInt<64>(0h0) connect rom[706], UInt<64>(0h0) connect rom[707], UInt<64>(0h0) connect rom[708], UInt<64>(0h0) connect rom[709], UInt<64>(0h0) connect rom[710], UInt<64>(0h0) connect rom[711], UInt<64>(0h0) connect rom[712], UInt<64>(0h0) connect rom[713], UInt<64>(0h0) connect rom[714], UInt<64>(0h0) connect rom[715], UInt<64>(0h0) connect rom[716], UInt<64>(0h0) connect rom[717], UInt<64>(0h0) connect rom[718], UInt<64>(0h0) connect rom[719], UInt<64>(0h0) connect rom[720], UInt<64>(0h0) connect rom[721], UInt<64>(0h0) connect rom[722], UInt<64>(0h0) connect rom[723], UInt<64>(0h0) connect rom[724], UInt<64>(0h0) connect rom[725], UInt<64>(0h0) connect rom[726], UInt<64>(0h0) connect rom[727], UInt<64>(0h0) connect rom[728], UInt<64>(0h0) connect rom[729], UInt<64>(0h0) connect rom[730], UInt<64>(0h0) connect rom[731], UInt<64>(0h0) connect rom[732], UInt<64>(0h0) connect rom[733], UInt<64>(0h0) connect rom[734], UInt<64>(0h0) connect rom[735], UInt<64>(0h0) connect rom[736], UInt<64>(0h0) connect rom[737], UInt<64>(0h0) connect rom[738], UInt<64>(0h0) connect rom[739], UInt<64>(0h0) connect rom[740], UInt<64>(0h0) connect rom[741], UInt<64>(0h0) connect rom[742], UInt<64>(0h0) connect rom[743], UInt<64>(0h0) connect rom[744], UInt<64>(0h0) connect rom[745], UInt<64>(0h0) connect rom[746], UInt<64>(0h0) connect rom[747], UInt<64>(0h0) connect rom[748], UInt<64>(0h0) connect rom[749], UInt<64>(0h0) connect rom[750], UInt<64>(0h0) connect rom[751], UInt<64>(0h0) connect rom[752], UInt<64>(0h0) connect rom[753], UInt<64>(0h0) connect rom[754], UInt<64>(0h0) connect rom[755], UInt<64>(0h0) connect rom[756], UInt<64>(0h0) connect rom[757], UInt<64>(0h0) connect rom[758], UInt<64>(0h0) connect rom[759], UInt<64>(0h0) connect rom[760], UInt<64>(0h0) connect rom[761], UInt<64>(0h0) connect rom[762], UInt<64>(0h0) connect rom[763], UInt<64>(0h0) connect rom[764], UInt<64>(0h0) connect rom[765], UInt<64>(0h0) connect rom[766], UInt<64>(0h0) connect rom[767], UInt<64>(0h0) connect rom[768], UInt<64>(0h0) connect rom[769], UInt<64>(0h0) connect rom[770], UInt<64>(0h0) connect rom[771], UInt<64>(0h0) connect rom[772], UInt<64>(0h0) connect rom[773], UInt<64>(0h0) connect rom[774], UInt<64>(0h0) connect rom[775], UInt<64>(0h0) connect rom[776], UInt<64>(0h0) connect rom[777], UInt<64>(0h0) connect rom[778], UInt<64>(0h0) connect rom[779], UInt<64>(0h0) connect rom[780], UInt<64>(0h0) connect rom[781], UInt<64>(0h0) connect rom[782], UInt<64>(0h0) connect rom[783], UInt<64>(0h0) connect rom[784], UInt<64>(0h0) connect rom[785], UInt<64>(0h0) connect rom[786], UInt<64>(0h0) connect rom[787], UInt<64>(0h0) connect rom[788], UInt<64>(0h0) connect rom[789], UInt<64>(0h0) connect rom[790], UInt<64>(0h0) connect rom[791], UInt<64>(0h0) connect rom[792], UInt<64>(0h0) connect rom[793], UInt<64>(0h0) connect rom[794], UInt<64>(0h0) connect rom[795], UInt<64>(0h0) connect rom[796], UInt<64>(0h0) connect rom[797], UInt<64>(0h0) connect rom[798], UInt<64>(0h0) connect rom[799], UInt<64>(0h0) connect rom[800], UInt<64>(0h0) connect rom[801], UInt<64>(0h0) connect rom[802], UInt<64>(0h0) connect rom[803], UInt<64>(0h0) connect rom[804], UInt<64>(0h0) connect rom[805], UInt<64>(0h0) connect rom[806], UInt<64>(0h0) connect rom[807], UInt<64>(0h0) connect rom[808], UInt<64>(0h0) connect rom[809], UInt<64>(0h0) connect rom[810], UInt<64>(0h0) connect rom[811], UInt<64>(0h0) connect rom[812], UInt<64>(0h0) connect rom[813], UInt<64>(0h0) connect rom[814], UInt<64>(0h0) connect rom[815], UInt<64>(0h0) connect rom[816], UInt<64>(0h0) connect rom[817], UInt<64>(0h0) connect rom[818], UInt<64>(0h0) connect rom[819], UInt<64>(0h0) connect rom[820], UInt<64>(0h0) connect rom[821], UInt<64>(0h0) connect rom[822], UInt<64>(0h0) connect rom[823], UInt<64>(0h0) connect rom[824], UInt<64>(0h0) connect rom[825], UInt<64>(0h0) connect rom[826], UInt<64>(0h0) connect rom[827], UInt<64>(0h0) connect rom[828], UInt<64>(0h0) connect rom[829], UInt<64>(0h0) connect rom[830], UInt<64>(0h0) connect rom[831], UInt<64>(0h0) connect rom[832], UInt<64>(0h0) connect rom[833], UInt<64>(0h0) connect rom[834], UInt<64>(0h0) connect rom[835], UInt<64>(0h0) connect rom[836], UInt<64>(0h0) connect rom[837], UInt<64>(0h0) connect rom[838], UInt<64>(0h0) connect rom[839], UInt<64>(0h0) connect rom[840], UInt<64>(0h0) connect rom[841], UInt<64>(0h0) connect rom[842], UInt<64>(0h0) connect rom[843], UInt<64>(0h0) connect rom[844], UInt<64>(0h0) connect rom[845], UInt<64>(0h0) connect rom[846], UInt<64>(0h0) connect rom[847], UInt<64>(0h0) connect rom[848], UInt<64>(0h0) connect rom[849], UInt<64>(0h0) connect rom[850], UInt<64>(0h0) connect rom[851], UInt<64>(0h0) connect rom[852], UInt<64>(0h0) connect rom[853], UInt<64>(0h0) connect rom[854], UInt<64>(0h0) connect rom[855], UInt<64>(0h0) connect rom[856], UInt<64>(0h0) connect rom[857], UInt<64>(0h0) connect rom[858], UInt<64>(0h0) connect rom[859], UInt<64>(0h0) connect rom[860], UInt<64>(0h0) connect rom[861], UInt<64>(0h0) connect rom[862], UInt<64>(0h0) connect rom[863], UInt<64>(0h0) connect rom[864], UInt<64>(0h0) connect rom[865], UInt<64>(0h0) connect rom[866], UInt<64>(0h0) connect rom[867], UInt<64>(0h0) connect rom[868], UInt<64>(0h0) connect rom[869], UInt<64>(0h0) connect rom[870], UInt<64>(0h0) connect rom[871], UInt<64>(0h0) connect rom[872], UInt<64>(0h0) connect rom[873], UInt<64>(0h0) connect rom[874], UInt<64>(0h0) connect rom[875], UInt<64>(0h0) connect rom[876], UInt<64>(0h0) connect rom[877], UInt<64>(0h0) connect rom[878], UInt<64>(0h0) connect rom[879], UInt<64>(0h0) connect rom[880], UInt<64>(0h0) connect rom[881], UInt<64>(0h0) connect rom[882], UInt<64>(0h0) connect rom[883], UInt<64>(0h0) connect rom[884], UInt<64>(0h0) connect rom[885], UInt<64>(0h0) connect rom[886], UInt<64>(0h0) connect rom[887], UInt<64>(0h0) connect rom[888], UInt<64>(0h0) connect rom[889], UInt<64>(0h0) connect rom[890], UInt<64>(0h0) connect rom[891], UInt<64>(0h0) connect rom[892], UInt<64>(0h0) connect rom[893], UInt<64>(0h0) connect rom[894], UInt<64>(0h0) connect rom[895], UInt<64>(0h0) connect rom[896], UInt<64>(0h0) connect rom[897], UInt<64>(0h0) connect rom[898], UInt<64>(0h0) connect rom[899], UInt<64>(0h0) connect rom[900], UInt<64>(0h0) connect rom[901], UInt<64>(0h0) connect rom[902], UInt<64>(0h0) connect rom[903], UInt<64>(0h0) connect rom[904], UInt<64>(0h0) connect rom[905], UInt<64>(0h0) connect rom[906], UInt<64>(0h0) connect rom[907], UInt<64>(0h0) connect rom[908], UInt<64>(0h0) connect rom[909], UInt<64>(0h0) connect rom[910], UInt<64>(0h0) connect rom[911], UInt<64>(0h0) connect rom[912], UInt<64>(0h0) connect rom[913], UInt<64>(0h0) connect rom[914], UInt<64>(0h0) connect rom[915], UInt<64>(0h0) connect rom[916], UInt<64>(0h0) connect rom[917], UInt<64>(0h0) connect rom[918], UInt<64>(0h0) connect rom[919], UInt<64>(0h0) connect rom[920], UInt<64>(0h0) connect rom[921], UInt<64>(0h0) connect rom[922], UInt<64>(0h0) connect rom[923], UInt<64>(0h0) connect rom[924], UInt<64>(0h0) connect rom[925], UInt<64>(0h0) connect rom[926], UInt<64>(0h0) connect rom[927], UInt<64>(0h0) connect rom[928], UInt<64>(0h0) connect rom[929], UInt<64>(0h0) connect rom[930], UInt<64>(0h0) connect rom[931], UInt<64>(0h0) connect rom[932], UInt<64>(0h0) connect rom[933], UInt<64>(0h0) connect rom[934], UInt<64>(0h0) connect rom[935], UInt<64>(0h0) connect rom[936], UInt<64>(0h0) connect rom[937], UInt<64>(0h0) connect rom[938], UInt<64>(0h0) connect rom[939], UInt<64>(0h0) connect rom[940], UInt<64>(0h0) connect rom[941], UInt<64>(0h0) connect rom[942], UInt<64>(0h0) connect rom[943], UInt<64>(0h0) connect rom[944], UInt<64>(0h0) connect rom[945], UInt<64>(0h0) connect rom[946], UInt<64>(0h0) connect rom[947], UInt<64>(0h0) connect rom[948], UInt<64>(0h0) connect rom[949], UInt<64>(0h0) connect rom[950], UInt<64>(0h0) connect rom[951], UInt<64>(0h0) connect rom[952], UInt<64>(0h0) connect rom[953], UInt<64>(0h0) connect rom[954], UInt<64>(0h0) connect rom[955], UInt<64>(0h0) connect rom[956], UInt<64>(0h0) connect rom[957], UInt<64>(0h0) connect rom[958], UInt<64>(0h0) connect rom[959], UInt<64>(0h0) connect rom[960], UInt<64>(0h0) connect rom[961], UInt<64>(0h0) connect rom[962], UInt<64>(0h0) connect rom[963], UInt<64>(0h0) connect rom[964], UInt<64>(0h0) connect rom[965], UInt<64>(0h0) connect rom[966], UInt<64>(0h0) connect rom[967], UInt<64>(0h0) connect rom[968], UInt<64>(0h0) connect rom[969], UInt<64>(0h0) connect rom[970], UInt<64>(0h0) connect rom[971], UInt<64>(0h0) connect rom[972], UInt<64>(0h0) connect rom[973], UInt<64>(0h0) connect rom[974], UInt<64>(0h0) connect rom[975], UInt<64>(0h0) connect rom[976], UInt<64>(0h0) connect rom[977], UInt<64>(0h0) connect rom[978], UInt<64>(0h0) connect rom[979], UInt<64>(0h0) connect rom[980], UInt<64>(0h0) connect rom[981], UInt<64>(0h0) connect rom[982], UInt<64>(0h0) connect rom[983], UInt<64>(0h0) connect rom[984], UInt<64>(0h0) connect rom[985], UInt<64>(0h0) connect rom[986], UInt<64>(0h0) connect rom[987], UInt<64>(0h0) connect rom[988], UInt<64>(0h0) connect rom[989], UInt<64>(0h0) connect rom[990], UInt<64>(0h0) connect rom[991], UInt<64>(0h0) connect rom[992], UInt<64>(0h0) connect rom[993], UInt<64>(0h0) connect rom[994], UInt<64>(0h0) connect rom[995], UInt<64>(0h0) connect rom[996], UInt<64>(0h0) connect rom[997], UInt<64>(0h0) connect rom[998], UInt<64>(0h0) connect rom[999], UInt<64>(0h0) connect rom[1000], UInt<64>(0h0) connect rom[1001], UInt<64>(0h0) connect rom[1002], UInt<64>(0h0) connect rom[1003], UInt<64>(0h0) connect rom[1004], UInt<64>(0h0) connect rom[1005], UInt<64>(0h0) connect rom[1006], UInt<64>(0h0) connect rom[1007], UInt<64>(0h0) connect rom[1008], UInt<64>(0h0) connect rom[1009], UInt<64>(0h0) connect rom[1010], UInt<64>(0h0) connect rom[1011], UInt<64>(0h0) connect rom[1012], UInt<64>(0h0) connect rom[1013], UInt<64>(0h0) connect rom[1014], UInt<64>(0h0) connect rom[1015], UInt<64>(0h0) connect rom[1016], UInt<64>(0h0) connect rom[1017], UInt<64>(0h0) connect rom[1018], UInt<64>(0h0) connect rom[1019], UInt<64>(0h0) connect rom[1020], UInt<64>(0h0) connect rom[1021], UInt<64>(0h0) connect rom[1022], UInt<64>(0h0) connect rom[1023], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 12, 3) node high = bits(nodeIn.a.bits.address, 15, 13) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [1023:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 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64'h300000000800000, 64'hF100000004000000, 64'h300000040000000, 64'hE400000004000000, 64'h300000040000000, 64'hD100000004000000, 64'h300000000000000, 64'hB200000004000000, 64'h300000000757063, 64'hA600000004000000, 64'h300000010000000, 64'h9B00000004000000, 64'h300000001000000, 64'h9000000004000000, 64'h300000000800000, 64'h8300000004000000, 64'h300000040000000, 64'h7600000004000000, 64'h300000040000000, 64'h6300000004000000, 64'h300000000766373, 64'h697200306D6F6F62, 64'h2C7261622D626375, 64'h1B00000014000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000032, 64'h4075706301000000, 64'h200000002000000, 64'h500000099010000, 64'h400000003000000, 64'h8401000000000000, 64'h300000000006374, 64'h6E692D7570632C76, 64'h637369721B000000, 64'hF00000003000000, 64'h100000073010000, 64'h400000003000000, 64'h72656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000069010000, 64'h3000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'h6201000005000000, 64'h300000008000000, 64'h5101000004000000, 64'h300000004000000, 64'h3C01000004000000, 64'h30000000074656B, 64'h636F72785F73627A, 64'h5F62627A5F61627A, 64'h5F68667A5F6D7068, 64'h697A5F6965636E65, 64'h66697A5F72736369, 64'h7A62636466616D69, 64'h3436767232010000, 64'h3800000003000000, 64'h10000002E010000, 64'h400000003000000, 64'h10000001D010000, 64'h400000003000000, 64'h393376732C76, 64'h6373697214010000, 64'hB00000003000000, 64'h2000000009010000, 64'h400000003000000, 64'h1000000FE000000, 64'h400000003000000, 64'h800000F1000000, 64'h400000003000000, 64'h40000000E4000000, 64'h400000003000000, 64'h40000000D1000000, 64'h400000003000000, 64'h1000000B2000000, 64'h400000003000000, 64'h757063A6000000, 64'h400000003000000, 64'h200000009B000000, 64'h400000003000000, 64'h100000090000000, 64'h400000003000000, 64'h80000083000000, 64'h400000003000000, 64'h4000000076000000, 64'h400000003000000, 64'h4000000063000000, 64'h400000003000000, 64'h76637369, 64'h72003074656B636F, 64'h722C657669666973, 64'h1B00000015000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000031, 64'h4075706301000000, 64'h200000002000000, 64'h400000099010000, 64'h400000003000000, 64'h8401000000000000, 64'h300000000006374, 64'h6E692D7570632C76, 64'h637369721B000000, 64'hF00000003000000, 64'h100000073010000, 64'h400000003000000, 64'h72656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000069010000, 64'h3000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'h6201000005000000, 64'h300000008000000, 64'h5101000004000000, 64'h300000004000000, 64'h3C01000004000000, 64'h30000000074656B, 64'h636F72785F73627A, 64'h5F62627A5F61627A, 64'h5F68667A5F6D7068, 64'h697A5F6965636E65, 64'h66697A5F72736369, 64'h7A62636466616D69, 64'h3436767232010000, 64'h3800000003000000, 64'h2E010000, 64'h400000003000000, 64'h10000001D010000, 64'h400000003000000, 64'h393376732C76, 64'h6373697214010000, 64'hB00000003000000, 64'h2000000009010000, 64'h400000003000000, 64'h1000000FE000000, 64'h400000003000000, 64'h800000F1000000, 64'h400000003000000, 64'h40000000E4000000, 64'h400000003000000, 64'h40000000D1000000, 64'h400000003000000, 64'h1000000B2000000, 64'h400000003000000, 64'h757063A6000000, 64'h400000003000000, 64'h200000009B000000, 64'h400000003000000, 64'h100000090000000, 64'h400000003000000, 64'h80000083000000, 64'h400000003000000, 64'h4000000076000000, 64'h400000003000000, 64'h4000000063000000, 64'h400000003000000, 64'h76637369, 64'h72003074656B636F, 64'h722C657669666973, 64'h1B00000015000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'h6012000060020000, 64'h10000000, 64'h1100000028000000, 64'h9812000038000000, 64'hF8140000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5350300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'hF8140000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'h9812000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'h6012000060020000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h2E010000; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h400000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'h300000000000031; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h1B00000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'h722C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h72003074656B636F; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h76637369; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h200000009B000000; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'h200000009B000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h1000000B2000000; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'h1000000B2000000; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h10000002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h3800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'h3800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h7A62636466616D69; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h7A62636466616D69; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h66697A5F72736369; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h66697A5F72736369; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h636F72785F73627A; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h636F72785F73627A; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h30000000074656B; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'h30000000074656B; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h500000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'h300000000000032; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'h1B00000014000000; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'h697200306D6F6F62; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h300000000766373; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h6300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'h7600000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'h8300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'h9000000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'h9B00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h300000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'hA600000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'h300000000757063; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'hB200000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'hD100000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'hE400000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'hF100000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h300000000800000; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h300000000800000; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'hFE00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'h300000020000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'h140100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h76732C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'h300000000003933; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h1D01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h2E01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h320100001F000000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'h66616D6934367672; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'h5F727363697A6364; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'h6965636E6566697A; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'h6D7068697A5F; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h40000003C010000; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h800000051010000; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h79616B6F62010000; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h4000000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h300000020A10700; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h6901000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h1B0000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h70632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h63746E692D75; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h300000084010000; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'h200000006000000; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'h3340757063; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h53000000; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h1400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h6D6F6F622C726162; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'h76637369720030; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h4000000063000000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h4000000063000000; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h4000000063000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h4000000076000000; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h4000000076000000; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h4000000076000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h80000083000000; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h80000083000000; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'h80000083000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h100000090000000; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'h100000090000000; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h100000090000000; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'h100000009B000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'h757063A6000000; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h757063A6000000; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'h757063A6000000; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'hB2000000; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h40000000D1000000; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'h40000000D1000000; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h40000000D1000000; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h40000000E4000000; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h40000000E4000000; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'h40000000E4000000; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'h800000F1000000; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h800000F1000000; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'h800000F1000000; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'h1000000FE000000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h1000000FE000000; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'h1000000FE000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'h2000000009010000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h2000000009010000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'h2000000009010000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'h6373697214010000; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h6373697214010000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'h6373697214010000; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h393376732C76; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h393376732C76; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h393376732C76; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h10000001D010000; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'h10000001D010000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h10000001D010000; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h30000002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h1F00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h3436767232010000; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h3436767232010000; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h3436767232010000; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h697A636466616D69; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h6566697A5F727363; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h68697A5F6965636E; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h300000000006D70; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h3C01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h3C01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h3C01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h5101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h5101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'h5101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h6201000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h6201000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'h6201000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h100000069010000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'h100000069010000; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h100000069010000; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h72656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'h72656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h72656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h100000073010000; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'h100000073010000; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'h100000073010000; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'hF00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'hF00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'hF00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h300000000006374; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'h300000000006374; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'h300000000006374; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h700000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h66697468; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'hA00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h2C6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h3066697468; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'h303030303030; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h10000000008; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'h900000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h6173696462010000; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h64656C62; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h300000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'h384079726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'h384079726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'h30303030303030; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'h300000000007972; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h300000000007972; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h1000000080; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h200000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h300000000636F73; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'h4000000; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'hF00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'h1B00000020000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'h6D697300636F732D; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h7375622D656C70; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h1000000A1010000; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h6765722D73736572; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h3030303140; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'h1000002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'h6F632D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'h3030303031303240; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h6500000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'hB201000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h7800000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h300000000040000; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h8500000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h300000000000800; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'hBE01000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h1D00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'h756C636E692C6576; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h6863616365766973; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h6568636163003065; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h1D01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h1022E010000; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'hC000000CC010000; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h100000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h6E696C6301000000; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h3030303030324074; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h1B0000000D000000; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h6C632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h30746E69; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h500000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h600000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h600000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h700000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h300000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h10000000002; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h636F6C6301000000; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h4072657461672D6B; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h303030303031; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h10002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h6F632D6775626564; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h300000000003040; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h1B00000021000000; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h642C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h642C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h3331302D67756265; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h3331302D67756265; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h1202000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h6761746A; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h2000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h5000000FFFF0000; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h6000000FFFF0000; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h7000000FFFF0000; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h10000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h6F72726501000000; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h6563697665642D72; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h3030303340; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'hE00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h726F7272652C6576; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h10000000300000; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h2000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h2000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_512 = 64'h3030303030306340; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h7301000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_514 = 64'h7301000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_517 = 64'h6C702C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_518 = 64'h300000000306369; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_519 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h4000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_520 = 64'h4000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_521 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_522 = 64'h40000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_523 = 64'h500000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_524 = 64'h50000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_525 = 64'h600000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_526 = 64'h60000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_527 = 64'h700000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_528 = 64'h70000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_531 = 64'h40000000C; // @[BootROM.scala:50:22] wire [63:0] rom_534 = 64'h3000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_535 = 64'h1F02000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_537 = 64'h3202000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_540 = 64'h200000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_541 = 64'h7375626D01000000; // @[BootROM.scala:50:22] wire [63:0] rom_548 = 64'h7375626DEB010000; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_556 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_558 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_559 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_560 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_554 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_561 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_555 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_562 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_516 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_563 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_564 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_565 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_539 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_566 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_567 = 64'h200000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_568 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_569 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_572 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_574 = 64'h1002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_575 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_576 = 64'hA801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_577 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_578 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_544 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_581 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_546 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_583 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_547 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_584 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_585 = 64'h73756273EB010000; // @[BootROM.scala:50:22] wire [63:0] rom_542 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_549 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_579 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_586 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_550 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_570 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_587 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_551 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_588 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_552 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_589 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_553 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_590 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_591 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_592 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_543 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_545 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_580 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_582 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_593 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_594 = 64'h80000003D020000; // @[BootROM.scala:50:22] wire [63:0] rom_595 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_571 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_596 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_597 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_513 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_557 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_598 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_599 = 64'h4402000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_529 = 64'h300000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_600 = 64'h300000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_601 = 64'h5502000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_515 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_536 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_538 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_602 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_530 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_603 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_604 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_533 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_606 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_607 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_608 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_609 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_610 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_611 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_532 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_573 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_605 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_612 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_613 = 64'h11002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_614 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_615 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_616 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_617 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_618 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_619 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_620 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_621 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_622 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_623 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_624 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_625 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_626 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_627 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_629 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_628 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_630 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_631 = 64'h6361632D64007963; // @[BootROM.scala:50:22] wire [63:0] rom_632 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22] wire [63:0] rom_633 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_634 = 64'h65732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_635 = 64'h6361632D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_636 = 64'h657A69732D6568; // @[BootROM.scala:50:22] wire [63:0] rom_637 = 64'h65732D626C742D64; // @[BootROM.scala:50:22] wire [63:0] rom_638 = 64'h626C742D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_639 = 64'h656400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_640 = 64'h7079745F65636976; // @[BootROM.scala:50:22] wire [63:0] rom_641 = 64'h6177647261680065; // @[BootROM.scala:50:22] wire [63:0] rom_642 = 64'h2D636578652D6572; // @[BootROM.scala:50:22] wire [63:0] rom_643 = 64'h696F706B61657262; // @[BootROM.scala:50:22] wire [63:0] rom_644 = 64'h746E756F632D746E; // @[BootROM.scala:50:22] wire [63:0] rom_646 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22] wire [63:0] rom_647 = 64'h61632D6900657A69; // @[BootROM.scala:50:22] wire [63:0] rom_648 = 64'h737465732D656863; // @[BootROM.scala:50:22] wire [63:0] rom_645 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_649 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_650 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_651 = 64'h737465732D626C74; // @[BootROM.scala:50:22] wire [63:0] rom_652 = 64'h732D626C742D6900; // @[BootROM.scala:50:22] wire [63:0] rom_653 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22] wire [63:0] rom_654 = 64'h78656E0065707974; // @[BootROM.scala:50:22] wire [63:0] rom_655 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22] wire [63:0] rom_656 = 64'h6572006568636163; // @[BootROM.scala:50:22] wire [63:0] rom_657 = 64'h2C76637369720067; // @[BootROM.scala:50:22] wire [63:0] rom_658 = 64'h6373697200617369; // @[BootROM.scala:50:22] wire [63:0] rom_659 = 64'h617267706D702C76; // @[BootROM.scala:50:22] wire [63:0] rom_660 = 64'h79746972616C756E; // @[BootROM.scala:50:22] wire [63:0] rom_661 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_662 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22] wire [63:0] rom_663 = 64'h7375746174730073; // @[BootROM.scala:50:22] wire [63:0] rom_664 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22] wire [63:0] rom_665 = 64'h65746E6923007469; // @[BootROM.scala:50:22] wire [63:0] rom_666 = 64'h65632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_667 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_668 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_669 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_670 = 64'h656C646E61687000; // @[BootROM.scala:50:22] wire [63:0] rom_671 = 64'h7365676E617200; // @[BootROM.scala:50:22] wire [63:0] rom_672 = 64'h656D616E2D676572; // @[BootROM.scala:50:22] wire [63:0] rom_673 = 64'h2D65686361630073; // @[BootROM.scala:50:22] wire [63:0] rom_674 = 64'h6163006C6576656C; // @[BootROM.scala:50:22] wire [63:0] rom_675 = 64'h66696E752D656863; // @[BootROM.scala:50:22] wire [63:0] rom_676 = 64'h6966697300646569; // @[BootROM.scala:50:22] wire [63:0] rom_677 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22] wire [63:0] rom_678 = 64'h632300746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_679 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22] wire [63:0] rom_680 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_681 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22] wire [63:0] rom_682 = 64'h6E690073656D616E; // @[BootROM.scala:50:22] wire [63:0] rom_683 = 64'h7374707572726574; // @[BootROM.scala:50:22] wire [63:0] rom_684 = 64'h65646E657478652D; // @[BootROM.scala:50:22] wire [63:0] rom_685 = 64'h2D67756265640064; // @[BootROM.scala:50:22] wire [63:0] rom_686 = 64'h7200686361747461; // @[BootROM.scala:50:22] wire [63:0] rom_687 = 64'h78616D2C76637369; // @[BootROM.scala:50:22] wire [63:0] rom_688 = 64'h7469726F6972702D; // @[BootROM.scala:50:22] wire [63:0] rom_689 = 64'h2C76637369720079; // @[BootROM.scala:50:22] wire [63:0] rom_690 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22] wire [63:0] rom_691 = 64'h65746E6900736B63; // @[BootROM.scala:50:22] wire [63:0] rom_692 = 64'h61702D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_693 = 64'h746E6900746E6572; // @[BootROM.scala:50:22] wire [63:0] rom_694 = 64'h73747075727265; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_695 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_696 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_697 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_698 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_699 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_700 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_701 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_702 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_703 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_704 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_705 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_706 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_707 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_708 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_709 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_710 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_711 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_712 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_713 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_714 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_715 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_716 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_717 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_718 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_719 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_720 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_721 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_722 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_723 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_724 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_725 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_726 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_727 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_728 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_729 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_730 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_731 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_732 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_733 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_734 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_735 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_736 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_737 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_738 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_739 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_740 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_741 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_742 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_743 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_744 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_745 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_746 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_747 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_748 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_749 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_750 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_751 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_752 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_753 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_754 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_755 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_756 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_757 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_758 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_759 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_760 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_761 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_762 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_763 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_764 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_765 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_766 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_767 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_768 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_769 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_770 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_771 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_772 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_773 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_774 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_775 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_776 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_777 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_778 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_779 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_780 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_781 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_782 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_783 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_784 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_785 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_786 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_787 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_788 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_789 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_790 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_791 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_792 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_793 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_794 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_795 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_796 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_797 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_798 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_799 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_800 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_801 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_802 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_803 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_804 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_805 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_806 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_807 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_808 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_809 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_810 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_811 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_812 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_813 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_814 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_815 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_816 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_817 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_818 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_819 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_820 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_821 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_822 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_823 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_824 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_825 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_826 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_827 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_828 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_829 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_830 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_831 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_832 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_833 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_834 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_835 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_836 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_837 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_838 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_839 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_840 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_841 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_842 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_843 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_844 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_845 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_846 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_847 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_848 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_849 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_850 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_851 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_852 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_853 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_854 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_855 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_856 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_857 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_858 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_859 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_860 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_861 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_862 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_863 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_864 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_865 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_866 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_867 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_868 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_869 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_870 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_871 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_872 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_873 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_874 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_875 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_876 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_877 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_878 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_879 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_880 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_881 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_882 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_883 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_884 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_885 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_886 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_887 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_888 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_889 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_890 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_891 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_892 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_893 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_894 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_895 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_896 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_897 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_898 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_899 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_900 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_901 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_902 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_903 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_904 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_905 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_906 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_907 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_908 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_909 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_910 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_911 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_912 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_913 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_914 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_915 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_916 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_917 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_918 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_919 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_920 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_921 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_922 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_923 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_924 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_925 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_926 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_927 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_928 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_929 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_930 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_931 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_932 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_933 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_934 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_935 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_936 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_937 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_938 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_939 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_940 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_941 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_942 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_943 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_944 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_945 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_946 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_947 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_948 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_949 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_950 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_951 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_952 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_953 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_954 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_955 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_956 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_957 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_958 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_959 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_960 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_961 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_962 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_963 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_964 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_965 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_966 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_967 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_968 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_969 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_970 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_971 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_972 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_973 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_974 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_975 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_976 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_977 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_978 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_979 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_980 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_981 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_982 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_983 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_984 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_985 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_986 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_987 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_988 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_989 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_990 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_991 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_992 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_993 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_994 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_995 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_996 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_997 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_998 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_999 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1000 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1001 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1002 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1003 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1004 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1005 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1006 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1007 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1008 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1009 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1010 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1011 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1012 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1013 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1014 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1015 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1016 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1017 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1018 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1019 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1020 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1021 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1022 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_1023 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [11:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [11:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [9:0] index = nodeIn_a_bits_address[12:3]; // @[BootROM.scala:55:34] wire [2:0] high = nodeIn_a_bits_address[15:13]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_64 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_26 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg
module AsyncResetRegVec_w1_i0_26( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset // @[AsyncResetReg.scala:56:7] ); wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7] wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_168 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_424 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_168( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_424 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceE_5 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} wire e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} inst io_e_q of Queue2_TLBundleE_a32d64s4k3z3c_5 connect io_e_q.clock, clock connect io_e_q.reset, reset connect io_e_q.io.enq.valid, e.valid connect io_e_q.io.enq.bits.sink, e.bits.sink connect e.ready, io_e_q.io.enq.ready connect io.e.bits, io_e_q.io.deq.bits connect io.e.valid, io_e_q.io.deq.valid connect io_e_q.io.deq.ready, io.e.ready connect io.req.ready, e.ready connect e.valid, io.req.valid connect e.bits.sink, io.req.bits.sink
module SourceE_5( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_5 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceE_2 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} wire e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} inst io_e_q of Queue2_TLBundleE_a32d64s4k3z3c_2 connect io_e_q.clock, clock connect io_e_q.reset, reset connect io_e_q.io.enq.valid, e.valid connect io_e_q.io.enq.bits.sink, e.bits.sink connect e.ready, io_e_q.io.enq.ready connect io.e.bits, io_e_q.io.deq.bits connect io.e.valid, io_e_q.io.deq.valid connect io_e_q.io.deq.ready, io.e.ready connect io.req.ready, e.ready connect e.valid, io.req.valid connect e.bits.sink, io.req.bits.sink
module SourceE_2( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_2 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_117 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_138 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_117( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_138 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_180 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_180( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_163 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_173 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_163( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_173 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<2>(0h2)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h7)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 3) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h7)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 3) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h7)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 node _source_ok_T_18 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_18, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<2>(0h2)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h7)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_17 = shr(io.in.a.bits.source, 3) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<3>(0h7)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_30 = shr(io.in.a.bits.source, 3) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<3>(0h7)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _T_43 = and(_T_16, _T_29) node _T_44 = and(_T_43, _T_42) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_44, UInt<1>(0h1), "") : assert_1 node _T_48 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_48 : node _T_49 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_50 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_51 = and(_T_49, _T_50) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_52 = shr(io.in.a.bits.source, 3) node _T_53 = eq(_T_52, UInt<2>(0h2)) node _T_54 = leq(UInt<1>(0h0), uncommonBits_3) node _T_55 = and(_T_53, _T_54) node _T_56 = leq(uncommonBits_3, UInt<3>(0h7)) node _T_57 = and(_T_55, _T_56) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_58 = shr(io.in.a.bits.source, 3) node _T_59 = eq(_T_58, UInt<1>(0h1)) node _T_60 = leq(UInt<1>(0h0), uncommonBits_4) node _T_61 = and(_T_59, _T_60) node _T_62 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_63 = and(_T_61, _T_62) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_5) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = or(_T_57, _T_63) node _T_71 = or(_T_70, _T_69) node _T_72 = and(_T_51, _T_71) node _T_73 = or(UInt<1>(0h0), _T_72) node _T_74 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_75 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<14>(0h2000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<17>(0h10000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<18>(0h2f000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<27>(0h4000000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_79, _T_84) node _T_116 = or(_T_115, _T_89) node _T_117 = or(_T_116, _T_94) node _T_118 = or(_T_117, _T_99) node _T_119 = or(_T_118, _T_104) node _T_120 = or(_T_119, _T_109) node _T_121 = or(_T_120, _T_114) node _T_122 = and(_T_74, _T_121) node _T_123 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_124 = or(UInt<1>(0h0), _T_123) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<29>(0h10000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = and(_T_124, _T_135) node _T_137 = or(UInt<1>(0h0), _T_122) node _T_138 = or(_T_137, _T_136) node _T_139 = and(_T_73, _T_138) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_139, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_143 = shr(io.in.a.bits.source, 3) node _T_144 = eq(_T_143, UInt<2>(0h2)) node _T_145 = leq(UInt<1>(0h0), uncommonBits_6) node _T_146 = and(_T_144, _T_145) node _T_147 = leq(uncommonBits_6, UInt<3>(0h7)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_149 = shr(io.in.a.bits.source, 3) node _T_150 = eq(_T_149, UInt<1>(0h1)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_7) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_7, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_155 = shr(io.in.a.bits.source, 3) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_8) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_8, UInt<3>(0h7)) node _T_160 = and(_T_158, _T_159) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_148 connect _WIRE[1], _T_154 connect _WIRE[2], _T_160 node _T_161 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_162 = mux(_WIRE[0], _T_161, UInt<1>(0h0)) node _T_163 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_165 = or(_T_162, _T_163) node _T_166 = or(_T_165, _T_164) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_166 node _T_167 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_168 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<14>(0h2000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<13>(0h1000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<17>(0h10000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<18>(0h2f000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<27>(0h4000000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<29>(0h10000000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = or(_T_175, _T_180) node _T_222 = or(_T_221, _T_185) node _T_223 = or(_T_222, _T_190) node _T_224 = or(_T_223, _T_195) node _T_225 = or(_T_224, _T_200) node _T_226 = or(_T_225, _T_205) node _T_227 = or(_T_226, _T_210) node _T_228 = or(_T_227, _T_215) node _T_229 = or(_T_228, _T_220) node _T_230 = and(_T_170, _T_229) node _T_231 = or(UInt<1>(0h0), _T_230) node _T_232 = and(_WIRE_1, _T_231) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_232, UInt<1>(0h1), "") : assert_3 node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(source_ok, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_239 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_239, UInt<1>(0h1), "") : assert_5 node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(is_aligned, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_246 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_246, UInt<1>(0h1), "") : assert_7 node _T_250 = not(io.in.a.bits.mask) node _T_251 = eq(_T_250, UInt<1>(0h0)) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_251, UInt<1>(0h1), "") : assert_8 node _T_255 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_255, UInt<1>(0h1), "") : assert_9 node _T_259 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_259 : node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_263 = shr(io.in.a.bits.source, 3) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_9) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_269 = shr(io.in.a.bits.source, 3) node _T_270 = eq(_T_269, UInt<1>(0h1)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_10) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_10, UInt<3>(0h7)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_275 = shr(io.in.a.bits.source, 3) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_11) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_280 = and(_T_278, _T_279) node _T_281 = or(_T_268, _T_274) node _T_282 = or(_T_281, _T_280) node _T_283 = and(_T_262, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<14>(0h2000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<18>(0h2f000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = or(_T_290, _T_295) node _T_327 = or(_T_326, _T_300) node _T_328 = or(_T_327, _T_305) node _T_329 = or(_T_328, _T_310) node _T_330 = or(_T_329, _T_315) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_325) node _T_333 = and(_T_285, _T_332) node _T_334 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_335 = or(UInt<1>(0h0), _T_334) node _T_336 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<17>(0h10000))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<29>(0h10000000))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = or(_T_340, _T_345) node _T_347 = and(_T_335, _T_346) node _T_348 = or(UInt<1>(0h0), _T_333) node _T_349 = or(_T_348, _T_347) node _T_350 = and(_T_284, _T_349) node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_T_350, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_350, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_354 = shr(io.in.a.bits.source, 3) node _T_355 = eq(_T_354, UInt<2>(0h2)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_12) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_359 = and(_T_357, _T_358) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_360 = shr(io.in.a.bits.source, 3) node _T_361 = eq(_T_360, UInt<1>(0h1)) node _T_362 = leq(UInt<1>(0h0), uncommonBits_13) node _T_363 = and(_T_361, _T_362) node _T_364 = leq(uncommonBits_13, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_366 = shr(io.in.a.bits.source, 3) node _T_367 = eq(_T_366, UInt<1>(0h0)) node _T_368 = leq(UInt<1>(0h0), uncommonBits_14) node _T_369 = and(_T_367, _T_368) node _T_370 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_371 = and(_T_369, _T_370) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_359 connect _WIRE_2[1], _T_365 connect _WIRE_2[2], _T_371 node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_373 = mux(_WIRE_2[0], _T_372, UInt<1>(0h0)) node _T_374 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_375 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = or(_T_373, _T_374) node _T_377 = or(_T_376, _T_375) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_377 node _T_378 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_379 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_380 = and(_T_378, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<14>(0h2000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<18>(0h2f000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<17>(0h10000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<17>(0h10000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<27>(0h4000000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_423 = cvt(_T_422) node _T_424 = and(_T_423, asSInt(UInt<13>(0h1000))) node _T_425 = asSInt(_T_424) node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = or(_T_386, _T_391) node _T_433 = or(_T_432, _T_396) node _T_434 = or(_T_433, _T_401) node _T_435 = or(_T_434, _T_406) node _T_436 = or(_T_435, _T_411) node _T_437 = or(_T_436, _T_416) node _T_438 = or(_T_437, _T_421) node _T_439 = or(_T_438, _T_426) node _T_440 = or(_T_439, _T_431) node _T_441 = and(_T_381, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_WIRE_3, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_443, UInt<1>(0h1), "") : assert_11 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(source_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_450 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_450, UInt<1>(0h1), "") : assert_13 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_457 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_457, UInt<1>(0h1), "") : assert_15 node _T_461 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_461, UInt<1>(0h1), "") : assert_16 node _T_465 = not(io.in.a.bits.mask) node _T_466 = eq(_T_465, UInt<1>(0h0)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_466, UInt<1>(0h1), "") : assert_17 node _T_470 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(_T_470, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_470, UInt<1>(0h1), "") : assert_18 node _T_474 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_474 : node _T_475 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_476 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_478 = shr(io.in.a.bits.source, 3) node _T_479 = eq(_T_478, UInt<2>(0h2)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_15) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_15, UInt<3>(0h7)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_484 = shr(io.in.a.bits.source, 3) node _T_485 = eq(_T_484, UInt<1>(0h1)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_16) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_16, UInt<3>(0h7)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_490 = shr(io.in.a.bits.source, 3) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_17) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_17, UInt<3>(0h7)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(_T_483, _T_489) node _T_497 = or(_T_496, _T_495) node _T_498 = and(_T_477, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_499, UInt<1>(0h1), "") : assert_19 node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_505 = and(_T_503, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = and(_T_506, _T_511) node _T_513 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_514 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = or(UInt<1>(0h0), _T_515) node _T_517 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<14>(0h2000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<18>(0h2f000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<17>(0h10000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<17>(0h10000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<27>(0h4000000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_553 = cvt(_T_552) node _T_554 = and(_T_553, asSInt(UInt<13>(0h1000))) node _T_555 = asSInt(_T_554) node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0))) node _T_557 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<29>(0h10000000))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = or(_T_521, _T_526) node _T_563 = or(_T_562, _T_531) node _T_564 = or(_T_563, _T_536) node _T_565 = or(_T_564, _T_541) node _T_566 = or(_T_565, _T_546) node _T_567 = or(_T_566, _T_551) node _T_568 = or(_T_567, _T_556) node _T_569 = or(_T_568, _T_561) node _T_570 = and(_T_516, _T_569) node _T_571 = or(UInt<1>(0h0), _T_512) node _T_572 = or(_T_571, _T_570) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_572, UInt<1>(0h1), "") : assert_20 node _T_576 = asUInt(reset) node _T_577 = eq(_T_576, UInt<1>(0h0)) when _T_577 : node _T_578 = eq(source_ok, UInt<1>(0h0)) when _T_578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(is_aligned, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_582 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_582, UInt<1>(0h1), "") : assert_23 node _T_586 = eq(io.in.a.bits.mask, mask) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_586, UInt<1>(0h1), "") : assert_24 node _T_590 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(_T_590, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_590, UInt<1>(0h1), "") : assert_25 node _T_594 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_594 : node _T_595 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_596 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_598 = shr(io.in.a.bits.source, 3) node _T_599 = eq(_T_598, UInt<2>(0h2)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_18) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_603 = and(_T_601, _T_602) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_604 = shr(io.in.a.bits.source, 3) node _T_605 = eq(_T_604, UInt<1>(0h1)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_19) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_609 = and(_T_607, _T_608) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_610 = shr(io.in.a.bits.source, 3) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = leq(UInt<1>(0h0), uncommonBits_20) node _T_613 = and(_T_611, _T_612) node _T_614 = leq(uncommonBits_20, UInt<3>(0h7)) node _T_615 = and(_T_613, _T_614) node _T_616 = or(_T_603, _T_609) node _T_617 = or(_T_616, _T_615) node _T_618 = and(_T_597, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_621 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<13>(0h1000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = and(_T_623, _T_628) node _T_630 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_631 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_632 = and(_T_630, _T_631) node _T_633 = or(UInt<1>(0h0), _T_632) node _T_634 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<14>(0h2000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<18>(0h2f000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_645 = cvt(_T_644) node _T_646 = and(_T_645, asSInt(UInt<17>(0h10000))) node _T_647 = asSInt(_T_646) node _T_648 = eq(_T_647, asSInt(UInt<1>(0h0))) node _T_649 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_650 = cvt(_T_649) node _T_651 = and(_T_650, asSInt(UInt<13>(0h1000))) node _T_652 = asSInt(_T_651) node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0))) node _T_654 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_655 = cvt(_T_654) node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000))) node _T_657 = asSInt(_T_656) node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0))) node _T_659 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<27>(0h4000000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_665 = cvt(_T_664) node _T_666 = and(_T_665, asSInt(UInt<13>(0h1000))) node _T_667 = asSInt(_T_666) node _T_668 = eq(_T_667, asSInt(UInt<1>(0h0))) node _T_669 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_670 = cvt(_T_669) node _T_671 = and(_T_670, asSInt(UInt<29>(0h10000000))) node _T_672 = asSInt(_T_671) node _T_673 = eq(_T_672, asSInt(UInt<1>(0h0))) node _T_674 = or(_T_638, _T_643) node _T_675 = or(_T_674, _T_648) node _T_676 = or(_T_675, _T_653) node _T_677 = or(_T_676, _T_658) node _T_678 = or(_T_677, _T_663) node _T_679 = or(_T_678, _T_668) node _T_680 = or(_T_679, _T_673) node _T_681 = and(_T_633, _T_680) node _T_682 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<17>(0h10000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = and(_T_682, _T_687) node _T_689 = or(UInt<1>(0h0), _T_629) node _T_690 = or(_T_689, _T_681) node _T_691 = or(_T_690, _T_688) node _T_692 = and(_T_619, _T_691) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_692, UInt<1>(0h1), "") : assert_26 node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(source_ok, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(is_aligned, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_702 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_702, UInt<1>(0h1), "") : assert_29 node _T_706 = eq(io.in.a.bits.mask, mask) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_706, UInt<1>(0h1), "") : assert_30 node _T_710 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_710 : node _T_711 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_712 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 2, 0) node _T_714 = shr(io.in.a.bits.source, 3) node _T_715 = eq(_T_714, UInt<2>(0h2)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_21) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_21, UInt<3>(0h7)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0) node _T_720 = shr(io.in.a.bits.source, 3) node _T_721 = eq(_T_720, UInt<1>(0h1)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_22) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_22, UInt<3>(0h7)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0) node _T_726 = shr(io.in.a.bits.source, 3) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_23) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_23, UInt<3>(0h7)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(_T_719, _T_725) node _T_733 = or(_T_732, _T_731) node _T_734 = and(_T_713, _T_733) node _T_735 = or(UInt<1>(0h0), _T_734) node _T_736 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_737 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_738 = and(_T_736, _T_737) node _T_739 = or(UInt<1>(0h0), _T_738) node _T_740 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = and(_T_739, _T_744) node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_747 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_748 = and(_T_746, _T_747) node _T_749 = or(UInt<1>(0h0), _T_748) node _T_750 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<14>(0h2000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<18>(0h2f000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<17>(0h10000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<27>(0h4000000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<29>(0h10000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = or(_T_754, _T_759) node _T_791 = or(_T_790, _T_764) node _T_792 = or(_T_791, _T_769) node _T_793 = or(_T_792, _T_774) node _T_794 = or(_T_793, _T_779) node _T_795 = or(_T_794, _T_784) node _T_796 = or(_T_795, _T_789) node _T_797 = and(_T_749, _T_796) node _T_798 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_799 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_800 = cvt(_T_799) node _T_801 = and(_T_800, asSInt(UInt<17>(0h10000))) node _T_802 = asSInt(_T_801) node _T_803 = eq(_T_802, asSInt(UInt<1>(0h0))) node _T_804 = and(_T_798, _T_803) node _T_805 = or(UInt<1>(0h0), _T_745) node _T_806 = or(_T_805, _T_797) node _T_807 = or(_T_806, _T_804) node _T_808 = and(_T_735, _T_807) node _T_809 = asUInt(reset) node _T_810 = eq(_T_809, UInt<1>(0h0)) when _T_810 : node _T_811 = eq(_T_808, UInt<1>(0h0)) when _T_811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_808, UInt<1>(0h1), "") : assert_31 node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(source_ok, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(is_aligned, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_818 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_818, UInt<1>(0h1), "") : assert_34 node _T_822 = not(mask) node _T_823 = and(io.in.a.bits.mask, _T_822) node _T_824 = eq(_T_823, UInt<1>(0h0)) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_824, UInt<1>(0h1), "") : assert_35 node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_828 : node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_832 = shr(io.in.a.bits.source, 3) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_24) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_838 = shr(io.in.a.bits.source, 3) node _T_839 = eq(_T_838, UInt<1>(0h1)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_25) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_843 = and(_T_841, _T_842) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_844 = shr(io.in.a.bits.source, 3) node _T_845 = eq(_T_844, UInt<1>(0h0)) node _T_846 = leq(UInt<1>(0h0), uncommonBits_26) node _T_847 = and(_T_845, _T_846) node _T_848 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_849 = and(_T_847, _T_848) node _T_850 = or(_T_837, _T_843) node _T_851 = or(_T_850, _T_849) node _T_852 = and(_T_831, _T_851) node _T_853 = or(UInt<1>(0h0), _T_852) node _T_854 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_855 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = or(UInt<1>(0h0), _T_856) node _T_858 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_859 = cvt(_T_858) node _T_860 = and(_T_859, asSInt(UInt<14>(0h2000))) node _T_861 = asSInt(_T_860) node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0))) node _T_863 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_864 = cvt(_T_863) node _T_865 = and(_T_864, asSInt(UInt<13>(0h1000))) node _T_866 = asSInt(_T_865) node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0))) node _T_868 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<18>(0h2f000))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<17>(0h10000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<13>(0h1000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<17>(0h10000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<27>(0h4000000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<13>(0h1000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<29>(0h10000000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = or(_T_862, _T_867) node _T_904 = or(_T_903, _T_872) node _T_905 = or(_T_904, _T_877) node _T_906 = or(_T_905, _T_882) node _T_907 = or(_T_906, _T_887) node _T_908 = or(_T_907, _T_892) node _T_909 = or(_T_908, _T_897) node _T_910 = or(_T_909, _T_902) node _T_911 = and(_T_857, _T_910) node _T_912 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_913 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<17>(0h10000))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = and(_T_912, _T_917) node _T_919 = or(UInt<1>(0h0), _T_911) node _T_920 = or(_T_919, _T_918) node _T_921 = and(_T_853, _T_920) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_921, UInt<1>(0h1), "") : assert_36 node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(is_aligned, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_931 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_931, UInt<1>(0h1), "") : assert_39 node _T_935 = eq(io.in.a.bits.mask, mask) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_935, UInt<1>(0h1), "") : assert_40 node _T_939 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_939 : node _T_940 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_941 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_942 = and(_T_940, _T_941) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_943 = shr(io.in.a.bits.source, 3) node _T_944 = eq(_T_943, UInt<2>(0h2)) node _T_945 = leq(UInt<1>(0h0), uncommonBits_27) node _T_946 = and(_T_944, _T_945) node _T_947 = leq(uncommonBits_27, UInt<3>(0h7)) node _T_948 = and(_T_946, _T_947) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0) node _T_949 = shr(io.in.a.bits.source, 3) node _T_950 = eq(_T_949, UInt<1>(0h1)) node _T_951 = leq(UInt<1>(0h0), uncommonBits_28) node _T_952 = and(_T_950, _T_951) node _T_953 = leq(uncommonBits_28, UInt<3>(0h7)) node _T_954 = and(_T_952, _T_953) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_955 = shr(io.in.a.bits.source, 3) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = leq(UInt<1>(0h0), uncommonBits_29) node _T_958 = and(_T_956, _T_957) node _T_959 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_960 = and(_T_958, _T_959) node _T_961 = or(_T_948, _T_954) node _T_962 = or(_T_961, _T_960) node _T_963 = and(_T_942, _T_962) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_966 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_967 = and(_T_965, _T_966) node _T_968 = or(UInt<1>(0h0), _T_967) node _T_969 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_970 = cvt(_T_969) node _T_971 = and(_T_970, asSInt(UInt<14>(0h2000))) node _T_972 = asSInt(_T_971) node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0))) node _T_974 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<13>(0h1000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<18>(0h2f000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<17>(0h10000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<13>(0h1000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<27>(0h4000000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<13>(0h1000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1010 = cvt(_T_1009) node _T_1011 = and(_T_1010, asSInt(UInt<29>(0h10000000))) node _T_1012 = asSInt(_T_1011) node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0))) node _T_1014 = or(_T_973, _T_978) node _T_1015 = or(_T_1014, _T_983) node _T_1016 = or(_T_1015, _T_988) node _T_1017 = or(_T_1016, _T_993) node _T_1018 = or(_T_1017, _T_998) node _T_1019 = or(_T_1018, _T_1003) node _T_1020 = or(_T_1019, _T_1008) node _T_1021 = or(_T_1020, _T_1013) node _T_1022 = and(_T_968, _T_1021) node _T_1023 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1024 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<17>(0h10000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = and(_T_1023, _T_1028) node _T_1030 = or(UInt<1>(0h0), _T_1022) node _T_1031 = or(_T_1030, _T_1029) node _T_1032 = and(_T_964, _T_1031) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_41 node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(source_ok, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(is_aligned, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1042 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_44 node _T_1046 = eq(io.in.a.bits.mask, mask) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_45 node _T_1050 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1050 : node _T_1051 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1052 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0) node _T_1054 = shr(io.in.a.bits.source, 3) node _T_1055 = eq(_T_1054, UInt<2>(0h2)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_30, UInt<3>(0h7)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0) node _T_1060 = shr(io.in.a.bits.source, 3) node _T_1061 = eq(_T_1060, UInt<1>(0h1)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_31, UInt<3>(0h7)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_1066 = shr(io.in.a.bits.source, 3) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(_T_1059, _T_1065) node _T_1073 = or(_T_1072, _T_1071) node _T_1074 = and(_T_1053, _T_1073) node _T_1075 = or(UInt<1>(0h0), _T_1074) node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = or(UInt<1>(0h0), _T_1078) node _T_1080 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1081 = cvt(_T_1080) node _T_1082 = and(_T_1081, asSInt(UInt<13>(0h1000))) node _T_1083 = asSInt(_T_1082) node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0))) node _T_1085 = and(_T_1079, _T_1084) node _T_1086 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1087 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1088 = cvt(_T_1087) node _T_1089 = and(_T_1088, asSInt(UInt<14>(0h2000))) node _T_1090 = asSInt(_T_1089) node _T_1091 = eq(_T_1090, asSInt(UInt<1>(0h0))) node _T_1092 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1093 = cvt(_T_1092) node _T_1094 = and(_T_1093, asSInt(UInt<17>(0h10000))) node _T_1095 = asSInt(_T_1094) node _T_1096 = eq(_T_1095, asSInt(UInt<1>(0h0))) node _T_1097 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1098 = cvt(_T_1097) node _T_1099 = and(_T_1098, asSInt(UInt<18>(0h2f000))) node _T_1100 = asSInt(_T_1099) node _T_1101 = eq(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<17>(0h10000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1108 = cvt(_T_1107) node _T_1109 = and(_T_1108, asSInt(UInt<13>(0h1000))) node _T_1110 = asSInt(_T_1109) node _T_1111 = eq(_T_1110, asSInt(UInt<1>(0h0))) node _T_1112 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<27>(0h4000000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1118 = cvt(_T_1117) node _T_1119 = and(_T_1118, asSInt(UInt<13>(0h1000))) node _T_1120 = asSInt(_T_1119) node _T_1121 = eq(_T_1120, asSInt(UInt<1>(0h0))) node _T_1122 = or(_T_1091, _T_1096) node _T_1123 = or(_T_1122, _T_1101) node _T_1124 = or(_T_1123, _T_1106) node _T_1125 = or(_T_1124, _T_1111) node _T_1126 = or(_T_1125, _T_1116) node _T_1127 = or(_T_1126, _T_1121) node _T_1128 = and(_T_1086, _T_1127) node _T_1129 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1130 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1131) node _T_1133 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<17>(0h10000))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1139 = cvt(_T_1138) node _T_1140 = and(_T_1139, asSInt(UInt<29>(0h10000000))) node _T_1141 = asSInt(_T_1140) node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0))) node _T_1143 = or(_T_1137, _T_1142) node _T_1144 = and(_T_1132, _T_1143) node _T_1145 = or(UInt<1>(0h0), _T_1085) node _T_1146 = or(_T_1145, _T_1128) node _T_1147 = or(_T_1146, _T_1144) node _T_1148 = and(_T_1075, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_46 node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(is_aligned, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1158 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_49 node _T_1162 = eq(io.in.a.bits.mask, mask) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_50 node _T_1166 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1170 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 2, 0) node _source_ok_T_19 = shr(io.in.d.bits.source, 3) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h2)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<3>(0h7)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.d.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.d.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_24 connect _source_ok_WIRE_1[1], _source_ok_T_30 connect _source_ok_WIRE_1[2], _source_ok_T_36 node _source_ok_T_37 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_37, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1174 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1174 : node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(source_ok_1, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1178 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_54 node _T_1182 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_55 node _T_1186 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_56 node _T_1190 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_57 node _T_1194 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1194 : node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(source_ok_1, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(sink_ok, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1201 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_60 node _T_1205 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_61 node _T_1209 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_62 node _T_1213 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(_T_1213, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1213, UInt<1>(0h1), "") : assert_63 node _T_1217 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1218 = or(UInt<1>(0h1), _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_64 node _T_1222 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1222 : node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(source_ok_1, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(sink_ok, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1229 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_67 node _T_1233 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_68 node _T_1237 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_69 node _T_1241 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1242 = or(_T_1241, io.in.d.bits.corrupt) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_70 node _T_1246 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1247 = or(UInt<1>(0h1), _T_1246) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_71 node _T_1251 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1251 : node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(source_ok_1, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1255 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_73 node _T_1259 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_74 node _T_1263 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1264 = or(UInt<1>(0h1), _T_1263) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_75 node _T_1268 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1268 : node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(source_ok_1, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1272 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1273 = asUInt(reset) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) when _T_1274 : node _T_1275 = eq(_T_1272, UInt<1>(0h0)) when _T_1275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1272, UInt<1>(0h1), "") : assert_77 node _T_1276 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1277 = or(_T_1276, io.in.d.bits.corrupt) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_78 node _T_1281 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1282 = or(UInt<1>(0h1), _T_1281) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_79 node _T_1286 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1286 : node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(source_ok_1, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1290 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_81 node _T_1294 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_82 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(UInt<1>(0h1), _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1303 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_33 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_1307 = shr(io.in.b.bits.source, 3) node _T_1308 = eq(_T_1307, UInt<2>(0h2)) node _T_1309 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1310 = and(_T_1308, _T_1309) node _T_1311 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) node _T_1314 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<1>(0h0))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = or(_T_1313, _T_1318) node _uncommonBits_T_34 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_1320 = shr(io.in.b.bits.source, 3) node _T_1321 = eq(_T_1320, UInt<1>(0h1)) node _T_1322 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) node _T_1327 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<1>(0h0))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = or(_T_1326, _T_1331) node _uncommonBits_T_35 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0) node _T_1333 = shr(io.in.b.bits.source, 3) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_35, UInt<3>(0h7)) node _T_1338 = and(_T_1336, _T_1337) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) node _T_1340 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1341 = cvt(_T_1340) node _T_1342 = and(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = asSInt(_T_1342) node _T_1344 = eq(_T_1343, asSInt(UInt<1>(0h0))) node _T_1345 = or(_T_1339, _T_1344) node _T_1346 = and(_T_1319, _T_1332) node _T_1347 = and(_T_1346, _T_1345) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<2>(0h2)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h7)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 2, 0) node _legal_source_T_6 = shr(io.in.b.bits.source, 3) node _legal_source_T_7 = eq(_legal_source_T_6, UInt<1>(0h1)) node _legal_source_T_8 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_9 = and(_legal_source_T_7, _legal_source_T_8) node _legal_source_T_10 = leq(legal_source_uncommonBits_1, UInt<3>(0h7)) node _legal_source_T_11 = and(_legal_source_T_9, _legal_source_T_10) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 2, 0) node _legal_source_T_12 = shr(io.in.b.bits.source, 3) node _legal_source_T_13 = eq(_legal_source_T_12, UInt<1>(0h0)) node _legal_source_T_14 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_15 = and(_legal_source_T_13, _legal_source_T_14) node _legal_source_T_16 = leq(legal_source_uncommonBits_2, UInt<3>(0h7)) node _legal_source_T_17 = and(_legal_source_T_15, _legal_source_T_16) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_11 connect _legal_source_WIRE[2], _legal_source_T_17 node _legal_source_T_18 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_19 = mux(_legal_source_WIRE[1], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_20 = mux(_legal_source_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_21 = or(_legal_source_T_18, _legal_source_T_19) node _legal_source_T_22 = or(_legal_source_T_21, _legal_source_T_20) wire _legal_source_WIRE_1 : UInt<5> connect _legal_source_WIRE_1, _legal_source_T_22 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1351 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1351 : node _uncommonBits_T_36 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0) node _T_1352 = shr(io.in.b.bits.source, 3) node _T_1353 = eq(_T_1352, UInt<2>(0h2)) node _T_1354 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1355 = and(_T_1353, _T_1354) node _T_1356 = leq(uncommonBits_36, UInt<3>(0h7)) node _T_1357 = and(_T_1355, _T_1356) node _uncommonBits_T_37 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0) node _T_1358 = shr(io.in.b.bits.source, 3) node _T_1359 = eq(_T_1358, UInt<1>(0h1)) node _T_1360 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1361 = and(_T_1359, _T_1360) node _T_1362 = leq(uncommonBits_37, UInt<3>(0h7)) node _T_1363 = and(_T_1361, _T_1362) node _uncommonBits_T_38 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 2, 0) node _T_1364 = shr(io.in.b.bits.source, 3) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) node _T_1366 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1367 = and(_T_1365, _T_1366) node _T_1368 = leq(uncommonBits_38, UInt<3>(0h7)) node _T_1369 = and(_T_1367, _T_1368) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1357 connect _WIRE_4[1], _T_1363 connect _WIRE_4[2], _T_1369 node _T_1370 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1371 = mux(_WIRE_4[0], _T_1370, UInt<1>(0h0)) node _T_1372 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1373 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1374 = or(_T_1371, _T_1372) node _T_1375 = or(_T_1374, _T_1373) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1375 node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = or(UInt<1>(0h0), _T_1378) node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1391 = cvt(_T_1390) node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000))) node _T_1393 = asSInt(_T_1392) node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0))) node _T_1395 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1396 = cvt(_T_1395) node _T_1397 = and(_T_1396, asSInt(UInt<18>(0h2f000))) node _T_1398 = asSInt(_T_1397) node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0))) node _T_1400 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1401 = cvt(_T_1400) node _T_1402 = and(_T_1401, asSInt(UInt<17>(0h10000))) node _T_1403 = asSInt(_T_1402) node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0))) node _T_1405 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<13>(0h1000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1416 = cvt(_T_1415) node _T_1417 = and(_T_1416, asSInt(UInt<27>(0h4000000))) node _T_1418 = asSInt(_T_1417) node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0))) node _T_1420 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1421 = cvt(_T_1420) node _T_1422 = and(_T_1421, asSInt(UInt<13>(0h1000))) node _T_1423 = asSInt(_T_1422) node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1426 = cvt(_T_1425) node _T_1427 = and(_T_1426, asSInt(UInt<29>(0h10000000))) node _T_1428 = asSInt(_T_1427) node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0))) node _T_1430 = or(_T_1384, _T_1389) node _T_1431 = or(_T_1430, _T_1394) node _T_1432 = or(_T_1431, _T_1399) node _T_1433 = or(_T_1432, _T_1404) node _T_1434 = or(_T_1433, _T_1409) node _T_1435 = or(_T_1434, _T_1414) node _T_1436 = or(_T_1435, _T_1419) node _T_1437 = or(_T_1436, _T_1424) node _T_1438 = or(_T_1437, _T_1429) node _T_1439 = and(_T_1379, _T_1438) node _T_1440 = or(UInt<1>(0h0), _T_1439) node _T_1441 = and(_WIRE_5, _T_1440) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_86 node _T_1445 = asUInt(reset) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) when _T_1446 : node _T_1447 = eq(address_ok, UInt<1>(0h0)) when _T_1447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(legal_source, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1454 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1455 = asUInt(reset) node _T_1456 = eq(_T_1455, UInt<1>(0h0)) when _T_1456 : node _T_1457 = eq(_T_1454, UInt<1>(0h0)) when _T_1457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1454, UInt<1>(0h1), "") : assert_90 node _T_1458 = eq(io.in.b.bits.mask, mask_1) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_91 node _T_1462 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_92 node _T_1466 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1466 : node _T_1467 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1468 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<14>(0h2000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<13>(0h1000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<17>(0h10000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<18>(0h2f000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<17>(0h10000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<13>(0h1000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<17>(0h10000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<27>(0h4000000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1512 = cvt(_T_1511) node _T_1513 = and(_T_1512, asSInt(UInt<13>(0h1000))) node _T_1514 = asSInt(_T_1513) node _T_1515 = eq(_T_1514, asSInt(UInt<1>(0h0))) node _T_1516 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1517 = cvt(_T_1516) node _T_1518 = and(_T_1517, asSInt(UInt<29>(0h10000000))) node _T_1519 = asSInt(_T_1518) node _T_1520 = eq(_T_1519, asSInt(UInt<1>(0h0))) node _T_1521 = or(_T_1475, _T_1480) node _T_1522 = or(_T_1521, _T_1485) node _T_1523 = or(_T_1522, _T_1490) node _T_1524 = or(_T_1523, _T_1495) node _T_1525 = or(_T_1524, _T_1500) node _T_1526 = or(_T_1525, _T_1505) node _T_1527 = or(_T_1526, _T_1510) node _T_1528 = or(_T_1527, _T_1515) node _T_1529 = or(_T_1528, _T_1520) node _T_1530 = and(_T_1470, _T_1529) node _T_1531 = or(UInt<1>(0h0), _T_1530) node _T_1532 = and(UInt<1>(0h0), _T_1531) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_93 node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(address_ok, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(legal_source, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1545 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_97 node _T_1549 = eq(io.in.b.bits.mask, mask_1) node _T_1550 = asUInt(reset) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) when _T_1551 : node _T_1552 = eq(_T_1549, UInt<1>(0h0)) when _T_1552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1549, UInt<1>(0h1), "") : assert_98 node _T_1553 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1554 = asUInt(reset) node _T_1555 = eq(_T_1554, UInt<1>(0h0)) when _T_1555 : node _T_1556 = eq(_T_1553, UInt<1>(0h0)) when _T_1556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1553, UInt<1>(0h1), "") : assert_99 node _T_1557 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1557 : node _T_1558 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1559 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1560 = and(_T_1558, _T_1559) node _T_1561 = or(UInt<1>(0h0), _T_1560) node _T_1562 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1563 = cvt(_T_1562) node _T_1564 = and(_T_1563, asSInt(UInt<14>(0h2000))) node _T_1565 = asSInt(_T_1564) node _T_1566 = eq(_T_1565, asSInt(UInt<1>(0h0))) node _T_1567 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1568 = cvt(_T_1567) node _T_1569 = and(_T_1568, asSInt(UInt<13>(0h1000))) node _T_1570 = asSInt(_T_1569) node _T_1571 = eq(_T_1570, asSInt(UInt<1>(0h0))) node _T_1572 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<17>(0h10000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1578 = cvt(_T_1577) node _T_1579 = and(_T_1578, asSInt(UInt<18>(0h2f000))) node _T_1580 = asSInt(_T_1579) node _T_1581 = eq(_T_1580, asSInt(UInt<1>(0h0))) node _T_1582 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1583 = cvt(_T_1582) node _T_1584 = and(_T_1583, asSInt(UInt<17>(0h10000))) node _T_1585 = asSInt(_T_1584) node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0))) node _T_1587 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<27>(0h4000000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<29>(0h10000000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = or(_T_1566, _T_1571) node _T_1613 = or(_T_1612, _T_1576) node _T_1614 = or(_T_1613, _T_1581) node _T_1615 = or(_T_1614, _T_1586) node _T_1616 = or(_T_1615, _T_1591) node _T_1617 = or(_T_1616, _T_1596) node _T_1618 = or(_T_1617, _T_1601) node _T_1619 = or(_T_1618, _T_1606) node _T_1620 = or(_T_1619, _T_1611) node _T_1621 = and(_T_1561, _T_1620) node _T_1622 = or(UInt<1>(0h0), _T_1621) node _T_1623 = and(UInt<1>(0h0), _T_1622) node _T_1624 = asUInt(reset) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(_T_1623, UInt<1>(0h0)) when _T_1626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1623, UInt<1>(0h1), "") : assert_100 node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(address_ok, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(legal_source, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1636 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(_T_1636, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1636, UInt<1>(0h1), "") : assert_104 node _T_1640 = eq(io.in.b.bits.mask, mask_1) node _T_1641 = asUInt(reset) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) when _T_1642 : node _T_1643 = eq(_T_1640, UInt<1>(0h0)) when _T_1643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1640, UInt<1>(0h1), "") : assert_105 node _T_1644 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1644 : node _T_1645 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1646 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = or(UInt<1>(0h0), _T_1647) node _T_1649 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1650 = cvt(_T_1649) node _T_1651 = and(_T_1650, asSInt(UInt<14>(0h2000))) node _T_1652 = asSInt(_T_1651) node _T_1653 = eq(_T_1652, asSInt(UInt<1>(0h0))) node _T_1654 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1655 = cvt(_T_1654) node _T_1656 = and(_T_1655, asSInt(UInt<13>(0h1000))) node _T_1657 = asSInt(_T_1656) node _T_1658 = eq(_T_1657, asSInt(UInt<1>(0h0))) node _T_1659 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1660 = cvt(_T_1659) node _T_1661 = and(_T_1660, asSInt(UInt<17>(0h10000))) node _T_1662 = asSInt(_T_1661) node _T_1663 = eq(_T_1662, asSInt(UInt<1>(0h0))) node _T_1664 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1665 = cvt(_T_1664) node _T_1666 = and(_T_1665, asSInt(UInt<18>(0h2f000))) node _T_1667 = asSInt(_T_1666) node _T_1668 = eq(_T_1667, asSInt(UInt<1>(0h0))) node _T_1669 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1670 = cvt(_T_1669) node _T_1671 = and(_T_1670, asSInt(UInt<17>(0h10000))) node _T_1672 = asSInt(_T_1671) node _T_1673 = eq(_T_1672, asSInt(UInt<1>(0h0))) node _T_1674 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<13>(0h1000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1680 = cvt(_T_1679) node _T_1681 = and(_T_1680, asSInt(UInt<17>(0h10000))) node _T_1682 = asSInt(_T_1681) node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0))) node _T_1684 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<27>(0h4000000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<13>(0h1000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<29>(0h10000000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = or(_T_1653, _T_1658) node _T_1700 = or(_T_1699, _T_1663) node _T_1701 = or(_T_1700, _T_1668) node _T_1702 = or(_T_1701, _T_1673) node _T_1703 = or(_T_1702, _T_1678) node _T_1704 = or(_T_1703, _T_1683) node _T_1705 = or(_T_1704, _T_1688) node _T_1706 = or(_T_1705, _T_1693) node _T_1707 = or(_T_1706, _T_1698) node _T_1708 = and(_T_1648, _T_1707) node _T_1709 = or(UInt<1>(0h0), _T_1708) node _T_1710 = and(UInt<1>(0h0), _T_1709) node _T_1711 = asUInt(reset) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) when _T_1712 : node _T_1713 = eq(_T_1710, UInt<1>(0h0)) when _T_1713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1710, UInt<1>(0h1), "") : assert_106 node _T_1714 = asUInt(reset) node _T_1715 = eq(_T_1714, UInt<1>(0h0)) when _T_1715 : node _T_1716 = eq(address_ok, UInt<1>(0h0)) when _T_1716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(legal_source, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1723 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_110 node _T_1727 = not(mask_1) node _T_1728 = and(io.in.b.bits.mask, _T_1727) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_111 node _T_1733 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1733 : node _T_1734 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1735 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = or(UInt<1>(0h0), _T_1736) node _T_1738 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<14>(0h2000))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1744 = cvt(_T_1743) node _T_1745 = and(_T_1744, asSInt(UInt<13>(0h1000))) node _T_1746 = asSInt(_T_1745) node _T_1747 = eq(_T_1746, asSInt(UInt<1>(0h0))) node _T_1748 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1749 = cvt(_T_1748) node _T_1750 = and(_T_1749, asSInt(UInt<17>(0h10000))) node _T_1751 = asSInt(_T_1750) node _T_1752 = eq(_T_1751, asSInt(UInt<1>(0h0))) node _T_1753 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1754 = cvt(_T_1753) node _T_1755 = and(_T_1754, asSInt(UInt<18>(0h2f000))) node _T_1756 = asSInt(_T_1755) node _T_1757 = eq(_T_1756, asSInt(UInt<1>(0h0))) node _T_1758 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1759 = cvt(_T_1758) node _T_1760 = and(_T_1759, asSInt(UInt<17>(0h10000))) node _T_1761 = asSInt(_T_1760) node _T_1762 = eq(_T_1761, asSInt(UInt<1>(0h0))) node _T_1763 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1764 = cvt(_T_1763) node _T_1765 = and(_T_1764, asSInt(UInt<13>(0h1000))) node _T_1766 = asSInt(_T_1765) node _T_1767 = eq(_T_1766, asSInt(UInt<1>(0h0))) node _T_1768 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1769 = cvt(_T_1768) node _T_1770 = and(_T_1769, asSInt(UInt<17>(0h10000))) node _T_1771 = asSInt(_T_1770) node _T_1772 = eq(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1774 = cvt(_T_1773) node _T_1775 = and(_T_1774, asSInt(UInt<27>(0h4000000))) node _T_1776 = asSInt(_T_1775) node _T_1777 = eq(_T_1776, asSInt(UInt<1>(0h0))) node _T_1778 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1779 = cvt(_T_1778) node _T_1780 = and(_T_1779, asSInt(UInt<13>(0h1000))) node _T_1781 = asSInt(_T_1780) node _T_1782 = eq(_T_1781, asSInt(UInt<1>(0h0))) node _T_1783 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1784 = cvt(_T_1783) node _T_1785 = and(_T_1784, asSInt(UInt<29>(0h10000000))) node _T_1786 = asSInt(_T_1785) node _T_1787 = eq(_T_1786, asSInt(UInt<1>(0h0))) node _T_1788 = or(_T_1742, _T_1747) node _T_1789 = or(_T_1788, _T_1752) node _T_1790 = or(_T_1789, _T_1757) node _T_1791 = or(_T_1790, _T_1762) node _T_1792 = or(_T_1791, _T_1767) node _T_1793 = or(_T_1792, _T_1772) node _T_1794 = or(_T_1793, _T_1777) node _T_1795 = or(_T_1794, _T_1782) node _T_1796 = or(_T_1795, _T_1787) node _T_1797 = and(_T_1737, _T_1796) node _T_1798 = or(UInt<1>(0h0), _T_1797) node _T_1799 = and(UInt<1>(0h0), _T_1798) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_112 node _T_1803 = asUInt(reset) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) when _T_1804 : node _T_1805 = eq(address_ok, UInt<1>(0h0)) when _T_1805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(legal_source, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1809 = asUInt(reset) node _T_1810 = eq(_T_1809, UInt<1>(0h0)) when _T_1810 : node _T_1811 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1812 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(_T_1812, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1812, UInt<1>(0h1), "") : assert_116 node _T_1816 = eq(io.in.b.bits.mask, mask_1) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_117 node _T_1820 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1820 : node _T_1821 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1822 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = or(UInt<1>(0h0), _T_1823) node _T_1825 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1826 = cvt(_T_1825) node _T_1827 = and(_T_1826, asSInt(UInt<14>(0h2000))) node _T_1828 = asSInt(_T_1827) node _T_1829 = eq(_T_1828, asSInt(UInt<1>(0h0))) node _T_1830 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<13>(0h1000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<17>(0h10000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<18>(0h2f000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<17>(0h10000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1851 = cvt(_T_1850) node _T_1852 = and(_T_1851, asSInt(UInt<13>(0h1000))) node _T_1853 = asSInt(_T_1852) node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0))) node _T_1855 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1856 = cvt(_T_1855) node _T_1857 = and(_T_1856, asSInt(UInt<17>(0h10000))) node _T_1858 = asSInt(_T_1857) node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0))) node _T_1860 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1861 = cvt(_T_1860) node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000))) node _T_1863 = asSInt(_T_1862) node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0))) node _T_1865 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1866 = cvt(_T_1865) node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000))) node _T_1868 = asSInt(_T_1867) node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0))) node _T_1870 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1871 = cvt(_T_1870) node _T_1872 = and(_T_1871, asSInt(UInt<29>(0h10000000))) node _T_1873 = asSInt(_T_1872) node _T_1874 = eq(_T_1873, asSInt(UInt<1>(0h0))) node _T_1875 = or(_T_1829, _T_1834) node _T_1876 = or(_T_1875, _T_1839) node _T_1877 = or(_T_1876, _T_1844) node _T_1878 = or(_T_1877, _T_1849) node _T_1879 = or(_T_1878, _T_1854) node _T_1880 = or(_T_1879, _T_1859) node _T_1881 = or(_T_1880, _T_1864) node _T_1882 = or(_T_1881, _T_1869) node _T_1883 = or(_T_1882, _T_1874) node _T_1884 = and(_T_1824, _T_1883) node _T_1885 = or(UInt<1>(0h0), _T_1884) node _T_1886 = and(UInt<1>(0h0), _T_1885) node _T_1887 = asUInt(reset) node _T_1888 = eq(_T_1887, UInt<1>(0h0)) when _T_1888 : node _T_1889 = eq(_T_1886, UInt<1>(0h0)) when _T_1889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1886, UInt<1>(0h1), "") : assert_118 node _T_1890 = asUInt(reset) node _T_1891 = eq(_T_1890, UInt<1>(0h0)) when _T_1891 : node _T_1892 = eq(address_ok, UInt<1>(0h0)) when _T_1892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1893 = asUInt(reset) node _T_1894 = eq(_T_1893, UInt<1>(0h0)) when _T_1894 : node _T_1895 = eq(legal_source, UInt<1>(0h0)) when _T_1895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1899 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1900 = asUInt(reset) node _T_1901 = eq(_T_1900, UInt<1>(0h0)) when _T_1901 : node _T_1902 = eq(_T_1899, UInt<1>(0h0)) when _T_1902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1899, UInt<1>(0h1), "") : assert_122 node _T_1903 = eq(io.in.b.bits.mask, mask_1) node _T_1904 = asUInt(reset) node _T_1905 = eq(_T_1904, UInt<1>(0h0)) when _T_1905 : node _T_1906 = eq(_T_1903, UInt<1>(0h0)) when _T_1906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1903, UInt<1>(0h1), "") : assert_123 node _T_1907 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1907 : node _T_1908 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1909 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1910 = and(_T_1908, _T_1909) node _T_1911 = or(UInt<1>(0h0), _T_1910) node _T_1912 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1913 = cvt(_T_1912) node _T_1914 = and(_T_1913, asSInt(UInt<14>(0h2000))) node _T_1915 = asSInt(_T_1914) node _T_1916 = eq(_T_1915, asSInt(UInt<1>(0h0))) node _T_1917 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1918 = cvt(_T_1917) node _T_1919 = and(_T_1918, asSInt(UInt<13>(0h1000))) node _T_1920 = asSInt(_T_1919) node _T_1921 = eq(_T_1920, asSInt(UInt<1>(0h0))) node _T_1922 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1923 = cvt(_T_1922) node _T_1924 = and(_T_1923, asSInt(UInt<17>(0h10000))) node _T_1925 = asSInt(_T_1924) node _T_1926 = eq(_T_1925, asSInt(UInt<1>(0h0))) node _T_1927 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1928 = cvt(_T_1927) node _T_1929 = and(_T_1928, asSInt(UInt<18>(0h2f000))) node _T_1930 = asSInt(_T_1929) node _T_1931 = eq(_T_1930, asSInt(UInt<1>(0h0))) node _T_1932 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1933 = cvt(_T_1932) node _T_1934 = and(_T_1933, asSInt(UInt<17>(0h10000))) node _T_1935 = asSInt(_T_1934) node _T_1936 = eq(_T_1935, asSInt(UInt<1>(0h0))) node _T_1937 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1938 = cvt(_T_1937) node _T_1939 = and(_T_1938, asSInt(UInt<13>(0h1000))) node _T_1940 = asSInt(_T_1939) node _T_1941 = eq(_T_1940, asSInt(UInt<1>(0h0))) node _T_1942 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1943 = cvt(_T_1942) node _T_1944 = and(_T_1943, asSInt(UInt<17>(0h10000))) node _T_1945 = asSInt(_T_1944) node _T_1946 = eq(_T_1945, asSInt(UInt<1>(0h0))) node _T_1947 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1948 = cvt(_T_1947) node _T_1949 = and(_T_1948, asSInt(UInt<27>(0h4000000))) node _T_1950 = asSInt(_T_1949) node _T_1951 = eq(_T_1950, asSInt(UInt<1>(0h0))) node _T_1952 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1953 = cvt(_T_1952) node _T_1954 = and(_T_1953, asSInt(UInt<13>(0h1000))) node _T_1955 = asSInt(_T_1954) node _T_1956 = eq(_T_1955, asSInt(UInt<1>(0h0))) node _T_1957 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1958 = cvt(_T_1957) node _T_1959 = and(_T_1958, asSInt(UInt<29>(0h10000000))) node _T_1960 = asSInt(_T_1959) node _T_1961 = eq(_T_1960, asSInt(UInt<1>(0h0))) node _T_1962 = or(_T_1916, _T_1921) node _T_1963 = or(_T_1962, _T_1926) node _T_1964 = or(_T_1963, _T_1931) node _T_1965 = or(_T_1964, _T_1936) node _T_1966 = or(_T_1965, _T_1941) node _T_1967 = or(_T_1966, _T_1946) node _T_1968 = or(_T_1967, _T_1951) node _T_1969 = or(_T_1968, _T_1956) node _T_1970 = or(_T_1969, _T_1961) node _T_1971 = and(_T_1911, _T_1970) node _T_1972 = or(UInt<1>(0h0), _T_1971) node _T_1973 = and(UInt<1>(0h0), _T_1972) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_124 node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(address_ok, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(legal_source, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1983 = asUInt(reset) node _T_1984 = eq(_T_1983, UInt<1>(0h0)) when _T_1984 : node _T_1985 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1986 = eq(io.in.b.bits.mask, mask_1) node _T_1987 = asUInt(reset) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) when _T_1988 : node _T_1989 = eq(_T_1986, UInt<1>(0h0)) when _T_1989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1986, UInt<1>(0h1), "") : assert_128 node _T_1990 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1994 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_6 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_38 = shr(io.in.c.bits.source, 3) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<3>(0h7)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0) node _source_ok_T_44 = shr(io.in.c.bits.source, 3) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h1)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<3>(0h7)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 2, 0) node _source_ok_T_50 = shr(io.in.c.bits.source, 3) node _source_ok_T_51 = eq(_source_ok_T_50, UInt<1>(0h0)) node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_T_54 = leq(source_ok_uncommonBits_8, UInt<3>(0h7)) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_43 connect _source_ok_WIRE_2[1], _source_ok_T_49 connect _source_ok_WIRE_2[2], _source_ok_T_55 node _source_ok_T_56 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_56, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_39 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_1998 = shr(io.in.c.bits.source, 3) node _T_1999 = eq(_T_1998, UInt<2>(0h2)) node _T_2000 = leq(UInt<1>(0h0), uncommonBits_39) node _T_2001 = and(_T_1999, _T_2000) node _T_2002 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_2003 = and(_T_2001, _T_2002) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) node _T_2005 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = or(_T_2004, _T_2009) node _uncommonBits_T_40 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_2011 = shr(io.in.c.bits.source, 3) node _T_2012 = eq(_T_2011, UInt<1>(0h1)) node _T_2013 = leq(UInt<1>(0h0), uncommonBits_40) node _T_2014 = and(_T_2012, _T_2013) node _T_2015 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_2016 = and(_T_2014, _T_2015) node _T_2017 = eq(_T_2016, UInt<1>(0h0)) node _T_2018 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2019 = cvt(_T_2018) node _T_2020 = and(_T_2019, asSInt(UInt<1>(0h0))) node _T_2021 = asSInt(_T_2020) node _T_2022 = eq(_T_2021, asSInt(UInt<1>(0h0))) node _T_2023 = or(_T_2017, _T_2022) node _uncommonBits_T_41 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_2024 = shr(io.in.c.bits.source, 3) node _T_2025 = eq(_T_2024, UInt<1>(0h0)) node _T_2026 = leq(UInt<1>(0h0), uncommonBits_41) node _T_2027 = and(_T_2025, _T_2026) node _T_2028 = leq(uncommonBits_41, UInt<3>(0h7)) node _T_2029 = and(_T_2027, _T_2028) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) node _T_2031 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2032 = cvt(_T_2031) node _T_2033 = and(_T_2032, asSInt(UInt<1>(0h0))) node _T_2034 = asSInt(_T_2033) node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0))) node _T_2036 = or(_T_2030, _T_2035) node _T_2037 = and(_T_2010, _T_2023) node _T_2038 = and(_T_2037, _T_2036) node _T_2039 = asUInt(reset) node _T_2040 = eq(_T_2039, UInt<1>(0h0)) when _T_2040 : node _T_2041 = eq(_T_2038, UInt<1>(0h0)) when _T_2041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2038, UInt<1>(0h1), "") : assert_131 node _T_2042 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2042 : node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(address_ok_1, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2046 = asUInt(reset) node _T_2047 = eq(_T_2046, UInt<1>(0h0)) when _T_2047 : node _T_2048 = eq(source_ok_2, UInt<1>(0h0)) when _T_2048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2049 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_134 node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2056 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_136 node _T_2060 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2061 = asUInt(reset) node _T_2062 = eq(_T_2061, UInt<1>(0h0)) when _T_2062 : node _T_2063 = eq(_T_2060, UInt<1>(0h0)) when _T_2063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2060, UInt<1>(0h1), "") : assert_137 node _T_2064 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2064 : node _T_2065 = asUInt(reset) node _T_2066 = eq(_T_2065, UInt<1>(0h0)) when _T_2066 : node _T_2067 = eq(address_ok_1, UInt<1>(0h0)) when _T_2067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(source_ok_2, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2071 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_140 node _T_2075 = asUInt(reset) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) when _T_2076 : node _T_2077 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2078 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2079 = asUInt(reset) node _T_2080 = eq(_T_2079, UInt<1>(0h0)) when _T_2080 : node _T_2081 = eq(_T_2078, UInt<1>(0h0)) when _T_2081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2078, UInt<1>(0h1), "") : assert_142 node _T_2082 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2082 : node _T_2083 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2084 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2085 = and(_T_2083, _T_2084) node _uncommonBits_T_42 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0) node _T_2086 = shr(io.in.c.bits.source, 3) node _T_2087 = eq(_T_2086, UInt<2>(0h2)) node _T_2088 = leq(UInt<1>(0h0), uncommonBits_42) node _T_2089 = and(_T_2087, _T_2088) node _T_2090 = leq(uncommonBits_42, UInt<3>(0h7)) node _T_2091 = and(_T_2089, _T_2090) node _uncommonBits_T_43 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0) node _T_2092 = shr(io.in.c.bits.source, 3) node _T_2093 = eq(_T_2092, UInt<1>(0h1)) node _T_2094 = leq(UInt<1>(0h0), uncommonBits_43) node _T_2095 = and(_T_2093, _T_2094) node _T_2096 = leq(uncommonBits_43, UInt<3>(0h7)) node _T_2097 = and(_T_2095, _T_2096) node _uncommonBits_T_44 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_2098 = shr(io.in.c.bits.source, 3) node _T_2099 = eq(_T_2098, UInt<1>(0h0)) node _T_2100 = leq(UInt<1>(0h0), uncommonBits_44) node _T_2101 = and(_T_2099, _T_2100) node _T_2102 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_2103 = and(_T_2101, _T_2102) node _T_2104 = or(_T_2091, _T_2097) node _T_2105 = or(_T_2104, _T_2103) node _T_2106 = and(_T_2085, _T_2105) node _T_2107 = or(UInt<1>(0h0), _T_2106) node _T_2108 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2109 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2110 = cvt(_T_2109) node _T_2111 = and(_T_2110, asSInt(UInt<14>(0h2000))) node _T_2112 = asSInt(_T_2111) node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0))) node _T_2114 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2115 = cvt(_T_2114) node _T_2116 = and(_T_2115, asSInt(UInt<13>(0h1000))) node _T_2117 = asSInt(_T_2116) node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0))) node _T_2119 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2120 = cvt(_T_2119) node _T_2121 = and(_T_2120, asSInt(UInt<17>(0h10000))) node _T_2122 = asSInt(_T_2121) node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0))) node _T_2124 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2125 = cvt(_T_2124) node _T_2126 = and(_T_2125, asSInt(UInt<18>(0h2f000))) node _T_2127 = asSInt(_T_2126) node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2130 = cvt(_T_2129) node _T_2131 = and(_T_2130, asSInt(UInt<17>(0h10000))) node _T_2132 = asSInt(_T_2131) node _T_2133 = eq(_T_2132, asSInt(UInt<1>(0h0))) node _T_2134 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2135 = cvt(_T_2134) node _T_2136 = and(_T_2135, asSInt(UInt<13>(0h1000))) node _T_2137 = asSInt(_T_2136) node _T_2138 = eq(_T_2137, asSInt(UInt<1>(0h0))) node _T_2139 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2140 = cvt(_T_2139) node _T_2141 = and(_T_2140, asSInt(UInt<27>(0h4000000))) node _T_2142 = asSInt(_T_2141) node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0))) node _T_2144 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2145 = cvt(_T_2144) node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000))) node _T_2147 = asSInt(_T_2146) node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0))) node _T_2149 = or(_T_2113, _T_2118) node _T_2150 = or(_T_2149, _T_2123) node _T_2151 = or(_T_2150, _T_2128) node _T_2152 = or(_T_2151, _T_2133) node _T_2153 = or(_T_2152, _T_2138) node _T_2154 = or(_T_2153, _T_2143) node _T_2155 = or(_T_2154, _T_2148) node _T_2156 = and(_T_2108, _T_2155) node _T_2157 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2158 = or(UInt<1>(0h0), _T_2157) node _T_2159 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2160 = cvt(_T_2159) node _T_2161 = and(_T_2160, asSInt(UInt<17>(0h10000))) node _T_2162 = asSInt(_T_2161) node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0))) node _T_2164 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2165 = cvt(_T_2164) node _T_2166 = and(_T_2165, asSInt(UInt<29>(0h10000000))) node _T_2167 = asSInt(_T_2166) node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = or(_T_2163, _T_2168) node _T_2170 = and(_T_2158, _T_2169) node _T_2171 = or(UInt<1>(0h0), _T_2156) node _T_2172 = or(_T_2171, _T_2170) node _T_2173 = and(_T_2107, _T_2172) node _T_2174 = asUInt(reset) node _T_2175 = eq(_T_2174, UInt<1>(0h0)) when _T_2175 : node _T_2176 = eq(_T_2173, UInt<1>(0h0)) when _T_2176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2173, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_45 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 2, 0) node _T_2177 = shr(io.in.c.bits.source, 3) node _T_2178 = eq(_T_2177, UInt<2>(0h2)) node _T_2179 = leq(UInt<1>(0h0), uncommonBits_45) node _T_2180 = and(_T_2178, _T_2179) node _T_2181 = leq(uncommonBits_45, UInt<3>(0h7)) node _T_2182 = and(_T_2180, _T_2181) node _uncommonBits_T_46 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_2183 = shr(io.in.c.bits.source, 3) node _T_2184 = eq(_T_2183, UInt<1>(0h1)) node _T_2185 = leq(UInt<1>(0h0), uncommonBits_46) node _T_2186 = and(_T_2184, _T_2185) node _T_2187 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_2188 = and(_T_2186, _T_2187) node _uncommonBits_T_47 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_2189 = shr(io.in.c.bits.source, 3) node _T_2190 = eq(_T_2189, UInt<1>(0h0)) node _T_2191 = leq(UInt<1>(0h0), uncommonBits_47) node _T_2192 = and(_T_2190, _T_2191) node _T_2193 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_2194 = and(_T_2192, _T_2193) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2182 connect _WIRE_6[1], _T_2188 connect _WIRE_6[2], _T_2194 node _T_2195 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2196 = mux(_WIRE_6[0], _T_2195, UInt<1>(0h0)) node _T_2197 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2198 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2199 = or(_T_2196, _T_2197) node _T_2200 = or(_T_2199, _T_2198) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2200 node _T_2201 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2202 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2203 = and(_T_2201, _T_2202) node _T_2204 = or(UInt<1>(0h0), _T_2203) node _T_2205 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2206 = cvt(_T_2205) node _T_2207 = and(_T_2206, asSInt(UInt<14>(0h2000))) node _T_2208 = asSInt(_T_2207) node _T_2209 = eq(_T_2208, asSInt(UInt<1>(0h0))) node _T_2210 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2211 = cvt(_T_2210) node _T_2212 = and(_T_2211, asSInt(UInt<13>(0h1000))) node _T_2213 = asSInt(_T_2212) node _T_2214 = eq(_T_2213, asSInt(UInt<1>(0h0))) node _T_2215 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2216 = cvt(_T_2215) node _T_2217 = and(_T_2216, asSInt(UInt<17>(0h10000))) node _T_2218 = asSInt(_T_2217) node _T_2219 = eq(_T_2218, asSInt(UInt<1>(0h0))) node _T_2220 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2221 = cvt(_T_2220) node _T_2222 = and(_T_2221, asSInt(UInt<18>(0h2f000))) node _T_2223 = asSInt(_T_2222) node _T_2224 = eq(_T_2223, asSInt(UInt<1>(0h0))) node _T_2225 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2226 = cvt(_T_2225) node _T_2227 = and(_T_2226, asSInt(UInt<17>(0h10000))) node _T_2228 = asSInt(_T_2227) node _T_2229 = eq(_T_2228, asSInt(UInt<1>(0h0))) node _T_2230 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2231 = cvt(_T_2230) node _T_2232 = and(_T_2231, asSInt(UInt<13>(0h1000))) node _T_2233 = asSInt(_T_2232) node _T_2234 = eq(_T_2233, asSInt(UInt<1>(0h0))) node _T_2235 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2236 = cvt(_T_2235) node _T_2237 = and(_T_2236, asSInt(UInt<17>(0h10000))) node _T_2238 = asSInt(_T_2237) node _T_2239 = eq(_T_2238, asSInt(UInt<1>(0h0))) node _T_2240 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2241 = cvt(_T_2240) node _T_2242 = and(_T_2241, asSInt(UInt<27>(0h4000000))) node _T_2243 = asSInt(_T_2242) node _T_2244 = eq(_T_2243, asSInt(UInt<1>(0h0))) node _T_2245 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2246 = cvt(_T_2245) node _T_2247 = and(_T_2246, asSInt(UInt<13>(0h1000))) node _T_2248 = asSInt(_T_2247) node _T_2249 = eq(_T_2248, asSInt(UInt<1>(0h0))) node _T_2250 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2251 = cvt(_T_2250) node _T_2252 = and(_T_2251, asSInt(UInt<29>(0h10000000))) node _T_2253 = asSInt(_T_2252) node _T_2254 = eq(_T_2253, asSInt(UInt<1>(0h0))) node _T_2255 = or(_T_2209, _T_2214) node _T_2256 = or(_T_2255, _T_2219) node _T_2257 = or(_T_2256, _T_2224) node _T_2258 = or(_T_2257, _T_2229) node _T_2259 = or(_T_2258, _T_2234) node _T_2260 = or(_T_2259, _T_2239) node _T_2261 = or(_T_2260, _T_2244) node _T_2262 = or(_T_2261, _T_2249) node _T_2263 = or(_T_2262, _T_2254) node _T_2264 = and(_T_2204, _T_2263) node _T_2265 = or(UInt<1>(0h0), _T_2264) node _T_2266 = and(_WIRE_7, _T_2265) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_144 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(source_ok_2, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2273 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : node _T_2276 = eq(_T_2273, UInt<1>(0h0)) when _T_2276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2273, UInt<1>(0h1), "") : assert_146 node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2280 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(_T_2280, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2280, UInt<1>(0h1), "") : assert_148 node _T_2284 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2285 = asUInt(reset) node _T_2286 = eq(_T_2285, UInt<1>(0h0)) when _T_2286 : node _T_2287 = eq(_T_2284, UInt<1>(0h0)) when _T_2287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2284, UInt<1>(0h1), "") : assert_149 node _T_2288 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2288 : node _T_2289 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2290 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2291 = and(_T_2289, _T_2290) node _uncommonBits_T_48 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_2292 = shr(io.in.c.bits.source, 3) node _T_2293 = eq(_T_2292, UInt<2>(0h2)) node _T_2294 = leq(UInt<1>(0h0), uncommonBits_48) node _T_2295 = and(_T_2293, _T_2294) node _T_2296 = leq(uncommonBits_48, UInt<3>(0h7)) node _T_2297 = and(_T_2295, _T_2296) node _uncommonBits_T_49 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_2298 = shr(io.in.c.bits.source, 3) node _T_2299 = eq(_T_2298, UInt<1>(0h1)) node _T_2300 = leq(UInt<1>(0h0), uncommonBits_49) node _T_2301 = and(_T_2299, _T_2300) node _T_2302 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_2303 = and(_T_2301, _T_2302) node _uncommonBits_T_50 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 2, 0) node _T_2304 = shr(io.in.c.bits.source, 3) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) node _T_2306 = leq(UInt<1>(0h0), uncommonBits_50) node _T_2307 = and(_T_2305, _T_2306) node _T_2308 = leq(uncommonBits_50, UInt<3>(0h7)) node _T_2309 = and(_T_2307, _T_2308) node _T_2310 = or(_T_2297, _T_2303) node _T_2311 = or(_T_2310, _T_2309) node _T_2312 = and(_T_2291, _T_2311) node _T_2313 = or(UInt<1>(0h0), _T_2312) node _T_2314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2315 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2316 = cvt(_T_2315) node _T_2317 = and(_T_2316, asSInt(UInt<14>(0h2000))) node _T_2318 = asSInt(_T_2317) node _T_2319 = eq(_T_2318, asSInt(UInt<1>(0h0))) node _T_2320 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2321 = cvt(_T_2320) node _T_2322 = and(_T_2321, asSInt(UInt<13>(0h1000))) node _T_2323 = asSInt(_T_2322) node _T_2324 = eq(_T_2323, asSInt(UInt<1>(0h0))) node _T_2325 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2326 = cvt(_T_2325) node _T_2327 = and(_T_2326, asSInt(UInt<17>(0h10000))) node _T_2328 = asSInt(_T_2327) node _T_2329 = eq(_T_2328, asSInt(UInt<1>(0h0))) node _T_2330 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2331 = cvt(_T_2330) node _T_2332 = and(_T_2331, asSInt(UInt<18>(0h2f000))) node _T_2333 = asSInt(_T_2332) node _T_2334 = eq(_T_2333, asSInt(UInt<1>(0h0))) node _T_2335 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2336 = cvt(_T_2335) node _T_2337 = and(_T_2336, asSInt(UInt<17>(0h10000))) node _T_2338 = asSInt(_T_2337) node _T_2339 = eq(_T_2338, asSInt(UInt<1>(0h0))) node _T_2340 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2341 = cvt(_T_2340) node _T_2342 = and(_T_2341, asSInt(UInt<13>(0h1000))) node _T_2343 = asSInt(_T_2342) node _T_2344 = eq(_T_2343, asSInt(UInt<1>(0h0))) node _T_2345 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2346 = cvt(_T_2345) node _T_2347 = and(_T_2346, asSInt(UInt<27>(0h4000000))) node _T_2348 = asSInt(_T_2347) node _T_2349 = eq(_T_2348, asSInt(UInt<1>(0h0))) node _T_2350 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2351 = cvt(_T_2350) node _T_2352 = and(_T_2351, asSInt(UInt<13>(0h1000))) node _T_2353 = asSInt(_T_2352) node _T_2354 = eq(_T_2353, asSInt(UInt<1>(0h0))) node _T_2355 = or(_T_2319, _T_2324) node _T_2356 = or(_T_2355, _T_2329) node _T_2357 = or(_T_2356, _T_2334) node _T_2358 = or(_T_2357, _T_2339) node _T_2359 = or(_T_2358, _T_2344) node _T_2360 = or(_T_2359, _T_2349) node _T_2361 = or(_T_2360, _T_2354) node _T_2362 = and(_T_2314, _T_2361) node _T_2363 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2364 = or(UInt<1>(0h0), _T_2363) node _T_2365 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2366 = cvt(_T_2365) node _T_2367 = and(_T_2366, asSInt(UInt<17>(0h10000))) node _T_2368 = asSInt(_T_2367) node _T_2369 = eq(_T_2368, asSInt(UInt<1>(0h0))) node _T_2370 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2371 = cvt(_T_2370) node _T_2372 = and(_T_2371, asSInt(UInt<29>(0h10000000))) node _T_2373 = asSInt(_T_2372) node _T_2374 = eq(_T_2373, asSInt(UInt<1>(0h0))) node _T_2375 = or(_T_2369, _T_2374) node _T_2376 = and(_T_2364, _T_2375) node _T_2377 = or(UInt<1>(0h0), _T_2362) node _T_2378 = or(_T_2377, _T_2376) node _T_2379 = and(_T_2313, _T_2378) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_51 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 2, 0) node _T_2383 = shr(io.in.c.bits.source, 3) node _T_2384 = eq(_T_2383, UInt<2>(0h2)) node _T_2385 = leq(UInt<1>(0h0), uncommonBits_51) node _T_2386 = and(_T_2384, _T_2385) node _T_2387 = leq(uncommonBits_51, UInt<3>(0h7)) node _T_2388 = and(_T_2386, _T_2387) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0) node _T_2389 = shr(io.in.c.bits.source, 3) node _T_2390 = eq(_T_2389, UInt<1>(0h1)) node _T_2391 = leq(UInt<1>(0h0), uncommonBits_52) node _T_2392 = and(_T_2390, _T_2391) node _T_2393 = leq(uncommonBits_52, UInt<3>(0h7)) node _T_2394 = and(_T_2392, _T_2393) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_2395 = shr(io.in.c.bits.source, 3) node _T_2396 = eq(_T_2395, UInt<1>(0h0)) node _T_2397 = leq(UInt<1>(0h0), uncommonBits_53) node _T_2398 = and(_T_2396, _T_2397) node _T_2399 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_2400 = and(_T_2398, _T_2399) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2388 connect _WIRE_8[1], _T_2394 connect _WIRE_8[2], _T_2400 node _T_2401 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2402 = mux(_WIRE_8[0], _T_2401, UInt<1>(0h0)) node _T_2403 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2404 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2405 = or(_T_2402, _T_2403) node _T_2406 = or(_T_2405, _T_2404) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2406 node _T_2407 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2408 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2409 = and(_T_2407, _T_2408) node _T_2410 = or(UInt<1>(0h0), _T_2409) node _T_2411 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2412 = cvt(_T_2411) node _T_2413 = and(_T_2412, asSInt(UInt<14>(0h2000))) node _T_2414 = asSInt(_T_2413) node _T_2415 = eq(_T_2414, asSInt(UInt<1>(0h0))) node _T_2416 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2417 = cvt(_T_2416) node _T_2418 = and(_T_2417, asSInt(UInt<13>(0h1000))) node _T_2419 = asSInt(_T_2418) node _T_2420 = eq(_T_2419, asSInt(UInt<1>(0h0))) node _T_2421 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2422 = cvt(_T_2421) node _T_2423 = and(_T_2422, asSInt(UInt<17>(0h10000))) node _T_2424 = asSInt(_T_2423) node _T_2425 = eq(_T_2424, asSInt(UInt<1>(0h0))) node _T_2426 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2427 = cvt(_T_2426) node _T_2428 = and(_T_2427, asSInt(UInt<18>(0h2f000))) node _T_2429 = asSInt(_T_2428) node _T_2430 = eq(_T_2429, asSInt(UInt<1>(0h0))) node _T_2431 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2432 = cvt(_T_2431) node _T_2433 = and(_T_2432, asSInt(UInt<17>(0h10000))) node _T_2434 = asSInt(_T_2433) node _T_2435 = eq(_T_2434, asSInt(UInt<1>(0h0))) node _T_2436 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2437 = cvt(_T_2436) node _T_2438 = and(_T_2437, asSInt(UInt<13>(0h1000))) node _T_2439 = asSInt(_T_2438) node _T_2440 = eq(_T_2439, asSInt(UInt<1>(0h0))) node _T_2441 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2442 = cvt(_T_2441) node _T_2443 = and(_T_2442, asSInt(UInt<17>(0h10000))) node _T_2444 = asSInt(_T_2443) node _T_2445 = eq(_T_2444, asSInt(UInt<1>(0h0))) node _T_2446 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2447 = cvt(_T_2446) node _T_2448 = and(_T_2447, asSInt(UInt<27>(0h4000000))) node _T_2449 = asSInt(_T_2448) node _T_2450 = eq(_T_2449, asSInt(UInt<1>(0h0))) node _T_2451 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2452 = cvt(_T_2451) node _T_2453 = and(_T_2452, asSInt(UInt<13>(0h1000))) node _T_2454 = asSInt(_T_2453) node _T_2455 = eq(_T_2454, asSInt(UInt<1>(0h0))) node _T_2456 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2457 = cvt(_T_2456) node _T_2458 = and(_T_2457, asSInt(UInt<29>(0h10000000))) node _T_2459 = asSInt(_T_2458) node _T_2460 = eq(_T_2459, asSInt(UInt<1>(0h0))) node _T_2461 = or(_T_2415, _T_2420) node _T_2462 = or(_T_2461, _T_2425) node _T_2463 = or(_T_2462, _T_2430) node _T_2464 = or(_T_2463, _T_2435) node _T_2465 = or(_T_2464, _T_2440) node _T_2466 = or(_T_2465, _T_2445) node _T_2467 = or(_T_2466, _T_2450) node _T_2468 = or(_T_2467, _T_2455) node _T_2469 = or(_T_2468, _T_2460) node _T_2470 = and(_T_2410, _T_2469) node _T_2471 = or(UInt<1>(0h0), _T_2470) node _T_2472 = and(_WIRE_9, _T_2471) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_151 node _T_2476 = asUInt(reset) node _T_2477 = eq(_T_2476, UInt<1>(0h0)) when _T_2477 : node _T_2478 = eq(source_ok_2, UInt<1>(0h0)) when _T_2478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2479 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2480 = asUInt(reset) node _T_2481 = eq(_T_2480, UInt<1>(0h0)) when _T_2481 : node _T_2482 = eq(_T_2479, UInt<1>(0h0)) when _T_2482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2479, UInt<1>(0h1), "") : assert_153 node _T_2483 = asUInt(reset) node _T_2484 = eq(_T_2483, UInt<1>(0h0)) when _T_2484 : node _T_2485 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2486 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2487 = asUInt(reset) node _T_2488 = eq(_T_2487, UInt<1>(0h0)) when _T_2488 : node _T_2489 = eq(_T_2486, UInt<1>(0h0)) when _T_2489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2486, UInt<1>(0h1), "") : assert_155 node _T_2490 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2490 : node _T_2491 = asUInt(reset) node _T_2492 = eq(_T_2491, UInt<1>(0h0)) when _T_2492 : node _T_2493 = eq(address_ok_1, UInt<1>(0h0)) when _T_2493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2494 = asUInt(reset) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) when _T_2495 : node _T_2496 = eq(source_ok_2, UInt<1>(0h0)) when _T_2496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2500 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2501 = asUInt(reset) node _T_2502 = eq(_T_2501, UInt<1>(0h0)) when _T_2502 : node _T_2503 = eq(_T_2500, UInt<1>(0h0)) when _T_2503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2500, UInt<1>(0h1), "") : assert_159 node _T_2504 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_160 node _T_2508 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2508 : node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(address_ok_1, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(source_ok_2, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2515 = asUInt(reset) node _T_2516 = eq(_T_2515, UInt<1>(0h0)) when _T_2516 : node _T_2517 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2518 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_164 node _T_2522 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2522 : node _T_2523 = asUInt(reset) node _T_2524 = eq(_T_2523, UInt<1>(0h0)) when _T_2524 : node _T_2525 = eq(address_ok_1, UInt<1>(0h0)) when _T_2525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2526 = asUInt(reset) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) when _T_2527 : node _T_2528 = eq(source_ok_2, UInt<1>(0h0)) when _T_2528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2529 = asUInt(reset) node _T_2530 = eq(_T_2529, UInt<1>(0h0)) when _T_2530 : node _T_2531 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2532 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_168 node _T_2536 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2537 = asUInt(reset) node _T_2538 = eq(_T_2537, UInt<1>(0h0)) when _T_2538 : node _T_2539 = eq(_T_2536, UInt<1>(0h0)) when _T_2539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2536, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2540 = asUInt(reset) node _T_2541 = eq(_T_2540, UInt<1>(0h0)) when _T_2541 : node _T_2542 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2543 = eq(a_first, UInt<1>(0h0)) node _T_2544 = and(io.in.a.valid, _T_2543) when _T_2544 : node _T_2545 = eq(io.in.a.bits.opcode, opcode) node _T_2546 = asUInt(reset) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) when _T_2547 : node _T_2548 = eq(_T_2545, UInt<1>(0h0)) when _T_2548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2545, UInt<1>(0h1), "") : assert_171 node _T_2549 = eq(io.in.a.bits.param, param) node _T_2550 = asUInt(reset) node _T_2551 = eq(_T_2550, UInt<1>(0h0)) when _T_2551 : node _T_2552 = eq(_T_2549, UInt<1>(0h0)) when _T_2552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2549, UInt<1>(0h1), "") : assert_172 node _T_2553 = eq(io.in.a.bits.size, size) node _T_2554 = asUInt(reset) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) when _T_2555 : node _T_2556 = eq(_T_2553, UInt<1>(0h0)) when _T_2556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2553, UInt<1>(0h1), "") : assert_173 node _T_2557 = eq(io.in.a.bits.source, source) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_174 node _T_2561 = eq(io.in.a.bits.address, address) node _T_2562 = asUInt(reset) node _T_2563 = eq(_T_2562, UInt<1>(0h0)) when _T_2563 : node _T_2564 = eq(_T_2561, UInt<1>(0h0)) when _T_2564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2561, UInt<1>(0h1), "") : assert_175 node _T_2565 = and(io.in.a.ready, io.in.a.valid) node _T_2566 = and(_T_2565, a_first) when _T_2566 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2567 = eq(d_first, UInt<1>(0h0)) node _T_2568 = and(io.in.d.valid, _T_2567) when _T_2568 : node _T_2569 = eq(io.in.d.bits.opcode, opcode_1) node _T_2570 = asUInt(reset) node _T_2571 = eq(_T_2570, UInt<1>(0h0)) when _T_2571 : node _T_2572 = eq(_T_2569, UInt<1>(0h0)) when _T_2572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2569, UInt<1>(0h1), "") : assert_176 node _T_2573 = eq(io.in.d.bits.param, param_1) node _T_2574 = asUInt(reset) node _T_2575 = eq(_T_2574, UInt<1>(0h0)) when _T_2575 : node _T_2576 = eq(_T_2573, UInt<1>(0h0)) when _T_2576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2573, UInt<1>(0h1), "") : assert_177 node _T_2577 = eq(io.in.d.bits.size, size_1) node _T_2578 = asUInt(reset) node _T_2579 = eq(_T_2578, UInt<1>(0h0)) when _T_2579 : node _T_2580 = eq(_T_2577, UInt<1>(0h0)) when _T_2580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2577, UInt<1>(0h1), "") : assert_178 node _T_2581 = eq(io.in.d.bits.source, source_1) node _T_2582 = asUInt(reset) node _T_2583 = eq(_T_2582, UInt<1>(0h0)) when _T_2583 : node _T_2584 = eq(_T_2581, UInt<1>(0h0)) when _T_2584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2581, UInt<1>(0h1), "") : assert_179 node _T_2585 = eq(io.in.d.bits.sink, sink) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_180 node _T_2589 = eq(io.in.d.bits.denied, denied) node _T_2590 = asUInt(reset) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) when _T_2591 : node _T_2592 = eq(_T_2589, UInt<1>(0h0)) when _T_2592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2589, UInt<1>(0h1), "") : assert_181 node _T_2593 = and(io.in.d.ready, io.in.d.valid) node _T_2594 = and(_T_2593, d_first) when _T_2594 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2595 = eq(b_first, UInt<1>(0h0)) node _T_2596 = and(io.in.b.valid, _T_2595) when _T_2596 : node _T_2597 = eq(io.in.b.bits.opcode, opcode_2) node _T_2598 = asUInt(reset) node _T_2599 = eq(_T_2598, UInt<1>(0h0)) when _T_2599 : node _T_2600 = eq(_T_2597, UInt<1>(0h0)) when _T_2600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2597, UInt<1>(0h1), "") : assert_182 node _T_2601 = eq(io.in.b.bits.param, param_2) node _T_2602 = asUInt(reset) node _T_2603 = eq(_T_2602, UInt<1>(0h0)) when _T_2603 : node _T_2604 = eq(_T_2601, UInt<1>(0h0)) when _T_2604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2601, UInt<1>(0h1), "") : assert_183 node _T_2605 = eq(io.in.b.bits.size, size_2) node _T_2606 = asUInt(reset) node _T_2607 = eq(_T_2606, UInt<1>(0h0)) when _T_2607 : node _T_2608 = eq(_T_2605, UInt<1>(0h0)) when _T_2608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2605, UInt<1>(0h1), "") : assert_184 node _T_2609 = eq(io.in.b.bits.source, source_2) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_185 node _T_2613 = eq(io.in.b.bits.address, address_1) node _T_2614 = asUInt(reset) node _T_2615 = eq(_T_2614, UInt<1>(0h0)) when _T_2615 : node _T_2616 = eq(_T_2613, UInt<1>(0h0)) when _T_2616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2613, UInt<1>(0h1), "") : assert_186 node _T_2617 = and(io.in.b.ready, io.in.b.valid) node _T_2618 = and(_T_2617, b_first) when _T_2618 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2619 = eq(c_first, UInt<1>(0h0)) node _T_2620 = and(io.in.c.valid, _T_2619) when _T_2620 : node _T_2621 = eq(io.in.c.bits.opcode, opcode_3) node _T_2622 = asUInt(reset) node _T_2623 = eq(_T_2622, UInt<1>(0h0)) when _T_2623 : node _T_2624 = eq(_T_2621, UInt<1>(0h0)) when _T_2624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2621, UInt<1>(0h1), "") : assert_187 node _T_2625 = eq(io.in.c.bits.param, param_3) node _T_2626 = asUInt(reset) node _T_2627 = eq(_T_2626, UInt<1>(0h0)) when _T_2627 : node _T_2628 = eq(_T_2625, UInt<1>(0h0)) when _T_2628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2625, UInt<1>(0h1), "") : assert_188 node _T_2629 = eq(io.in.c.bits.size, size_3) node _T_2630 = asUInt(reset) node _T_2631 = eq(_T_2630, UInt<1>(0h0)) when _T_2631 : node _T_2632 = eq(_T_2629, UInt<1>(0h0)) when _T_2632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2629, UInt<1>(0h1), "") : assert_189 node _T_2633 = eq(io.in.c.bits.source, source_3) node _T_2634 = asUInt(reset) node _T_2635 = eq(_T_2634, UInt<1>(0h0)) when _T_2635 : node _T_2636 = eq(_T_2633, UInt<1>(0h0)) when _T_2636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2633, UInt<1>(0h1), "") : assert_190 node _T_2637 = eq(io.in.c.bits.address, address_2) node _T_2638 = asUInt(reset) node _T_2639 = eq(_T_2638, UInt<1>(0h0)) when _T_2639 : node _T_2640 = eq(_T_2637, UInt<1>(0h0)) when _T_2640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2637, UInt<1>(0h1), "") : assert_191 node _T_2641 = and(io.in.c.ready, io.in.c.valid) node _T_2642 = and(_T_2641, c_first) when _T_2642 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<24>, clock, reset, UInt<24>(0h0) regreset inflight_opcodes : UInt<96>, clock, reset, UInt<96>(0h0) regreset inflight_sizes : UInt<192>, clock, reset, UInt<192>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<24> connect a_set, UInt<24>(0h0) wire a_set_wo_ready : UInt<24> connect a_set_wo_ready, UInt<24>(0h0) wire a_opcodes_set : UInt<96> connect a_opcodes_set, UInt<96>(0h0) wire a_sizes_set : UInt<192> connect a_sizes_set, UInt<192>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2643 = and(io.in.a.valid, a_first_1) node _T_2644 = and(_T_2643, UInt<1>(0h1)) when _T_2644 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2645 = and(io.in.a.ready, io.in.a.valid) node _T_2646 = and(_T_2645, a_first_1) node _T_2647 = and(_T_2646, UInt<1>(0h1)) when _T_2647 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2648 = dshr(inflight, io.in.a.bits.source) node _T_2649 = bits(_T_2648, 0, 0) node _T_2650 = eq(_T_2649, UInt<1>(0h0)) node _T_2651 = asUInt(reset) node _T_2652 = eq(_T_2651, UInt<1>(0h0)) when _T_2652 : node _T_2653 = eq(_T_2650, UInt<1>(0h0)) when _T_2653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2650, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<24> connect d_clr, UInt<24>(0h0) wire d_clr_wo_ready : UInt<24> connect d_clr_wo_ready, UInt<24>(0h0) wire d_opcodes_clr : UInt<96> connect d_opcodes_clr, UInt<96>(0h0) wire d_sizes_clr : UInt<192> connect d_sizes_clr, UInt<192>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2654 = and(io.in.d.valid, d_first_1) node _T_2655 = and(_T_2654, UInt<1>(0h1)) node _T_2656 = eq(d_release_ack, UInt<1>(0h0)) node _T_2657 = and(_T_2655, _T_2656) when _T_2657 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2658 = and(io.in.d.ready, io.in.d.valid) node _T_2659 = and(_T_2658, d_first_1) node _T_2660 = and(_T_2659, UInt<1>(0h1)) node _T_2661 = eq(d_release_ack, UInt<1>(0h0)) node _T_2662 = and(_T_2660, _T_2661) when _T_2662 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2663 = and(io.in.d.valid, d_first_1) node _T_2664 = and(_T_2663, UInt<1>(0h1)) node _T_2665 = eq(d_release_ack, UInt<1>(0h0)) node _T_2666 = and(_T_2664, _T_2665) when _T_2666 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2667 = dshr(inflight, io.in.d.bits.source) node _T_2668 = bits(_T_2667, 0, 0) node _T_2669 = or(_T_2668, same_cycle_resp) node _T_2670 = asUInt(reset) node _T_2671 = eq(_T_2670, UInt<1>(0h0)) when _T_2671 : node _T_2672 = eq(_T_2669, UInt<1>(0h0)) when _T_2672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2669, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2673 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2674 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2675 = or(_T_2673, _T_2674) node _T_2676 = asUInt(reset) node _T_2677 = eq(_T_2676, UInt<1>(0h0)) when _T_2677 : node _T_2678 = eq(_T_2675, UInt<1>(0h0)) when _T_2678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2675, UInt<1>(0h1), "") : assert_194 node _T_2679 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2680 = asUInt(reset) node _T_2681 = eq(_T_2680, UInt<1>(0h0)) when _T_2681 : node _T_2682 = eq(_T_2679, UInt<1>(0h0)) when _T_2682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2679, UInt<1>(0h1), "") : assert_195 else : node _T_2683 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2684 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2685 = or(_T_2683, _T_2684) node _T_2686 = asUInt(reset) node _T_2687 = eq(_T_2686, UInt<1>(0h0)) when _T_2687 : node _T_2688 = eq(_T_2685, UInt<1>(0h0)) when _T_2688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2685, UInt<1>(0h1), "") : assert_196 node _T_2689 = eq(io.in.d.bits.size, a_size_lookup) node _T_2690 = asUInt(reset) node _T_2691 = eq(_T_2690, UInt<1>(0h0)) when _T_2691 : node _T_2692 = eq(_T_2689, UInt<1>(0h0)) when _T_2692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2689, UInt<1>(0h1), "") : assert_197 node _T_2693 = and(io.in.d.valid, d_first_1) node _T_2694 = and(_T_2693, a_first_1) node _T_2695 = and(_T_2694, io.in.a.valid) node _T_2696 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2697 = and(_T_2695, _T_2696) node _T_2698 = eq(d_release_ack, UInt<1>(0h0)) node _T_2699 = and(_T_2697, _T_2698) when _T_2699 : node _T_2700 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2701 = or(_T_2700, io.in.a.ready) node _T_2702 = asUInt(reset) node _T_2703 = eq(_T_2702, UInt<1>(0h0)) when _T_2703 : node _T_2704 = eq(_T_2701, UInt<1>(0h0)) when _T_2704 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2701, UInt<1>(0h1), "") : assert_198 node _T_2705 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2706 = orr(a_set_wo_ready) node _T_2707 = eq(_T_2706, UInt<1>(0h0)) node _T_2708 = or(_T_2705, _T_2707) node _T_2709 = asUInt(reset) node _T_2710 = eq(_T_2709, UInt<1>(0h0)) when _T_2710 : node _T_2711 = eq(_T_2708, UInt<1>(0h0)) when _T_2711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2708, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_2712 = orr(inflight) node _T_2713 = eq(_T_2712, UInt<1>(0h0)) node _T_2714 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2715 = or(_T_2713, _T_2714) node _T_2716 = lt(watchdog, plusarg_reader.out) node _T_2717 = or(_T_2715, _T_2716) node _T_2718 = asUInt(reset) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) when _T_2719 : node _T_2720 = eq(_T_2717, UInt<1>(0h0)) when _T_2720 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2717, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2721 = and(io.in.a.ready, io.in.a.valid) node _T_2722 = and(io.in.d.ready, io.in.d.valid) node _T_2723 = or(_T_2721, _T_2722) when _T_2723 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<24>, clock, reset, UInt<24>(0h0) regreset inflight_opcodes_1 : UInt<96>, clock, reset, UInt<96>(0h0) regreset inflight_sizes_1 : UInt<192>, clock, reset, UInt<192>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<24> connect c_set, UInt<24>(0h0) wire c_set_wo_ready : UInt<24> connect c_set_wo_ready, UInt<24>(0h0) wire c_opcodes_set : UInt<96> connect c_opcodes_set, UInt<96>(0h0) wire c_sizes_set : UInt<192> connect c_sizes_set, UInt<192>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2724 = and(io.in.c.valid, c_first_1) node _T_2725 = bits(io.in.c.bits.opcode, 2, 2) node _T_2726 = bits(io.in.c.bits.opcode, 1, 1) node _T_2727 = and(_T_2725, _T_2726) node _T_2728 = and(_T_2724, _T_2727) when _T_2728 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2729 = and(io.in.c.ready, io.in.c.valid) node _T_2730 = and(_T_2729, c_first_1) node _T_2731 = bits(io.in.c.bits.opcode, 2, 2) node _T_2732 = bits(io.in.c.bits.opcode, 1, 1) node _T_2733 = and(_T_2731, _T_2732) node _T_2734 = and(_T_2730, _T_2733) when _T_2734 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2735 = dshr(inflight_1, io.in.c.bits.source) node _T_2736 = bits(_T_2735, 0, 0) node _T_2737 = eq(_T_2736, UInt<1>(0h0)) node _T_2738 = asUInt(reset) node _T_2739 = eq(_T_2738, UInt<1>(0h0)) when _T_2739 : node _T_2740 = eq(_T_2737, UInt<1>(0h0)) when _T_2740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2737, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<24> connect d_clr_1, UInt<24>(0h0) wire d_clr_wo_ready_1 : UInt<24> connect d_clr_wo_ready_1, UInt<24>(0h0) wire d_opcodes_clr_1 : UInt<96> connect d_opcodes_clr_1, UInt<96>(0h0) wire d_sizes_clr_1 : UInt<192> connect d_sizes_clr_1, UInt<192>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2741 = and(io.in.d.valid, d_first_2) node _T_2742 = and(_T_2741, UInt<1>(0h1)) node _T_2743 = and(_T_2742, d_release_ack_1) when _T_2743 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2744 = and(io.in.d.ready, io.in.d.valid) node _T_2745 = and(_T_2744, d_first_2) node _T_2746 = and(_T_2745, UInt<1>(0h1)) node _T_2747 = and(_T_2746, d_release_ack_1) when _T_2747 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2748 = and(io.in.d.valid, d_first_2) node _T_2749 = and(_T_2748, UInt<1>(0h1)) node _T_2750 = and(_T_2749, d_release_ack_1) when _T_2750 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2751 = dshr(inflight_1, io.in.d.bits.source) node _T_2752 = bits(_T_2751, 0, 0) node _T_2753 = or(_T_2752, same_cycle_resp_1) node _T_2754 = asUInt(reset) node _T_2755 = eq(_T_2754, UInt<1>(0h0)) when _T_2755 : node _T_2756 = eq(_T_2753, UInt<1>(0h0)) when _T_2756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2753, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2757 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2758 = asUInt(reset) node _T_2759 = eq(_T_2758, UInt<1>(0h0)) when _T_2759 : node _T_2760 = eq(_T_2757, UInt<1>(0h0)) when _T_2760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2757, UInt<1>(0h1), "") : assert_203 else : node _T_2761 = eq(io.in.d.bits.size, c_size_lookup) node _T_2762 = asUInt(reset) node _T_2763 = eq(_T_2762, UInt<1>(0h0)) when _T_2763 : node _T_2764 = eq(_T_2761, UInt<1>(0h0)) when _T_2764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2761, UInt<1>(0h1), "") : assert_204 node _T_2765 = and(io.in.d.valid, d_first_2) node _T_2766 = and(_T_2765, c_first_1) node _T_2767 = and(_T_2766, io.in.c.valid) node _T_2768 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2769 = and(_T_2767, _T_2768) node _T_2770 = and(_T_2769, d_release_ack_1) node _T_2771 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2772 = and(_T_2770, _T_2771) when _T_2772 : node _T_2773 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2774 = or(_T_2773, io.in.c.ready) node _T_2775 = asUInt(reset) node _T_2776 = eq(_T_2775, UInt<1>(0h0)) when _T_2776 : node _T_2777 = eq(_T_2774, UInt<1>(0h0)) when _T_2777 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2774, UInt<1>(0h1), "") : assert_205 node _T_2778 = orr(c_set_wo_ready) when _T_2778 : node _T_2779 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2780 = asUInt(reset) node _T_2781 = eq(_T_2780, UInt<1>(0h0)) when _T_2781 : node _T_2782 = eq(_T_2779, UInt<1>(0h0)) when _T_2782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2779, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_2783 = orr(inflight_1) node _T_2784 = eq(_T_2783, UInt<1>(0h0)) node _T_2785 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2786 = or(_T_2784, _T_2785) node _T_2787 = lt(watchdog_1, plusarg_reader_1.out) node _T_2788 = or(_T_2786, _T_2787) node _T_2789 = asUInt(reset) node _T_2790 = eq(_T_2789, UInt<1>(0h0)) when _T_2790 : node _T_2791 = eq(_T_2788, UInt<1>(0h0)) when _T_2791 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2788, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2792 = and(io.in.c.ready, io.in.c.valid) node _T_2793 = and(io.in.d.ready, io.in.d.valid) node _T_2794 = or(_T_2792, _T_2793) when _T_2794 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2795 = and(io.in.d.ready, io.in.d.valid) node _T_2796 = and(_T_2795, d_first_3) node _T_2797 = bits(io.in.d.bits.opcode, 2, 2) node _T_2798 = bits(io.in.d.bits.opcode, 1, 1) node _T_2799 = eq(_T_2798, UInt<1>(0h0)) node _T_2800 = and(_T_2797, _T_2799) node _T_2801 = and(_T_2796, _T_2800) when _T_2801 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2802 = dshr(inflight_2, io.in.d.bits.sink) node _T_2803 = bits(_T_2802, 0, 0) node _T_2804 = eq(_T_2803, UInt<1>(0h0)) node _T_2805 = asUInt(reset) node _T_2806 = eq(_T_2805, UInt<1>(0h0)) when _T_2806 : node _T_2807 = eq(_T_2804, UInt<1>(0h0)) when _T_2807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2804, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2808 = and(io.in.e.ready, io.in.e.valid) node _T_2809 = and(_T_2808, UInt<1>(0h1)) node _T_2810 = and(_T_2809, UInt<1>(0h1)) when _T_2810 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2811 = or(d_set, inflight_2) node _T_2812 = dshr(_T_2811, io.in.e.bits.sink) node _T_2813 = bits(_T_2812, 0, 0) node _T_2814 = asUInt(reset) node _T_2815 = eq(_T_2814, UInt<1>(0h0)) when _T_2815 : node _T_2816 = eq(_T_2813, UInt<1>(0h0)) when _T_2816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2813, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [4:0] io_in_b_bits_source = 5'h10; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _uncommonBits_T_34 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _uncommonBits_T_35 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _legal_source_uncommonBits_T = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _legal_source_uncommonBits_T_1 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _legal_source_uncommonBits_T_2 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _legal_source_T_18 = 5'h10; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_21 = 5'h10; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_22 = 5'h10; // @[Mux.scala:30:73] wire [4:0] _legal_source_WIRE_1 = 5'h10; // @[Mux.scala:30:73] wire [4:0] _uncommonBits_T_36 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _uncommonBits_T_37 = 5'h10; // @[Parameters.scala:52:29] wire [4:0] _uncommonBits_T_38 = 5'h10; // @[Parameters.scala:52:29] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_7 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_9 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_11 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_13 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_15 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_17 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_20 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_33 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_34 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_35 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_2 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_36 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_37 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_38 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] _legal_source_T_19 = 4'h0; // @[Mux.scala:30:73] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _legal_source_T = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _legal_source_T_6 = 2'h2; // @[Parameters.scala:54:10] wire [1:0] _legal_source_T_12 = 2'h2; // @[Parameters.scala:54:10] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_8 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_39 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_40 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_41 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_42 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_43 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_44 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_45 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_46 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_47 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_48 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_49 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_50 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_51 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire _source_ok_T_18 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_18 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_21 = _uncommonBits_T_21[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_19 = io_in_d_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_25 = io_in_d_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_31 = io_in_d_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire _source_ok_T_20 = _source_ok_T_19 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_37 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_38 = io_in_c_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_c_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_50 = io_in_c_bits_source_0[4:3]; // @[Monitor.scala:36:7] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_0 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = _source_ok_T_44 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = _source_ok_T_50 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire _source_ok_T_56 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_56 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_45 = _uncommonBits_T_45[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_50 = _uncommonBits_T_50[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_51 = _uncommonBits_T_51[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2721 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2721; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2721; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2795 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2795; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2795; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2795; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2795; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2792 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2792; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2792; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [4:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [23:0] inflight; // @[Monitor.scala:614:27] reg [95:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [191:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [23:0] a_set; // @[Monitor.scala:626:34] wire [23:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [95:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [191:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [95:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [95:0] _a_opcode_lookup_T_6 = {92'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [95:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[95:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [191:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [191:0] _a_size_lookup_T_6 = {184'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [191:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[191:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_20 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[23:0] : 24'h0; // @[OneHot.scala:58:35] wire _T_2647 = _T_2721 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2647 ? _a_set_T[23:0] : 24'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2647 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2647 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2647 ? _a_opcodes_set_T_1[95:0] : 96'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2647 ? _a_sizes_set_T_1[191:0] : 192'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [23:0] d_clr; // @[Monitor.scala:664:34] wire [23:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [95:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [191:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2693 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_22 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2693 & ~d_release_ack ? _d_clr_wo_ready_T[23:0] : 24'h0; // @[OneHot.scala:58:35] wire _T_2662 = _T_2795 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2662 ? _d_clr_T[23:0] : 24'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2662 ? _d_opcodes_clr_T_5[95:0] : 96'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2662 ? _d_sizes_clr_T_5[191:0] : 192'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [23:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [23:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [23:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [95:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [95:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [95:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [191:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [191:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [191:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [23:0] inflight_1; // @[Monitor.scala:726:35] reg [95:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [191:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [23:0] c_set; // @[Monitor.scala:738:34] wire [23:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [95:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [191:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [95:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [95:0] _c_opcode_lookup_T_6 = {92'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [95:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[95:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [191:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [191:0] _c_size_lookup_T_6 = {184'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [191:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[191:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [31:0] _GEN_23 = 32'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [31:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[23:0] : 24'h0; // @[OneHot.scala:58:35] wire _T_2734 = _T_2792 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2734 ? _c_set_T[23:0] : 24'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2734 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2734 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [7:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [258:0] _c_opcodes_set_T_1 = {255'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2734 ? _c_opcodes_set_T_1[95:0] : 96'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [7:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [259:0] _c_sizes_set_T_1 = {255'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2734 ? _c_sizes_set_T_1[191:0] : 192'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [23:0] d_clr_1; // @[Monitor.scala:774:34] wire [23:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [95:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [191:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2765 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2765 & d_release_ack_1 ? _d_clr_wo_ready_T_1[23:0] : 24'h0; // @[OneHot.scala:58:35] wire _T_2747 = _T_2795 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2747 ? _d_clr_T_1[23:0] : 24'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2747 ? _d_opcodes_clr_T_11[95:0] : 96'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2747 ? _d_sizes_clr_T_11[191:0] : 192'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [23:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [23:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [23:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [95:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [95:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [95:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [191:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [191:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [191:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2801 = _T_2795 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2801 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module ScratchpadBank_3 : input clock : Clock input reset : Reset output io : { flip read : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<12>, fromDMA : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}}, flip write : { en : UInt<1>, addr : UInt<12>, mask : UInt<1>[16], data : UInt<128>}} smem mem : UInt<8>[16] [4096] node singleport_busy_with_write = and(UInt<1>(0h1), io.write.en) when io.write.en : wire _WIRE : UInt<8>[16] wire _WIRE_1 : UInt<128> connect _WIRE_1, io.write.data node _T = bits(_WIRE_1, 7, 0) connect _WIRE[0], _T node _T_1 = bits(_WIRE_1, 15, 8) connect _WIRE[1], _T_1 node _T_2 = bits(_WIRE_1, 23, 16) connect _WIRE[2], _T_2 node _T_3 = bits(_WIRE_1, 31, 24) connect _WIRE[3], _T_3 node _T_4 = bits(_WIRE_1, 39, 32) connect _WIRE[4], _T_4 node _T_5 = bits(_WIRE_1, 47, 40) connect _WIRE[5], _T_5 node _T_6 = bits(_WIRE_1, 55, 48) connect _WIRE[6], _T_6 node _T_7 = bits(_WIRE_1, 63, 56) connect _WIRE[7], _T_7 node _T_8 = bits(_WIRE_1, 71, 64) connect _WIRE[8], _T_8 node _T_9 = bits(_WIRE_1, 79, 72) connect _WIRE[9], _T_9 node _T_10 = bits(_WIRE_1, 87, 80) connect _WIRE[10], _T_10 node _T_11 = bits(_WIRE_1, 95, 88) connect _WIRE[11], _T_11 node _T_12 = bits(_WIRE_1, 103, 96) connect _WIRE[12], _T_12 node _T_13 = bits(_WIRE_1, 111, 104) connect _WIRE[13], _T_13 node _T_14 = bits(_WIRE_1, 119, 112) connect _WIRE[14], _T_14 node _T_15 = bits(_WIRE_1, 127, 120) connect _WIRE[15], _T_15 write mport MPORT = mem[io.write.addr], clock when io.write.mask[0] : connect MPORT[0], _WIRE[0] when io.write.mask[1] : connect MPORT[1], _WIRE[1] when io.write.mask[2] : connect MPORT[2], _WIRE[2] when io.write.mask[3] : connect MPORT[3], _WIRE[3] when io.write.mask[4] : connect MPORT[4], _WIRE[4] when io.write.mask[5] : connect MPORT[5], _WIRE[5] when io.write.mask[6] : connect MPORT[6], _WIRE[6] when io.write.mask[7] : connect MPORT[7], _WIRE[7] when io.write.mask[8] : connect MPORT[8], _WIRE[8] when io.write.mask[9] : connect MPORT[9], _WIRE[9] when io.write.mask[10] : connect MPORT[10], _WIRE[10] when io.write.mask[11] : connect MPORT[11], _WIRE[11] when io.write.mask[12] : connect MPORT[12], _WIRE[12] when io.write.mask[13] : connect MPORT[13], _WIRE[13] when io.write.mask[14] : connect MPORT[14], _WIRE[14] when io.write.mask[15] : connect MPORT[15], _WIRE[15] node ren = and(io.read.req.ready, io.read.req.valid) node _rdata_T = and(ren, io.write.en) node _rdata_T_1 = eq(_rdata_T, UInt<1>(0h0)) node _rdata_T_2 = asUInt(reset) node _rdata_T_3 = eq(_rdata_T_2, UInt<1>(0h0)) when _rdata_T_3 : node _rdata_T_4 = eq(_rdata_T_1, UInt<1>(0h0)) when _rdata_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scratchpad.scala:151 assert(!(ren && io.write.en))\n") : rdata_printf assert(clock, _rdata_T_1, UInt<1>(0h1), "") : rdata_assert node _rdata_T_5 = eq(io.write.en, UInt<1>(0h0)) node _rdata_T_6 = and(ren, _rdata_T_5) wire _rdata_WIRE : UInt<12> invalidate _rdata_WIRE when _rdata_T_6 : connect _rdata_WIRE, io.read.req.bits.addr read mport rdata_MPORT = mem[_rdata_WIRE], clock node rdata_lo_lo_lo = cat(rdata_MPORT[1], rdata_MPORT[0]) node rdata_lo_lo_hi = cat(rdata_MPORT[3], rdata_MPORT[2]) node rdata_lo_lo = cat(rdata_lo_lo_hi, rdata_lo_lo_lo) node rdata_lo_hi_lo = cat(rdata_MPORT[5], rdata_MPORT[4]) node rdata_lo_hi_hi = cat(rdata_MPORT[7], rdata_MPORT[6]) node rdata_lo_hi = cat(rdata_lo_hi_hi, rdata_lo_hi_lo) node rdata_lo = cat(rdata_lo_hi, rdata_lo_lo) node rdata_hi_lo_lo = cat(rdata_MPORT[9], rdata_MPORT[8]) node rdata_hi_lo_hi = cat(rdata_MPORT[11], rdata_MPORT[10]) node rdata_hi_lo = cat(rdata_hi_lo_hi, rdata_hi_lo_lo) node rdata_hi_hi_lo = cat(rdata_MPORT[13], rdata_MPORT[12]) node rdata_hi_hi_hi = cat(rdata_MPORT[15], rdata_MPORT[14]) node rdata_hi_hi = cat(rdata_hi_hi_hi, rdata_hi_hi_lo) node rdata_hi = cat(rdata_hi_hi, rdata_hi_lo) node rdata = cat(rdata_hi, rdata_lo) inst q of Queue1_ScratchpadReadResp_3 connect q.clock, clock connect q.reset, reset reg q_io_enq_valid_REG : UInt<1>, clock connect q_io_enq_valid_REG, ren connect q.io.enq.valid, q_io_enq_valid_REG connect q.io.enq.bits.data, rdata reg q_io_enq_bits_fromDMA_REG : UInt<1>, clock connect q_io_enq_bits_fromDMA_REG, io.read.req.bits.fromDMA connect q.io.enq.bits.fromDMA, q_io_enq_bits_fromDMA_REG node _q_will_be_empty_T = and(q.io.enq.ready, q.io.enq.valid) node _q_will_be_empty_T_1 = add(q.io.count, _q_will_be_empty_T) node _q_will_be_empty_T_2 = and(q.io.deq.ready, q.io.deq.valid) node _q_will_be_empty_T_3 = sub(_q_will_be_empty_T_1, _q_will_be_empty_T_2) node _q_will_be_empty_T_4 = tail(_q_will_be_empty_T_3, 1) node q_will_be_empty = eq(_q_will_be_empty_T_4, UInt<1>(0h0)) node _io_read_req_ready_T = eq(singleport_busy_with_write, UInt<1>(0h0)) node _io_read_req_ready_T_1 = and(q_will_be_empty, _io_read_req_ready_T) connect io.read.req.ready, _io_read_req_ready_T_1 connect io.read.resp.bits, q.io.deq.bits connect io.read.resp.valid, q.io.deq.valid connect q.io.deq.ready, io.read.resp.ready
module ScratchpadBank_3( // @[Scratchpad.scala:97:7] input clock, // @[Scratchpad.scala:97:7] input reset, // @[Scratchpad.scala:97:7] output io_read_req_ready, // @[Scratchpad.scala:104:14] input io_read_req_valid, // @[Scratchpad.scala:104:14] input [11:0] io_read_req_bits_addr, // @[Scratchpad.scala:104:14] input io_read_req_bits_fromDMA, // @[Scratchpad.scala:104:14] input io_read_resp_ready, // @[Scratchpad.scala:104:14] output io_read_resp_valid, // @[Scratchpad.scala:104:14] output [127:0] io_read_resp_bits_data, // @[Scratchpad.scala:104:14] output io_read_resp_bits_fromDMA, // @[Scratchpad.scala:104:14] input io_write_en, // @[Scratchpad.scala:104:14] input [11:0] io_write_addr, // @[Scratchpad.scala:104:14] input io_write_mask_0, // @[Scratchpad.scala:104:14] input io_write_mask_1, // @[Scratchpad.scala:104:14] input io_write_mask_2, // @[Scratchpad.scala:104:14] input io_write_mask_3, // @[Scratchpad.scala:104:14] input io_write_mask_4, // @[Scratchpad.scala:104:14] input io_write_mask_5, // @[Scratchpad.scala:104:14] input io_write_mask_6, // @[Scratchpad.scala:104:14] input io_write_mask_7, // @[Scratchpad.scala:104:14] input io_write_mask_8, // @[Scratchpad.scala:104:14] input io_write_mask_9, // @[Scratchpad.scala:104:14] input io_write_mask_10, // @[Scratchpad.scala:104:14] input io_write_mask_11, // @[Scratchpad.scala:104:14] input io_write_mask_12, // @[Scratchpad.scala:104:14] input io_write_mask_13, // @[Scratchpad.scala:104:14] input io_write_mask_14, // @[Scratchpad.scala:104:14] input io_write_mask_15, // @[Scratchpad.scala:104:14] input [127:0] io_write_data // @[Scratchpad.scala:104:14] ); wire _q_io_enq_ready; // @[Scratchpad.scala:160:17] wire _q_io_deq_valid; // @[Scratchpad.scala:160:17] wire _q_io_count; // @[Scratchpad.scala:160:17] wire [127:0] _mem_RW0_rdata; // @[Scratchpad.scala:132:26] wire io_read_req_valid_0 = io_read_req_valid; // @[Scratchpad.scala:97:7] wire [11:0] io_read_req_bits_addr_0 = io_read_req_bits_addr; // @[Scratchpad.scala:97:7] wire io_read_req_bits_fromDMA_0 = io_read_req_bits_fromDMA; // @[Scratchpad.scala:97:7] wire io_read_resp_ready_0 = io_read_resp_ready; // @[Scratchpad.scala:97:7] wire io_write_en_0 = io_write_en; // @[Scratchpad.scala:97:7] wire [11:0] io_write_addr_0 = io_write_addr; // @[Scratchpad.scala:97:7] wire io_write_mask_0_0 = io_write_mask_0; // @[Scratchpad.scala:97:7] wire io_write_mask_1_0 = io_write_mask_1; // @[Scratchpad.scala:97:7] wire io_write_mask_2_0 = io_write_mask_2; // @[Scratchpad.scala:97:7] wire io_write_mask_3_0 = io_write_mask_3; // @[Scratchpad.scala:97:7] wire io_write_mask_4_0 = io_write_mask_4; // @[Scratchpad.scala:97:7] wire io_write_mask_5_0 = io_write_mask_5; // @[Scratchpad.scala:97:7] wire io_write_mask_6_0 = io_write_mask_6; // @[Scratchpad.scala:97:7] wire io_write_mask_7_0 = io_write_mask_7; // @[Scratchpad.scala:97:7] wire io_write_mask_8_0 = io_write_mask_8; // @[Scratchpad.scala:97:7] wire io_write_mask_9_0 = io_write_mask_9; // @[Scratchpad.scala:97:7] wire io_write_mask_10_0 = io_write_mask_10; // @[Scratchpad.scala:97:7] wire io_write_mask_11_0 = io_write_mask_11; // @[Scratchpad.scala:97:7] wire io_write_mask_12_0 = io_write_mask_12; // @[Scratchpad.scala:97:7] wire io_write_mask_13_0 = io_write_mask_13; // @[Scratchpad.scala:97:7] wire io_write_mask_14_0 = io_write_mask_14; // @[Scratchpad.scala:97:7] wire io_write_mask_15_0 = io_write_mask_15; // @[Scratchpad.scala:97:7] wire [127:0] io_write_data_0 = io_write_data; // @[Scratchpad.scala:97:7] wire _rdata_T_2 = reset; // @[Scratchpad.scala:151:11] wire _io_read_req_ready_T_1; // @[Scratchpad.scala:166:40] wire [11:0] _rdata_WIRE = io_read_req_bits_addr_0; // @[Scratchpad.scala:97:7, :133:53] wire singleport_busy_with_write = io_write_en_0; // @[Scratchpad.scala:97:7, :139:52] wire io_read_req_ready_0; // @[Scratchpad.scala:97:7] wire [127:0] io_read_resp_bits_data_0; // @[Scratchpad.scala:97:7] wire io_read_resp_bits_fromDMA_0; // @[Scratchpad.scala:97:7] wire io_read_resp_valid_0; // @[Scratchpad.scala:97:7] wire _rdata_T_6; // @[Scratchpad.scala:152:21] wire ren = io_read_req_ready_0 & io_read_req_valid_0; // @[Decoupled.scala:51:35] wire _rdata_T = ren & io_write_en_0; // @[Decoupled.scala:51:35] wire _rdata_T_1 = ~_rdata_T; // @[Scratchpad.scala:151:{12,18}] wire _rdata_T_3 = ~_rdata_T_2; // @[Scratchpad.scala:151:11] wire _rdata_T_4 = ~_rdata_T_1; // @[Scratchpad.scala:151:{11,12}]
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s7k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s7k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s7k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s7k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_18 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [6:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [6:0] in_xbar__addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar__requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar__requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] in_xbar_requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56] wire [6:0] in_xbar__beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar__beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar__portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar_portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] in_xbar__portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar_portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire in_ready; // @[RegisterRouter.scala:73:18] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34] wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52] wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35] bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_pbus_out_i1_o2_a29d64s7k1z3u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s7k1z3u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] TLBuffer_a29d64s7k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (bus_xingOut_a_ready), .auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (bus_xingOut_d_valid), .auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode), .auto_in_d_bits_param (bus_xingOut_d_bits_param), .auto_in_d_bits_size (bus_xingOut_d_bits_size), .auto_in_d_bits_source (bus_xingOut_d_bits_source), .auto_in_d_bits_sink (bus_xingOut_d_bits_sink), .auto_in_d_bits_denied (bus_xingOut_d_bits_denied), .auto_in_d_bits_data (bus_xingOut_d_bits_data), .auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt), .auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_out_a_valid (in_xbar_auto_anon_in_a_valid), .auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param), .auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size), .auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source), .auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (in_xbar_auto_anon_in_d_ready), .auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9] .auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9] .auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_a_valid (nodeIn_a_valid), .auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param), .auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size), .auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source), .auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address), .auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask), .auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data), .auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_fragmenter_anon_out_d_ready (nodeIn_d_ready), .auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0), .auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0), .auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0), .auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0), .auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0), .auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0), .auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0), .auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0), .auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0), .auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0), .auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLMonitor_18 monitor ( // @[Nodes.scala:27:25] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BTB : input clock : Clock input reset : Reset output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<39>}}, resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}, flip btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}, flip bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, flip bht_advance : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}, flip ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<39>}}, ras_head : { valid : UInt<1>, bits : UInt<39>}, flip flush : UInt<1>} reg idxs : UInt<13>[28], clock reg idxPages : UInt<3>[28], clock reg tgts : UInt<13>[28], clock reg tgtPages : UInt<3>[28], clock reg pages : UInt<25>[6], clock regreset pageValid : UInt<6>, clock, reset, UInt<6>(0h0) node _pagesMasked_T = bits(pageValid, 0, 0) node _pagesMasked_T_1 = bits(pageValid, 1, 1) node _pagesMasked_T_2 = bits(pageValid, 2, 2) node _pagesMasked_T_3 = bits(pageValid, 3, 3) node _pagesMasked_T_4 = bits(pageValid, 4, 4) node _pagesMasked_T_5 = bits(pageValid, 5, 5) node pagesMasked_0 = mux(_pagesMasked_T, pages[0], UInt<1>(0h0)) node pagesMasked_1 = mux(_pagesMasked_T_1, pages[1], UInt<1>(0h0)) node pagesMasked_2 = mux(_pagesMasked_T_2, pages[2], UInt<1>(0h0)) node pagesMasked_3 = mux(_pagesMasked_T_3, pages[3], UInt<1>(0h0)) node pagesMasked_4 = mux(_pagesMasked_T_4, pages[4], UInt<1>(0h0)) node pagesMasked_5 = mux(_pagesMasked_T_5, pages[5], UInt<1>(0h0)) regreset isValid : UInt<28>, clock, reset, UInt<28>(0h0) reg cfiType : UInt<2>[28], clock reg brIdx : UInt<1>[28], clock regreset r_btb_update_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect r_btb_update_pipe_v, io.btb_update.valid reg r_btb_update_pipe_b : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}, clock when io.btb_update.valid : connect r_btb_update_pipe_b, io.btb_update.bits wire r_btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}} connect r_btb_update.valid, r_btb_update_pipe_v connect r_btb_update.bits, r_btb_update_pipe_b node pageHit_p = shr(io.req.bits.addr, 14) node _pageHit_T = eq(pages[0], pageHit_p) node _pageHit_T_1 = eq(pages[1], pageHit_p) node _pageHit_T_2 = eq(pages[2], pageHit_p) node _pageHit_T_3 = eq(pages[3], pageHit_p) node _pageHit_T_4 = eq(pages[4], pageHit_p) node _pageHit_T_5 = eq(pages[5], pageHit_p) node pageHit_lo_hi = cat(_pageHit_T_2, _pageHit_T_1) node pageHit_lo = cat(pageHit_lo_hi, _pageHit_T) node pageHit_hi_hi = cat(_pageHit_T_5, _pageHit_T_4) node pageHit_hi = cat(pageHit_hi_hi, _pageHit_T_3) node _pageHit_T_6 = cat(pageHit_hi, pageHit_lo) node pageHit = and(pageValid, _pageHit_T_6) node idxHit_idx = bits(io.req.bits.addr, 13, 1) node _idxHit_T = eq(idxs[0], idxHit_idx) node _idxHit_T_1 = eq(idxs[1], idxHit_idx) node _idxHit_T_2 = eq(idxs[2], idxHit_idx) node _idxHit_T_3 = eq(idxs[3], idxHit_idx) node _idxHit_T_4 = eq(idxs[4], idxHit_idx) node _idxHit_T_5 = eq(idxs[5], idxHit_idx) node _idxHit_T_6 = eq(idxs[6], idxHit_idx) node _idxHit_T_7 = eq(idxs[7], idxHit_idx) node _idxHit_T_8 = eq(idxs[8], idxHit_idx) node _idxHit_T_9 = eq(idxs[9], idxHit_idx) node _idxHit_T_10 = eq(idxs[10], idxHit_idx) node _idxHit_T_11 = eq(idxs[11], idxHit_idx) node _idxHit_T_12 = eq(idxs[12], idxHit_idx) node _idxHit_T_13 = eq(idxs[13], idxHit_idx) node _idxHit_T_14 = eq(idxs[14], idxHit_idx) node _idxHit_T_15 = eq(idxs[15], idxHit_idx) node _idxHit_T_16 = eq(idxs[16], idxHit_idx) node _idxHit_T_17 = eq(idxs[17], idxHit_idx) node _idxHit_T_18 = eq(idxs[18], idxHit_idx) node _idxHit_T_19 = eq(idxs[19], idxHit_idx) node _idxHit_T_20 = eq(idxs[20], idxHit_idx) node _idxHit_T_21 = eq(idxs[21], idxHit_idx) node _idxHit_T_22 = eq(idxs[22], idxHit_idx) node _idxHit_T_23 = eq(idxs[23], idxHit_idx) node _idxHit_T_24 = eq(idxs[24], idxHit_idx) node _idxHit_T_25 = eq(idxs[25], idxHit_idx) node _idxHit_T_26 = eq(idxs[26], idxHit_idx) node _idxHit_T_27 = eq(idxs[27], idxHit_idx) node idxHit_lo_lo_lo_hi = cat(_idxHit_T_2, _idxHit_T_1) node idxHit_lo_lo_lo = cat(idxHit_lo_lo_lo_hi, _idxHit_T) node idxHit_lo_lo_hi_lo = cat(_idxHit_T_4, _idxHit_T_3) node idxHit_lo_lo_hi_hi = cat(_idxHit_T_6, _idxHit_T_5) node idxHit_lo_lo_hi = cat(idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo) node idxHit_lo_lo = cat(idxHit_lo_lo_hi, idxHit_lo_lo_lo) node idxHit_lo_hi_lo_hi = cat(_idxHit_T_9, _idxHit_T_8) node idxHit_lo_hi_lo = cat(idxHit_lo_hi_lo_hi, _idxHit_T_7) node idxHit_lo_hi_hi_lo = cat(_idxHit_T_11, _idxHit_T_10) node idxHit_lo_hi_hi_hi = cat(_idxHit_T_13, _idxHit_T_12) node idxHit_lo_hi_hi = cat(idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo) node idxHit_lo_hi = cat(idxHit_lo_hi_hi, idxHit_lo_hi_lo) node idxHit_lo = cat(idxHit_lo_hi, idxHit_lo_lo) node idxHit_hi_lo_lo_hi = cat(_idxHit_T_16, _idxHit_T_15) node idxHit_hi_lo_lo = cat(idxHit_hi_lo_lo_hi, _idxHit_T_14) node idxHit_hi_lo_hi_lo = cat(_idxHit_T_18, _idxHit_T_17) node idxHit_hi_lo_hi_hi = cat(_idxHit_T_20, _idxHit_T_19) node idxHit_hi_lo_hi = cat(idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo) node idxHit_hi_lo = cat(idxHit_hi_lo_hi, idxHit_hi_lo_lo) node idxHit_hi_hi_lo_hi = cat(_idxHit_T_23, _idxHit_T_22) node idxHit_hi_hi_lo = cat(idxHit_hi_hi_lo_hi, _idxHit_T_21) node idxHit_hi_hi_hi_lo = cat(_idxHit_T_25, _idxHit_T_24) node idxHit_hi_hi_hi_hi = cat(_idxHit_T_27, _idxHit_T_26) node idxHit_hi_hi_hi = cat(idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo) node idxHit_hi_hi = cat(idxHit_hi_hi_hi, idxHit_hi_hi_lo) node idxHit_hi = cat(idxHit_hi_hi, idxHit_hi_lo) node _idxHit_T_28 = cat(idxHit_hi, idxHit_lo) node idxHit = and(_idxHit_T_28, isValid) node updatePageHit_p = shr(r_btb_update.bits.pc, 14) node _updatePageHit_T = eq(pages[0], updatePageHit_p) node _updatePageHit_T_1 = eq(pages[1], updatePageHit_p) node _updatePageHit_T_2 = eq(pages[2], updatePageHit_p) node _updatePageHit_T_3 = eq(pages[3], updatePageHit_p) node _updatePageHit_T_4 = eq(pages[4], updatePageHit_p) node _updatePageHit_T_5 = eq(pages[5], updatePageHit_p) node updatePageHit_lo_hi = cat(_updatePageHit_T_2, _updatePageHit_T_1) node updatePageHit_lo = cat(updatePageHit_lo_hi, _updatePageHit_T) node updatePageHit_hi_hi = cat(_updatePageHit_T_5, _updatePageHit_T_4) node updatePageHit_hi = cat(updatePageHit_hi_hi, _updatePageHit_T_3) node _updatePageHit_T_6 = cat(updatePageHit_hi, updatePageHit_lo) node updatePageHit = and(pageValid, _updatePageHit_T_6) node updateHit = lt(r_btb_update.bits.prediction.entry, UInt<5>(0h1c)) node useUpdatePageHit = orr(updatePageHit) node usePageHit = orr(pageHit) node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>(0h0)) regreset nextPageRepl : UInt<3>, clock, reset, UInt<3>(0h0) node _idxPageRepl_T = bits(pageHit, 4, 0) node _idxPageRepl_T_1 = bits(pageHit, 5, 5) node _idxPageRepl_T_2 = cat(_idxPageRepl_T, _idxPageRepl_T_1) node _idxPageRepl_T_3 = dshl(UInt<1>(0h1), nextPageRepl) node _idxPageRepl_T_4 = mux(usePageHit, UInt<1>(0h0), _idxPageRepl_T_3) node idxPageRepl = or(_idxPageRepl_T_2, _idxPageRepl_T_4) node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) node idxPageUpdate_hi = bits(idxPageUpdateOH, 7, 4) node idxPageUpdate_lo = bits(idxPageUpdateOH, 3, 0) node _idxPageUpdate_T = orr(idxPageUpdate_hi) node _idxPageUpdate_T_1 = or(idxPageUpdate_hi, idxPageUpdate_lo) node idxPageUpdate_hi_1 = bits(_idxPageUpdate_T_1, 3, 2) node idxPageUpdate_lo_1 = bits(_idxPageUpdate_T_1, 1, 0) node _idxPageUpdate_T_2 = orr(idxPageUpdate_hi_1) node _idxPageUpdate_T_3 = or(idxPageUpdate_hi_1, idxPageUpdate_lo_1) node _idxPageUpdate_T_4 = bits(_idxPageUpdate_T_3, 1, 1) node _idxPageUpdate_T_5 = cat(_idxPageUpdate_T_2, _idxPageUpdate_T_4) node idxPageUpdate = cat(_idxPageUpdate_T, _idxPageUpdate_T_5) node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>(0h0)) node _samePage_T = shr(r_btb_update.bits.pc, 14) node _samePage_T_1 = shr(io.req.bits.addr, 14) node samePage = eq(_samePage_T, _samePage_T_1) node _doTgtPageRepl_T = eq(samePage, UInt<1>(0h0)) node _doTgtPageRepl_T_1 = eq(usePageHit, UInt<1>(0h0)) node doTgtPageRepl = and(_doTgtPageRepl_T, _doTgtPageRepl_T_1) node _tgtPageRepl_T = bits(idxPageUpdateOH, 4, 0) node _tgtPageRepl_T_1 = bits(idxPageUpdateOH, 5, 5) node _tgtPageRepl_T_2 = cat(_tgtPageRepl_T, _tgtPageRepl_T_1) node tgtPageRepl = mux(samePage, idxPageUpdateOH, _tgtPageRepl_T_2) node _tgtPageUpdate_T = mux(usePageHit, UInt<1>(0h0), tgtPageRepl) node _tgtPageUpdate_T_1 = or(pageHit, _tgtPageUpdate_T) node tgtPageUpdate_hi = bits(_tgtPageUpdate_T_1, 7, 4) node tgtPageUpdate_lo = bits(_tgtPageUpdate_T_1, 3, 0) node _tgtPageUpdate_T_2 = orr(tgtPageUpdate_hi) node _tgtPageUpdate_T_3 = or(tgtPageUpdate_hi, tgtPageUpdate_lo) node tgtPageUpdate_hi_1 = bits(_tgtPageUpdate_T_3, 3, 2) node tgtPageUpdate_lo_1 = bits(_tgtPageUpdate_T_3, 1, 0) node _tgtPageUpdate_T_4 = orr(tgtPageUpdate_hi_1) node _tgtPageUpdate_T_5 = or(tgtPageUpdate_hi_1, tgtPageUpdate_lo_1) node _tgtPageUpdate_T_6 = bits(_tgtPageUpdate_T_5, 1, 1) node _tgtPageUpdate_T_7 = cat(_tgtPageUpdate_T_4, _tgtPageUpdate_T_6) node tgtPageUpdate = cat(_tgtPageUpdate_T_2, _tgtPageUpdate_T_7) node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>(0h0)) node _T = or(doIdxPageRepl, doTgtPageRepl) node _T_1 = and(r_btb_update.valid, _T) when _T_1 : node both = and(doIdxPageRepl, doTgtPageRepl) node _next_T = mux(both, UInt<2>(0h2), UInt<1>(0h1)) node _next_T_1 = add(nextPageRepl, _next_T) node next = tail(_next_T_1, 1) node _nextPageRepl_T = geq(next, UInt<3>(0h6)) node _nextPageRepl_T_1 = bits(next, 0, 0) node _nextPageRepl_T_2 = mux(_nextPageRepl_T, _nextPageRepl_T_1, next) connect nextPageRepl, _nextPageRepl_T_2 regreset state_reg : UInt<27>, clock, reset, UInt<27>(0h0) node waddr_left_subtree_older = bits(state_reg, 26, 26) node waddr_left_subtree_state = bits(state_reg, 25, 15) node waddr_right_subtree_state = bits(state_reg, 14, 0) node waddr_left_subtree_older_1 = bits(waddr_left_subtree_state, 10, 10) node waddr_left_subtree_state_1 = bits(waddr_left_subtree_state, 9, 7) node waddr_right_subtree_state_1 = bits(waddr_left_subtree_state, 6, 0) node waddr_left_subtree_older_2 = bits(waddr_left_subtree_state_1, 2, 2) node waddr_left_subtree_state_2 = bits(waddr_left_subtree_state_1, 1, 1) node waddr_right_subtree_state_2 = bits(waddr_left_subtree_state_1, 0, 0) node _waddr_T = bits(waddr_left_subtree_state_2, 0, 0) node _waddr_T_1 = bits(waddr_right_subtree_state_2, 0, 0) node _waddr_T_2 = mux(waddr_left_subtree_older_2, _waddr_T, _waddr_T_1) node _waddr_T_3 = cat(waddr_left_subtree_older_2, _waddr_T_2) node waddr_left_subtree_older_3 = bits(waddr_right_subtree_state_1, 6, 6) node waddr_left_subtree_state_3 = bits(waddr_right_subtree_state_1, 5, 3) node waddr_right_subtree_state_3 = bits(waddr_right_subtree_state_1, 2, 0) node waddr_left_subtree_older_4 = bits(waddr_left_subtree_state_3, 2, 2) node waddr_left_subtree_state_4 = bits(waddr_left_subtree_state_3, 1, 1) node waddr_right_subtree_state_4 = bits(waddr_left_subtree_state_3, 0, 0) node _waddr_T_4 = bits(waddr_left_subtree_state_4, 0, 0) node _waddr_T_5 = bits(waddr_right_subtree_state_4, 0, 0) node _waddr_T_6 = mux(waddr_left_subtree_older_4, _waddr_T_4, _waddr_T_5) node _waddr_T_7 = cat(waddr_left_subtree_older_4, _waddr_T_6) node waddr_left_subtree_older_5 = bits(waddr_right_subtree_state_3, 2, 2) node waddr_left_subtree_state_5 = bits(waddr_right_subtree_state_3, 1, 1) node waddr_right_subtree_state_5 = bits(waddr_right_subtree_state_3, 0, 0) node _waddr_T_8 = bits(waddr_left_subtree_state_5, 0, 0) node _waddr_T_9 = bits(waddr_right_subtree_state_5, 0, 0) node _waddr_T_10 = mux(waddr_left_subtree_older_5, _waddr_T_8, _waddr_T_9) node _waddr_T_11 = cat(waddr_left_subtree_older_5, _waddr_T_10) node _waddr_T_12 = mux(waddr_left_subtree_older_3, _waddr_T_7, _waddr_T_11) node _waddr_T_13 = cat(waddr_left_subtree_older_3, _waddr_T_12) node _waddr_T_14 = mux(waddr_left_subtree_older_1, _waddr_T_3, _waddr_T_13) node _waddr_T_15 = cat(waddr_left_subtree_older_1, _waddr_T_14) node waddr_left_subtree_older_6 = bits(waddr_right_subtree_state, 14, 14) node waddr_left_subtree_state_6 = bits(waddr_right_subtree_state, 13, 7) node waddr_right_subtree_state_6 = bits(waddr_right_subtree_state, 6, 0) node waddr_left_subtree_older_7 = bits(waddr_left_subtree_state_6, 6, 6) node waddr_left_subtree_state_7 = bits(waddr_left_subtree_state_6, 5, 3) node waddr_right_subtree_state_7 = bits(waddr_left_subtree_state_6, 2, 0) node waddr_left_subtree_older_8 = bits(waddr_left_subtree_state_7, 2, 2) node waddr_left_subtree_state_8 = bits(waddr_left_subtree_state_7, 1, 1) node waddr_right_subtree_state_8 = bits(waddr_left_subtree_state_7, 0, 0) node _waddr_T_16 = bits(waddr_left_subtree_state_8, 0, 0) node _waddr_T_17 = bits(waddr_right_subtree_state_8, 0, 0) node _waddr_T_18 = mux(waddr_left_subtree_older_8, _waddr_T_16, _waddr_T_17) node _waddr_T_19 = cat(waddr_left_subtree_older_8, _waddr_T_18) node waddr_left_subtree_older_9 = bits(waddr_right_subtree_state_7, 2, 2) node waddr_left_subtree_state_9 = bits(waddr_right_subtree_state_7, 1, 1) node waddr_right_subtree_state_9 = bits(waddr_right_subtree_state_7, 0, 0) node _waddr_T_20 = bits(waddr_left_subtree_state_9, 0, 0) node _waddr_T_21 = bits(waddr_right_subtree_state_9, 0, 0) node _waddr_T_22 = mux(waddr_left_subtree_older_9, _waddr_T_20, _waddr_T_21) node _waddr_T_23 = cat(waddr_left_subtree_older_9, _waddr_T_22) node _waddr_T_24 = mux(waddr_left_subtree_older_7, _waddr_T_19, _waddr_T_23) node _waddr_T_25 = cat(waddr_left_subtree_older_7, _waddr_T_24) node waddr_left_subtree_older_10 = bits(waddr_right_subtree_state_6, 6, 6) node waddr_left_subtree_state_10 = bits(waddr_right_subtree_state_6, 5, 3) node waddr_right_subtree_state_10 = bits(waddr_right_subtree_state_6, 2, 0) node waddr_left_subtree_older_11 = bits(waddr_left_subtree_state_10, 2, 2) node waddr_left_subtree_state_11 = bits(waddr_left_subtree_state_10, 1, 1) node waddr_right_subtree_state_11 = bits(waddr_left_subtree_state_10, 0, 0) node _waddr_T_26 = bits(waddr_left_subtree_state_11, 0, 0) node _waddr_T_27 = bits(waddr_right_subtree_state_11, 0, 0) node _waddr_T_28 = mux(waddr_left_subtree_older_11, _waddr_T_26, _waddr_T_27) node _waddr_T_29 = cat(waddr_left_subtree_older_11, _waddr_T_28) node waddr_left_subtree_older_12 = bits(waddr_right_subtree_state_10, 2, 2) node waddr_left_subtree_state_12 = bits(waddr_right_subtree_state_10, 1, 1) node waddr_right_subtree_state_12 = bits(waddr_right_subtree_state_10, 0, 0) node _waddr_T_30 = bits(waddr_left_subtree_state_12, 0, 0) node _waddr_T_31 = bits(waddr_right_subtree_state_12, 0, 0) node _waddr_T_32 = mux(waddr_left_subtree_older_12, _waddr_T_30, _waddr_T_31) node _waddr_T_33 = cat(waddr_left_subtree_older_12, _waddr_T_32) node _waddr_T_34 = mux(waddr_left_subtree_older_10, _waddr_T_29, _waddr_T_33) node _waddr_T_35 = cat(waddr_left_subtree_older_10, _waddr_T_34) node _waddr_T_36 = mux(waddr_left_subtree_older_6, _waddr_T_25, _waddr_T_35) node _waddr_T_37 = cat(waddr_left_subtree_older_6, _waddr_T_36) node _waddr_T_38 = mux(waddr_left_subtree_older, _waddr_T_15, _waddr_T_37) node _waddr_T_39 = cat(waddr_left_subtree_older, _waddr_T_38) node waddr = mux(updateHit, r_btb_update.bits.prediction.entry, _waddr_T_39) regreset r_resp_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect r_resp_pipe_v, io.resp.valid reg r_resp_pipe_b : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock when io.resp.valid : connect r_resp_pipe_b.bht.value, io.resp.bits.bht.value connect r_resp_pipe_b.bht.history, io.resp.bits.bht.history connect r_resp_pipe_b.entry, io.resp.bits.entry connect r_resp_pipe_b.target, io.resp.bits.target connect r_resp_pipe_b.bridx, io.resp.bits.bridx connect r_resp_pipe_b.mask, io.resp.bits.mask connect r_resp_pipe_b.taken, io.resp.bits.taken connect r_resp_pipe_b.cfiType, io.resp.bits.cfiType wire r_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}} connect r_resp.valid, r_resp_pipe_v connect r_resp.bits, r_resp_pipe_b node _T_2 = and(r_resp.valid, r_resp.bits.taken) node _T_3 = or(_T_2, r_btb_update.valid) when _T_3 : node _T_4 = mux(r_btb_update.valid, waddr, r_resp.bits.entry) node state_reg_touch_way_sized = bits(_T_4, 4, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 4, 4) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 25, 15) node state_reg_right_subtree_state = bits(state_reg, 14, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 3, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 3, 3) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 9, 7) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 6, 0) node _state_reg_T_1 = bits(_state_reg_T, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_1, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_left_subtree_state_1, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_left_subtree_state_1, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = bits(_state_reg_T_2, 0, 0) node _state_reg_T_4 = eq(_state_reg_T_3, UInt<1>(0h0)) node _state_reg_T_5 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_4) node _state_reg_T_6 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_7 = bits(_state_reg_T_6, 0, 0) node _state_reg_T_8 = eq(_state_reg_T_7, UInt<1>(0h0)) node _state_reg_T_9 = mux(state_reg_set_left_older_2, _state_reg_T_8, state_reg_right_subtree_state_2) node state_reg_hi = cat(state_reg_set_left_older_2, _state_reg_T_5) node _state_reg_T_10 = cat(state_reg_hi, _state_reg_T_9) node _state_reg_T_11 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_10) node _state_reg_T_12 = bits(_state_reg_T, 2, 0) node _state_reg_set_left_older_T_3 = bits(_state_reg_T_12, 2, 2) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg_right_subtree_state_1, 5, 3) node state_reg_right_subtree_state_3 = bits(state_reg_right_subtree_state_1, 2, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 1, 0) node _state_reg_set_left_older_T_4 = bits(_state_reg_T_13, 1, 1) node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0)) node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1) node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0) node _state_reg_T_14 = bits(_state_reg_T_13, 0, 0) node _state_reg_T_15 = bits(_state_reg_T_14, 0, 0) node _state_reg_T_16 = eq(_state_reg_T_15, UInt<1>(0h0)) node _state_reg_T_17 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_16) node _state_reg_T_18 = bits(_state_reg_T_13, 0, 0) node _state_reg_T_19 = bits(_state_reg_T_18, 0, 0) node _state_reg_T_20 = eq(_state_reg_T_19, UInt<1>(0h0)) node _state_reg_T_21 = mux(state_reg_set_left_older_4, _state_reg_T_20, state_reg_right_subtree_state_4) node state_reg_hi_1 = cat(state_reg_set_left_older_4, _state_reg_T_17) node _state_reg_T_22 = cat(state_reg_hi_1, _state_reg_T_21) node _state_reg_T_23 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_22) node _state_reg_T_24 = bits(_state_reg_T_12, 1, 0) node _state_reg_set_left_older_T_5 = bits(_state_reg_T_24, 1, 1) node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0)) node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1) node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0) node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_26 = bits(_state_reg_T_25, 0, 0) node _state_reg_T_27 = eq(_state_reg_T_26, UInt<1>(0h0)) node _state_reg_T_28 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_27) node _state_reg_T_29 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_30 = bits(_state_reg_T_29, 0, 0) node _state_reg_T_31 = eq(_state_reg_T_30, UInt<1>(0h0)) node _state_reg_T_32 = mux(state_reg_set_left_older_5, _state_reg_T_31, state_reg_right_subtree_state_5) node state_reg_hi_2 = cat(state_reg_set_left_older_5, _state_reg_T_28) node _state_reg_T_33 = cat(state_reg_hi_2, _state_reg_T_32) node _state_reg_T_34 = mux(state_reg_set_left_older_3, _state_reg_T_33, state_reg_right_subtree_state_3) node state_reg_hi_3 = cat(state_reg_set_left_older_3, _state_reg_T_23) node _state_reg_T_35 = cat(state_reg_hi_3, _state_reg_T_34) node _state_reg_T_36 = mux(state_reg_set_left_older_1, _state_reg_T_35, state_reg_right_subtree_state_1) node state_reg_hi_4 = cat(state_reg_set_left_older_1, _state_reg_T_11) node _state_reg_T_37 = cat(state_reg_hi_4, _state_reg_T_36) node _state_reg_T_38 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_37) node _state_reg_T_39 = bits(state_reg_touch_way_sized, 3, 0) node _state_reg_set_left_older_T_6 = bits(_state_reg_T_39, 3, 3) node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0)) node state_reg_left_subtree_state_6 = bits(state_reg_right_subtree_state, 13, 7) node state_reg_right_subtree_state_6 = bits(state_reg_right_subtree_state, 6, 0) node _state_reg_T_40 = bits(_state_reg_T_39, 2, 0) node _state_reg_set_left_older_T_7 = bits(_state_reg_T_40, 2, 2) node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0)) node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 5, 3) node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 2, 0) node _state_reg_T_41 = bits(_state_reg_T_40, 1, 0) node _state_reg_set_left_older_T_8 = bits(_state_reg_T_41, 1, 1) node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0)) node state_reg_left_subtree_state_8 = bits(state_reg_left_subtree_state_7, 1, 1) node state_reg_right_subtree_state_8 = bits(state_reg_left_subtree_state_7, 0, 0) node _state_reg_T_42 = bits(_state_reg_T_41, 0, 0) node _state_reg_T_43 = bits(_state_reg_T_42, 0, 0) node _state_reg_T_44 = eq(_state_reg_T_43, UInt<1>(0h0)) node _state_reg_T_45 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_44) node _state_reg_T_46 = bits(_state_reg_T_41, 0, 0) node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_48 = eq(_state_reg_T_47, UInt<1>(0h0)) node _state_reg_T_49 = mux(state_reg_set_left_older_8, _state_reg_T_48, state_reg_right_subtree_state_8) node state_reg_hi_5 = cat(state_reg_set_left_older_8, _state_reg_T_45) node _state_reg_T_50 = cat(state_reg_hi_5, _state_reg_T_49) node _state_reg_T_51 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_50) node _state_reg_T_52 = bits(_state_reg_T_40, 1, 0) node _state_reg_set_left_older_T_9 = bits(_state_reg_T_52, 1, 1) node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0)) node state_reg_left_subtree_state_9 = bits(state_reg_right_subtree_state_7, 1, 1) node state_reg_right_subtree_state_9 = bits(state_reg_right_subtree_state_7, 0, 0) node _state_reg_T_53 = bits(_state_reg_T_52, 0, 0) node _state_reg_T_54 = bits(_state_reg_T_53, 0, 0) node _state_reg_T_55 = eq(_state_reg_T_54, UInt<1>(0h0)) node _state_reg_T_56 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_55) node _state_reg_T_57 = bits(_state_reg_T_52, 0, 0) node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_59 = eq(_state_reg_T_58, UInt<1>(0h0)) node _state_reg_T_60 = mux(state_reg_set_left_older_9, _state_reg_T_59, state_reg_right_subtree_state_9) node state_reg_hi_6 = cat(state_reg_set_left_older_9, _state_reg_T_56) node _state_reg_T_61 = cat(state_reg_hi_6, _state_reg_T_60) node _state_reg_T_62 = mux(state_reg_set_left_older_7, _state_reg_T_61, state_reg_right_subtree_state_7) node state_reg_hi_7 = cat(state_reg_set_left_older_7, _state_reg_T_51) node _state_reg_T_63 = cat(state_reg_hi_7, _state_reg_T_62) node _state_reg_T_64 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_63) node _state_reg_T_65 = bits(_state_reg_T_39, 2, 0) node _state_reg_set_left_older_T_10 = bits(_state_reg_T_65, 2, 2) node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0)) node state_reg_left_subtree_state_10 = bits(state_reg_right_subtree_state_6, 5, 3) node state_reg_right_subtree_state_10 = bits(state_reg_right_subtree_state_6, 2, 0) node _state_reg_T_66 = bits(_state_reg_T_65, 1, 0) node _state_reg_set_left_older_T_11 = bits(_state_reg_T_66, 1, 1) node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0)) node state_reg_left_subtree_state_11 = bits(state_reg_left_subtree_state_10, 1, 1) node state_reg_right_subtree_state_11 = bits(state_reg_left_subtree_state_10, 0, 0) node _state_reg_T_67 = bits(_state_reg_T_66, 0, 0) node _state_reg_T_68 = bits(_state_reg_T_67, 0, 0) node _state_reg_T_69 = eq(_state_reg_T_68, UInt<1>(0h0)) node _state_reg_T_70 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_69) node _state_reg_T_71 = bits(_state_reg_T_66, 0, 0) node _state_reg_T_72 = bits(_state_reg_T_71, 0, 0) node _state_reg_T_73 = eq(_state_reg_T_72, UInt<1>(0h0)) node _state_reg_T_74 = mux(state_reg_set_left_older_11, _state_reg_T_73, state_reg_right_subtree_state_11) node state_reg_hi_8 = cat(state_reg_set_left_older_11, _state_reg_T_70) node _state_reg_T_75 = cat(state_reg_hi_8, _state_reg_T_74) node _state_reg_T_76 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_75) node _state_reg_T_77 = bits(_state_reg_T_65, 1, 0) node _state_reg_set_left_older_T_12 = bits(_state_reg_T_77, 1, 1) node state_reg_set_left_older_12 = eq(_state_reg_set_left_older_T_12, UInt<1>(0h0)) node state_reg_left_subtree_state_12 = bits(state_reg_right_subtree_state_10, 1, 1) node state_reg_right_subtree_state_12 = bits(state_reg_right_subtree_state_10, 0, 0) node _state_reg_T_78 = bits(_state_reg_T_77, 0, 0) node _state_reg_T_79 = bits(_state_reg_T_78, 0, 0) node _state_reg_T_80 = eq(_state_reg_T_79, UInt<1>(0h0)) node _state_reg_T_81 = mux(state_reg_set_left_older_12, state_reg_left_subtree_state_12, _state_reg_T_80) node _state_reg_T_82 = bits(_state_reg_T_77, 0, 0) node _state_reg_T_83 = bits(_state_reg_T_82, 0, 0) node _state_reg_T_84 = eq(_state_reg_T_83, UInt<1>(0h0)) node _state_reg_T_85 = mux(state_reg_set_left_older_12, _state_reg_T_84, state_reg_right_subtree_state_12) node state_reg_hi_9 = cat(state_reg_set_left_older_12, _state_reg_T_81) node _state_reg_T_86 = cat(state_reg_hi_9, _state_reg_T_85) node _state_reg_T_87 = mux(state_reg_set_left_older_10, _state_reg_T_86, state_reg_right_subtree_state_10) node state_reg_hi_10 = cat(state_reg_set_left_older_10, _state_reg_T_76) node _state_reg_T_88 = cat(state_reg_hi_10, _state_reg_T_87) node _state_reg_T_89 = mux(state_reg_set_left_older_6, _state_reg_T_88, state_reg_right_subtree_state_6) node state_reg_hi_11 = cat(state_reg_set_left_older_6, _state_reg_T_64) node _state_reg_T_90 = cat(state_reg_hi_11, _state_reg_T_89) node _state_reg_T_91 = mux(state_reg_set_left_older, _state_reg_T_90, state_reg_right_subtree_state) node state_reg_hi_12 = cat(state_reg_set_left_older, _state_reg_T_38) node _state_reg_T_92 = cat(state_reg_hi_12, _state_reg_T_91) connect state_reg, _state_reg_T_92 when r_btb_update.valid : node mask = dshl(UInt<1>(0h1), waddr) node _idxs_T = bits(r_btb_update.bits.pc, 13, 1) connect idxs[waddr], _idxs_T node _tgts_T = bits(io.req.bits.addr, 13, 1) connect tgts[waddr], _tgts_T node _idxPages_T = add(idxPageUpdate, UInt<1>(0h1)) connect idxPages[waddr], _idxPages_T connect tgtPages[waddr], tgtPageUpdate connect cfiType[waddr], r_btb_update.bits.cfiType node _isValid_T = or(isValid, mask) node _isValid_T_1 = not(mask) node _isValid_T_2 = and(isValid, _isValid_T_1) node _isValid_T_3 = mux(r_btb_update.bits.isValid, _isValid_T, _isValid_T_2) connect isValid, _isValid_T_3 node _brIdx_T = shr(r_btb_update.bits.br_pc, 1) connect brIdx[waddr], _brIdx_T node _idxWritesEven_T = bits(idxPageUpdate, 0, 0) node idxWritesEven = eq(_idxWritesEven_T, UInt<1>(0h0)) node _T_5 = mux(idxWritesEven, idxPageReplEn, tgtPageReplEn) node _T_6 = shr(r_btb_update.bits.pc, 14) node _T_7 = shr(io.req.bits.addr, 14) node _T_8 = mux(idxWritesEven, _T_6, _T_7) node _T_9 = bits(_T_5, 0, 0) when _T_9 : connect pages[0], _T_8 node _T_10 = bits(_T_5, 2, 2) when _T_10 : connect pages[2], _T_8 node _T_11 = bits(_T_5, 4, 4) when _T_11 : connect pages[4], _T_8 node _T_12 = mux(idxWritesEven, tgtPageReplEn, idxPageReplEn) node _T_13 = shr(io.req.bits.addr, 14) node _T_14 = shr(r_btb_update.bits.pc, 14) node _T_15 = mux(idxWritesEven, _T_13, _T_14) node _T_16 = bits(_T_12, 1, 1) when _T_16 : connect pages[1], _T_15 node _T_17 = bits(_T_12, 3, 3) when _T_17 : connect pages[3], _T_15 node _T_18 = bits(_T_12, 5, 5) when _T_18 : connect pages[5], _T_15 node _pageValid_T = or(pageValid, tgtPageReplEn) node _pageValid_T_1 = or(_pageValid_T, idxPageReplEn) connect pageValid, _pageValid_T_1 node _io_resp_valid_T = shl(pageHit, 1) node _io_resp_valid_T_1 = bits(idxHit, 0, 0) node _io_resp_valid_T_2 = bits(idxHit, 1, 1) node _io_resp_valid_T_3 = bits(idxHit, 2, 2) node _io_resp_valid_T_4 = bits(idxHit, 3, 3) node _io_resp_valid_T_5 = bits(idxHit, 4, 4) node _io_resp_valid_T_6 = bits(idxHit, 5, 5) node _io_resp_valid_T_7 = bits(idxHit, 6, 6) node _io_resp_valid_T_8 = bits(idxHit, 7, 7) node _io_resp_valid_T_9 = bits(idxHit, 8, 8) node _io_resp_valid_T_10 = bits(idxHit, 9, 9) node _io_resp_valid_T_11 = bits(idxHit, 10, 10) node _io_resp_valid_T_12 = bits(idxHit, 11, 11) node _io_resp_valid_T_13 = bits(idxHit, 12, 12) node _io_resp_valid_T_14 = bits(idxHit, 13, 13) node _io_resp_valid_T_15 = bits(idxHit, 14, 14) node _io_resp_valid_T_16 = bits(idxHit, 15, 15) node _io_resp_valid_T_17 = bits(idxHit, 16, 16) node _io_resp_valid_T_18 = bits(idxHit, 17, 17) node _io_resp_valid_T_19 = bits(idxHit, 18, 18) node _io_resp_valid_T_20 = bits(idxHit, 19, 19) node _io_resp_valid_T_21 = bits(idxHit, 20, 20) node _io_resp_valid_T_22 = bits(idxHit, 21, 21) node _io_resp_valid_T_23 = bits(idxHit, 22, 22) node _io_resp_valid_T_24 = bits(idxHit, 23, 23) node _io_resp_valid_T_25 = bits(idxHit, 24, 24) node _io_resp_valid_T_26 = bits(idxHit, 25, 25) node _io_resp_valid_T_27 = bits(idxHit, 26, 26) node _io_resp_valid_T_28 = bits(idxHit, 27, 27) node _io_resp_valid_T_29 = mux(_io_resp_valid_T_1, idxPages[0], UInt<1>(0h0)) node _io_resp_valid_T_30 = mux(_io_resp_valid_T_2, idxPages[1], UInt<1>(0h0)) node _io_resp_valid_T_31 = mux(_io_resp_valid_T_3, idxPages[2], UInt<1>(0h0)) node _io_resp_valid_T_32 = mux(_io_resp_valid_T_4, idxPages[3], UInt<1>(0h0)) node _io_resp_valid_T_33 = mux(_io_resp_valid_T_5, idxPages[4], UInt<1>(0h0)) node _io_resp_valid_T_34 = mux(_io_resp_valid_T_6, idxPages[5], UInt<1>(0h0)) node _io_resp_valid_T_35 = mux(_io_resp_valid_T_7, idxPages[6], UInt<1>(0h0)) node _io_resp_valid_T_36 = mux(_io_resp_valid_T_8, idxPages[7], UInt<1>(0h0)) node _io_resp_valid_T_37 = mux(_io_resp_valid_T_9, idxPages[8], UInt<1>(0h0)) node _io_resp_valid_T_38 = mux(_io_resp_valid_T_10, idxPages[9], UInt<1>(0h0)) node _io_resp_valid_T_39 = mux(_io_resp_valid_T_11, idxPages[10], UInt<1>(0h0)) node _io_resp_valid_T_40 = mux(_io_resp_valid_T_12, idxPages[11], UInt<1>(0h0)) node _io_resp_valid_T_41 = mux(_io_resp_valid_T_13, idxPages[12], UInt<1>(0h0)) node _io_resp_valid_T_42 = mux(_io_resp_valid_T_14, idxPages[13], UInt<1>(0h0)) node _io_resp_valid_T_43 = mux(_io_resp_valid_T_15, idxPages[14], UInt<1>(0h0)) node _io_resp_valid_T_44 = mux(_io_resp_valid_T_16, idxPages[15], UInt<1>(0h0)) node _io_resp_valid_T_45 = mux(_io_resp_valid_T_17, idxPages[16], UInt<1>(0h0)) node _io_resp_valid_T_46 = mux(_io_resp_valid_T_18, idxPages[17], UInt<1>(0h0)) node _io_resp_valid_T_47 = mux(_io_resp_valid_T_19, idxPages[18], UInt<1>(0h0)) node _io_resp_valid_T_48 = mux(_io_resp_valid_T_20, idxPages[19], UInt<1>(0h0)) node _io_resp_valid_T_49 = mux(_io_resp_valid_T_21, idxPages[20], UInt<1>(0h0)) node _io_resp_valid_T_50 = mux(_io_resp_valid_T_22, idxPages[21], UInt<1>(0h0)) node _io_resp_valid_T_51 = mux(_io_resp_valid_T_23, idxPages[22], UInt<1>(0h0)) node _io_resp_valid_T_52 = mux(_io_resp_valid_T_24, idxPages[23], UInt<1>(0h0)) node _io_resp_valid_T_53 = mux(_io_resp_valid_T_25, idxPages[24], UInt<1>(0h0)) node _io_resp_valid_T_54 = mux(_io_resp_valid_T_26, idxPages[25], UInt<1>(0h0)) node _io_resp_valid_T_55 = mux(_io_resp_valid_T_27, idxPages[26], UInt<1>(0h0)) node _io_resp_valid_T_56 = mux(_io_resp_valid_T_28, idxPages[27], UInt<1>(0h0)) node _io_resp_valid_T_57 = or(_io_resp_valid_T_29, _io_resp_valid_T_30) node _io_resp_valid_T_58 = or(_io_resp_valid_T_57, _io_resp_valid_T_31) node _io_resp_valid_T_59 = or(_io_resp_valid_T_58, _io_resp_valid_T_32) node _io_resp_valid_T_60 = or(_io_resp_valid_T_59, _io_resp_valid_T_33) node _io_resp_valid_T_61 = or(_io_resp_valid_T_60, _io_resp_valid_T_34) node _io_resp_valid_T_62 = or(_io_resp_valid_T_61, _io_resp_valid_T_35) node _io_resp_valid_T_63 = or(_io_resp_valid_T_62, _io_resp_valid_T_36) node _io_resp_valid_T_64 = or(_io_resp_valid_T_63, _io_resp_valid_T_37) node _io_resp_valid_T_65 = or(_io_resp_valid_T_64, _io_resp_valid_T_38) node _io_resp_valid_T_66 = or(_io_resp_valid_T_65, _io_resp_valid_T_39) node _io_resp_valid_T_67 = or(_io_resp_valid_T_66, _io_resp_valid_T_40) node _io_resp_valid_T_68 = or(_io_resp_valid_T_67, _io_resp_valid_T_41) node _io_resp_valid_T_69 = or(_io_resp_valid_T_68, _io_resp_valid_T_42) node _io_resp_valid_T_70 = or(_io_resp_valid_T_69, _io_resp_valid_T_43) node _io_resp_valid_T_71 = or(_io_resp_valid_T_70, _io_resp_valid_T_44) node _io_resp_valid_T_72 = or(_io_resp_valid_T_71, _io_resp_valid_T_45) node _io_resp_valid_T_73 = or(_io_resp_valid_T_72, _io_resp_valid_T_46) node _io_resp_valid_T_74 = or(_io_resp_valid_T_73, _io_resp_valid_T_47) node _io_resp_valid_T_75 = or(_io_resp_valid_T_74, _io_resp_valid_T_48) node _io_resp_valid_T_76 = or(_io_resp_valid_T_75, _io_resp_valid_T_49) node _io_resp_valid_T_77 = or(_io_resp_valid_T_76, _io_resp_valid_T_50) node _io_resp_valid_T_78 = or(_io_resp_valid_T_77, _io_resp_valid_T_51) node _io_resp_valid_T_79 = or(_io_resp_valid_T_78, _io_resp_valid_T_52) node _io_resp_valid_T_80 = or(_io_resp_valid_T_79, _io_resp_valid_T_53) node _io_resp_valid_T_81 = or(_io_resp_valid_T_80, _io_resp_valid_T_54) node _io_resp_valid_T_82 = or(_io_resp_valid_T_81, _io_resp_valid_T_55) node _io_resp_valid_T_83 = or(_io_resp_valid_T_82, _io_resp_valid_T_56) wire _io_resp_valid_WIRE : UInt<3> connect _io_resp_valid_WIRE, _io_resp_valid_T_83 node _io_resp_valid_T_84 = dshr(_io_resp_valid_T, _io_resp_valid_WIRE) node _io_resp_valid_T_85 = bits(_io_resp_valid_T_84, 0, 0) connect io.resp.valid, _io_resp_valid_T_85 connect io.resp.bits.taken, UInt<1>(0h1) node _io_resp_bits_target_T = bits(idxHit, 0, 0) node _io_resp_bits_target_T_1 = bits(idxHit, 1, 1) node _io_resp_bits_target_T_2 = bits(idxHit, 2, 2) node _io_resp_bits_target_T_3 = bits(idxHit, 3, 3) node _io_resp_bits_target_T_4 = bits(idxHit, 4, 4) node _io_resp_bits_target_T_5 = bits(idxHit, 5, 5) node _io_resp_bits_target_T_6 = bits(idxHit, 6, 6) node _io_resp_bits_target_T_7 = bits(idxHit, 7, 7) node _io_resp_bits_target_T_8 = bits(idxHit, 8, 8) node _io_resp_bits_target_T_9 = bits(idxHit, 9, 9) node _io_resp_bits_target_T_10 = bits(idxHit, 10, 10) node _io_resp_bits_target_T_11 = bits(idxHit, 11, 11) node _io_resp_bits_target_T_12 = bits(idxHit, 12, 12) node _io_resp_bits_target_T_13 = bits(idxHit, 13, 13) node _io_resp_bits_target_T_14 = bits(idxHit, 14, 14) node _io_resp_bits_target_T_15 = bits(idxHit, 15, 15) node _io_resp_bits_target_T_16 = bits(idxHit, 16, 16) node _io_resp_bits_target_T_17 = bits(idxHit, 17, 17) node _io_resp_bits_target_T_18 = bits(idxHit, 18, 18) node _io_resp_bits_target_T_19 = bits(idxHit, 19, 19) node _io_resp_bits_target_T_20 = bits(idxHit, 20, 20) node _io_resp_bits_target_T_21 = bits(idxHit, 21, 21) node _io_resp_bits_target_T_22 = bits(idxHit, 22, 22) node _io_resp_bits_target_T_23 = bits(idxHit, 23, 23) node _io_resp_bits_target_T_24 = bits(idxHit, 24, 24) node _io_resp_bits_target_T_25 = bits(idxHit, 25, 25) node _io_resp_bits_target_T_26 = bits(idxHit, 26, 26) node _io_resp_bits_target_T_27 = bits(idxHit, 27, 27) node _io_resp_bits_target_T_28 = mux(_io_resp_bits_target_T, tgtPages[0], UInt<1>(0h0)) node _io_resp_bits_target_T_29 = mux(_io_resp_bits_target_T_1, tgtPages[1], UInt<1>(0h0)) node _io_resp_bits_target_T_30 = mux(_io_resp_bits_target_T_2, tgtPages[2], UInt<1>(0h0)) node _io_resp_bits_target_T_31 = mux(_io_resp_bits_target_T_3, tgtPages[3], UInt<1>(0h0)) node _io_resp_bits_target_T_32 = mux(_io_resp_bits_target_T_4, tgtPages[4], UInt<1>(0h0)) node _io_resp_bits_target_T_33 = mux(_io_resp_bits_target_T_5, tgtPages[5], UInt<1>(0h0)) node _io_resp_bits_target_T_34 = mux(_io_resp_bits_target_T_6, tgtPages[6], UInt<1>(0h0)) node _io_resp_bits_target_T_35 = mux(_io_resp_bits_target_T_7, tgtPages[7], UInt<1>(0h0)) node _io_resp_bits_target_T_36 = mux(_io_resp_bits_target_T_8, tgtPages[8], UInt<1>(0h0)) node _io_resp_bits_target_T_37 = mux(_io_resp_bits_target_T_9, tgtPages[9], UInt<1>(0h0)) node _io_resp_bits_target_T_38 = mux(_io_resp_bits_target_T_10, tgtPages[10], UInt<1>(0h0)) node _io_resp_bits_target_T_39 = mux(_io_resp_bits_target_T_11, tgtPages[11], UInt<1>(0h0)) node _io_resp_bits_target_T_40 = mux(_io_resp_bits_target_T_12, tgtPages[12], UInt<1>(0h0)) node _io_resp_bits_target_T_41 = mux(_io_resp_bits_target_T_13, tgtPages[13], UInt<1>(0h0)) node _io_resp_bits_target_T_42 = mux(_io_resp_bits_target_T_14, tgtPages[14], UInt<1>(0h0)) node _io_resp_bits_target_T_43 = mux(_io_resp_bits_target_T_15, tgtPages[15], UInt<1>(0h0)) node _io_resp_bits_target_T_44 = mux(_io_resp_bits_target_T_16, tgtPages[16], UInt<1>(0h0)) node _io_resp_bits_target_T_45 = mux(_io_resp_bits_target_T_17, tgtPages[17], UInt<1>(0h0)) node _io_resp_bits_target_T_46 = mux(_io_resp_bits_target_T_18, tgtPages[18], UInt<1>(0h0)) node _io_resp_bits_target_T_47 = mux(_io_resp_bits_target_T_19, tgtPages[19], UInt<1>(0h0)) node _io_resp_bits_target_T_48 = mux(_io_resp_bits_target_T_20, tgtPages[20], UInt<1>(0h0)) node _io_resp_bits_target_T_49 = mux(_io_resp_bits_target_T_21, tgtPages[21], UInt<1>(0h0)) node _io_resp_bits_target_T_50 = mux(_io_resp_bits_target_T_22, tgtPages[22], UInt<1>(0h0)) node _io_resp_bits_target_T_51 = mux(_io_resp_bits_target_T_23, tgtPages[23], UInt<1>(0h0)) node _io_resp_bits_target_T_52 = mux(_io_resp_bits_target_T_24, tgtPages[24], UInt<1>(0h0)) node _io_resp_bits_target_T_53 = mux(_io_resp_bits_target_T_25, tgtPages[25], UInt<1>(0h0)) node _io_resp_bits_target_T_54 = mux(_io_resp_bits_target_T_26, tgtPages[26], UInt<1>(0h0)) node _io_resp_bits_target_T_55 = mux(_io_resp_bits_target_T_27, tgtPages[27], UInt<1>(0h0)) node _io_resp_bits_target_T_56 = or(_io_resp_bits_target_T_28, _io_resp_bits_target_T_29) node _io_resp_bits_target_T_57 = or(_io_resp_bits_target_T_56, _io_resp_bits_target_T_30) node _io_resp_bits_target_T_58 = or(_io_resp_bits_target_T_57, _io_resp_bits_target_T_31) node _io_resp_bits_target_T_59 = or(_io_resp_bits_target_T_58, _io_resp_bits_target_T_32) node _io_resp_bits_target_T_60 = or(_io_resp_bits_target_T_59, _io_resp_bits_target_T_33) node _io_resp_bits_target_T_61 = or(_io_resp_bits_target_T_60, _io_resp_bits_target_T_34) node _io_resp_bits_target_T_62 = or(_io_resp_bits_target_T_61, _io_resp_bits_target_T_35) node _io_resp_bits_target_T_63 = or(_io_resp_bits_target_T_62, _io_resp_bits_target_T_36) node _io_resp_bits_target_T_64 = or(_io_resp_bits_target_T_63, _io_resp_bits_target_T_37) node _io_resp_bits_target_T_65 = or(_io_resp_bits_target_T_64, _io_resp_bits_target_T_38) node _io_resp_bits_target_T_66 = or(_io_resp_bits_target_T_65, _io_resp_bits_target_T_39) node _io_resp_bits_target_T_67 = or(_io_resp_bits_target_T_66, _io_resp_bits_target_T_40) node _io_resp_bits_target_T_68 = or(_io_resp_bits_target_T_67, _io_resp_bits_target_T_41) node _io_resp_bits_target_T_69 = or(_io_resp_bits_target_T_68, _io_resp_bits_target_T_42) node _io_resp_bits_target_T_70 = or(_io_resp_bits_target_T_69, _io_resp_bits_target_T_43) node _io_resp_bits_target_T_71 = or(_io_resp_bits_target_T_70, _io_resp_bits_target_T_44) node _io_resp_bits_target_T_72 = or(_io_resp_bits_target_T_71, _io_resp_bits_target_T_45) node _io_resp_bits_target_T_73 = or(_io_resp_bits_target_T_72, _io_resp_bits_target_T_46) node _io_resp_bits_target_T_74 = or(_io_resp_bits_target_T_73, _io_resp_bits_target_T_47) node _io_resp_bits_target_T_75 = or(_io_resp_bits_target_T_74, _io_resp_bits_target_T_48) node _io_resp_bits_target_T_76 = or(_io_resp_bits_target_T_75, _io_resp_bits_target_T_49) node _io_resp_bits_target_T_77 = or(_io_resp_bits_target_T_76, _io_resp_bits_target_T_50) node _io_resp_bits_target_T_78 = or(_io_resp_bits_target_T_77, _io_resp_bits_target_T_51) node _io_resp_bits_target_T_79 = or(_io_resp_bits_target_T_78, _io_resp_bits_target_T_52) node _io_resp_bits_target_T_80 = or(_io_resp_bits_target_T_79, _io_resp_bits_target_T_53) node _io_resp_bits_target_T_81 = or(_io_resp_bits_target_T_80, _io_resp_bits_target_T_54) node _io_resp_bits_target_T_82 = or(_io_resp_bits_target_T_81, _io_resp_bits_target_T_55) wire _io_resp_bits_target_WIRE : UInt<3> connect _io_resp_bits_target_WIRE, _io_resp_bits_target_T_82 node _io_resp_bits_target_T_83 = eq(_io_resp_bits_target_WIRE, UInt<1>(0h1)) node _io_resp_bits_target_T_84 = mux(_io_resp_bits_target_T_83, pagesMasked_1, pagesMasked_0) node _io_resp_bits_target_T_85 = eq(_io_resp_bits_target_WIRE, UInt<2>(0h2)) node _io_resp_bits_target_T_86 = mux(_io_resp_bits_target_T_85, pagesMasked_2, _io_resp_bits_target_T_84) node _io_resp_bits_target_T_87 = eq(_io_resp_bits_target_WIRE, UInt<2>(0h3)) node _io_resp_bits_target_T_88 = mux(_io_resp_bits_target_T_87, pagesMasked_3, _io_resp_bits_target_T_86) node _io_resp_bits_target_T_89 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h4)) node _io_resp_bits_target_T_90 = mux(_io_resp_bits_target_T_89, pagesMasked_4, _io_resp_bits_target_T_88) node _io_resp_bits_target_T_91 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h5)) node _io_resp_bits_target_T_92 = mux(_io_resp_bits_target_T_91, pagesMasked_5, _io_resp_bits_target_T_90) node _io_resp_bits_target_T_93 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h6)) node _io_resp_bits_target_T_94 = mux(_io_resp_bits_target_T_93, pagesMasked_4, _io_resp_bits_target_T_92) node _io_resp_bits_target_T_95 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h7)) node _io_resp_bits_target_T_96 = mux(_io_resp_bits_target_T_95, pagesMasked_5, _io_resp_bits_target_T_94) node _io_resp_bits_target_T_97 = bits(idxHit, 0, 0) node _io_resp_bits_target_T_98 = bits(idxHit, 1, 1) node _io_resp_bits_target_T_99 = bits(idxHit, 2, 2) node _io_resp_bits_target_T_100 = bits(idxHit, 3, 3) node _io_resp_bits_target_T_101 = bits(idxHit, 4, 4) node _io_resp_bits_target_T_102 = bits(idxHit, 5, 5) node _io_resp_bits_target_T_103 = bits(idxHit, 6, 6) node _io_resp_bits_target_T_104 = bits(idxHit, 7, 7) node _io_resp_bits_target_T_105 = bits(idxHit, 8, 8) node _io_resp_bits_target_T_106 = bits(idxHit, 9, 9) node _io_resp_bits_target_T_107 = bits(idxHit, 10, 10) node _io_resp_bits_target_T_108 = bits(idxHit, 11, 11) node _io_resp_bits_target_T_109 = bits(idxHit, 12, 12) node _io_resp_bits_target_T_110 = bits(idxHit, 13, 13) node _io_resp_bits_target_T_111 = bits(idxHit, 14, 14) node _io_resp_bits_target_T_112 = bits(idxHit, 15, 15) node _io_resp_bits_target_T_113 = bits(idxHit, 16, 16) node _io_resp_bits_target_T_114 = bits(idxHit, 17, 17) node _io_resp_bits_target_T_115 = bits(idxHit, 18, 18) node _io_resp_bits_target_T_116 = bits(idxHit, 19, 19) node _io_resp_bits_target_T_117 = bits(idxHit, 20, 20) node _io_resp_bits_target_T_118 = bits(idxHit, 21, 21) node _io_resp_bits_target_T_119 = bits(idxHit, 22, 22) node _io_resp_bits_target_T_120 = bits(idxHit, 23, 23) node _io_resp_bits_target_T_121 = bits(idxHit, 24, 24) node _io_resp_bits_target_T_122 = bits(idxHit, 25, 25) node _io_resp_bits_target_T_123 = bits(idxHit, 26, 26) node _io_resp_bits_target_T_124 = bits(idxHit, 27, 27) node _io_resp_bits_target_T_125 = mux(_io_resp_bits_target_T_97, tgts[0], UInt<1>(0h0)) node _io_resp_bits_target_T_126 = mux(_io_resp_bits_target_T_98, tgts[1], UInt<1>(0h0)) node _io_resp_bits_target_T_127 = mux(_io_resp_bits_target_T_99, tgts[2], UInt<1>(0h0)) node _io_resp_bits_target_T_128 = mux(_io_resp_bits_target_T_100, tgts[3], UInt<1>(0h0)) node _io_resp_bits_target_T_129 = mux(_io_resp_bits_target_T_101, tgts[4], UInt<1>(0h0)) node _io_resp_bits_target_T_130 = mux(_io_resp_bits_target_T_102, tgts[5], UInt<1>(0h0)) node _io_resp_bits_target_T_131 = mux(_io_resp_bits_target_T_103, tgts[6], UInt<1>(0h0)) node _io_resp_bits_target_T_132 = mux(_io_resp_bits_target_T_104, tgts[7], UInt<1>(0h0)) node _io_resp_bits_target_T_133 = mux(_io_resp_bits_target_T_105, tgts[8], UInt<1>(0h0)) node _io_resp_bits_target_T_134 = mux(_io_resp_bits_target_T_106, tgts[9], UInt<1>(0h0)) node _io_resp_bits_target_T_135 = mux(_io_resp_bits_target_T_107, tgts[10], UInt<1>(0h0)) node _io_resp_bits_target_T_136 = mux(_io_resp_bits_target_T_108, tgts[11], UInt<1>(0h0)) node _io_resp_bits_target_T_137 = mux(_io_resp_bits_target_T_109, tgts[12], UInt<1>(0h0)) node _io_resp_bits_target_T_138 = mux(_io_resp_bits_target_T_110, tgts[13], UInt<1>(0h0)) node _io_resp_bits_target_T_139 = mux(_io_resp_bits_target_T_111, tgts[14], UInt<1>(0h0)) node _io_resp_bits_target_T_140 = mux(_io_resp_bits_target_T_112, tgts[15], UInt<1>(0h0)) node _io_resp_bits_target_T_141 = mux(_io_resp_bits_target_T_113, tgts[16], UInt<1>(0h0)) node _io_resp_bits_target_T_142 = mux(_io_resp_bits_target_T_114, tgts[17], UInt<1>(0h0)) node _io_resp_bits_target_T_143 = mux(_io_resp_bits_target_T_115, tgts[18], UInt<1>(0h0)) node _io_resp_bits_target_T_144 = mux(_io_resp_bits_target_T_116, tgts[19], UInt<1>(0h0)) node _io_resp_bits_target_T_145 = mux(_io_resp_bits_target_T_117, tgts[20], UInt<1>(0h0)) node _io_resp_bits_target_T_146 = mux(_io_resp_bits_target_T_118, tgts[21], UInt<1>(0h0)) node _io_resp_bits_target_T_147 = mux(_io_resp_bits_target_T_119, tgts[22], UInt<1>(0h0)) node _io_resp_bits_target_T_148 = mux(_io_resp_bits_target_T_120, tgts[23], UInt<1>(0h0)) node _io_resp_bits_target_T_149 = mux(_io_resp_bits_target_T_121, tgts[24], UInt<1>(0h0)) node _io_resp_bits_target_T_150 = mux(_io_resp_bits_target_T_122, tgts[25], UInt<1>(0h0)) node _io_resp_bits_target_T_151 = mux(_io_resp_bits_target_T_123, tgts[26], UInt<1>(0h0)) node _io_resp_bits_target_T_152 = mux(_io_resp_bits_target_T_124, tgts[27], UInt<1>(0h0)) node _io_resp_bits_target_T_153 = or(_io_resp_bits_target_T_125, _io_resp_bits_target_T_126) node _io_resp_bits_target_T_154 = or(_io_resp_bits_target_T_153, _io_resp_bits_target_T_127) node _io_resp_bits_target_T_155 = or(_io_resp_bits_target_T_154, _io_resp_bits_target_T_128) node _io_resp_bits_target_T_156 = or(_io_resp_bits_target_T_155, _io_resp_bits_target_T_129) node _io_resp_bits_target_T_157 = or(_io_resp_bits_target_T_156, _io_resp_bits_target_T_130) node _io_resp_bits_target_T_158 = or(_io_resp_bits_target_T_157, _io_resp_bits_target_T_131) node _io_resp_bits_target_T_159 = or(_io_resp_bits_target_T_158, _io_resp_bits_target_T_132) node _io_resp_bits_target_T_160 = or(_io_resp_bits_target_T_159, _io_resp_bits_target_T_133) node _io_resp_bits_target_T_161 = or(_io_resp_bits_target_T_160, _io_resp_bits_target_T_134) node _io_resp_bits_target_T_162 = or(_io_resp_bits_target_T_161, _io_resp_bits_target_T_135) node _io_resp_bits_target_T_163 = or(_io_resp_bits_target_T_162, _io_resp_bits_target_T_136) node _io_resp_bits_target_T_164 = or(_io_resp_bits_target_T_163, _io_resp_bits_target_T_137) node _io_resp_bits_target_T_165 = or(_io_resp_bits_target_T_164, _io_resp_bits_target_T_138) node _io_resp_bits_target_T_166 = or(_io_resp_bits_target_T_165, _io_resp_bits_target_T_139) node _io_resp_bits_target_T_167 = or(_io_resp_bits_target_T_166, _io_resp_bits_target_T_140) node _io_resp_bits_target_T_168 = or(_io_resp_bits_target_T_167, _io_resp_bits_target_T_141) node _io_resp_bits_target_T_169 = or(_io_resp_bits_target_T_168, _io_resp_bits_target_T_142) node _io_resp_bits_target_T_170 = or(_io_resp_bits_target_T_169, _io_resp_bits_target_T_143) node _io_resp_bits_target_T_171 = or(_io_resp_bits_target_T_170, _io_resp_bits_target_T_144) node _io_resp_bits_target_T_172 = or(_io_resp_bits_target_T_171, _io_resp_bits_target_T_145) node _io_resp_bits_target_T_173 = or(_io_resp_bits_target_T_172, _io_resp_bits_target_T_146) node _io_resp_bits_target_T_174 = or(_io_resp_bits_target_T_173, _io_resp_bits_target_T_147) node _io_resp_bits_target_T_175 = or(_io_resp_bits_target_T_174, _io_resp_bits_target_T_148) node _io_resp_bits_target_T_176 = or(_io_resp_bits_target_T_175, _io_resp_bits_target_T_149) node _io_resp_bits_target_T_177 = or(_io_resp_bits_target_T_176, _io_resp_bits_target_T_150) node _io_resp_bits_target_T_178 = or(_io_resp_bits_target_T_177, _io_resp_bits_target_T_151) node _io_resp_bits_target_T_179 = or(_io_resp_bits_target_T_178, _io_resp_bits_target_T_152) wire _io_resp_bits_target_WIRE_1 : UInt<13> connect _io_resp_bits_target_WIRE_1, _io_resp_bits_target_T_179 node _io_resp_bits_target_T_180 = shl(_io_resp_bits_target_WIRE_1, 1) node _io_resp_bits_target_T_181 = cat(_io_resp_bits_target_T_96, _io_resp_bits_target_T_180) connect io.resp.bits.target, _io_resp_bits_target_T_181 node io_resp_bits_entry_hi = bits(idxHit, 27, 16) node io_resp_bits_entry_lo = bits(idxHit, 15, 0) node _io_resp_bits_entry_T = orr(io_resp_bits_entry_hi) node _io_resp_bits_entry_T_1 = or(io_resp_bits_entry_hi, io_resp_bits_entry_lo) node io_resp_bits_entry_hi_1 = bits(_io_resp_bits_entry_T_1, 15, 8) node io_resp_bits_entry_lo_1 = bits(_io_resp_bits_entry_T_1, 7, 0) node _io_resp_bits_entry_T_2 = orr(io_resp_bits_entry_hi_1) node _io_resp_bits_entry_T_3 = or(io_resp_bits_entry_hi_1, io_resp_bits_entry_lo_1) node io_resp_bits_entry_hi_2 = bits(_io_resp_bits_entry_T_3, 7, 4) node io_resp_bits_entry_lo_2 = bits(_io_resp_bits_entry_T_3, 3, 0) node _io_resp_bits_entry_T_4 = orr(io_resp_bits_entry_hi_2) node _io_resp_bits_entry_T_5 = or(io_resp_bits_entry_hi_2, io_resp_bits_entry_lo_2) node io_resp_bits_entry_hi_3 = bits(_io_resp_bits_entry_T_5, 3, 2) node io_resp_bits_entry_lo_3 = bits(_io_resp_bits_entry_T_5, 1, 0) node _io_resp_bits_entry_T_6 = orr(io_resp_bits_entry_hi_3) node _io_resp_bits_entry_T_7 = or(io_resp_bits_entry_hi_3, io_resp_bits_entry_lo_3) node _io_resp_bits_entry_T_8 = bits(_io_resp_bits_entry_T_7, 1, 1) node _io_resp_bits_entry_T_9 = cat(_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8) node _io_resp_bits_entry_T_10 = cat(_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9) node _io_resp_bits_entry_T_11 = cat(_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10) node _io_resp_bits_entry_T_12 = cat(_io_resp_bits_entry_T, _io_resp_bits_entry_T_11) connect io.resp.bits.entry, _io_resp_bits_entry_T_12 node _io_resp_bits_bridx_T = bits(idxHit, 0, 0) node _io_resp_bits_bridx_T_1 = bits(idxHit, 1, 1) node _io_resp_bits_bridx_T_2 = bits(idxHit, 2, 2) node _io_resp_bits_bridx_T_3 = bits(idxHit, 3, 3) node _io_resp_bits_bridx_T_4 = bits(idxHit, 4, 4) node _io_resp_bits_bridx_T_5 = bits(idxHit, 5, 5) node _io_resp_bits_bridx_T_6 = bits(idxHit, 6, 6) node _io_resp_bits_bridx_T_7 = bits(idxHit, 7, 7) node _io_resp_bits_bridx_T_8 = bits(idxHit, 8, 8) node _io_resp_bits_bridx_T_9 = bits(idxHit, 9, 9) node _io_resp_bits_bridx_T_10 = bits(idxHit, 10, 10) node _io_resp_bits_bridx_T_11 = bits(idxHit, 11, 11) node _io_resp_bits_bridx_T_12 = bits(idxHit, 12, 12) node _io_resp_bits_bridx_T_13 = bits(idxHit, 13, 13) node _io_resp_bits_bridx_T_14 = bits(idxHit, 14, 14) node _io_resp_bits_bridx_T_15 = bits(idxHit, 15, 15) node _io_resp_bits_bridx_T_16 = bits(idxHit, 16, 16) node _io_resp_bits_bridx_T_17 = bits(idxHit, 17, 17) node _io_resp_bits_bridx_T_18 = bits(idxHit, 18, 18) node _io_resp_bits_bridx_T_19 = bits(idxHit, 19, 19) node _io_resp_bits_bridx_T_20 = bits(idxHit, 20, 20) node _io_resp_bits_bridx_T_21 = bits(idxHit, 21, 21) node _io_resp_bits_bridx_T_22 = bits(idxHit, 22, 22) node _io_resp_bits_bridx_T_23 = bits(idxHit, 23, 23) node _io_resp_bits_bridx_T_24 = bits(idxHit, 24, 24) node _io_resp_bits_bridx_T_25 = bits(idxHit, 25, 25) node _io_resp_bits_bridx_T_26 = bits(idxHit, 26, 26) node _io_resp_bits_bridx_T_27 = bits(idxHit, 27, 27) node _io_resp_bits_bridx_T_28 = mux(_io_resp_bits_bridx_T, brIdx[0], UInt<1>(0h0)) node _io_resp_bits_bridx_T_29 = mux(_io_resp_bits_bridx_T_1, brIdx[1], UInt<1>(0h0)) node _io_resp_bits_bridx_T_30 = mux(_io_resp_bits_bridx_T_2, brIdx[2], UInt<1>(0h0)) node _io_resp_bits_bridx_T_31 = mux(_io_resp_bits_bridx_T_3, brIdx[3], UInt<1>(0h0)) node _io_resp_bits_bridx_T_32 = mux(_io_resp_bits_bridx_T_4, brIdx[4], UInt<1>(0h0)) node _io_resp_bits_bridx_T_33 = mux(_io_resp_bits_bridx_T_5, brIdx[5], UInt<1>(0h0)) node _io_resp_bits_bridx_T_34 = mux(_io_resp_bits_bridx_T_6, brIdx[6], UInt<1>(0h0)) node _io_resp_bits_bridx_T_35 = mux(_io_resp_bits_bridx_T_7, brIdx[7], UInt<1>(0h0)) node _io_resp_bits_bridx_T_36 = mux(_io_resp_bits_bridx_T_8, brIdx[8], UInt<1>(0h0)) node _io_resp_bits_bridx_T_37 = mux(_io_resp_bits_bridx_T_9, brIdx[9], UInt<1>(0h0)) node _io_resp_bits_bridx_T_38 = mux(_io_resp_bits_bridx_T_10, brIdx[10], UInt<1>(0h0)) node _io_resp_bits_bridx_T_39 = mux(_io_resp_bits_bridx_T_11, brIdx[11], UInt<1>(0h0)) node _io_resp_bits_bridx_T_40 = mux(_io_resp_bits_bridx_T_12, brIdx[12], UInt<1>(0h0)) node _io_resp_bits_bridx_T_41 = mux(_io_resp_bits_bridx_T_13, brIdx[13], UInt<1>(0h0)) node _io_resp_bits_bridx_T_42 = mux(_io_resp_bits_bridx_T_14, brIdx[14], UInt<1>(0h0)) node _io_resp_bits_bridx_T_43 = mux(_io_resp_bits_bridx_T_15, brIdx[15], UInt<1>(0h0)) node _io_resp_bits_bridx_T_44 = mux(_io_resp_bits_bridx_T_16, brIdx[16], UInt<1>(0h0)) node _io_resp_bits_bridx_T_45 = mux(_io_resp_bits_bridx_T_17, brIdx[17], UInt<1>(0h0)) node _io_resp_bits_bridx_T_46 = mux(_io_resp_bits_bridx_T_18, brIdx[18], UInt<1>(0h0)) node _io_resp_bits_bridx_T_47 = mux(_io_resp_bits_bridx_T_19, brIdx[19], UInt<1>(0h0)) node _io_resp_bits_bridx_T_48 = mux(_io_resp_bits_bridx_T_20, brIdx[20], UInt<1>(0h0)) node _io_resp_bits_bridx_T_49 = mux(_io_resp_bits_bridx_T_21, brIdx[21], UInt<1>(0h0)) node _io_resp_bits_bridx_T_50 = mux(_io_resp_bits_bridx_T_22, brIdx[22], UInt<1>(0h0)) node _io_resp_bits_bridx_T_51 = mux(_io_resp_bits_bridx_T_23, brIdx[23], UInt<1>(0h0)) node _io_resp_bits_bridx_T_52 = mux(_io_resp_bits_bridx_T_24, brIdx[24], UInt<1>(0h0)) node _io_resp_bits_bridx_T_53 = mux(_io_resp_bits_bridx_T_25, brIdx[25], UInt<1>(0h0)) node _io_resp_bits_bridx_T_54 = mux(_io_resp_bits_bridx_T_26, brIdx[26], UInt<1>(0h0)) node _io_resp_bits_bridx_T_55 = mux(_io_resp_bits_bridx_T_27, brIdx[27], UInt<1>(0h0)) node _io_resp_bits_bridx_T_56 = or(_io_resp_bits_bridx_T_28, _io_resp_bits_bridx_T_29) node _io_resp_bits_bridx_T_57 = or(_io_resp_bits_bridx_T_56, _io_resp_bits_bridx_T_30) node _io_resp_bits_bridx_T_58 = or(_io_resp_bits_bridx_T_57, _io_resp_bits_bridx_T_31) node _io_resp_bits_bridx_T_59 = or(_io_resp_bits_bridx_T_58, _io_resp_bits_bridx_T_32) node _io_resp_bits_bridx_T_60 = or(_io_resp_bits_bridx_T_59, _io_resp_bits_bridx_T_33) node _io_resp_bits_bridx_T_61 = or(_io_resp_bits_bridx_T_60, _io_resp_bits_bridx_T_34) node _io_resp_bits_bridx_T_62 = or(_io_resp_bits_bridx_T_61, _io_resp_bits_bridx_T_35) node _io_resp_bits_bridx_T_63 = or(_io_resp_bits_bridx_T_62, _io_resp_bits_bridx_T_36) node _io_resp_bits_bridx_T_64 = or(_io_resp_bits_bridx_T_63, _io_resp_bits_bridx_T_37) node _io_resp_bits_bridx_T_65 = or(_io_resp_bits_bridx_T_64, _io_resp_bits_bridx_T_38) node _io_resp_bits_bridx_T_66 = or(_io_resp_bits_bridx_T_65, _io_resp_bits_bridx_T_39) node _io_resp_bits_bridx_T_67 = or(_io_resp_bits_bridx_T_66, _io_resp_bits_bridx_T_40) node _io_resp_bits_bridx_T_68 = or(_io_resp_bits_bridx_T_67, _io_resp_bits_bridx_T_41) node _io_resp_bits_bridx_T_69 = or(_io_resp_bits_bridx_T_68, _io_resp_bits_bridx_T_42) node _io_resp_bits_bridx_T_70 = or(_io_resp_bits_bridx_T_69, _io_resp_bits_bridx_T_43) node _io_resp_bits_bridx_T_71 = or(_io_resp_bits_bridx_T_70, _io_resp_bits_bridx_T_44) node _io_resp_bits_bridx_T_72 = or(_io_resp_bits_bridx_T_71, _io_resp_bits_bridx_T_45) node _io_resp_bits_bridx_T_73 = or(_io_resp_bits_bridx_T_72, _io_resp_bits_bridx_T_46) node _io_resp_bits_bridx_T_74 = or(_io_resp_bits_bridx_T_73, _io_resp_bits_bridx_T_47) node _io_resp_bits_bridx_T_75 = or(_io_resp_bits_bridx_T_74, _io_resp_bits_bridx_T_48) node _io_resp_bits_bridx_T_76 = or(_io_resp_bits_bridx_T_75, _io_resp_bits_bridx_T_49) node _io_resp_bits_bridx_T_77 = or(_io_resp_bits_bridx_T_76, _io_resp_bits_bridx_T_50) node _io_resp_bits_bridx_T_78 = or(_io_resp_bits_bridx_T_77, _io_resp_bits_bridx_T_51) node _io_resp_bits_bridx_T_79 = or(_io_resp_bits_bridx_T_78, _io_resp_bits_bridx_T_52) node _io_resp_bits_bridx_T_80 = or(_io_resp_bits_bridx_T_79, _io_resp_bits_bridx_T_53) node _io_resp_bits_bridx_T_81 = or(_io_resp_bits_bridx_T_80, _io_resp_bits_bridx_T_54) node _io_resp_bits_bridx_T_82 = or(_io_resp_bits_bridx_T_81, _io_resp_bits_bridx_T_55) wire _io_resp_bits_bridx_WIRE : UInt<1> connect _io_resp_bits_bridx_WIRE, _io_resp_bits_bridx_T_82 connect io.resp.bits.bridx, _io_resp_bits_bridx_WIRE node _io_resp_bits_mask_T = not(io.resp.bits.bridx) node _io_resp_bits_mask_T_1 = mux(io.resp.bits.taken, _io_resp_bits_mask_T, UInt<1>(0h0)) node _io_resp_bits_mask_T_2 = not(_io_resp_bits_mask_T_1) node _io_resp_bits_mask_T_3 = dshl(UInt<1>(0h1), _io_resp_bits_mask_T_2) node _io_resp_bits_mask_T_4 = sub(_io_resp_bits_mask_T_3, UInt<1>(0h1)) node _io_resp_bits_mask_T_5 = tail(_io_resp_bits_mask_T_4, 1) node _io_resp_bits_mask_T_6 = cat(_io_resp_bits_mask_T_5, UInt<1>(0h1)) connect io.resp.bits.mask, _io_resp_bits_mask_T_6 node _io_resp_bits_cfiType_T = bits(idxHit, 0, 0) node _io_resp_bits_cfiType_T_1 = bits(idxHit, 1, 1) node _io_resp_bits_cfiType_T_2 = bits(idxHit, 2, 2) node _io_resp_bits_cfiType_T_3 = bits(idxHit, 3, 3) node _io_resp_bits_cfiType_T_4 = bits(idxHit, 4, 4) node _io_resp_bits_cfiType_T_5 = bits(idxHit, 5, 5) node _io_resp_bits_cfiType_T_6 = bits(idxHit, 6, 6) node _io_resp_bits_cfiType_T_7 = bits(idxHit, 7, 7) node _io_resp_bits_cfiType_T_8 = bits(idxHit, 8, 8) node _io_resp_bits_cfiType_T_9 = bits(idxHit, 9, 9) node _io_resp_bits_cfiType_T_10 = bits(idxHit, 10, 10) node _io_resp_bits_cfiType_T_11 = bits(idxHit, 11, 11) node _io_resp_bits_cfiType_T_12 = bits(idxHit, 12, 12) node _io_resp_bits_cfiType_T_13 = bits(idxHit, 13, 13) node _io_resp_bits_cfiType_T_14 = bits(idxHit, 14, 14) node _io_resp_bits_cfiType_T_15 = bits(idxHit, 15, 15) node _io_resp_bits_cfiType_T_16 = bits(idxHit, 16, 16) node _io_resp_bits_cfiType_T_17 = bits(idxHit, 17, 17) node _io_resp_bits_cfiType_T_18 = bits(idxHit, 18, 18) node _io_resp_bits_cfiType_T_19 = bits(idxHit, 19, 19) node _io_resp_bits_cfiType_T_20 = bits(idxHit, 20, 20) node _io_resp_bits_cfiType_T_21 = bits(idxHit, 21, 21) node _io_resp_bits_cfiType_T_22 = bits(idxHit, 22, 22) node _io_resp_bits_cfiType_T_23 = bits(idxHit, 23, 23) node _io_resp_bits_cfiType_T_24 = bits(idxHit, 24, 24) node _io_resp_bits_cfiType_T_25 = bits(idxHit, 25, 25) node _io_resp_bits_cfiType_T_26 = bits(idxHit, 26, 26) node _io_resp_bits_cfiType_T_27 = bits(idxHit, 27, 27) node _io_resp_bits_cfiType_T_28 = mux(_io_resp_bits_cfiType_T, cfiType[0], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_29 = mux(_io_resp_bits_cfiType_T_1, cfiType[1], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_30 = mux(_io_resp_bits_cfiType_T_2, cfiType[2], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_31 = mux(_io_resp_bits_cfiType_T_3, cfiType[3], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_32 = mux(_io_resp_bits_cfiType_T_4, cfiType[4], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_33 = mux(_io_resp_bits_cfiType_T_5, cfiType[5], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_34 = mux(_io_resp_bits_cfiType_T_6, cfiType[6], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_35 = mux(_io_resp_bits_cfiType_T_7, cfiType[7], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_36 = mux(_io_resp_bits_cfiType_T_8, cfiType[8], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_37 = mux(_io_resp_bits_cfiType_T_9, cfiType[9], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_38 = mux(_io_resp_bits_cfiType_T_10, cfiType[10], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_39 = mux(_io_resp_bits_cfiType_T_11, cfiType[11], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_40 = mux(_io_resp_bits_cfiType_T_12, cfiType[12], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_41 = mux(_io_resp_bits_cfiType_T_13, cfiType[13], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_42 = mux(_io_resp_bits_cfiType_T_14, cfiType[14], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_43 = mux(_io_resp_bits_cfiType_T_15, cfiType[15], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_44 = mux(_io_resp_bits_cfiType_T_16, cfiType[16], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_45 = mux(_io_resp_bits_cfiType_T_17, cfiType[17], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_46 = mux(_io_resp_bits_cfiType_T_18, cfiType[18], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_47 = mux(_io_resp_bits_cfiType_T_19, cfiType[19], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_48 = mux(_io_resp_bits_cfiType_T_20, cfiType[20], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_49 = mux(_io_resp_bits_cfiType_T_21, cfiType[21], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_50 = mux(_io_resp_bits_cfiType_T_22, cfiType[22], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_51 = mux(_io_resp_bits_cfiType_T_23, cfiType[23], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_52 = mux(_io_resp_bits_cfiType_T_24, cfiType[24], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_53 = mux(_io_resp_bits_cfiType_T_25, cfiType[25], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_54 = mux(_io_resp_bits_cfiType_T_26, cfiType[26], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_55 = mux(_io_resp_bits_cfiType_T_27, cfiType[27], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_56 = or(_io_resp_bits_cfiType_T_28, _io_resp_bits_cfiType_T_29) node _io_resp_bits_cfiType_T_57 = or(_io_resp_bits_cfiType_T_56, _io_resp_bits_cfiType_T_30) node _io_resp_bits_cfiType_T_58 = or(_io_resp_bits_cfiType_T_57, _io_resp_bits_cfiType_T_31) node _io_resp_bits_cfiType_T_59 = or(_io_resp_bits_cfiType_T_58, _io_resp_bits_cfiType_T_32) node _io_resp_bits_cfiType_T_60 = or(_io_resp_bits_cfiType_T_59, _io_resp_bits_cfiType_T_33) node _io_resp_bits_cfiType_T_61 = or(_io_resp_bits_cfiType_T_60, _io_resp_bits_cfiType_T_34) node _io_resp_bits_cfiType_T_62 = or(_io_resp_bits_cfiType_T_61, _io_resp_bits_cfiType_T_35) node _io_resp_bits_cfiType_T_63 = or(_io_resp_bits_cfiType_T_62, _io_resp_bits_cfiType_T_36) node _io_resp_bits_cfiType_T_64 = or(_io_resp_bits_cfiType_T_63, _io_resp_bits_cfiType_T_37) node _io_resp_bits_cfiType_T_65 = or(_io_resp_bits_cfiType_T_64, _io_resp_bits_cfiType_T_38) node _io_resp_bits_cfiType_T_66 = or(_io_resp_bits_cfiType_T_65, _io_resp_bits_cfiType_T_39) node _io_resp_bits_cfiType_T_67 = or(_io_resp_bits_cfiType_T_66, _io_resp_bits_cfiType_T_40) node _io_resp_bits_cfiType_T_68 = or(_io_resp_bits_cfiType_T_67, _io_resp_bits_cfiType_T_41) node _io_resp_bits_cfiType_T_69 = or(_io_resp_bits_cfiType_T_68, _io_resp_bits_cfiType_T_42) node _io_resp_bits_cfiType_T_70 = or(_io_resp_bits_cfiType_T_69, _io_resp_bits_cfiType_T_43) node _io_resp_bits_cfiType_T_71 = or(_io_resp_bits_cfiType_T_70, _io_resp_bits_cfiType_T_44) node _io_resp_bits_cfiType_T_72 = or(_io_resp_bits_cfiType_T_71, _io_resp_bits_cfiType_T_45) node _io_resp_bits_cfiType_T_73 = or(_io_resp_bits_cfiType_T_72, _io_resp_bits_cfiType_T_46) node _io_resp_bits_cfiType_T_74 = or(_io_resp_bits_cfiType_T_73, _io_resp_bits_cfiType_T_47) node _io_resp_bits_cfiType_T_75 = or(_io_resp_bits_cfiType_T_74, _io_resp_bits_cfiType_T_48) node _io_resp_bits_cfiType_T_76 = or(_io_resp_bits_cfiType_T_75, _io_resp_bits_cfiType_T_49) node _io_resp_bits_cfiType_T_77 = or(_io_resp_bits_cfiType_T_76, _io_resp_bits_cfiType_T_50) node _io_resp_bits_cfiType_T_78 = or(_io_resp_bits_cfiType_T_77, _io_resp_bits_cfiType_T_51) node _io_resp_bits_cfiType_T_79 = or(_io_resp_bits_cfiType_T_78, _io_resp_bits_cfiType_T_52) node _io_resp_bits_cfiType_T_80 = or(_io_resp_bits_cfiType_T_79, _io_resp_bits_cfiType_T_53) node _io_resp_bits_cfiType_T_81 = or(_io_resp_bits_cfiType_T_80, _io_resp_bits_cfiType_T_54) node _io_resp_bits_cfiType_T_82 = or(_io_resp_bits_cfiType_T_81, _io_resp_bits_cfiType_T_55) wire _io_resp_bits_cfiType_WIRE : UInt<2> connect _io_resp_bits_cfiType_WIRE, _io_resp_bits_cfiType_T_82 connect io.resp.bits.cfiType, _io_resp_bits_cfiType_WIRE node _T_19 = bits(idxHit, 13, 0) node _T_20 = bits(_T_19, 6, 0) node _T_21 = bits(_T_20, 2, 0) node _T_22 = bits(_T_21, 0, 0) node leftOne = bits(_T_22, 0, 0) node _T_23 = bits(_T_21, 2, 1) node _T_24 = bits(_T_23, 0, 0) node leftOne_1 = bits(_T_24, 0, 0) node _T_25 = bits(_T_23, 1, 1) node rightOne = bits(_T_25, 0, 0) node rightOne_1 = or(leftOne_1, rightOne) node _T_26 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_27 = and(leftOne_1, rightOne) node rightTwo = or(_T_26, _T_27) node leftOne_2 = or(leftOne, rightOne_1) node _T_28 = or(UInt<1>(0h0), rightTwo) node _T_29 = and(leftOne, rightOne_1) node leftTwo = or(_T_28, _T_29) node _T_30 = bits(_T_20, 6, 3) node _T_31 = bits(_T_30, 1, 0) node _T_32 = bits(_T_31, 0, 0) node leftOne_3 = bits(_T_32, 0, 0) node _T_33 = bits(_T_31, 1, 1) node rightOne_2 = bits(_T_33, 0, 0) node leftOne_4 = or(leftOne_3, rightOne_2) node _T_34 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_35 = and(leftOne_3, rightOne_2) node leftTwo_1 = or(_T_34, _T_35) node _T_36 = bits(_T_30, 3, 2) node _T_37 = bits(_T_36, 0, 0) node leftOne_5 = bits(_T_37, 0, 0) node _T_38 = bits(_T_36, 1, 1) node rightOne_3 = bits(_T_38, 0, 0) node rightOne_4 = or(leftOne_5, rightOne_3) node _T_39 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_40 = and(leftOne_5, rightOne_3) node rightTwo_1 = or(_T_39, _T_40) node rightOne_5 = or(leftOne_4, rightOne_4) node _T_41 = or(leftTwo_1, rightTwo_1) node _T_42 = and(leftOne_4, rightOne_4) node rightTwo_2 = or(_T_41, _T_42) node leftOne_6 = or(leftOne_2, rightOne_5) node _T_43 = or(leftTwo, rightTwo_2) node _T_44 = and(leftOne_2, rightOne_5) node leftTwo_2 = or(_T_43, _T_44) node _T_45 = bits(_T_19, 13, 7) node _T_46 = bits(_T_45, 2, 0) node _T_47 = bits(_T_46, 0, 0) node leftOne_7 = bits(_T_47, 0, 0) node _T_48 = bits(_T_46, 2, 1) node _T_49 = bits(_T_48, 0, 0) node leftOne_8 = bits(_T_49, 0, 0) node _T_50 = bits(_T_48, 1, 1) node rightOne_6 = bits(_T_50, 0, 0) node rightOne_7 = or(leftOne_8, rightOne_6) node _T_51 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_52 = and(leftOne_8, rightOne_6) node rightTwo_3 = or(_T_51, _T_52) node leftOne_9 = or(leftOne_7, rightOne_7) node _T_53 = or(UInt<1>(0h0), rightTwo_3) node _T_54 = and(leftOne_7, rightOne_7) node leftTwo_3 = or(_T_53, _T_54) node _T_55 = bits(_T_45, 6, 3) node _T_56 = bits(_T_55, 1, 0) node _T_57 = bits(_T_56, 0, 0) node leftOne_10 = bits(_T_57, 0, 0) node _T_58 = bits(_T_56, 1, 1) node rightOne_8 = bits(_T_58, 0, 0) node leftOne_11 = or(leftOne_10, rightOne_8) node _T_59 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_60 = and(leftOne_10, rightOne_8) node leftTwo_4 = or(_T_59, _T_60) node _T_61 = bits(_T_55, 3, 2) node _T_62 = bits(_T_61, 0, 0) node leftOne_12 = bits(_T_62, 0, 0) node _T_63 = bits(_T_61, 1, 1) node rightOne_9 = bits(_T_63, 0, 0) node rightOne_10 = or(leftOne_12, rightOne_9) node _T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_65 = and(leftOne_12, rightOne_9) node rightTwo_4 = or(_T_64, _T_65) node rightOne_11 = or(leftOne_11, rightOne_10) node _T_66 = or(leftTwo_4, rightTwo_4) node _T_67 = and(leftOne_11, rightOne_10) node rightTwo_5 = or(_T_66, _T_67) node rightOne_12 = or(leftOne_9, rightOne_11) node _T_68 = or(leftTwo_3, rightTwo_5) node _T_69 = and(leftOne_9, rightOne_11) node rightTwo_6 = or(_T_68, _T_69) node leftOne_13 = or(leftOne_6, rightOne_12) node _T_70 = or(leftTwo_2, rightTwo_6) node _T_71 = and(leftOne_6, rightOne_12) node leftTwo_5 = or(_T_70, _T_71) node _T_72 = bits(idxHit, 27, 14) node _T_73 = bits(_T_72, 6, 0) node _T_74 = bits(_T_73, 2, 0) node _T_75 = bits(_T_74, 0, 0) node leftOne_14 = bits(_T_75, 0, 0) node _T_76 = bits(_T_74, 2, 1) node _T_77 = bits(_T_76, 0, 0) node leftOne_15 = bits(_T_77, 0, 0) node _T_78 = bits(_T_76, 1, 1) node rightOne_13 = bits(_T_78, 0, 0) node rightOne_14 = or(leftOne_15, rightOne_13) node _T_79 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_80 = and(leftOne_15, rightOne_13) node rightTwo_7 = or(_T_79, _T_80) node leftOne_16 = or(leftOne_14, rightOne_14) node _T_81 = or(UInt<1>(0h0), rightTwo_7) node _T_82 = and(leftOne_14, rightOne_14) node leftTwo_6 = or(_T_81, _T_82) node _T_83 = bits(_T_73, 6, 3) node _T_84 = bits(_T_83, 1, 0) node _T_85 = bits(_T_84, 0, 0) node leftOne_17 = bits(_T_85, 0, 0) node _T_86 = bits(_T_84, 1, 1) node rightOne_15 = bits(_T_86, 0, 0) node leftOne_18 = or(leftOne_17, rightOne_15) node _T_87 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_88 = and(leftOne_17, rightOne_15) node leftTwo_7 = or(_T_87, _T_88) node _T_89 = bits(_T_83, 3, 2) node _T_90 = bits(_T_89, 0, 0) node leftOne_19 = bits(_T_90, 0, 0) node _T_91 = bits(_T_89, 1, 1) node rightOne_16 = bits(_T_91, 0, 0) node rightOne_17 = or(leftOne_19, rightOne_16) node _T_92 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_93 = and(leftOne_19, rightOne_16) node rightTwo_8 = or(_T_92, _T_93) node rightOne_18 = or(leftOne_18, rightOne_17) node _T_94 = or(leftTwo_7, rightTwo_8) node _T_95 = and(leftOne_18, rightOne_17) node rightTwo_9 = or(_T_94, _T_95) node leftOne_20 = or(leftOne_16, rightOne_18) node _T_96 = or(leftTwo_6, rightTwo_9) node _T_97 = and(leftOne_16, rightOne_18) node leftTwo_8 = or(_T_96, _T_97) node _T_98 = bits(_T_72, 13, 7) node _T_99 = bits(_T_98, 2, 0) node _T_100 = bits(_T_99, 0, 0) node leftOne_21 = bits(_T_100, 0, 0) node _T_101 = bits(_T_99, 2, 1) node _T_102 = bits(_T_101, 0, 0) node leftOne_22 = bits(_T_102, 0, 0) node _T_103 = bits(_T_101, 1, 1) node rightOne_19 = bits(_T_103, 0, 0) node rightOne_20 = or(leftOne_22, rightOne_19) node _T_104 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_105 = and(leftOne_22, rightOne_19) node rightTwo_10 = or(_T_104, _T_105) node leftOne_23 = or(leftOne_21, rightOne_20) node _T_106 = or(UInt<1>(0h0), rightTwo_10) node _T_107 = and(leftOne_21, rightOne_20) node leftTwo_9 = or(_T_106, _T_107) node _T_108 = bits(_T_98, 6, 3) node _T_109 = bits(_T_108, 1, 0) node _T_110 = bits(_T_109, 0, 0) node leftOne_24 = bits(_T_110, 0, 0) node _T_111 = bits(_T_109, 1, 1) node rightOne_21 = bits(_T_111, 0, 0) node leftOne_25 = or(leftOne_24, rightOne_21) node _T_112 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_113 = and(leftOne_24, rightOne_21) node leftTwo_10 = or(_T_112, _T_113) node _T_114 = bits(_T_108, 3, 2) node _T_115 = bits(_T_114, 0, 0) node leftOne_26 = bits(_T_115, 0, 0) node _T_116 = bits(_T_114, 1, 1) node rightOne_22 = bits(_T_116, 0, 0) node rightOne_23 = or(leftOne_26, rightOne_22) node _T_117 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_118 = and(leftOne_26, rightOne_22) node rightTwo_11 = or(_T_117, _T_118) node rightOne_24 = or(leftOne_25, rightOne_23) node _T_119 = or(leftTwo_10, rightTwo_11) node _T_120 = and(leftOne_25, rightOne_23) node rightTwo_12 = or(_T_119, _T_120) node rightOne_25 = or(leftOne_23, rightOne_24) node _T_121 = or(leftTwo_9, rightTwo_12) node _T_122 = and(leftOne_23, rightOne_24) node rightTwo_13 = or(_T_121, _T_122) node rightOne_26 = or(leftOne_20, rightOne_25) node _T_123 = or(leftTwo_8, rightTwo_13) node _T_124 = and(leftOne_20, rightOne_25) node rightTwo_14 = or(_T_123, _T_124) node _T_125 = or(leftOne_13, rightOne_26) node _T_126 = or(leftTwo_5, rightTwo_14) node _T_127 = and(leftOne_13, rightOne_26) node _T_128 = or(_T_126, _T_127) when _T_128 : node _isValid_T_4 = not(idxHit) node _isValid_T_5 = and(isValid, _isValid_T_4) connect isValid, _isValid_T_5 when io.flush : connect isValid, UInt<1>(0h0) cmem table : UInt<1> [512] regreset history : UInt<8>, clock, reset, UInt<8>(0h0) regreset reset_waddr : UInt<10>, clock, reset, UInt<10>(0h0) node _resetting_T = bits(reset_waddr, 9, 9) node resetting = eq(_resetting_T, UInt<1>(0h0)) wire wen : UInt<1> connect wen, resetting wire waddr_1 : UInt connect waddr_1, reset_waddr wire wdata : UInt connect wdata, UInt<1>(0h0) when resetting : node _reset_waddr_T = add(reset_waddr, UInt<1>(0h1)) node _reset_waddr_T_1 = tail(_reset_waddr_T, 1) connect reset_waddr, _reset_waddr_T_1 when wen : node _T_129 = or(waddr_1, UInt<9>(0h0)) node _T_130 = bits(_T_129, 8, 0) infer mport MPORT = table[_T_130], clock connect MPORT, wdata node _isBranch_T = eq(cfiType[0], UInt<1>(0h0)) node _isBranch_T_1 = eq(cfiType[1], UInt<1>(0h0)) node _isBranch_T_2 = eq(cfiType[2], UInt<1>(0h0)) node _isBranch_T_3 = eq(cfiType[3], UInt<1>(0h0)) node _isBranch_T_4 = eq(cfiType[4], UInt<1>(0h0)) node _isBranch_T_5 = eq(cfiType[5], UInt<1>(0h0)) node _isBranch_T_6 = eq(cfiType[6], UInt<1>(0h0)) node _isBranch_T_7 = eq(cfiType[7], UInt<1>(0h0)) node _isBranch_T_8 = eq(cfiType[8], UInt<1>(0h0)) node _isBranch_T_9 = eq(cfiType[9], UInt<1>(0h0)) node _isBranch_T_10 = eq(cfiType[10], UInt<1>(0h0)) node _isBranch_T_11 = eq(cfiType[11], UInt<1>(0h0)) node _isBranch_T_12 = eq(cfiType[12], UInt<1>(0h0)) node _isBranch_T_13 = eq(cfiType[13], UInt<1>(0h0)) node _isBranch_T_14 = eq(cfiType[14], UInt<1>(0h0)) node _isBranch_T_15 = eq(cfiType[15], UInt<1>(0h0)) node _isBranch_T_16 = eq(cfiType[16], UInt<1>(0h0)) node _isBranch_T_17 = eq(cfiType[17], UInt<1>(0h0)) node _isBranch_T_18 = eq(cfiType[18], UInt<1>(0h0)) node _isBranch_T_19 = eq(cfiType[19], UInt<1>(0h0)) node _isBranch_T_20 = eq(cfiType[20], UInt<1>(0h0)) node _isBranch_T_21 = eq(cfiType[21], UInt<1>(0h0)) node _isBranch_T_22 = eq(cfiType[22], UInt<1>(0h0)) node _isBranch_T_23 = eq(cfiType[23], UInt<1>(0h0)) node _isBranch_T_24 = eq(cfiType[24], UInt<1>(0h0)) node _isBranch_T_25 = eq(cfiType[25], UInt<1>(0h0)) node _isBranch_T_26 = eq(cfiType[26], UInt<1>(0h0)) node _isBranch_T_27 = eq(cfiType[27], UInt<1>(0h0)) node isBranch_lo_lo_lo_hi = cat(_isBranch_T_2, _isBranch_T_1) node isBranch_lo_lo_lo = cat(isBranch_lo_lo_lo_hi, _isBranch_T) node isBranch_lo_lo_hi_lo = cat(_isBranch_T_4, _isBranch_T_3) node isBranch_lo_lo_hi_hi = cat(_isBranch_T_6, _isBranch_T_5) node isBranch_lo_lo_hi = cat(isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo) node isBranch_lo_lo = cat(isBranch_lo_lo_hi, isBranch_lo_lo_lo) node isBranch_lo_hi_lo_hi = cat(_isBranch_T_9, _isBranch_T_8) node isBranch_lo_hi_lo = cat(isBranch_lo_hi_lo_hi, _isBranch_T_7) node isBranch_lo_hi_hi_lo = cat(_isBranch_T_11, _isBranch_T_10) node isBranch_lo_hi_hi_hi = cat(_isBranch_T_13, _isBranch_T_12) node isBranch_lo_hi_hi = cat(isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo) node isBranch_lo_hi = cat(isBranch_lo_hi_hi, isBranch_lo_hi_lo) node isBranch_lo = cat(isBranch_lo_hi, isBranch_lo_lo) node isBranch_hi_lo_lo_hi = cat(_isBranch_T_16, _isBranch_T_15) node isBranch_hi_lo_lo = cat(isBranch_hi_lo_lo_hi, _isBranch_T_14) node isBranch_hi_lo_hi_lo = cat(_isBranch_T_18, _isBranch_T_17) node isBranch_hi_lo_hi_hi = cat(_isBranch_T_20, _isBranch_T_19) node isBranch_hi_lo_hi = cat(isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo) node isBranch_hi_lo = cat(isBranch_hi_lo_hi, isBranch_hi_lo_lo) node isBranch_hi_hi_lo_hi = cat(_isBranch_T_23, _isBranch_T_22) node isBranch_hi_hi_lo = cat(isBranch_hi_hi_lo_hi, _isBranch_T_21) node isBranch_hi_hi_hi_lo = cat(_isBranch_T_25, _isBranch_T_24) node isBranch_hi_hi_hi_hi = cat(_isBranch_T_27, _isBranch_T_26) node isBranch_hi_hi_hi = cat(isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo) node isBranch_hi_hi = cat(isBranch_hi_hi_hi, isBranch_hi_hi_lo) node isBranch_hi = cat(isBranch_hi_hi, isBranch_hi_lo) node _isBranch_T_28 = cat(isBranch_hi, isBranch_lo) node _isBranch_T_29 = and(idxHit, _isBranch_T_28) node isBranch = orr(_isBranch_T_29) wire res : { history : UInt<8>, value : UInt<1>} node res_res_value_hi = shr(io.req.bits.addr, 2) node _res_res_value_T = bits(res_res_value_hi, 8, 0) node _res_res_value_T_1 = shr(res_res_value_hi, 9) node _res_res_value_T_2 = bits(_res_res_value_T_1, 1, 0) node _res_res_value_T_3 = xor(_res_res_value_T, _res_res_value_T_2) node _res_res_value_T_4 = mul(UInt<8>(0hdd), history) node _res_res_value_T_5 = bits(_res_res_value_T_4, 7, 5) node _res_res_value_T_6 = shl(_res_res_value_T_5, 6) node _res_res_value_T_7 = xor(_res_res_value_T_3, _res_res_value_T_6) infer mport res_res_value_MPORT = table[_res_res_value_T_7], clock node _res_res_value_T_8 = mux(resetting, UInt<1>(0h0), res_res_value_MPORT) connect res.value, _res_res_value_T_8 connect res.history, history when io.bht_advance.valid : node _T_131 = bits(io.bht_advance.bits.bht.value, 0, 0) node _history_T = shr(history, 1) node _history_T_1 = cat(_T_131, _history_T) connect history, _history_T_1 when io.bht_update.valid : when io.bht_update.bits.branch : connect wen, UInt<1>(0h1) node _T_132 = eq(resetting, UInt<1>(0h0)) when _T_132 : node waddr_hi = shr(io.bht_update.bits.pc, 2) node _waddr_T_40 = bits(waddr_hi, 8, 0) node _waddr_T_41 = shr(waddr_hi, 9) node _waddr_T_42 = bits(_waddr_T_41, 1, 0) node _waddr_T_43 = xor(_waddr_T_40, _waddr_T_42) node _waddr_T_44 = mul(UInt<8>(0hdd), io.bht_update.bits.prediction.history) node _waddr_T_45 = bits(_waddr_T_44, 7, 5) node _waddr_T_46 = shl(_waddr_T_45, 6) node _waddr_T_47 = xor(_waddr_T_43, _waddr_T_46) connect waddr_1, _waddr_T_47 connect wdata, io.bht_update.bits.taken when io.bht_update.bits.mispredict : node _history_T_2 = shr(io.bht_update.bits.prediction.history, 1) node _history_T_3 = cat(io.bht_update.bits.taken, _history_T_2) connect history, _history_T_3 else : when io.bht_update.bits.mispredict : connect history, io.bht_update.bits.prediction.history node _T_133 = bits(res.value, 0, 0) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = and(_T_134, isBranch) when _T_135 : connect io.resp.bits.taken, UInt<1>(0h0) connect io.resp.bits.bht, res regreset count : UInt<3>, clock, reset, UInt<3>(0h0) regreset pos : UInt<3>, clock, reset, UInt<3>(0h0) reg stack : UInt[6], clock node _doPeek_T = eq(cfiType[0], UInt<2>(0h3)) node _doPeek_T_1 = eq(cfiType[1], UInt<2>(0h3)) node _doPeek_T_2 = eq(cfiType[2], UInt<2>(0h3)) node _doPeek_T_3 = eq(cfiType[3], UInt<2>(0h3)) node _doPeek_T_4 = eq(cfiType[4], UInt<2>(0h3)) node _doPeek_T_5 = eq(cfiType[5], UInt<2>(0h3)) node _doPeek_T_6 = eq(cfiType[6], UInt<2>(0h3)) node _doPeek_T_7 = eq(cfiType[7], UInt<2>(0h3)) node _doPeek_T_8 = eq(cfiType[8], UInt<2>(0h3)) node _doPeek_T_9 = eq(cfiType[9], UInt<2>(0h3)) node _doPeek_T_10 = eq(cfiType[10], UInt<2>(0h3)) node _doPeek_T_11 = eq(cfiType[11], UInt<2>(0h3)) node _doPeek_T_12 = eq(cfiType[12], UInt<2>(0h3)) node _doPeek_T_13 = eq(cfiType[13], UInt<2>(0h3)) node _doPeek_T_14 = eq(cfiType[14], UInt<2>(0h3)) node _doPeek_T_15 = eq(cfiType[15], UInt<2>(0h3)) node _doPeek_T_16 = eq(cfiType[16], UInt<2>(0h3)) node _doPeek_T_17 = eq(cfiType[17], UInt<2>(0h3)) node _doPeek_T_18 = eq(cfiType[18], UInt<2>(0h3)) node _doPeek_T_19 = eq(cfiType[19], UInt<2>(0h3)) node _doPeek_T_20 = eq(cfiType[20], UInt<2>(0h3)) node _doPeek_T_21 = eq(cfiType[21], UInt<2>(0h3)) node _doPeek_T_22 = eq(cfiType[22], UInt<2>(0h3)) node _doPeek_T_23 = eq(cfiType[23], UInt<2>(0h3)) node _doPeek_T_24 = eq(cfiType[24], UInt<2>(0h3)) node _doPeek_T_25 = eq(cfiType[25], UInt<2>(0h3)) node _doPeek_T_26 = eq(cfiType[26], UInt<2>(0h3)) node _doPeek_T_27 = eq(cfiType[27], UInt<2>(0h3)) node doPeek_lo_lo_lo_hi = cat(_doPeek_T_2, _doPeek_T_1) node doPeek_lo_lo_lo = cat(doPeek_lo_lo_lo_hi, _doPeek_T) node doPeek_lo_lo_hi_lo = cat(_doPeek_T_4, _doPeek_T_3) node doPeek_lo_lo_hi_hi = cat(_doPeek_T_6, _doPeek_T_5) node doPeek_lo_lo_hi = cat(doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo) node doPeek_lo_lo = cat(doPeek_lo_lo_hi, doPeek_lo_lo_lo) node doPeek_lo_hi_lo_hi = cat(_doPeek_T_9, _doPeek_T_8) node doPeek_lo_hi_lo = cat(doPeek_lo_hi_lo_hi, _doPeek_T_7) node doPeek_lo_hi_hi_lo = cat(_doPeek_T_11, _doPeek_T_10) node doPeek_lo_hi_hi_hi = cat(_doPeek_T_13, _doPeek_T_12) node doPeek_lo_hi_hi = cat(doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo) node doPeek_lo_hi = cat(doPeek_lo_hi_hi, doPeek_lo_hi_lo) node doPeek_lo = cat(doPeek_lo_hi, doPeek_lo_lo) node doPeek_hi_lo_lo_hi = cat(_doPeek_T_16, _doPeek_T_15) node doPeek_hi_lo_lo = cat(doPeek_hi_lo_lo_hi, _doPeek_T_14) node doPeek_hi_lo_hi_lo = cat(_doPeek_T_18, _doPeek_T_17) node doPeek_hi_lo_hi_hi = cat(_doPeek_T_20, _doPeek_T_19) node doPeek_hi_lo_hi = cat(doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo) node doPeek_hi_lo = cat(doPeek_hi_lo_hi, doPeek_hi_lo_lo) node doPeek_hi_hi_lo_hi = cat(_doPeek_T_23, _doPeek_T_22) node doPeek_hi_hi_lo = cat(doPeek_hi_hi_lo_hi, _doPeek_T_21) node doPeek_hi_hi_hi_lo = cat(_doPeek_T_25, _doPeek_T_24) node doPeek_hi_hi_hi_hi = cat(_doPeek_T_27, _doPeek_T_26) node doPeek_hi_hi_hi = cat(doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo) node doPeek_hi_hi = cat(doPeek_hi_hi_hi, doPeek_hi_hi_lo) node doPeek_hi = cat(doPeek_hi_hi, doPeek_hi_lo) node _doPeek_T_28 = cat(doPeek_hi, doPeek_lo) node _doPeek_T_29 = and(idxHit, _doPeek_T_28) node doPeek = orr(_doPeek_T_29) node _io_ras_head_valid_T = eq(count, UInt<1>(0h0)) node _io_ras_head_valid_T_1 = eq(_io_ras_head_valid_T, UInt<1>(0h0)) connect io.ras_head.valid, _io_ras_head_valid_T_1 connect io.ras_head.bits, stack[pos] node _T_136 = eq(count, UInt<1>(0h0)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = and(_T_137, doPeek) when _T_138 : connect io.resp.bits.target, stack[pos] when io.ras_update.valid : node _T_139 = eq(io.ras_update.bits.cfiType, UInt<2>(0h2)) when _T_139 : node _T_140 = lt(count, UInt<3>(0h6)) when _T_140 : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 node _nextPos_T = lt(pos, UInt<3>(0h5)) node _nextPos_T_1 = or(UInt<1>(0h0), _nextPos_T) node _nextPos_T_2 = add(pos, UInt<1>(0h1)) node _nextPos_T_3 = tail(_nextPos_T_2, 1) node nextPos = mux(_nextPos_T_1, _nextPos_T_3, UInt<1>(0h0)) connect stack[nextPos], io.ras_update.bits.returnAddr connect pos, nextPos else : node _T_141 = eq(io.ras_update.bits.cfiType, UInt<2>(0h3)) when _T_141 : node _T_142 = eq(count, UInt<1>(0h0)) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _count_T_2 = sub(count, UInt<1>(0h1)) node _count_T_3 = tail(_count_T_2, 1) connect count, _count_T_3 node _pos_T = gt(pos, UInt<1>(0h0)) node _pos_T_1 = or(UInt<1>(0h0), _pos_T) node _pos_T_2 = sub(pos, UInt<1>(0h1)) node _pos_T_3 = tail(_pos_T_2, 1) node _pos_T_4 = mux(_pos_T_1, _pos_T_3, UInt<3>(0h5)) connect pos, _pos_T_4
module BTB( // @[BTB.scala:187:7] input clock, // @[BTB.scala:187:7] input reset, // @[BTB.scala:187:7] input [38:0] io_req_bits_addr, // @[BTB.scala:188:14] output io_resp_valid, // @[BTB.scala:188:14] output io_resp_bits_taken, // @[BTB.scala:188:14] output io_resp_bits_bridx, // @[BTB.scala:188:14] output [38:0] io_resp_bits_target, // @[BTB.scala:188:14] output [4:0] io_resp_bits_entry, // @[BTB.scala:188:14] output [7:0] io_resp_bits_bht_history, // @[BTB.scala:188:14] output io_resp_bits_bht_value, // @[BTB.scala:188:14] input io_btb_update_valid, // @[BTB.scala:188:14] input [4:0] io_btb_update_bits_prediction_entry, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_pc, // @[BTB.scala:188:14] input io_btb_update_bits_isValid, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_br_pc, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_cfiType, // @[BTB.scala:188:14] input io_bht_update_valid, // @[BTB.scala:188:14] input [7:0] io_bht_update_bits_prediction_history, // @[BTB.scala:188:14] input [38:0] io_bht_update_bits_pc, // @[BTB.scala:188:14] input io_bht_update_bits_branch, // @[BTB.scala:188:14] input io_bht_update_bits_taken, // @[BTB.scala:188:14] input io_bht_update_bits_mispredict, // @[BTB.scala:188:14] input io_bht_advance_valid, // @[BTB.scala:188:14] input io_bht_advance_bits_bht_value, // @[BTB.scala:188:14] input io_ras_update_valid, // @[BTB.scala:188:14] input [1:0] io_ras_update_bits_cfiType, // @[BTB.scala:188:14] input [38:0] io_ras_update_bits_returnAddr, // @[BTB.scala:188:14] output io_ras_head_valid, // @[BTB.scala:188:14] output [38:0] io_ras_head_bits, // @[BTB.scala:188:14] input io_flush // @[BTB.scala:188:14] ); wire _table_ext_R0_data; // @[BTB.scala:116:26] reg [12:0] idxs_0; // @[BTB.scala:199:17] reg [12:0] idxs_1; // @[BTB.scala:199:17] reg [12:0] idxs_2; // @[BTB.scala:199:17] reg [12:0] idxs_3; // @[BTB.scala:199:17] reg [12:0] idxs_4; // @[BTB.scala:199:17] reg [12:0] idxs_5; // @[BTB.scala:199:17] reg [12:0] idxs_6; // @[BTB.scala:199:17] reg [12:0] idxs_7; // @[BTB.scala:199:17] reg [12:0] idxs_8; // @[BTB.scala:199:17] reg [12:0] idxs_9; // @[BTB.scala:199:17] reg [12:0] idxs_10; // @[BTB.scala:199:17] reg [12:0] idxs_11; // @[BTB.scala:199:17] reg [12:0] idxs_12; // @[BTB.scala:199:17] reg [12:0] idxs_13; // @[BTB.scala:199:17] reg [12:0] idxs_14; // @[BTB.scala:199:17] reg [12:0] idxs_15; // @[BTB.scala:199:17] reg [12:0] idxs_16; // @[BTB.scala:199:17] reg [12:0] idxs_17; // @[BTB.scala:199:17] reg [12:0] idxs_18; // @[BTB.scala:199:17] reg [12:0] idxs_19; // @[BTB.scala:199:17] reg [12:0] idxs_20; // @[BTB.scala:199:17] reg [12:0] idxs_21; // @[BTB.scala:199:17] reg [12:0] idxs_22; // @[BTB.scala:199:17] reg [12:0] idxs_23; // @[BTB.scala:199:17] reg [12:0] idxs_24; // @[BTB.scala:199:17] reg [12:0] idxs_25; // @[BTB.scala:199:17] reg [12:0] idxs_26; // @[BTB.scala:199:17] reg [12:0] idxs_27; // @[BTB.scala:199:17] reg [2:0] idxPages_0; // @[BTB.scala:200:21] reg [2:0] idxPages_1; // @[BTB.scala:200:21] reg [2:0] idxPages_2; // @[BTB.scala:200:21] reg [2:0] idxPages_3; // @[BTB.scala:200:21] reg [2:0] idxPages_4; // @[BTB.scala:200:21] reg [2:0] idxPages_5; // @[BTB.scala:200:21] reg [2:0] idxPages_6; // @[BTB.scala:200:21] reg [2:0] idxPages_7; // @[BTB.scala:200:21] reg [2:0] idxPages_8; // @[BTB.scala:200:21] reg [2:0] idxPages_9; // @[BTB.scala:200:21] reg [2:0] idxPages_10; // @[BTB.scala:200:21] reg [2:0] idxPages_11; // @[BTB.scala:200:21] reg [2:0] idxPages_12; // @[BTB.scala:200:21] reg [2:0] idxPages_13; // @[BTB.scala:200:21] reg [2:0] idxPages_14; // @[BTB.scala:200:21] reg [2:0] idxPages_15; // @[BTB.scala:200:21] reg [2:0] idxPages_16; // @[BTB.scala:200:21] reg [2:0] idxPages_17; // @[BTB.scala:200:21] reg [2:0] idxPages_18; // @[BTB.scala:200:21] reg [2:0] idxPages_19; // @[BTB.scala:200:21] reg [2:0] idxPages_20; // @[BTB.scala:200:21] reg [2:0] idxPages_21; // @[BTB.scala:200:21] reg [2:0] idxPages_22; // @[BTB.scala:200:21] reg [2:0] idxPages_23; // @[BTB.scala:200:21] reg [2:0] idxPages_24; // @[BTB.scala:200:21] reg [2:0] idxPages_25; // @[BTB.scala:200:21] reg [2:0] idxPages_26; // @[BTB.scala:200:21] reg [2:0] idxPages_27; // @[BTB.scala:200:21] reg [12:0] tgts_0; // @[BTB.scala:201:17] reg [12:0] tgts_1; // @[BTB.scala:201:17] reg [12:0] tgts_2; // @[BTB.scala:201:17] reg [12:0] tgts_3; // @[BTB.scala:201:17] reg [12:0] tgts_4; // @[BTB.scala:201:17] reg [12:0] tgts_5; // @[BTB.scala:201:17] reg [12:0] tgts_6; // @[BTB.scala:201:17] reg [12:0] tgts_7; // @[BTB.scala:201:17] reg [12:0] tgts_8; // @[BTB.scala:201:17] reg [12:0] tgts_9; // @[BTB.scala:201:17] reg [12:0] tgts_10; // @[BTB.scala:201:17] reg [12:0] tgts_11; // @[BTB.scala:201:17] reg [12:0] tgts_12; // @[BTB.scala:201:17] reg [12:0] tgts_13; // @[BTB.scala:201:17] reg [12:0] tgts_14; // @[BTB.scala:201:17] reg [12:0] tgts_15; // @[BTB.scala:201:17] reg [12:0] tgts_16; // @[BTB.scala:201:17] reg [12:0] tgts_17; // @[BTB.scala:201:17] reg [12:0] tgts_18; // @[BTB.scala:201:17] reg [12:0] tgts_19; // @[BTB.scala:201:17] reg [12:0] tgts_20; // @[BTB.scala:201:17] reg [12:0] tgts_21; // @[BTB.scala:201:17] reg [12:0] tgts_22; // @[BTB.scala:201:17] reg [12:0] tgts_23; // @[BTB.scala:201:17] reg [12:0] tgts_24; // @[BTB.scala:201:17] reg [12:0] tgts_25; // @[BTB.scala:201:17] reg [12:0] tgts_26; // @[BTB.scala:201:17] reg [12:0] tgts_27; // @[BTB.scala:201:17] reg [2:0] tgtPages_0; // @[BTB.scala:202:21] reg [2:0] tgtPages_1; // @[BTB.scala:202:21] reg [2:0] tgtPages_2; // @[BTB.scala:202:21] reg [2:0] tgtPages_3; // @[BTB.scala:202:21] reg [2:0] tgtPages_4; // @[BTB.scala:202:21] reg [2:0] tgtPages_5; // @[BTB.scala:202:21] reg [2:0] tgtPages_6; // @[BTB.scala:202:21] reg [2:0] tgtPages_7; // @[BTB.scala:202:21] reg [2:0] tgtPages_8; // @[BTB.scala:202:21] reg [2:0] tgtPages_9; // @[BTB.scala:202:21] reg [2:0] tgtPages_10; // @[BTB.scala:202:21] reg [2:0] tgtPages_11; // @[BTB.scala:202:21] reg [2:0] tgtPages_12; // @[BTB.scala:202:21] reg [2:0] tgtPages_13; // @[BTB.scala:202:21] reg [2:0] tgtPages_14; // @[BTB.scala:202:21] reg [2:0] tgtPages_15; // @[BTB.scala:202:21] reg [2:0] tgtPages_16; // @[BTB.scala:202:21] reg [2:0] tgtPages_17; // @[BTB.scala:202:21] reg [2:0] tgtPages_18; // @[BTB.scala:202:21] reg [2:0] tgtPages_19; // @[BTB.scala:202:21] reg [2:0] tgtPages_20; // @[BTB.scala:202:21] reg [2:0] tgtPages_21; // @[BTB.scala:202:21] reg [2:0] tgtPages_22; // @[BTB.scala:202:21] reg [2:0] tgtPages_23; // @[BTB.scala:202:21] reg [2:0] tgtPages_24; // @[BTB.scala:202:21] reg [2:0] tgtPages_25; // @[BTB.scala:202:21] reg [2:0] tgtPages_26; // @[BTB.scala:202:21] reg [2:0] tgtPages_27; // @[BTB.scala:202:21] reg [24:0] pages_0; // @[BTB.scala:203:18] reg [24:0] pages_1; // @[BTB.scala:203:18] reg [24:0] pages_2; // @[BTB.scala:203:18] reg [24:0] pages_3; // @[BTB.scala:203:18] reg [24:0] pages_4; // @[BTB.scala:203:18] reg [24:0] pages_5; // @[BTB.scala:203:18] reg [5:0] pageValid; // @[BTB.scala:204:26] wire [24:0] pagesMasked_4 = pageValid[4] ? pages_4 : 25'h0; // @[BTB.scala:203:18, :204:26, :205:{32,75}] wire [24:0] pagesMasked_5 = pageValid[5] ? pages_5 : 25'h0; // @[BTB.scala:203:18, :204:26, :205:{32,75}] reg [27:0] isValid; // @[BTB.scala:207:24] reg [1:0] cfiType_0; // @[BTB.scala:208:20] reg [1:0] cfiType_1; // @[BTB.scala:208:20] reg [1:0] cfiType_2; // @[BTB.scala:208:20] reg [1:0] cfiType_3; // @[BTB.scala:208:20] reg [1:0] cfiType_4; // @[BTB.scala:208:20] reg [1:0] cfiType_5; // @[BTB.scala:208:20] reg [1:0] cfiType_6; // @[BTB.scala:208:20] reg [1:0] cfiType_7; // @[BTB.scala:208:20] reg [1:0] cfiType_8; // @[BTB.scala:208:20] reg [1:0] cfiType_9; // @[BTB.scala:208:20] reg [1:0] cfiType_10; // @[BTB.scala:208:20] reg [1:0] cfiType_11; // @[BTB.scala:208:20] reg [1:0] cfiType_12; // @[BTB.scala:208:20] reg [1:0] cfiType_13; // @[BTB.scala:208:20] reg [1:0] cfiType_14; // @[BTB.scala:208:20] reg [1:0] cfiType_15; // @[BTB.scala:208:20] reg [1:0] cfiType_16; // @[BTB.scala:208:20] reg [1:0] cfiType_17; // @[BTB.scala:208:20] reg [1:0] cfiType_18; // @[BTB.scala:208:20] reg [1:0] cfiType_19; // @[BTB.scala:208:20] reg [1:0] cfiType_20; // @[BTB.scala:208:20] reg [1:0] cfiType_21; // @[BTB.scala:208:20] reg [1:0] cfiType_22; // @[BTB.scala:208:20] reg [1:0] cfiType_23; // @[BTB.scala:208:20] reg [1:0] cfiType_24; // @[BTB.scala:208:20] reg [1:0] cfiType_25; // @[BTB.scala:208:20] reg [1:0] cfiType_26; // @[BTB.scala:208:20] reg [1:0] cfiType_27; // @[BTB.scala:208:20] reg brIdx_0; // @[BTB.scala:209:18] reg brIdx_1; // @[BTB.scala:209:18] reg brIdx_2; // @[BTB.scala:209:18] reg brIdx_3; // @[BTB.scala:209:18] reg brIdx_4; // @[BTB.scala:209:18] reg brIdx_5; // @[BTB.scala:209:18] reg brIdx_6; // @[BTB.scala:209:18] reg brIdx_7; // @[BTB.scala:209:18] reg brIdx_8; // @[BTB.scala:209:18] reg brIdx_9; // @[BTB.scala:209:18] reg brIdx_10; // @[BTB.scala:209:18] reg brIdx_11; // @[BTB.scala:209:18] reg brIdx_12; // @[BTB.scala:209:18] reg brIdx_13; // @[BTB.scala:209:18] reg brIdx_14; // @[BTB.scala:209:18] reg brIdx_15; // @[BTB.scala:209:18] reg brIdx_16; // @[BTB.scala:209:18] reg brIdx_17; // @[BTB.scala:209:18] reg brIdx_18; // @[BTB.scala:209:18] reg brIdx_19; // @[BTB.scala:209:18] reg brIdx_20; // @[BTB.scala:209:18] reg brIdx_21; // @[BTB.scala:209:18] reg brIdx_22; // @[BTB.scala:209:18] reg brIdx_23; // @[BTB.scala:209:18] reg brIdx_24; // @[BTB.scala:209:18] reg brIdx_25; // @[BTB.scala:209:18] reg brIdx_26; // @[BTB.scala:209:18] reg brIdx_27; // @[BTB.scala:209:18] reg r_btb_update_pipe_v; // @[Valid.scala:141:24] reg [4:0] r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:142:26] reg [38:0] r_btb_update_pipe_b_pc; // @[Valid.scala:142:26] reg r_btb_update_pipe_b_isValid; // @[Valid.scala:142:26] reg [38:0] r_btb_update_pipe_b_br_pc; // @[Valid.scala:142:26] reg [1:0] r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] wire _pageHit_T = pages_0 == io_req_bits_addr[38:14]; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_1 = pages_1 == io_req_bits_addr[38:14]; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_2 = pages_2 == io_req_bits_addr[38:14]; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_3 = pages_3 == io_req_bits_addr[38:14]; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_4 = pages_4 == io_req_bits_addr[38:14]; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_5 = pages_5 == io_req_bits_addr[38:14]; // @[BTB.scala:203:18, :211:39, :214:29] wire [5:0] pageHit = pageValid & {_pageHit_T_5, _pageHit_T_4, _pageHit_T_3, _pageHit_T_2, _pageHit_T_1, _pageHit_T}; // @[package.scala:45:27] wire _idxHit_T = idxs_0 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_1 = idxs_1 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_2 = idxs_2 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_3 = idxs_3 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_4 = idxs_4 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_5 = idxs_5 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_6 = idxs_6 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_7 = idxs_7 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_8 = idxs_8 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_9 = idxs_9 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_10 = idxs_10 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_11 = idxs_11 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_12 = idxs_12 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_13 = idxs_13 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_14 = idxs_14 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_15 = idxs_15 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_16 = idxs_16 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_17 = idxs_17 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_18 = idxs_18 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_19 = idxs_19 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_20 = idxs_20 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_21 = idxs_21 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_22 = idxs_22 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_23 = idxs_23 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_24 = idxs_24 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_25 = idxs_25 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_26 = idxs_26 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_27 = idxs_27 == io_req_bits_addr[13:1]; // @[BTB.scala:199:17, :217:19, :218:16] wire [27:0] idxHit = {_idxHit_T_27, _idxHit_T_26, _idxHit_T_25, _idxHit_T_24, _idxHit_T_23, _idxHit_T_22, _idxHit_T_21, _idxHit_T_20, _idxHit_T_19, _idxHit_T_18, _idxHit_T_17, _idxHit_T_16, _idxHit_T_15, _idxHit_T_14, _idxHit_T_13, _idxHit_T_12, _idxHit_T_11, _idxHit_T_10, _idxHit_T_9, _idxHit_T_8, _idxHit_T_7, _idxHit_T_6, _idxHit_T_5, _idxHit_T_4, _idxHit_T_3, _idxHit_T_2, _idxHit_T_1, _idxHit_T} & isValid; // @[package.scala:45:27] reg [2:0] nextPageRepl; // @[BTB.scala:237:29] reg [26:0] state_reg; // @[Replacement.scala:168:70] reg r_resp_pipe_v; // @[Valid.scala:141:24] reg r_resp_pipe_b_taken; // @[Valid.scala:142:26] reg [4:0] r_resp_pipe_b_entry; // @[Valid.scala:142:26] wire _io_resp_bits_cfiType_T = _idxHit_T & isValid[0]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_1 = _idxHit_T_1 & isValid[1]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_2 = _idxHit_T_2 & isValid[2]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_3 = _idxHit_T_3 & isValid[3]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_4 = _idxHit_T_4 & isValid[4]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_5 = _idxHit_T_5 & isValid[5]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_6 = _idxHit_T_6 & isValid[6]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_7 = _idxHit_T_7 & isValid[7]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_8 = _idxHit_T_8 & isValid[8]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_9 = _idxHit_T_9 & isValid[9]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_10 = _idxHit_T_10 & isValid[10]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_11 = _idxHit_T_11 & isValid[11]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_12 = _idxHit_T_12 & isValid[12]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_13 = _idxHit_T_13 & isValid[13]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_14 = _idxHit_T_14 & isValid[14]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_15 = _idxHit_T_15 & isValid[15]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_16 = _idxHit_T_16 & isValid[16]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_17 = _idxHit_T_17 & isValid[17]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_18 = _idxHit_T_18 & isValid[18]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_19 = _idxHit_T_19 & isValid[19]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_20 = _idxHit_T_20 & isValid[20]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_21 = _idxHit_T_21 & isValid[21]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_22 = _idxHit_T_22 & isValid[22]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_23 = _idxHit_T_23 & isValid[23]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_24 = _idxHit_T_24 & isValid[24]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_25 = _idxHit_T_25 & isValid[25]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_26 = _idxHit_T_26 & isValid[26]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_27 = _idxHit_T_27 & isValid[27]; // @[Mux.scala:32:36] wire [6:0] _io_resp_valid_T_84 = {pageHit, 1'h0} >> ((_io_resp_bits_cfiType_T ? idxPages_0 : 3'h0) | (_io_resp_bits_cfiType_T_1 ? idxPages_1 : 3'h0) | (_io_resp_bits_cfiType_T_2 ? idxPages_2 : 3'h0) | (_io_resp_bits_cfiType_T_3 ? idxPages_3 : 3'h0) | (_io_resp_bits_cfiType_T_4 ? idxPages_4 : 3'h0) | (_io_resp_bits_cfiType_T_5 ? idxPages_5 : 3'h0) | (_io_resp_bits_cfiType_T_6 ? idxPages_6 : 3'h0) | (_io_resp_bits_cfiType_T_7 ? idxPages_7 : 3'h0) | (_io_resp_bits_cfiType_T_8 ? idxPages_8 : 3'h0) | (_io_resp_bits_cfiType_T_9 ? idxPages_9 : 3'h0) | (_io_resp_bits_cfiType_T_10 ? idxPages_10 : 3'h0) | (_io_resp_bits_cfiType_T_11 ? idxPages_11 : 3'h0) | (_io_resp_bits_cfiType_T_12 ? idxPages_12 : 3'h0) | (_io_resp_bits_cfiType_T_13 ? idxPages_13 : 3'h0) | (_io_resp_bits_cfiType_T_14 ? idxPages_14 : 3'h0) | (_io_resp_bits_cfiType_T_15 ? idxPages_15 : 3'h0) | (_io_resp_bits_cfiType_T_16 ? idxPages_16 : 3'h0) | (_io_resp_bits_cfiType_T_17 ? idxPages_17 : 3'h0) | (_io_resp_bits_cfiType_T_18 ? idxPages_18 : 3'h0) | (_io_resp_bits_cfiType_T_19 ? idxPages_19 : 3'h0) | (_io_resp_bits_cfiType_T_20 ? idxPages_20 : 3'h0) | (_io_resp_bits_cfiType_T_21 ? idxPages_21 : 3'h0) | (_io_resp_bits_cfiType_T_22 ? idxPages_22 : 3'h0) | (_io_resp_bits_cfiType_T_23 ? idxPages_23 : 3'h0) | (_io_resp_bits_cfiType_T_24 ? idxPages_24 : 3'h0) | (_io_resp_bits_cfiType_T_25 ? idxPages_25 : 3'h0) | (_io_resp_bits_cfiType_T_26 ? idxPages_26 : 3'h0) | (_io_resp_bits_cfiType_T_27 ? idxPages_27 : 3'h0)); // @[Mux.scala:30:73, :32:36] wire [7:0][24:0] _GEN = {{pagesMasked_5}, {pagesMasked_4}, {pagesMasked_5}, {pagesMasked_4}, {pageValid[3] ? pages_3 : 25'h0}, {pageValid[2] ? pages_2 : 25'h0}, {pageValid[1] ? pages_1 : 25'h0}, {pageValid[0] ? pages_0 : 25'h0}}; // @[package.scala:39:{76,86}] wire [11:0] io_resp_bits_entry_hi = {_idxHit_T_27, _idxHit_T_26, _idxHit_T_25, _idxHit_T_24, _idxHit_T_23, _idxHit_T_22, _idxHit_T_21, _idxHit_T_20, _idxHit_T_19, _idxHit_T_18, _idxHit_T_17, _idxHit_T_16} & isValid[27:16]; // @[OneHot.scala:30:18] wire [14:0] _io_resp_bits_entry_T_1 = {4'h0, io_resp_bits_entry_hi[11:1]} | {_idxHit_T_15, _idxHit_T_14, _idxHit_T_13, _idxHit_T_12, _idxHit_T_11, _idxHit_T_10, _idxHit_T_9, _idxHit_T_8, _idxHit_T_7, _idxHit_T_6, _idxHit_T_5, _idxHit_T_4, _idxHit_T_3, _idxHit_T_2, _idxHit_T_1} & isValid[15:1]; // @[OneHot.scala:30:18, :31:18, :32:{14,28}] wire [6:0] _io_resp_bits_entry_T_3 = _io_resp_bits_entry_T_1[14:8] | _io_resp_bits_entry_T_1[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _io_resp_bits_entry_T_5 = _io_resp_bits_entry_T_3[6:4] | _io_resp_bits_entry_T_3[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] io_resp_bits_entry_0 = {|io_resp_bits_entry_hi, |(_io_resp_bits_entry_T_1[14:7]), |(_io_resp_bits_entry_T_3[6:3]), |(_io_resp_bits_entry_T_5[2:1]), _io_resp_bits_entry_T_5[2] | _io_resp_bits_entry_T_5[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] reg [7:0] history; // @[BTB.scala:117:24] reg [9:0] reset_waddr; // @[BTB.scala:119:36] wire [7:0] _res_res_value_T_4 = history * 8'hDD; // @[BTB.scala:82:12, :117:24] wire res_value = reset_waddr[9] & _table_ext_R0_data; // @[BTB.scala:92:21, :116:26, :119:36, :120:39] wire _GEN_0 = io_bht_update_valid & io_bht_update_bits_branch; // @[BTB.scala:97:9, :121:29, :310:32, :311:40] wire [7:0] _waddr_T_44 = io_bht_update_bits_prediction_history * 8'hDD; // @[BTB.scala:82:12] wire _GEN_1 = ~res_value & (|(idxHit & {cfiType_27 == 2'h0, cfiType_26 == 2'h0, cfiType_25 == 2'h0, cfiType_24 == 2'h0, cfiType_23 == 2'h0, cfiType_22 == 2'h0, cfiType_21 == 2'h0, cfiType_20 == 2'h0, cfiType_19 == 2'h0, cfiType_18 == 2'h0, cfiType_17 == 2'h0, cfiType_16 == 2'h0, cfiType_15 == 2'h0, cfiType_14 == 2'h0, cfiType_13 == 2'h0, cfiType_12 == 2'h0, cfiType_11 == 2'h0, cfiType_10 == 2'h0, cfiType_9 == 2'h0, cfiType_8 == 2'h0, cfiType_7 == 2'h0, cfiType_6 == 2'h0, cfiType_5 == 2'h0, cfiType_4 == 2'h0, cfiType_3 == 2'h0, cfiType_2 == 2'h0, cfiType_1 == 2'h0, cfiType_0 == 2'h0})); // @[package.scala:45:27] reg [2:0] count; // @[BTB.scala:56:30] reg [2:0] pos; // @[BTB.scala:57:28] reg [38:0] stack_0; // @[BTB.scala:58:26] reg [38:0] stack_1; // @[BTB.scala:58:26] reg [38:0] stack_2; // @[BTB.scala:58:26] reg [38:0] stack_3; // @[BTB.scala:58:26] reg [38:0] stack_4; // @[BTB.scala:58:26] reg [38:0] stack_5; // @[BTB.scala:58:26] wire [7:0][38:0] _GEN_2 = {{stack_0}, {stack_0}, {stack_5}, {stack_4}, {stack_3}, {stack_2}, {stack_1}, {stack_0}}; // @[BTB.scala:58:26, :328:22] wire [38:0] io_ras_head_bits_0 = _GEN_2[pos]; // @[BTB.scala:57:28, :328:22] wire leftOne = _idxHit_T & isValid[0]; // @[Mux.scala:32:36] wire leftOne_1 = _idxHit_T_1 & isValid[1]; // @[Mux.scala:32:36] wire rightOne = _idxHit_T_2 & isValid[2]; // @[Mux.scala:32:36] wire rightOne_1 = leftOne_1 | rightOne; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_2 = leftOne | rightOne_1; // @[Misc.scala:181:37, :183:16] wire leftOne_3 = _idxHit_T_3 & isValid[3]; // @[Mux.scala:32:36] wire rightOne_2 = _idxHit_T_4 & isValid[4]; // @[Mux.scala:32:36] wire leftOne_4 = leftOne_3 | rightOne_2; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_5 = _idxHit_T_5 & isValid[5]; // @[Mux.scala:32:36] wire rightOne_3 = _idxHit_T_6 & isValid[6]; // @[Mux.scala:32:36] wire rightOne_4 = leftOne_5 | rightOne_3; // @[Misc.scala:181:37, :182:39, :183:16] wire rightOne_5 = leftOne_4 | rightOne_4; // @[Misc.scala:183:16] wire leftOne_6 = leftOne_2 | rightOne_5; // @[Misc.scala:183:16] wire leftOne_7 = _idxHit_T_7 & isValid[7]; // @[Mux.scala:32:36] wire leftOne_8 = _idxHit_T_8 & isValid[8]; // @[Mux.scala:32:36] wire rightOne_6 = _idxHit_T_9 & isValid[9]; // @[Mux.scala:32:36] wire rightOne_7 = leftOne_8 | rightOne_6; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_9 = leftOne_7 | rightOne_7; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_10 = _idxHit_T_10 & isValid[10]; // @[Mux.scala:32:36] wire rightOne_8 = _idxHit_T_11 & isValid[11]; // @[Mux.scala:32:36] wire leftOne_11 = leftOne_10 | rightOne_8; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_12 = _idxHit_T_12 & isValid[12]; // @[Mux.scala:32:36] wire rightOne_9 = _idxHit_T_13 & isValid[13]; // @[Mux.scala:32:36] wire rightOne_10 = leftOne_12 | rightOne_9; // @[Misc.scala:181:37, :182:39, :183:16] wire rightOne_11 = leftOne_11 | rightOne_10; // @[Misc.scala:183:16] wire rightOne_12 = leftOne_9 | rightOne_11; // @[Misc.scala:183:16] wire leftOne_14 = _idxHit_T_14 & isValid[14]; // @[Mux.scala:32:36] wire leftOne_15 = _idxHit_T_15 & isValid[15]; // @[Mux.scala:32:36] wire rightOne_13 = _idxHit_T_16 & isValid[16]; // @[Mux.scala:32:36] wire rightOne_14 = leftOne_15 | rightOne_13; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_16 = leftOne_14 | rightOne_14; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_17 = _idxHit_T_17 & isValid[17]; // @[Mux.scala:32:36] wire rightOne_15 = _idxHit_T_18 & isValid[18]; // @[Mux.scala:32:36] wire leftOne_18 = leftOne_17 | rightOne_15; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_19 = _idxHit_T_19 & isValid[19]; // @[Mux.scala:32:36] wire rightOne_16 = _idxHit_T_20 & isValid[20]; // @[Mux.scala:32:36] wire rightOne_17 = leftOne_19 | rightOne_16; // @[Misc.scala:181:37, :182:39, :183:16] wire rightOne_18 = leftOne_18 | rightOne_17; // @[Misc.scala:183:16] wire leftOne_20 = leftOne_16 | rightOne_18; // @[Misc.scala:183:16] wire leftOne_21 = _idxHit_T_21 & isValid[21]; // @[Mux.scala:32:36] wire leftOne_22 = _idxHit_T_22 & isValid[22]; // @[Mux.scala:32:36] wire rightOne_19 = _idxHit_T_23 & isValid[23]; // @[Mux.scala:32:36] wire rightOne_20 = leftOne_22 | rightOne_19; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_23 = leftOne_21 | rightOne_20; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_24 = _idxHit_T_24 & isValid[24]; // @[Mux.scala:32:36] wire rightOne_21 = _idxHit_T_25 & isValid[25]; // @[Mux.scala:32:36] wire leftOne_25 = leftOne_24 | rightOne_21; // @[Misc.scala:181:37, :182:39, :183:16] wire leftOne_26 = _idxHit_T_26 & isValid[26]; // @[Mux.scala:32:36] wire rightOne_22 = _idxHit_T_27 & isValid[27]; // @[Mux.scala:32:36] wire rightOne_23 = leftOne_26 | rightOne_22; // @[Misc.scala:181:37, :182:39, :183:16] wire rightOne_24 = leftOne_25 | rightOne_23; // @[Misc.scala:183:16] wire rightOne_25 = leftOne_23 | rightOne_24; // @[Misc.scala:183:16] wire [5:0] updatePageHit = pageValid & {pages_5 == r_btb_update_pipe_b_pc[38:14], pages_4 == r_btb_update_pipe_b_pc[38:14], pages_3 == r_btb_update_pipe_b_pc[38:14], pages_2 == r_btb_update_pipe_b_pc[38:14], pages_1 == r_btb_update_pipe_b_pc[38:14], pages_0 == r_btb_update_pipe_b_pc[38:14]}; // @[Valid.scala:142:26] wire [7:0] idxPageRepl = {2'h0, pageValid[4:0] & {_pageHit_T_4, _pageHit_T_3, _pageHit_T_2, _pageHit_T_1, _pageHit_T}, pageValid[5] & _pageHit_T_5} | ((|pageHit) ? 8'h0 : 8'h1 << nextPageRepl); // @[OneHot.scala:58:35] wire [7:0] idxPageUpdateOH = (|updatePageHit) ? {2'h0, updatePageHit} : idxPageRepl; // @[BTB.scala:214:15, :234:40, :238:65, :239:28] wire [2:0] _idxPageUpdate_T_1 = idxPageUpdateOH[7:5] | idxPageUpdateOH[3:1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _idxPageUpdate_T_3 = _idxPageUpdate_T_1[2] | _idxPageUpdate_T_1[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [5:0] idxPageReplEn = (|updatePageHit) ? 6'h0 : idxPageRepl[5:0]; // @[BTB.scala:187:7, :214:15, :234:40, :238:65, :241:26] wire doTgtPageRepl = r_btb_update_pipe_b_pc[38:14] != io_req_bits_addr[38:14] & ~(|pageHit); // @[Valid.scala:142:26] wire [7:0] tgtPageRepl = r_btb_update_pipe_b_pc[38:14] == io_req_bits_addr[38:14] ? idxPageUpdateOH : {2'h0, idxPageUpdateOH[4:0], idxPageUpdateOH[5]}; // @[Valid.scala:142:26] wire [6:0] _tgtPageUpdate_T_1 = {2'h0, pageHit[5:1]} | ((|pageHit) ? 7'h0 : tgtPageRepl[7:1]); // @[BTB.scala:214:15, :235:28, :238:65, :245:24, :246:{40,45}] wire [2:0] _tgtPageUpdate_T_3 = _tgtPageUpdate_T_1[6:4] | _tgtPageUpdate_T_1[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] tgtPageUpdate = {|(_tgtPageUpdate_T_1[6:3]), |(_tgtPageUpdate_T_3[2:1]), _tgtPageUpdate_T_3[2] | _tgtPageUpdate_T_3[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire [5:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl[5:0] : 6'h0; // @[BTB.scala:187:7, :244:33, :245:24, :247:26] wire [4:0] waddr = r_btb_update_pipe_b_prediction_entry[4:2] != 3'h7 ? r_btb_update_pipe_b_prediction_entry : {state_reg[26], state_reg[26] ? {state_reg[25], state_reg[25] ? {1'h0, state_reg[24], state_reg[24] ? state_reg[23] : state_reg[22]} : {state_reg[21], state_reg[21] ? {state_reg[20], state_reg[20] ? state_reg[19] : state_reg[18]} : {state_reg[17], state_reg[17] ? state_reg[16] : state_reg[15]}}} : {state_reg[14], state_reg[14] ? {state_reg[13], state_reg[13] ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]} : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}} : {state_reg[6], state_reg[6] ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}}; // @[Valid.scala:142:26] wire [2:0] _idxPages_T = {|(idxPageUpdateOH[7:4]), |(_idxPageUpdate_T_1[2:1]), _idxPageUpdate_T_3} + 3'h1; // @[OneHot.scala:30:18, :32:{14,28}] wire [4:0] _GEN_3 = _idxPageUpdate_T_3 ? tgtPageReplEn[4:0] : idxPageReplEn[4:0]; // @[OneHot.scala:32:28] wire [24:0] _GEN_4 = _idxPageUpdate_T_3 ? io_req_bits_addr[38:14] : r_btb_update_pipe_b_pc[38:14]; // @[Valid.scala:142:26] wire [4:0] _GEN_5 = _idxPageUpdate_T_3 ? idxPageReplEn[5:1] : tgtPageReplEn[5:1]; // @[OneHot.scala:32:28] wire [24:0] _GEN_6 = _idxPageUpdate_T_3 ? r_btb_update_pipe_b_pc[38:14] : io_req_bits_addr[38:14]; // @[Valid.scala:142:26] wire _GEN_7 = io_ras_update_bits_cfiType == 2'h2; // @[BTB.scala:333:40] wire [2:0] nextPos = pos < 3'h5 ? pos + 3'h1 : 3'h0; // @[BTB.scala:44:{22,47,64}, :51:40, :57:28] wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala:58:35] wire [2:0] _next_T_1 = nextPageRepl + {1'h0, ~(|updatePageHit) & doTgtPageRepl ? 2'h2 : 2'h1}; // @[BTB.scala:214:15, :234:40, :236:23, :237:29, :244:33, :250:30, :251:{29,40}] wire [4:0] state_reg_touch_way_sized = r_btb_update_pipe_v ? waddr : r_resp_pipe_b_entry; // @[Valid.scala:141:24, :142:26] always @(posedge clock) begin // @[BTB.scala:187:7] if (r_btb_update_pipe_v & waddr == 5'h0) begin // @[Valid.scala:141:24] idxs_0 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_0 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_0 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_0 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_0 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_0 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h1) begin // @[Valid.scala:141:24] idxs_1 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_1 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_1 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_1 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_1 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_1 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h2) begin // @[Valid.scala:141:24] idxs_2 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_2 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_2 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_2 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_2 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_2 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h3) begin // @[Valid.scala:141:24] idxs_3 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_3 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_3 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_3 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_3 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_3 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h4) begin // @[Valid.scala:141:24] idxs_4 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_4 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_4 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_4 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_4 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_4 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h5) begin // @[Valid.scala:141:24] idxs_5 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_5 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_5 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_5 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_5 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_5 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h6) begin // @[Valid.scala:141:24] idxs_6 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_6 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_6 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_6 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_6 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_6 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h7) begin // @[Valid.scala:141:24] idxs_7 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_7 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_7 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_7 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_7 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_7 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h8) begin // @[Valid.scala:141:24] idxs_8 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_8 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_8 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_8 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_8 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_8 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h9) begin // @[Valid.scala:141:24] idxs_9 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_9 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_9 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_9 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_9 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_9 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'hA) begin // @[Valid.scala:141:24] idxs_10 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_10 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_10 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_10 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_10 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_10 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'hB) begin // @[Valid.scala:141:24] idxs_11 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_11 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_11 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_11 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_11 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_11 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'hC) begin // @[Valid.scala:141:24] idxs_12 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_12 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_12 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_12 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_12 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_12 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'hD) begin // @[Valid.scala:141:24] idxs_13 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_13 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_13 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_13 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_13 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_13 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'hE) begin // @[Valid.scala:141:24] idxs_14 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_14 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_14 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_14 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_14 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_14 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'hF) begin // @[Valid.scala:141:24] idxs_15 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_15 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_15 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_15 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_15 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_15 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h10) begin // @[Valid.scala:141:24] idxs_16 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_16 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_16 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_16 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_16 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_16 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h11) begin // @[Valid.scala:141:24] idxs_17 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_17 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_17 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_17 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_17 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_17 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h12) begin // @[Valid.scala:141:24] idxs_18 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_18 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_18 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_18 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_18 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_18 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h13) begin // @[Valid.scala:141:24] idxs_19 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_19 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_19 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_19 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_19 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_19 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h14) begin // @[Valid.scala:141:24] idxs_20 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_20 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_20 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_20 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_20 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_20 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h15) begin // @[Valid.scala:141:24] idxs_21 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_21 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_21 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_21 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_21 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_21 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h16) begin // @[Valid.scala:141:24] idxs_22 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_22 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_22 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_22 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_22 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_22 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h17) begin // @[Valid.scala:141:24] idxs_23 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_23 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_23 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_23 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_23 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_23 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h18) begin // @[Valid.scala:141:24] idxs_24 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_24 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_24 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_24 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_24 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_24 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h19) begin // @[Valid.scala:141:24] idxs_25 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_25 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_25 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_25 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_25 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_25 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h1A) begin // @[Valid.scala:141:24] idxs_26 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_26 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_26 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_26 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_26 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_26 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & waddr == 5'h1B) begin // @[Valid.scala:141:24] idxs_27 <= r_btb_update_pipe_b_pc[13:1]; // @[Valid.scala:142:26] idxPages_27 <= _idxPages_T; // @[BTB.scala:200:21, :266:38] tgts_27 <= io_req_bits_addr[13:1]; // @[BTB.scala:201:17, :217:19] tgtPages_27 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_27 <= r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] brIdx_27 <= r_btb_update_pipe_b_br_pc[1]; // @[Valid.scala:142:26] end if (r_btb_update_pipe_v & _GEN_3[0]) // @[Valid.scala:141:24] pages_0 <= _GEN_4; // @[BTB.scala:203:18, :281:10] if (r_btb_update_pipe_v & _GEN_5[0]) // @[Valid.scala:141:24] pages_1 <= _GEN_6; // @[BTB.scala:203:18, :283:10] if (r_btb_update_pipe_v & _GEN_3[2]) // @[Valid.scala:141:24] pages_2 <= _GEN_4; // @[BTB.scala:203:18, :281:10] if (r_btb_update_pipe_v & _GEN_5[2]) // @[Valid.scala:141:24] pages_3 <= _GEN_6; // @[BTB.scala:203:18, :283:10] if (r_btb_update_pipe_v & _GEN_3[4]) // @[Valid.scala:141:24] pages_4 <= _GEN_4; // @[BTB.scala:203:18, :281:10] if (r_btb_update_pipe_v & _GEN_5[4]) // @[Valid.scala:141:24] pages_5 <= _GEN_6; // @[BTB.scala:203:18, :283:10] if (io_btb_update_valid) begin // @[BTB.scala:188:14] r_btb_update_pipe_b_prediction_entry <= io_btb_update_bits_prediction_entry; // @[Valid.scala:142:26] r_btb_update_pipe_b_pc <= io_btb_update_bits_pc; // @[Valid.scala:142:26] r_btb_update_pipe_b_isValid <= io_btb_update_bits_isValid; // @[Valid.scala:142:26] r_btb_update_pipe_b_br_pc <= io_btb_update_bits_br_pc; // @[Valid.scala:142:26] r_btb_update_pipe_b_cfiType <= io_btb_update_bits_cfiType; // @[Valid.scala:142:26] end if (_io_resp_valid_T_84[0]) begin // @[BTB.scala:287:34] r_resp_pipe_b_taken <= ~_GEN_1; // @[Valid.scala:142:26] r_resp_pipe_b_entry <= io_resp_bits_entry_0; // @[Valid.scala:142:26] end if (io_ras_update_valid & _GEN_7 & nextPos == 3'h0) // @[BTB.scala:44:22, :45:20, :51:40, :58:26, :332:32, :333:{40,58}] stack_0 <= io_ras_update_bits_returnAddr; // @[BTB.scala:58:26] if (io_ras_update_valid & _GEN_7 & nextPos == 3'h1) // @[BTB.scala:44:22, :45:20, :58:26, :332:32, :333:{40,58}] stack_1 <= io_ras_update_bits_returnAddr; // @[BTB.scala:58:26] if (io_ras_update_valid & _GEN_7 & nextPos == 3'h2) // @[package.scala:39:86] stack_2 <= io_ras_update_bits_returnAddr; // @[BTB.scala:58:26] if (io_ras_update_valid & _GEN_7 & nextPos == 3'h3) // @[package.scala:39:86] stack_3 <= io_ras_update_bits_returnAddr; // @[BTB.scala:58:26] if (io_ras_update_valid & _GEN_7 & nextPos == 3'h4) // @[BTB.scala:44:22, :45:20, :58:26, :332:32, :333:{40,58}] stack_4 <= io_ras_update_bits_returnAddr; // @[BTB.scala:58:26] if (io_ras_update_valid & _GEN_7 & nextPos == 3'h5) // @[BTB.scala:44:22, :45:20, :58:26, :332:32, :333:{40,58}] stack_5 <= io_ras_update_bits_returnAddr; // @[BTB.scala:58:26] if (reset) begin // @[BTB.scala:187:7] pageValid <= 6'h0; // @[BTB.scala:187:7, :204:26] isValid <= 28'h0; // @[BTB.scala:207:24] r_btb_update_pipe_v <= 1'h0; // @[Valid.scala:141:24] nextPageRepl <= 3'h0; // @[BTB.scala:51:40, :237:29] state_reg <= 27'h0; // @[Replacement.scala:168:70] r_resp_pipe_v <= 1'h0; // @[Valid.scala:141:24] history <= 8'h0; // @[BTB.scala:117:24] reset_waddr <= 10'h0; // @[BTB.scala:119:36] count <= 3'h0; // @[BTB.scala:51:40, :56:30] pos <= 3'h0; // @[BTB.scala:51:40, :57:28] end else begin // @[BTB.scala:187:7] pageValid <= {6{r_btb_update_pipe_v}} & (tgtPageReplEn | idxPageReplEn) | pageValid; // @[Valid.scala:141:24] if (io_flush) // @[BTB.scala:188:14] isValid <= 28'h0; // @[BTB.scala:207:24] else if (leftOne_1 & rightOne | leftOne & rightOne_1 | leftOne_3 & rightOne_2 | leftOne_5 & rightOne_3 | leftOne_4 & rightOne_4 | leftOne_2 & rightOne_5 | leftOne_8 & rightOne_6 | leftOne_7 & rightOne_7 | leftOne_10 & rightOne_8 | leftOne_12 & rightOne_9 | leftOne_11 & rightOne_10 | leftOne_9 & rightOne_11 | leftOne_6 & rightOne_12 | leftOne_15 & rightOne_13 | leftOne_14 & rightOne_14 | leftOne_17 & rightOne_15 | leftOne_19 & rightOne_16 | leftOne_18 & rightOne_17 | leftOne_16 & rightOne_18 | leftOne_22 & rightOne_19 | leftOne_21 & rightOne_20 | leftOne_24 & rightOne_21 | leftOne_26 & rightOne_22 | leftOne_25 & rightOne_23 | leftOne_23 & rightOne_24 | leftOne_20 & rightOne_25 | (leftOne_6 | rightOne_12) & (leftOne_20 | rightOne_25)) // @[Misc.scala:181:37, :182:39, :183:{16,37,49,61}] isValid <= isValid & ~idxHit; // @[BTB.scala:207:24, :218:32, :297:{24,26}] else if (r_btb_update_pipe_v) // @[Valid.scala:141:24] isValid <= r_btb_update_pipe_b_isValid ? isValid | mask[27:0] : ~(mask[27:0]) & isValid; // @[Valid.scala:142:26] r_btb_update_pipe_v <= io_btb_update_valid; // @[Valid.scala:141:24] if (r_btb_update_pipe_v & (~(|updatePageHit) | doTgtPageRepl)) // @[Valid.scala:141:24] nextPageRepl <= _next_T_1 > 3'h5 ? {2'h0, _next_T_1[0]} : _next_T_1; // @[BTB.scala:237:29, :238:65, :251:29, :252:{24,30,47}] if (r_resp_pipe_v & r_resp_pipe_b_taken | r_btb_update_pipe_v) // @[Valid.scala:141:24, :142:26] state_reg <= {~(state_reg_touch_way_sized[4]), state_reg_touch_way_sized[4] ? {~(state_reg_touch_way_sized[3]), state_reg_touch_way_sized[3] ? {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[23], state_reg_touch_way_sized[1] ? state_reg[22] : ~(state_reg_touch_way_sized[0])} : state_reg[24:22], state_reg_touch_way_sized[3] ? state_reg[21:15] : {~(state_reg_touch_way_sized[2]), state_reg_touch_way_sized[2] ? {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[19], state_reg_touch_way_sized[1] ? state_reg[18] : ~(state_reg_touch_way_sized[0])} : state_reg[20:18], state_reg_touch_way_sized[2] ? state_reg[17:15] : {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[16], state_reg_touch_way_sized[1] ? state_reg[15] : ~(state_reg_touch_way_sized[0])}}} : state_reg[25:15], state_reg_touch_way_sized[4] ? state_reg[14:0] : {~(state_reg_touch_way_sized[3]), state_reg_touch_way_sized[3] ? {~(state_reg_touch_way_sized[2]), state_reg_touch_way_sized[2] ? {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[11], state_reg_touch_way_sized[1] ? state_reg[10] : ~(state_reg_touch_way_sized[0])} : state_reg[12:10], state_reg_touch_way_sized[2] ? state_reg[9:7] : {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[8], state_reg_touch_way_sized[1] ? state_reg[7] : ~(state_reg_touch_way_sized[0])}} : state_reg[13:7], state_reg_touch_way_sized[3] ? state_reg[6:0] : {~(state_reg_touch_way_sized[2]), state_reg_touch_way_sized[2] ? {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[4], state_reg_touch_way_sized[1] ? state_reg[3] : ~(state_reg_touch_way_sized[0])} : state_reg[5:3], state_reg_touch_way_sized[2] ? state_reg[2:0] : {~(state_reg_touch_way_sized[1]), state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}}}}; // @[package.scala:163:13] r_resp_pipe_v <= _io_resp_valid_T_84[0]; // @[Valid.scala:141:24] if (io_bht_update_valid & io_bht_update_bits_mispredict) // @[BTB.scala:307:33, :310:32, :311:40] history <= io_bht_update_bits_branch ? {io_bht_update_bits_taken, io_bht_update_bits_prediction_history[7:1]} : io_bht_update_bits_prediction_history; // @[BTB.scala:107:13, :110:{13,19,37}, :117:24, :307:33, :313:46, :316:50] else if (io_bht_advance_valid) // @[BTB.scala:188:14] history <= {io_bht_advance_bits_bht_value, history[7:1]}; // @[BTB.scala:113:{19,35}, :117:24] if (reset_waddr[9]) begin // @[BTB.scala:119:36, :120:39] end else // @[BTB.scala:120:39] reset_waddr <= reset_waddr + 10'h1; // @[BTB.scala:119:36, :124:49] if (io_ras_update_valid) begin // @[BTB.scala:188:14] if (_GEN_7) begin // @[BTB.scala:333:40] if (count[2:1] != 2'h3) // @[BTB.scala:43:17, :56:30] count <= count + 3'h1; // @[BTB.scala:43:44, :56:30] pos <= nextPos; // @[BTB.scala:44:22, :57:28] end else if ((&io_ras_update_bits_cfiType) & (|count)) begin // @[BTB.scala:49:37, :50:11, :54:29, :56:30, :335:{46,63}] count <= count - 3'h1; // @[BTB.scala:50:20, :56:30] pos <= (|pos) ? pos - 3'h1 : 3'h5; // @[BTB.scala:51:{15,40,50}, :57:28] end end end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module ShuttleFetchBuffer : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<40>, next_pc : { valid : UInt<1>, bits : UInt<40>}, edge_inst : UInt<1>, insts : UInt<32>[4], exp_insts : UInt<32>[4], pcs : UInt<40>[4], mask : UInt<4>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, ras_head : UInt<3>, br_mask : UInt<4>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, end_half : { valid : UInt<1>, bits : UInt<16>}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], peek : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], flip clear : UInt<1>} reg ram : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[7], clock regreset enq_ptr : UInt<7>, clock, reset, UInt<7>(0h1) regreset deq_ptr : UInt<7>, clock, reset, UInt<7>(0h1) node _io_enq_ready_T = add(ram[1].valid, ram[2].valid) node _io_enq_ready_T_1 = bits(_io_enq_ready_T, 1, 0) node _io_enq_ready_T_2 = add(ram[0].valid, _io_enq_ready_T_1) node _io_enq_ready_T_3 = bits(_io_enq_ready_T_2, 1, 0) node _io_enq_ready_T_4 = add(ram[3].valid, ram[4].valid) node _io_enq_ready_T_5 = bits(_io_enq_ready_T_4, 1, 0) node _io_enq_ready_T_6 = add(ram[5].valid, ram[6].valid) node _io_enq_ready_T_7 = bits(_io_enq_ready_T_6, 1, 0) node _io_enq_ready_T_8 = add(_io_enq_ready_T_5, _io_enq_ready_T_7) node _io_enq_ready_T_9 = bits(_io_enq_ready_T_8, 2, 0) node _io_enq_ready_T_10 = add(_io_enq_ready_T_3, _io_enq_ready_T_9) node _io_enq_ready_T_11 = bits(_io_enq_ready_T_10, 2, 0) node _io_enq_ready_T_12 = bits(io.enq.bits.mask, 0, 0) node _io_enq_ready_T_13 = bits(io.enq.bits.mask, 1, 1) node _io_enq_ready_T_14 = bits(io.enq.bits.mask, 2, 2) node _io_enq_ready_T_15 = bits(io.enq.bits.mask, 3, 3) node _io_enq_ready_T_16 = add(_io_enq_ready_T_12, _io_enq_ready_T_13) node _io_enq_ready_T_17 = bits(_io_enq_ready_T_16, 1, 0) node _io_enq_ready_T_18 = add(_io_enq_ready_T_14, _io_enq_ready_T_15) node _io_enq_ready_T_19 = bits(_io_enq_ready_T_18, 1, 0) node _io_enq_ready_T_20 = add(_io_enq_ready_T_17, _io_enq_ready_T_19) node _io_enq_ready_T_21 = bits(_io_enq_ready_T_20, 2, 0) node _io_enq_ready_T_22 = add(_io_enq_ready_T_11, _io_enq_ready_T_21) node _io_enq_ready_T_23 = leq(_io_enq_ready_T_22, UInt<3>(0h7)) connect io.enq.ready, _io_enq_ready_T_23 wire in_uops : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[4] wire lower : UInt<4> node _lower_T = shr(io.enq.bits.mask, 1) node _lower_T_1 = dshr(_lower_T, UInt<1>(0h0)) node _lower_T_2 = dshr(_lower_T, UInt<1>(0h1)) node _lower_T_3 = dshr(_lower_T, UInt<2>(0h2)) node _lower_T_4 = or(_lower_T_1, _lower_T_2) node _lower_T_5 = or(_lower_T_4, _lower_T_3) connect lower, _lower_T_5 node _maybe_cfi_mask_T = not(lower) node maybe_cfi_mask = and(io.enq.bits.mask, _maybe_cfi_mask_T) node _rvc_T = bits(io.enq.bits.insts[0], 1, 0) node rvc = neq(_rvc_T, UInt<2>(0h3)) node _cond_br_T = and(io.enq.bits.exp_insts[0], UInt<15>(0h707f)) node _cond_br_T_1 = eq(UInt<13>(0h1063), _cond_br_T) node _cond_br_T_2 = and(io.enq.bits.exp_insts[0], UInt<15>(0h707f)) node _cond_br_T_3 = eq(UInt<15>(0h5063), _cond_br_T_2) node _cond_br_T_4 = and(io.enq.bits.exp_insts[0], UInt<15>(0h707f)) node _cond_br_T_5 = eq(UInt<15>(0h7063), _cond_br_T_4) node _cond_br_T_6 = and(io.enq.bits.exp_insts[0], UInt<15>(0h707f)) node _cond_br_T_7 = eq(UInt<7>(0h63), _cond_br_T_6) node _cond_br_T_8 = and(io.enq.bits.exp_insts[0], UInt<15>(0h707f)) node _cond_br_T_9 = eq(UInt<15>(0h4063), _cond_br_T_8) node _cond_br_T_10 = and(io.enq.bits.exp_insts[0], UInt<15>(0h707f)) node _cond_br_T_11 = eq(UInt<15>(0h6063), _cond_br_T_10) node _cond_br_T_12 = or(_cond_br_T_1, _cond_br_T_3) node _cond_br_T_13 = or(_cond_br_T_12, _cond_br_T_5) node _cond_br_T_14 = or(_cond_br_T_13, _cond_br_T_7) node _cond_br_T_15 = or(_cond_br_T_14, _cond_br_T_9) node cond_br = or(_cond_br_T_15, _cond_br_T_11) node _in_uops_0_valid_T = bits(io.enq.bits.mask, 0, 0) node _in_uops_0_valid_T_1 = and(io.enq.valid, _in_uops_0_valid_T) connect in_uops[0].valid, _in_uops_0_valid_T_1 invalidate in_uops[0].bits.flush_pipe invalidate in_uops[0].bits.mem_size invalidate in_uops[0].bits.fdivin.in3 invalidate in_uops[0].bits.fdivin.in2 invalidate in_uops[0].bits.fdivin.in1 invalidate in_uops[0].bits.fdivin.fmt invalidate in_uops[0].bits.fdivin.typ invalidate in_uops[0].bits.fdivin.fmaCmd invalidate in_uops[0].bits.fdivin.rm invalidate in_uops[0].bits.fdivin.vec invalidate in_uops[0].bits.fdivin.wflags invalidate in_uops[0].bits.fdivin.sqrt invalidate in_uops[0].bits.fdivin.div invalidate in_uops[0].bits.fdivin.fma invalidate in_uops[0].bits.fdivin.fastpipe invalidate in_uops[0].bits.fdivin.toint invalidate in_uops[0].bits.fdivin.fromint invalidate in_uops[0].bits.fdivin.typeTagOut invalidate in_uops[0].bits.fdivin.typeTagIn invalidate in_uops[0].bits.fdivin.swap23 invalidate in_uops[0].bits.fdivin.swap12 invalidate in_uops[0].bits.fdivin.ren3 invalidate in_uops[0].bits.fdivin.ren2 invalidate in_uops[0].bits.fdivin.ren1 invalidate in_uops[0].bits.fdivin.wen invalidate in_uops[0].bits.fdivin.ldst invalidate in_uops[0].bits.fexc invalidate in_uops[0].bits.fra3 invalidate in_uops[0].bits.fra2 invalidate in_uops[0].bits.fra1 invalidate in_uops[0].bits.wdata.bits invalidate in_uops[0].bits.wdata.valid invalidate in_uops[0].bits.uses_latealu invalidate in_uops[0].bits.uses_memalu invalidate in_uops[0].bits.rs3_data invalidate in_uops[0].bits.rs2_data invalidate in_uops[0].bits.rs1_data invalidate in_uops[0].bits.needs_replay invalidate in_uops[0].bits.xcpt_cause invalidate in_uops[0].bits.xcpt invalidate in_uops[0].bits.taken invalidate in_uops[0].bits.ras_head invalidate in_uops[0].bits.next_pc.bits invalidate in_uops[0].bits.next_pc.valid invalidate in_uops[0].bits.sfb_shadow invalidate in_uops[0].bits.sfb_br invalidate in_uops[0].bits.btb_resp.bits.bht.value invalidate in_uops[0].bits.btb_resp.bits.bht.history invalidate in_uops[0].bits.btb_resp.bits.entry invalidate in_uops[0].bits.btb_resp.bits.target invalidate in_uops[0].bits.btb_resp.bits.bridx invalidate in_uops[0].bits.btb_resp.bits.mask invalidate in_uops[0].bits.btb_resp.bits.taken invalidate in_uops[0].bits.btb_resp.bits.cfiType invalidate in_uops[0].bits.btb_resp.valid invalidate in_uops[0].bits.sets_vcfg invalidate in_uops[0].bits.rvc invalidate in_uops[0].bits.fp_ctrl.vec invalidate in_uops[0].bits.fp_ctrl.wflags invalidate in_uops[0].bits.fp_ctrl.sqrt invalidate in_uops[0].bits.fp_ctrl.div invalidate in_uops[0].bits.fp_ctrl.fma invalidate in_uops[0].bits.fp_ctrl.fastpipe invalidate in_uops[0].bits.fp_ctrl.toint invalidate in_uops[0].bits.fp_ctrl.fromint invalidate in_uops[0].bits.fp_ctrl.typeTagOut invalidate in_uops[0].bits.fp_ctrl.typeTagIn invalidate in_uops[0].bits.fp_ctrl.swap23 invalidate in_uops[0].bits.fp_ctrl.swap12 invalidate in_uops[0].bits.fp_ctrl.ren3 invalidate in_uops[0].bits.fp_ctrl.ren2 invalidate in_uops[0].bits.fp_ctrl.ren1 invalidate in_uops[0].bits.fp_ctrl.wen invalidate in_uops[0].bits.fp_ctrl.ldst invalidate in_uops[0].bits.ctrl.vec invalidate in_uops[0].bits.ctrl.dp invalidate in_uops[0].bits.ctrl.amo invalidate in_uops[0].bits.ctrl.fence invalidate in_uops[0].bits.ctrl.fence_i invalidate in_uops[0].bits.ctrl.csr invalidate in_uops[0].bits.ctrl.wxd invalidate in_uops[0].bits.ctrl.div invalidate in_uops[0].bits.ctrl.mul invalidate in_uops[0].bits.ctrl.wfd invalidate in_uops[0].bits.ctrl.rfs3 invalidate in_uops[0].bits.ctrl.rfs2 invalidate in_uops[0].bits.ctrl.rfs1 invalidate in_uops[0].bits.ctrl.mem_cmd invalidate in_uops[0].bits.ctrl.mem invalidate in_uops[0].bits.ctrl.alu_fn invalidate in_uops[0].bits.ctrl.alu_dw invalidate in_uops[0].bits.ctrl.sel_imm invalidate in_uops[0].bits.ctrl.sel_alu1 invalidate in_uops[0].bits.ctrl.sel_alu2 invalidate in_uops[0].bits.ctrl.rxs1 invalidate in_uops[0].bits.ctrl.rxs2 invalidate in_uops[0].bits.ctrl.jalr invalidate in_uops[0].bits.ctrl.jal invalidate in_uops[0].bits.ctrl.branch invalidate in_uops[0].bits.ctrl.rocc invalidate in_uops[0].bits.ctrl.fp invalidate in_uops[0].bits.ctrl.legal invalidate in_uops[0].bits.edge_inst invalidate in_uops[0].bits.pc invalidate in_uops[0].bits.raw_inst invalidate in_uops[0].bits.inst connect in_uops[0].bits.pc, io.enq.bits.pcs[0] invalidate in_uops[0].bits.ctrl.vec invalidate in_uops[0].bits.ctrl.dp invalidate in_uops[0].bits.ctrl.amo invalidate in_uops[0].bits.ctrl.fence invalidate in_uops[0].bits.ctrl.fence_i invalidate in_uops[0].bits.ctrl.csr invalidate in_uops[0].bits.ctrl.wxd invalidate in_uops[0].bits.ctrl.div invalidate in_uops[0].bits.ctrl.mul invalidate in_uops[0].bits.ctrl.wfd invalidate in_uops[0].bits.ctrl.rfs3 invalidate in_uops[0].bits.ctrl.rfs2 invalidate in_uops[0].bits.ctrl.rfs1 invalidate in_uops[0].bits.ctrl.mem_cmd invalidate in_uops[0].bits.ctrl.mem invalidate in_uops[0].bits.ctrl.alu_fn invalidate in_uops[0].bits.ctrl.alu_dw invalidate in_uops[0].bits.ctrl.sel_imm invalidate in_uops[0].bits.ctrl.sel_alu1 invalidate in_uops[0].bits.ctrl.sel_alu2 invalidate in_uops[0].bits.ctrl.rxs1 invalidate in_uops[0].bits.ctrl.rxs2 invalidate in_uops[0].bits.ctrl.jalr invalidate in_uops[0].bits.ctrl.jal invalidate in_uops[0].bits.ctrl.branch invalidate in_uops[0].bits.ctrl.rocc invalidate in_uops[0].bits.ctrl.fp invalidate in_uops[0].bits.ctrl.legal invalidate in_uops[0].bits.fp_ctrl.vec invalidate in_uops[0].bits.fp_ctrl.wflags invalidate in_uops[0].bits.fp_ctrl.sqrt invalidate in_uops[0].bits.fp_ctrl.div invalidate in_uops[0].bits.fp_ctrl.fma invalidate in_uops[0].bits.fp_ctrl.fastpipe invalidate in_uops[0].bits.fp_ctrl.toint invalidate in_uops[0].bits.fp_ctrl.fromint invalidate in_uops[0].bits.fp_ctrl.typeTagOut invalidate in_uops[0].bits.fp_ctrl.typeTagIn invalidate in_uops[0].bits.fp_ctrl.swap23 invalidate in_uops[0].bits.fp_ctrl.swap12 invalidate in_uops[0].bits.fp_ctrl.ren3 invalidate in_uops[0].bits.fp_ctrl.ren2 invalidate in_uops[0].bits.fp_ctrl.ren1 invalidate in_uops[0].bits.fp_ctrl.wen invalidate in_uops[0].bits.fp_ctrl.ldst connect in_uops[0].bits.inst, io.enq.bits.exp_insts[0] connect in_uops[0].bits.raw_inst, io.enq.bits.insts[0] node _in_uops_0_bits_rvc_T = bits(io.enq.bits.insts[0], 1, 0) node _in_uops_0_bits_rvc_T_1 = neq(_in_uops_0_bits_rvc_T, UInt<2>(0h3)) connect in_uops[0].bits.rvc, _in_uops_0_bits_rvc_T_1 node _in_uops_0_bits_sfb_br_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_0_bits_sfb_br_sign_T_1 = bits(io.enq.bits.exp_insts[0], 31, 31) node _in_uops_0_bits_sfb_br_sign_T_2 = asSInt(_in_uops_0_bits_sfb_br_sign_T_1) node in_uops_0_bits_sfb_br_sign = mux(_in_uops_0_bits_sfb_br_sign_T, asSInt(UInt<1>(0h0)), _in_uops_0_bits_sfb_br_sign_T_2) node _in_uops_0_bits_sfb_br_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_0_bits_sfb_br_b30_20_T_1 = bits(io.enq.bits.exp_insts[0], 30, 20) node _in_uops_0_bits_sfb_br_b30_20_T_2 = asSInt(_in_uops_0_bits_sfb_br_b30_20_T_1) node in_uops_0_bits_sfb_br_b30_20 = mux(_in_uops_0_bits_sfb_br_b30_20_T, _in_uops_0_bits_sfb_br_b30_20_T_2, in_uops_0_bits_sfb_br_sign) node _in_uops_0_bits_sfb_br_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_0_bits_sfb_br_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_0_bits_sfb_br_b19_12_T_2 = and(_in_uops_0_bits_sfb_br_b19_12_T, _in_uops_0_bits_sfb_br_b19_12_T_1) node _in_uops_0_bits_sfb_br_b19_12_T_3 = bits(io.enq.bits.exp_insts[0], 19, 12) node _in_uops_0_bits_sfb_br_b19_12_T_4 = asSInt(_in_uops_0_bits_sfb_br_b19_12_T_3) node in_uops_0_bits_sfb_br_b19_12 = mux(_in_uops_0_bits_sfb_br_b19_12_T_2, in_uops_0_bits_sfb_br_sign, _in_uops_0_bits_sfb_br_b19_12_T_4) node _in_uops_0_bits_sfb_br_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_0_bits_sfb_br_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_0_bits_sfb_br_b11_T_2 = or(_in_uops_0_bits_sfb_br_b11_T, _in_uops_0_bits_sfb_br_b11_T_1) node _in_uops_0_bits_sfb_br_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_0_bits_sfb_br_b11_T_4 = bits(io.enq.bits.exp_insts[0], 20, 20) node _in_uops_0_bits_sfb_br_b11_T_5 = asSInt(_in_uops_0_bits_sfb_br_b11_T_4) node _in_uops_0_bits_sfb_br_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_0_bits_sfb_br_b11_T_7 = bits(io.enq.bits.exp_insts[0], 7, 7) node _in_uops_0_bits_sfb_br_b11_T_8 = asSInt(_in_uops_0_bits_sfb_br_b11_T_7) node _in_uops_0_bits_sfb_br_b11_T_9 = mux(_in_uops_0_bits_sfb_br_b11_T_6, _in_uops_0_bits_sfb_br_b11_T_8, in_uops_0_bits_sfb_br_sign) node _in_uops_0_bits_sfb_br_b11_T_10 = mux(_in_uops_0_bits_sfb_br_b11_T_3, _in_uops_0_bits_sfb_br_b11_T_5, _in_uops_0_bits_sfb_br_b11_T_9) node in_uops_0_bits_sfb_br_b11 = mux(_in_uops_0_bits_sfb_br_b11_T_2, asSInt(UInt<1>(0h0)), _in_uops_0_bits_sfb_br_b11_T_10) node _in_uops_0_bits_sfb_br_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_0_bits_sfb_br_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_0_bits_sfb_br_b10_5_T_2 = or(_in_uops_0_bits_sfb_br_b10_5_T, _in_uops_0_bits_sfb_br_b10_5_T_1) node _in_uops_0_bits_sfb_br_b10_5_T_3 = bits(io.enq.bits.exp_insts[0], 30, 25) node in_uops_0_bits_sfb_br_b10_5 = mux(_in_uops_0_bits_sfb_br_b10_5_T_2, UInt<1>(0h0), _in_uops_0_bits_sfb_br_b10_5_T_3) node _in_uops_0_bits_sfb_br_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_0_bits_sfb_br_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_0_bits_sfb_br_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_0_bits_sfb_br_b4_1_T_3 = or(_in_uops_0_bits_sfb_br_b4_1_T_1, _in_uops_0_bits_sfb_br_b4_1_T_2) node _in_uops_0_bits_sfb_br_b4_1_T_4 = bits(io.enq.bits.exp_insts[0], 11, 8) node _in_uops_0_bits_sfb_br_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_0_bits_sfb_br_b4_1_T_6 = bits(io.enq.bits.exp_insts[0], 19, 16) node _in_uops_0_bits_sfb_br_b4_1_T_7 = bits(io.enq.bits.exp_insts[0], 24, 21) node _in_uops_0_bits_sfb_br_b4_1_T_8 = mux(_in_uops_0_bits_sfb_br_b4_1_T_5, _in_uops_0_bits_sfb_br_b4_1_T_6, _in_uops_0_bits_sfb_br_b4_1_T_7) node _in_uops_0_bits_sfb_br_b4_1_T_9 = mux(_in_uops_0_bits_sfb_br_b4_1_T_3, _in_uops_0_bits_sfb_br_b4_1_T_4, _in_uops_0_bits_sfb_br_b4_1_T_8) node in_uops_0_bits_sfb_br_b4_1 = mux(_in_uops_0_bits_sfb_br_b4_1_T, UInt<1>(0h0), _in_uops_0_bits_sfb_br_b4_1_T_9) node _in_uops_0_bits_sfb_br_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_0_bits_sfb_br_b0_T_1 = bits(io.enq.bits.exp_insts[0], 7, 7) node _in_uops_0_bits_sfb_br_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _in_uops_0_bits_sfb_br_b0_T_3 = bits(io.enq.bits.exp_insts[0], 20, 20) node _in_uops_0_bits_sfb_br_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_0_bits_sfb_br_b0_T_5 = bits(io.enq.bits.exp_insts[0], 15, 15) node _in_uops_0_bits_sfb_br_b0_T_6 = mux(_in_uops_0_bits_sfb_br_b0_T_4, _in_uops_0_bits_sfb_br_b0_T_5, UInt<1>(0h0)) node _in_uops_0_bits_sfb_br_b0_T_7 = mux(_in_uops_0_bits_sfb_br_b0_T_2, _in_uops_0_bits_sfb_br_b0_T_3, _in_uops_0_bits_sfb_br_b0_T_6) node in_uops_0_bits_sfb_br_b0 = mux(_in_uops_0_bits_sfb_br_b0_T, _in_uops_0_bits_sfb_br_b0_T_1, _in_uops_0_bits_sfb_br_b0_T_7) node in_uops_0_bits_sfb_br_lo_hi = cat(in_uops_0_bits_sfb_br_b10_5, in_uops_0_bits_sfb_br_b4_1) node in_uops_0_bits_sfb_br_lo = cat(in_uops_0_bits_sfb_br_lo_hi, in_uops_0_bits_sfb_br_b0) node in_uops_0_bits_sfb_br_hi_lo_lo = asUInt(in_uops_0_bits_sfb_br_b11) node in_uops_0_bits_sfb_br_hi_lo_hi = asUInt(in_uops_0_bits_sfb_br_b19_12) node in_uops_0_bits_sfb_br_hi_lo = cat(in_uops_0_bits_sfb_br_hi_lo_hi, in_uops_0_bits_sfb_br_hi_lo_lo) node in_uops_0_bits_sfb_br_hi_hi_lo = asUInt(in_uops_0_bits_sfb_br_b30_20) node in_uops_0_bits_sfb_br_hi_hi_hi = asUInt(in_uops_0_bits_sfb_br_sign) node in_uops_0_bits_sfb_br_hi_hi = cat(in_uops_0_bits_sfb_br_hi_hi_hi, in_uops_0_bits_sfb_br_hi_hi_lo) node in_uops_0_bits_sfb_br_hi = cat(in_uops_0_bits_sfb_br_hi_hi, in_uops_0_bits_sfb_br_hi_lo) node _in_uops_0_bits_sfb_br_T = cat(in_uops_0_bits_sfb_br_hi, in_uops_0_bits_sfb_br_lo) node _in_uops_0_bits_sfb_br_T_1 = asSInt(_in_uops_0_bits_sfb_br_T) node _in_uops_0_bits_sfb_br_T_2 = mux(rvc, asSInt(UInt<4>(0h4)), asSInt(UInt<4>(0h6))) node _in_uops_0_bits_sfb_br_T_3 = eq(_in_uops_0_bits_sfb_br_T_1, _in_uops_0_bits_sfb_br_T_2) node _in_uops_0_bits_sfb_br_T_4 = and(cond_br, _in_uops_0_bits_sfb_br_T_3) node _in_uops_0_bits_sfb_br_T_5 = eq(io.enq.bits.next_pc.valid, UInt<1>(0h0)) node _in_uops_0_bits_sfb_br_T_6 = and(_in_uops_0_bits_sfb_br_T_4, _in_uops_0_bits_sfb_br_T_5) connect in_uops[0].bits.sfb_br, _in_uops_0_bits_sfb_br_T_6 connect in_uops[0].bits.btb_resp, io.enq.bits.btb_resp node _in_uops_0_bits_next_pc_valid_T = bits(maybe_cfi_mask, 0, 0) node _in_uops_0_bits_next_pc_valid_T_1 = and(io.enq.bits.next_pc.valid, _in_uops_0_bits_next_pc_valid_T) connect in_uops[0].bits.next_pc.valid, _in_uops_0_bits_next_pc_valid_T_1 connect in_uops[0].bits.next_pc.bits, io.enq.bits.next_pc.bits connect in_uops[0].bits.needs_replay, UInt<1>(0h0) node _in_uops_0_bits_mem_size_T = bits(io.enq.bits.exp_insts[0], 13, 12) connect in_uops[0].bits.mem_size, _in_uops_0_bits_mem_size_T connect in_uops[0].bits.ras_head, io.enq.bits.ras_head node _in_uops_0_bits_xcpt_T = or(io.enq.bits.xcpt_pf_if, io.enq.bits.xcpt_ae_if) connect in_uops[0].bits.xcpt, _in_uops_0_bits_xcpt_T node _in_uops_0_bits_edge_inst_T = and(UInt<1>(0h1), io.enq.bits.edge_inst) connect in_uops[0].bits.edge_inst, _in_uops_0_bits_edge_inst_T node _in_uops_0_bits_xcpt_cause_T = mux(io.enq.bits.xcpt_pf_if, UInt<4>(0hc), UInt<1>(0h1)) connect in_uops[0].bits.xcpt_cause, _in_uops_0_bits_xcpt_cause_T node _rvc_T_1 = bits(io.enq.bits.insts[1], 1, 0) node rvc_1 = neq(_rvc_T_1, UInt<2>(0h3)) node _cond_br_T_16 = and(io.enq.bits.exp_insts[1], UInt<15>(0h707f)) node _cond_br_T_17 = eq(UInt<13>(0h1063), _cond_br_T_16) node _cond_br_T_18 = and(io.enq.bits.exp_insts[1], UInt<15>(0h707f)) node _cond_br_T_19 = eq(UInt<15>(0h5063), _cond_br_T_18) node _cond_br_T_20 = and(io.enq.bits.exp_insts[1], UInt<15>(0h707f)) node _cond_br_T_21 = eq(UInt<15>(0h7063), _cond_br_T_20) node _cond_br_T_22 = and(io.enq.bits.exp_insts[1], UInt<15>(0h707f)) node _cond_br_T_23 = eq(UInt<7>(0h63), _cond_br_T_22) node _cond_br_T_24 = and(io.enq.bits.exp_insts[1], UInt<15>(0h707f)) node _cond_br_T_25 = eq(UInt<15>(0h4063), _cond_br_T_24) node _cond_br_T_26 = and(io.enq.bits.exp_insts[1], UInt<15>(0h707f)) node _cond_br_T_27 = eq(UInt<15>(0h6063), _cond_br_T_26) node _cond_br_T_28 = or(_cond_br_T_17, _cond_br_T_19) node _cond_br_T_29 = or(_cond_br_T_28, _cond_br_T_21) node _cond_br_T_30 = or(_cond_br_T_29, _cond_br_T_23) node _cond_br_T_31 = or(_cond_br_T_30, _cond_br_T_25) node cond_br_1 = or(_cond_br_T_31, _cond_br_T_27) node _in_uops_1_valid_T = bits(io.enq.bits.mask, 1, 1) node _in_uops_1_valid_T_1 = and(io.enq.valid, _in_uops_1_valid_T) connect in_uops[1].valid, _in_uops_1_valid_T_1 invalidate in_uops[1].bits.flush_pipe invalidate in_uops[1].bits.mem_size invalidate in_uops[1].bits.fdivin.in3 invalidate in_uops[1].bits.fdivin.in2 invalidate in_uops[1].bits.fdivin.in1 invalidate in_uops[1].bits.fdivin.fmt invalidate in_uops[1].bits.fdivin.typ invalidate in_uops[1].bits.fdivin.fmaCmd invalidate in_uops[1].bits.fdivin.rm invalidate in_uops[1].bits.fdivin.vec invalidate in_uops[1].bits.fdivin.wflags invalidate in_uops[1].bits.fdivin.sqrt invalidate in_uops[1].bits.fdivin.div invalidate in_uops[1].bits.fdivin.fma invalidate in_uops[1].bits.fdivin.fastpipe invalidate in_uops[1].bits.fdivin.toint invalidate in_uops[1].bits.fdivin.fromint invalidate in_uops[1].bits.fdivin.typeTagOut invalidate in_uops[1].bits.fdivin.typeTagIn invalidate in_uops[1].bits.fdivin.swap23 invalidate in_uops[1].bits.fdivin.swap12 invalidate in_uops[1].bits.fdivin.ren3 invalidate in_uops[1].bits.fdivin.ren2 invalidate in_uops[1].bits.fdivin.ren1 invalidate in_uops[1].bits.fdivin.wen invalidate in_uops[1].bits.fdivin.ldst invalidate in_uops[1].bits.fexc invalidate in_uops[1].bits.fra3 invalidate in_uops[1].bits.fra2 invalidate in_uops[1].bits.fra1 invalidate in_uops[1].bits.wdata.bits invalidate in_uops[1].bits.wdata.valid invalidate in_uops[1].bits.uses_latealu invalidate in_uops[1].bits.uses_memalu invalidate in_uops[1].bits.rs3_data invalidate in_uops[1].bits.rs2_data invalidate in_uops[1].bits.rs1_data invalidate in_uops[1].bits.needs_replay invalidate in_uops[1].bits.xcpt_cause invalidate in_uops[1].bits.xcpt invalidate in_uops[1].bits.taken invalidate in_uops[1].bits.ras_head invalidate in_uops[1].bits.next_pc.bits invalidate in_uops[1].bits.next_pc.valid invalidate in_uops[1].bits.sfb_shadow invalidate in_uops[1].bits.sfb_br invalidate in_uops[1].bits.btb_resp.bits.bht.value invalidate in_uops[1].bits.btb_resp.bits.bht.history invalidate in_uops[1].bits.btb_resp.bits.entry invalidate in_uops[1].bits.btb_resp.bits.target invalidate in_uops[1].bits.btb_resp.bits.bridx invalidate in_uops[1].bits.btb_resp.bits.mask invalidate in_uops[1].bits.btb_resp.bits.taken invalidate in_uops[1].bits.btb_resp.bits.cfiType invalidate in_uops[1].bits.btb_resp.valid invalidate in_uops[1].bits.sets_vcfg invalidate in_uops[1].bits.rvc invalidate in_uops[1].bits.fp_ctrl.vec invalidate in_uops[1].bits.fp_ctrl.wflags invalidate in_uops[1].bits.fp_ctrl.sqrt invalidate in_uops[1].bits.fp_ctrl.div invalidate in_uops[1].bits.fp_ctrl.fma invalidate in_uops[1].bits.fp_ctrl.fastpipe invalidate in_uops[1].bits.fp_ctrl.toint invalidate in_uops[1].bits.fp_ctrl.fromint invalidate in_uops[1].bits.fp_ctrl.typeTagOut invalidate in_uops[1].bits.fp_ctrl.typeTagIn invalidate in_uops[1].bits.fp_ctrl.swap23 invalidate in_uops[1].bits.fp_ctrl.swap12 invalidate in_uops[1].bits.fp_ctrl.ren3 invalidate in_uops[1].bits.fp_ctrl.ren2 invalidate in_uops[1].bits.fp_ctrl.ren1 invalidate in_uops[1].bits.fp_ctrl.wen invalidate in_uops[1].bits.fp_ctrl.ldst invalidate in_uops[1].bits.ctrl.vec invalidate in_uops[1].bits.ctrl.dp invalidate in_uops[1].bits.ctrl.amo invalidate in_uops[1].bits.ctrl.fence invalidate in_uops[1].bits.ctrl.fence_i invalidate in_uops[1].bits.ctrl.csr invalidate in_uops[1].bits.ctrl.wxd invalidate in_uops[1].bits.ctrl.div invalidate in_uops[1].bits.ctrl.mul invalidate in_uops[1].bits.ctrl.wfd invalidate in_uops[1].bits.ctrl.rfs3 invalidate in_uops[1].bits.ctrl.rfs2 invalidate in_uops[1].bits.ctrl.rfs1 invalidate in_uops[1].bits.ctrl.mem_cmd invalidate in_uops[1].bits.ctrl.mem invalidate in_uops[1].bits.ctrl.alu_fn invalidate in_uops[1].bits.ctrl.alu_dw invalidate in_uops[1].bits.ctrl.sel_imm invalidate in_uops[1].bits.ctrl.sel_alu1 invalidate in_uops[1].bits.ctrl.sel_alu2 invalidate in_uops[1].bits.ctrl.rxs1 invalidate in_uops[1].bits.ctrl.rxs2 invalidate in_uops[1].bits.ctrl.jalr invalidate in_uops[1].bits.ctrl.jal invalidate in_uops[1].bits.ctrl.branch invalidate in_uops[1].bits.ctrl.rocc invalidate in_uops[1].bits.ctrl.fp invalidate in_uops[1].bits.ctrl.legal invalidate in_uops[1].bits.edge_inst invalidate in_uops[1].bits.pc invalidate in_uops[1].bits.raw_inst invalidate in_uops[1].bits.inst connect in_uops[1].bits.pc, io.enq.bits.pcs[1] invalidate in_uops[1].bits.ctrl.vec invalidate in_uops[1].bits.ctrl.dp invalidate in_uops[1].bits.ctrl.amo invalidate in_uops[1].bits.ctrl.fence invalidate in_uops[1].bits.ctrl.fence_i invalidate in_uops[1].bits.ctrl.csr invalidate in_uops[1].bits.ctrl.wxd invalidate in_uops[1].bits.ctrl.div invalidate in_uops[1].bits.ctrl.mul invalidate in_uops[1].bits.ctrl.wfd invalidate in_uops[1].bits.ctrl.rfs3 invalidate in_uops[1].bits.ctrl.rfs2 invalidate in_uops[1].bits.ctrl.rfs1 invalidate in_uops[1].bits.ctrl.mem_cmd invalidate in_uops[1].bits.ctrl.mem invalidate in_uops[1].bits.ctrl.alu_fn invalidate in_uops[1].bits.ctrl.alu_dw invalidate in_uops[1].bits.ctrl.sel_imm invalidate in_uops[1].bits.ctrl.sel_alu1 invalidate in_uops[1].bits.ctrl.sel_alu2 invalidate in_uops[1].bits.ctrl.rxs1 invalidate in_uops[1].bits.ctrl.rxs2 invalidate in_uops[1].bits.ctrl.jalr invalidate in_uops[1].bits.ctrl.jal invalidate in_uops[1].bits.ctrl.branch invalidate in_uops[1].bits.ctrl.rocc invalidate in_uops[1].bits.ctrl.fp invalidate in_uops[1].bits.ctrl.legal invalidate in_uops[1].bits.fp_ctrl.vec invalidate in_uops[1].bits.fp_ctrl.wflags invalidate in_uops[1].bits.fp_ctrl.sqrt invalidate in_uops[1].bits.fp_ctrl.div invalidate in_uops[1].bits.fp_ctrl.fma invalidate in_uops[1].bits.fp_ctrl.fastpipe invalidate in_uops[1].bits.fp_ctrl.toint invalidate in_uops[1].bits.fp_ctrl.fromint invalidate in_uops[1].bits.fp_ctrl.typeTagOut invalidate in_uops[1].bits.fp_ctrl.typeTagIn invalidate in_uops[1].bits.fp_ctrl.swap23 invalidate in_uops[1].bits.fp_ctrl.swap12 invalidate in_uops[1].bits.fp_ctrl.ren3 invalidate in_uops[1].bits.fp_ctrl.ren2 invalidate in_uops[1].bits.fp_ctrl.ren1 invalidate in_uops[1].bits.fp_ctrl.wen invalidate in_uops[1].bits.fp_ctrl.ldst connect in_uops[1].bits.inst, io.enq.bits.exp_insts[1] connect in_uops[1].bits.raw_inst, io.enq.bits.insts[1] node _in_uops_1_bits_rvc_T = bits(io.enq.bits.insts[1], 1, 0) node _in_uops_1_bits_rvc_T_1 = neq(_in_uops_1_bits_rvc_T, UInt<2>(0h3)) connect in_uops[1].bits.rvc, _in_uops_1_bits_rvc_T_1 node _in_uops_1_bits_sfb_br_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_1_bits_sfb_br_sign_T_1 = bits(io.enq.bits.exp_insts[1], 31, 31) node _in_uops_1_bits_sfb_br_sign_T_2 = asSInt(_in_uops_1_bits_sfb_br_sign_T_1) node in_uops_1_bits_sfb_br_sign = mux(_in_uops_1_bits_sfb_br_sign_T, asSInt(UInt<1>(0h0)), _in_uops_1_bits_sfb_br_sign_T_2) node _in_uops_1_bits_sfb_br_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_1_bits_sfb_br_b30_20_T_1 = bits(io.enq.bits.exp_insts[1], 30, 20) node _in_uops_1_bits_sfb_br_b30_20_T_2 = asSInt(_in_uops_1_bits_sfb_br_b30_20_T_1) node in_uops_1_bits_sfb_br_b30_20 = mux(_in_uops_1_bits_sfb_br_b30_20_T, _in_uops_1_bits_sfb_br_b30_20_T_2, in_uops_1_bits_sfb_br_sign) node _in_uops_1_bits_sfb_br_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_1_bits_sfb_br_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_1_bits_sfb_br_b19_12_T_2 = and(_in_uops_1_bits_sfb_br_b19_12_T, _in_uops_1_bits_sfb_br_b19_12_T_1) node _in_uops_1_bits_sfb_br_b19_12_T_3 = bits(io.enq.bits.exp_insts[1], 19, 12) node _in_uops_1_bits_sfb_br_b19_12_T_4 = asSInt(_in_uops_1_bits_sfb_br_b19_12_T_3) node in_uops_1_bits_sfb_br_b19_12 = mux(_in_uops_1_bits_sfb_br_b19_12_T_2, in_uops_1_bits_sfb_br_sign, _in_uops_1_bits_sfb_br_b19_12_T_4) node _in_uops_1_bits_sfb_br_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_1_bits_sfb_br_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_1_bits_sfb_br_b11_T_2 = or(_in_uops_1_bits_sfb_br_b11_T, _in_uops_1_bits_sfb_br_b11_T_1) node _in_uops_1_bits_sfb_br_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_1_bits_sfb_br_b11_T_4 = bits(io.enq.bits.exp_insts[1], 20, 20) node _in_uops_1_bits_sfb_br_b11_T_5 = asSInt(_in_uops_1_bits_sfb_br_b11_T_4) node _in_uops_1_bits_sfb_br_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_1_bits_sfb_br_b11_T_7 = bits(io.enq.bits.exp_insts[1], 7, 7) node _in_uops_1_bits_sfb_br_b11_T_8 = asSInt(_in_uops_1_bits_sfb_br_b11_T_7) node _in_uops_1_bits_sfb_br_b11_T_9 = mux(_in_uops_1_bits_sfb_br_b11_T_6, _in_uops_1_bits_sfb_br_b11_T_8, in_uops_1_bits_sfb_br_sign) node _in_uops_1_bits_sfb_br_b11_T_10 = mux(_in_uops_1_bits_sfb_br_b11_T_3, _in_uops_1_bits_sfb_br_b11_T_5, _in_uops_1_bits_sfb_br_b11_T_9) node in_uops_1_bits_sfb_br_b11 = mux(_in_uops_1_bits_sfb_br_b11_T_2, asSInt(UInt<1>(0h0)), _in_uops_1_bits_sfb_br_b11_T_10) node _in_uops_1_bits_sfb_br_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_1_bits_sfb_br_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_1_bits_sfb_br_b10_5_T_2 = or(_in_uops_1_bits_sfb_br_b10_5_T, _in_uops_1_bits_sfb_br_b10_5_T_1) node _in_uops_1_bits_sfb_br_b10_5_T_3 = bits(io.enq.bits.exp_insts[1], 30, 25) node in_uops_1_bits_sfb_br_b10_5 = mux(_in_uops_1_bits_sfb_br_b10_5_T_2, UInt<1>(0h0), _in_uops_1_bits_sfb_br_b10_5_T_3) node _in_uops_1_bits_sfb_br_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_1_bits_sfb_br_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_1_bits_sfb_br_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_1_bits_sfb_br_b4_1_T_3 = or(_in_uops_1_bits_sfb_br_b4_1_T_1, _in_uops_1_bits_sfb_br_b4_1_T_2) node _in_uops_1_bits_sfb_br_b4_1_T_4 = bits(io.enq.bits.exp_insts[1], 11, 8) node _in_uops_1_bits_sfb_br_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_1_bits_sfb_br_b4_1_T_6 = bits(io.enq.bits.exp_insts[1], 19, 16) node _in_uops_1_bits_sfb_br_b4_1_T_7 = bits(io.enq.bits.exp_insts[1], 24, 21) node _in_uops_1_bits_sfb_br_b4_1_T_8 = mux(_in_uops_1_bits_sfb_br_b4_1_T_5, _in_uops_1_bits_sfb_br_b4_1_T_6, _in_uops_1_bits_sfb_br_b4_1_T_7) node _in_uops_1_bits_sfb_br_b4_1_T_9 = mux(_in_uops_1_bits_sfb_br_b4_1_T_3, _in_uops_1_bits_sfb_br_b4_1_T_4, _in_uops_1_bits_sfb_br_b4_1_T_8) node in_uops_1_bits_sfb_br_b4_1 = mux(_in_uops_1_bits_sfb_br_b4_1_T, UInt<1>(0h0), _in_uops_1_bits_sfb_br_b4_1_T_9) node _in_uops_1_bits_sfb_br_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_1_bits_sfb_br_b0_T_1 = bits(io.enq.bits.exp_insts[1], 7, 7) node _in_uops_1_bits_sfb_br_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _in_uops_1_bits_sfb_br_b0_T_3 = bits(io.enq.bits.exp_insts[1], 20, 20) node _in_uops_1_bits_sfb_br_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_1_bits_sfb_br_b0_T_5 = bits(io.enq.bits.exp_insts[1], 15, 15) node _in_uops_1_bits_sfb_br_b0_T_6 = mux(_in_uops_1_bits_sfb_br_b0_T_4, _in_uops_1_bits_sfb_br_b0_T_5, UInt<1>(0h0)) node _in_uops_1_bits_sfb_br_b0_T_7 = mux(_in_uops_1_bits_sfb_br_b0_T_2, _in_uops_1_bits_sfb_br_b0_T_3, _in_uops_1_bits_sfb_br_b0_T_6) node in_uops_1_bits_sfb_br_b0 = mux(_in_uops_1_bits_sfb_br_b0_T, _in_uops_1_bits_sfb_br_b0_T_1, _in_uops_1_bits_sfb_br_b0_T_7) node in_uops_1_bits_sfb_br_lo_hi = cat(in_uops_1_bits_sfb_br_b10_5, in_uops_1_bits_sfb_br_b4_1) node in_uops_1_bits_sfb_br_lo = cat(in_uops_1_bits_sfb_br_lo_hi, in_uops_1_bits_sfb_br_b0) node in_uops_1_bits_sfb_br_hi_lo_lo = asUInt(in_uops_1_bits_sfb_br_b11) node in_uops_1_bits_sfb_br_hi_lo_hi = asUInt(in_uops_1_bits_sfb_br_b19_12) node in_uops_1_bits_sfb_br_hi_lo = cat(in_uops_1_bits_sfb_br_hi_lo_hi, in_uops_1_bits_sfb_br_hi_lo_lo) node in_uops_1_bits_sfb_br_hi_hi_lo = asUInt(in_uops_1_bits_sfb_br_b30_20) node in_uops_1_bits_sfb_br_hi_hi_hi = asUInt(in_uops_1_bits_sfb_br_sign) node in_uops_1_bits_sfb_br_hi_hi = cat(in_uops_1_bits_sfb_br_hi_hi_hi, in_uops_1_bits_sfb_br_hi_hi_lo) node in_uops_1_bits_sfb_br_hi = cat(in_uops_1_bits_sfb_br_hi_hi, in_uops_1_bits_sfb_br_hi_lo) node _in_uops_1_bits_sfb_br_T = cat(in_uops_1_bits_sfb_br_hi, in_uops_1_bits_sfb_br_lo) node _in_uops_1_bits_sfb_br_T_1 = asSInt(_in_uops_1_bits_sfb_br_T) node _in_uops_1_bits_sfb_br_T_2 = mux(rvc_1, asSInt(UInt<4>(0h4)), asSInt(UInt<4>(0h6))) node _in_uops_1_bits_sfb_br_T_3 = eq(_in_uops_1_bits_sfb_br_T_1, _in_uops_1_bits_sfb_br_T_2) node _in_uops_1_bits_sfb_br_T_4 = and(cond_br_1, _in_uops_1_bits_sfb_br_T_3) node _in_uops_1_bits_sfb_br_T_5 = eq(io.enq.bits.next_pc.valid, UInt<1>(0h0)) node _in_uops_1_bits_sfb_br_T_6 = and(_in_uops_1_bits_sfb_br_T_4, _in_uops_1_bits_sfb_br_T_5) connect in_uops[1].bits.sfb_br, _in_uops_1_bits_sfb_br_T_6 connect in_uops[1].bits.btb_resp, io.enq.bits.btb_resp node _in_uops_1_bits_next_pc_valid_T = bits(maybe_cfi_mask, 1, 1) node _in_uops_1_bits_next_pc_valid_T_1 = and(io.enq.bits.next_pc.valid, _in_uops_1_bits_next_pc_valid_T) connect in_uops[1].bits.next_pc.valid, _in_uops_1_bits_next_pc_valid_T_1 connect in_uops[1].bits.next_pc.bits, io.enq.bits.next_pc.bits connect in_uops[1].bits.needs_replay, UInt<1>(0h0) node _in_uops_1_bits_mem_size_T = bits(io.enq.bits.exp_insts[1], 13, 12) connect in_uops[1].bits.mem_size, _in_uops_1_bits_mem_size_T connect in_uops[1].bits.ras_head, io.enq.bits.ras_head node _in_uops_1_bits_xcpt_T = or(io.enq.bits.xcpt_pf_if, io.enq.bits.xcpt_ae_if) connect in_uops[1].bits.xcpt, _in_uops_1_bits_xcpt_T node _in_uops_1_bits_edge_inst_T = and(UInt<1>(0h0), io.enq.bits.edge_inst) connect in_uops[1].bits.edge_inst, _in_uops_1_bits_edge_inst_T node _in_uops_1_bits_xcpt_cause_T = mux(io.enq.bits.xcpt_pf_if, UInt<4>(0hc), UInt<1>(0h1)) connect in_uops[1].bits.xcpt_cause, _in_uops_1_bits_xcpt_cause_T node _rvc_T_2 = bits(io.enq.bits.insts[2], 1, 0) node rvc_2 = neq(_rvc_T_2, UInt<2>(0h3)) node _cond_br_T_32 = and(io.enq.bits.exp_insts[2], UInt<15>(0h707f)) node _cond_br_T_33 = eq(UInt<13>(0h1063), _cond_br_T_32) node _cond_br_T_34 = and(io.enq.bits.exp_insts[2], UInt<15>(0h707f)) node _cond_br_T_35 = eq(UInt<15>(0h5063), _cond_br_T_34) node _cond_br_T_36 = and(io.enq.bits.exp_insts[2], UInt<15>(0h707f)) node _cond_br_T_37 = eq(UInt<15>(0h7063), _cond_br_T_36) node _cond_br_T_38 = and(io.enq.bits.exp_insts[2], UInt<15>(0h707f)) node _cond_br_T_39 = eq(UInt<7>(0h63), _cond_br_T_38) node _cond_br_T_40 = and(io.enq.bits.exp_insts[2], UInt<15>(0h707f)) node _cond_br_T_41 = eq(UInt<15>(0h4063), _cond_br_T_40) node _cond_br_T_42 = and(io.enq.bits.exp_insts[2], UInt<15>(0h707f)) node _cond_br_T_43 = eq(UInt<15>(0h6063), _cond_br_T_42) node _cond_br_T_44 = or(_cond_br_T_33, _cond_br_T_35) node _cond_br_T_45 = or(_cond_br_T_44, _cond_br_T_37) node _cond_br_T_46 = or(_cond_br_T_45, _cond_br_T_39) node _cond_br_T_47 = or(_cond_br_T_46, _cond_br_T_41) node cond_br_2 = or(_cond_br_T_47, _cond_br_T_43) node _in_uops_2_valid_T = bits(io.enq.bits.mask, 2, 2) node _in_uops_2_valid_T_1 = and(io.enq.valid, _in_uops_2_valid_T) connect in_uops[2].valid, _in_uops_2_valid_T_1 invalidate in_uops[2].bits.flush_pipe invalidate in_uops[2].bits.mem_size invalidate in_uops[2].bits.fdivin.in3 invalidate in_uops[2].bits.fdivin.in2 invalidate in_uops[2].bits.fdivin.in1 invalidate in_uops[2].bits.fdivin.fmt invalidate in_uops[2].bits.fdivin.typ invalidate in_uops[2].bits.fdivin.fmaCmd invalidate in_uops[2].bits.fdivin.rm invalidate in_uops[2].bits.fdivin.vec invalidate in_uops[2].bits.fdivin.wflags invalidate in_uops[2].bits.fdivin.sqrt invalidate in_uops[2].bits.fdivin.div invalidate in_uops[2].bits.fdivin.fma invalidate in_uops[2].bits.fdivin.fastpipe invalidate in_uops[2].bits.fdivin.toint invalidate in_uops[2].bits.fdivin.fromint invalidate in_uops[2].bits.fdivin.typeTagOut invalidate in_uops[2].bits.fdivin.typeTagIn invalidate in_uops[2].bits.fdivin.swap23 invalidate in_uops[2].bits.fdivin.swap12 invalidate in_uops[2].bits.fdivin.ren3 invalidate in_uops[2].bits.fdivin.ren2 invalidate in_uops[2].bits.fdivin.ren1 invalidate in_uops[2].bits.fdivin.wen invalidate in_uops[2].bits.fdivin.ldst invalidate in_uops[2].bits.fexc invalidate in_uops[2].bits.fra3 invalidate in_uops[2].bits.fra2 invalidate in_uops[2].bits.fra1 invalidate in_uops[2].bits.wdata.bits invalidate in_uops[2].bits.wdata.valid invalidate in_uops[2].bits.uses_latealu invalidate in_uops[2].bits.uses_memalu invalidate in_uops[2].bits.rs3_data invalidate in_uops[2].bits.rs2_data invalidate in_uops[2].bits.rs1_data invalidate in_uops[2].bits.needs_replay invalidate in_uops[2].bits.xcpt_cause invalidate in_uops[2].bits.xcpt invalidate in_uops[2].bits.taken invalidate in_uops[2].bits.ras_head invalidate in_uops[2].bits.next_pc.bits invalidate in_uops[2].bits.next_pc.valid invalidate in_uops[2].bits.sfb_shadow invalidate in_uops[2].bits.sfb_br invalidate in_uops[2].bits.btb_resp.bits.bht.value invalidate in_uops[2].bits.btb_resp.bits.bht.history invalidate in_uops[2].bits.btb_resp.bits.entry invalidate in_uops[2].bits.btb_resp.bits.target invalidate in_uops[2].bits.btb_resp.bits.bridx invalidate in_uops[2].bits.btb_resp.bits.mask invalidate in_uops[2].bits.btb_resp.bits.taken invalidate in_uops[2].bits.btb_resp.bits.cfiType invalidate in_uops[2].bits.btb_resp.valid invalidate in_uops[2].bits.sets_vcfg invalidate in_uops[2].bits.rvc invalidate in_uops[2].bits.fp_ctrl.vec invalidate in_uops[2].bits.fp_ctrl.wflags invalidate in_uops[2].bits.fp_ctrl.sqrt invalidate in_uops[2].bits.fp_ctrl.div invalidate in_uops[2].bits.fp_ctrl.fma invalidate in_uops[2].bits.fp_ctrl.fastpipe invalidate in_uops[2].bits.fp_ctrl.toint invalidate in_uops[2].bits.fp_ctrl.fromint invalidate in_uops[2].bits.fp_ctrl.typeTagOut invalidate in_uops[2].bits.fp_ctrl.typeTagIn invalidate in_uops[2].bits.fp_ctrl.swap23 invalidate in_uops[2].bits.fp_ctrl.swap12 invalidate in_uops[2].bits.fp_ctrl.ren3 invalidate in_uops[2].bits.fp_ctrl.ren2 invalidate in_uops[2].bits.fp_ctrl.ren1 invalidate in_uops[2].bits.fp_ctrl.wen invalidate in_uops[2].bits.fp_ctrl.ldst invalidate in_uops[2].bits.ctrl.vec invalidate in_uops[2].bits.ctrl.dp invalidate in_uops[2].bits.ctrl.amo invalidate in_uops[2].bits.ctrl.fence invalidate in_uops[2].bits.ctrl.fence_i invalidate in_uops[2].bits.ctrl.csr invalidate in_uops[2].bits.ctrl.wxd invalidate in_uops[2].bits.ctrl.div invalidate in_uops[2].bits.ctrl.mul invalidate in_uops[2].bits.ctrl.wfd invalidate in_uops[2].bits.ctrl.rfs3 invalidate in_uops[2].bits.ctrl.rfs2 invalidate in_uops[2].bits.ctrl.rfs1 invalidate in_uops[2].bits.ctrl.mem_cmd invalidate in_uops[2].bits.ctrl.mem invalidate in_uops[2].bits.ctrl.alu_fn invalidate in_uops[2].bits.ctrl.alu_dw invalidate in_uops[2].bits.ctrl.sel_imm invalidate in_uops[2].bits.ctrl.sel_alu1 invalidate in_uops[2].bits.ctrl.sel_alu2 invalidate in_uops[2].bits.ctrl.rxs1 invalidate in_uops[2].bits.ctrl.rxs2 invalidate in_uops[2].bits.ctrl.jalr invalidate in_uops[2].bits.ctrl.jal invalidate in_uops[2].bits.ctrl.branch invalidate in_uops[2].bits.ctrl.rocc invalidate in_uops[2].bits.ctrl.fp invalidate in_uops[2].bits.ctrl.legal invalidate in_uops[2].bits.edge_inst invalidate in_uops[2].bits.pc invalidate in_uops[2].bits.raw_inst invalidate in_uops[2].bits.inst connect in_uops[2].bits.pc, io.enq.bits.pcs[2] invalidate in_uops[2].bits.ctrl.vec invalidate in_uops[2].bits.ctrl.dp invalidate in_uops[2].bits.ctrl.amo invalidate in_uops[2].bits.ctrl.fence invalidate in_uops[2].bits.ctrl.fence_i invalidate in_uops[2].bits.ctrl.csr invalidate in_uops[2].bits.ctrl.wxd invalidate in_uops[2].bits.ctrl.div invalidate in_uops[2].bits.ctrl.mul invalidate in_uops[2].bits.ctrl.wfd invalidate in_uops[2].bits.ctrl.rfs3 invalidate in_uops[2].bits.ctrl.rfs2 invalidate in_uops[2].bits.ctrl.rfs1 invalidate in_uops[2].bits.ctrl.mem_cmd invalidate in_uops[2].bits.ctrl.mem invalidate in_uops[2].bits.ctrl.alu_fn invalidate in_uops[2].bits.ctrl.alu_dw invalidate in_uops[2].bits.ctrl.sel_imm invalidate in_uops[2].bits.ctrl.sel_alu1 invalidate in_uops[2].bits.ctrl.sel_alu2 invalidate in_uops[2].bits.ctrl.rxs1 invalidate in_uops[2].bits.ctrl.rxs2 invalidate in_uops[2].bits.ctrl.jalr invalidate in_uops[2].bits.ctrl.jal invalidate in_uops[2].bits.ctrl.branch invalidate in_uops[2].bits.ctrl.rocc invalidate in_uops[2].bits.ctrl.fp invalidate in_uops[2].bits.ctrl.legal invalidate in_uops[2].bits.fp_ctrl.vec invalidate in_uops[2].bits.fp_ctrl.wflags invalidate in_uops[2].bits.fp_ctrl.sqrt invalidate in_uops[2].bits.fp_ctrl.div invalidate in_uops[2].bits.fp_ctrl.fma invalidate in_uops[2].bits.fp_ctrl.fastpipe invalidate in_uops[2].bits.fp_ctrl.toint invalidate in_uops[2].bits.fp_ctrl.fromint invalidate in_uops[2].bits.fp_ctrl.typeTagOut invalidate in_uops[2].bits.fp_ctrl.typeTagIn invalidate in_uops[2].bits.fp_ctrl.swap23 invalidate in_uops[2].bits.fp_ctrl.swap12 invalidate in_uops[2].bits.fp_ctrl.ren3 invalidate in_uops[2].bits.fp_ctrl.ren2 invalidate in_uops[2].bits.fp_ctrl.ren1 invalidate in_uops[2].bits.fp_ctrl.wen invalidate in_uops[2].bits.fp_ctrl.ldst connect in_uops[2].bits.inst, io.enq.bits.exp_insts[2] connect in_uops[2].bits.raw_inst, io.enq.bits.insts[2] node _in_uops_2_bits_rvc_T = bits(io.enq.bits.insts[2], 1, 0) node _in_uops_2_bits_rvc_T_1 = neq(_in_uops_2_bits_rvc_T, UInt<2>(0h3)) connect in_uops[2].bits.rvc, _in_uops_2_bits_rvc_T_1 node _in_uops_2_bits_sfb_br_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_2_bits_sfb_br_sign_T_1 = bits(io.enq.bits.exp_insts[2], 31, 31) node _in_uops_2_bits_sfb_br_sign_T_2 = asSInt(_in_uops_2_bits_sfb_br_sign_T_1) node in_uops_2_bits_sfb_br_sign = mux(_in_uops_2_bits_sfb_br_sign_T, asSInt(UInt<1>(0h0)), _in_uops_2_bits_sfb_br_sign_T_2) node _in_uops_2_bits_sfb_br_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_2_bits_sfb_br_b30_20_T_1 = bits(io.enq.bits.exp_insts[2], 30, 20) node _in_uops_2_bits_sfb_br_b30_20_T_2 = asSInt(_in_uops_2_bits_sfb_br_b30_20_T_1) node in_uops_2_bits_sfb_br_b30_20 = mux(_in_uops_2_bits_sfb_br_b30_20_T, _in_uops_2_bits_sfb_br_b30_20_T_2, in_uops_2_bits_sfb_br_sign) node _in_uops_2_bits_sfb_br_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_2_bits_sfb_br_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_2_bits_sfb_br_b19_12_T_2 = and(_in_uops_2_bits_sfb_br_b19_12_T, _in_uops_2_bits_sfb_br_b19_12_T_1) node _in_uops_2_bits_sfb_br_b19_12_T_3 = bits(io.enq.bits.exp_insts[2], 19, 12) node _in_uops_2_bits_sfb_br_b19_12_T_4 = asSInt(_in_uops_2_bits_sfb_br_b19_12_T_3) node in_uops_2_bits_sfb_br_b19_12 = mux(_in_uops_2_bits_sfb_br_b19_12_T_2, in_uops_2_bits_sfb_br_sign, _in_uops_2_bits_sfb_br_b19_12_T_4) node _in_uops_2_bits_sfb_br_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_2_bits_sfb_br_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_2_bits_sfb_br_b11_T_2 = or(_in_uops_2_bits_sfb_br_b11_T, _in_uops_2_bits_sfb_br_b11_T_1) node _in_uops_2_bits_sfb_br_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_2_bits_sfb_br_b11_T_4 = bits(io.enq.bits.exp_insts[2], 20, 20) node _in_uops_2_bits_sfb_br_b11_T_5 = asSInt(_in_uops_2_bits_sfb_br_b11_T_4) node _in_uops_2_bits_sfb_br_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_2_bits_sfb_br_b11_T_7 = bits(io.enq.bits.exp_insts[2], 7, 7) node _in_uops_2_bits_sfb_br_b11_T_8 = asSInt(_in_uops_2_bits_sfb_br_b11_T_7) node _in_uops_2_bits_sfb_br_b11_T_9 = mux(_in_uops_2_bits_sfb_br_b11_T_6, _in_uops_2_bits_sfb_br_b11_T_8, in_uops_2_bits_sfb_br_sign) node _in_uops_2_bits_sfb_br_b11_T_10 = mux(_in_uops_2_bits_sfb_br_b11_T_3, _in_uops_2_bits_sfb_br_b11_T_5, _in_uops_2_bits_sfb_br_b11_T_9) node in_uops_2_bits_sfb_br_b11 = mux(_in_uops_2_bits_sfb_br_b11_T_2, asSInt(UInt<1>(0h0)), _in_uops_2_bits_sfb_br_b11_T_10) node _in_uops_2_bits_sfb_br_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_2_bits_sfb_br_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_2_bits_sfb_br_b10_5_T_2 = or(_in_uops_2_bits_sfb_br_b10_5_T, _in_uops_2_bits_sfb_br_b10_5_T_1) node _in_uops_2_bits_sfb_br_b10_5_T_3 = bits(io.enq.bits.exp_insts[2], 30, 25) node in_uops_2_bits_sfb_br_b10_5 = mux(_in_uops_2_bits_sfb_br_b10_5_T_2, UInt<1>(0h0), _in_uops_2_bits_sfb_br_b10_5_T_3) node _in_uops_2_bits_sfb_br_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_2_bits_sfb_br_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_2_bits_sfb_br_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_2_bits_sfb_br_b4_1_T_3 = or(_in_uops_2_bits_sfb_br_b4_1_T_1, _in_uops_2_bits_sfb_br_b4_1_T_2) node _in_uops_2_bits_sfb_br_b4_1_T_4 = bits(io.enq.bits.exp_insts[2], 11, 8) node _in_uops_2_bits_sfb_br_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_2_bits_sfb_br_b4_1_T_6 = bits(io.enq.bits.exp_insts[2], 19, 16) node _in_uops_2_bits_sfb_br_b4_1_T_7 = bits(io.enq.bits.exp_insts[2], 24, 21) node _in_uops_2_bits_sfb_br_b4_1_T_8 = mux(_in_uops_2_bits_sfb_br_b4_1_T_5, _in_uops_2_bits_sfb_br_b4_1_T_6, _in_uops_2_bits_sfb_br_b4_1_T_7) node _in_uops_2_bits_sfb_br_b4_1_T_9 = mux(_in_uops_2_bits_sfb_br_b4_1_T_3, _in_uops_2_bits_sfb_br_b4_1_T_4, _in_uops_2_bits_sfb_br_b4_1_T_8) node in_uops_2_bits_sfb_br_b4_1 = mux(_in_uops_2_bits_sfb_br_b4_1_T, UInt<1>(0h0), _in_uops_2_bits_sfb_br_b4_1_T_9) node _in_uops_2_bits_sfb_br_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_2_bits_sfb_br_b0_T_1 = bits(io.enq.bits.exp_insts[2], 7, 7) node _in_uops_2_bits_sfb_br_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _in_uops_2_bits_sfb_br_b0_T_3 = bits(io.enq.bits.exp_insts[2], 20, 20) node _in_uops_2_bits_sfb_br_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_2_bits_sfb_br_b0_T_5 = bits(io.enq.bits.exp_insts[2], 15, 15) node _in_uops_2_bits_sfb_br_b0_T_6 = mux(_in_uops_2_bits_sfb_br_b0_T_4, _in_uops_2_bits_sfb_br_b0_T_5, UInt<1>(0h0)) node _in_uops_2_bits_sfb_br_b0_T_7 = mux(_in_uops_2_bits_sfb_br_b0_T_2, _in_uops_2_bits_sfb_br_b0_T_3, _in_uops_2_bits_sfb_br_b0_T_6) node in_uops_2_bits_sfb_br_b0 = mux(_in_uops_2_bits_sfb_br_b0_T, _in_uops_2_bits_sfb_br_b0_T_1, _in_uops_2_bits_sfb_br_b0_T_7) node in_uops_2_bits_sfb_br_lo_hi = cat(in_uops_2_bits_sfb_br_b10_5, in_uops_2_bits_sfb_br_b4_1) node in_uops_2_bits_sfb_br_lo = cat(in_uops_2_bits_sfb_br_lo_hi, in_uops_2_bits_sfb_br_b0) node in_uops_2_bits_sfb_br_hi_lo_lo = asUInt(in_uops_2_bits_sfb_br_b11) node in_uops_2_bits_sfb_br_hi_lo_hi = asUInt(in_uops_2_bits_sfb_br_b19_12) node in_uops_2_bits_sfb_br_hi_lo = cat(in_uops_2_bits_sfb_br_hi_lo_hi, in_uops_2_bits_sfb_br_hi_lo_lo) node in_uops_2_bits_sfb_br_hi_hi_lo = asUInt(in_uops_2_bits_sfb_br_b30_20) node in_uops_2_bits_sfb_br_hi_hi_hi = asUInt(in_uops_2_bits_sfb_br_sign) node in_uops_2_bits_sfb_br_hi_hi = cat(in_uops_2_bits_sfb_br_hi_hi_hi, in_uops_2_bits_sfb_br_hi_hi_lo) node in_uops_2_bits_sfb_br_hi = cat(in_uops_2_bits_sfb_br_hi_hi, in_uops_2_bits_sfb_br_hi_lo) node _in_uops_2_bits_sfb_br_T = cat(in_uops_2_bits_sfb_br_hi, in_uops_2_bits_sfb_br_lo) node _in_uops_2_bits_sfb_br_T_1 = asSInt(_in_uops_2_bits_sfb_br_T) node _in_uops_2_bits_sfb_br_T_2 = mux(rvc_2, asSInt(UInt<4>(0h4)), asSInt(UInt<4>(0h6))) node _in_uops_2_bits_sfb_br_T_3 = eq(_in_uops_2_bits_sfb_br_T_1, _in_uops_2_bits_sfb_br_T_2) node _in_uops_2_bits_sfb_br_T_4 = and(cond_br_2, _in_uops_2_bits_sfb_br_T_3) node _in_uops_2_bits_sfb_br_T_5 = eq(io.enq.bits.next_pc.valid, UInt<1>(0h0)) node _in_uops_2_bits_sfb_br_T_6 = and(_in_uops_2_bits_sfb_br_T_4, _in_uops_2_bits_sfb_br_T_5) connect in_uops[2].bits.sfb_br, _in_uops_2_bits_sfb_br_T_6 connect in_uops[2].bits.btb_resp, io.enq.bits.btb_resp node _in_uops_2_bits_next_pc_valid_T = bits(maybe_cfi_mask, 2, 2) node _in_uops_2_bits_next_pc_valid_T_1 = and(io.enq.bits.next_pc.valid, _in_uops_2_bits_next_pc_valid_T) connect in_uops[2].bits.next_pc.valid, _in_uops_2_bits_next_pc_valid_T_1 connect in_uops[2].bits.next_pc.bits, io.enq.bits.next_pc.bits connect in_uops[2].bits.needs_replay, UInt<1>(0h0) node _in_uops_2_bits_mem_size_T = bits(io.enq.bits.exp_insts[2], 13, 12) connect in_uops[2].bits.mem_size, _in_uops_2_bits_mem_size_T connect in_uops[2].bits.ras_head, io.enq.bits.ras_head node _in_uops_2_bits_xcpt_T = or(io.enq.bits.xcpt_pf_if, io.enq.bits.xcpt_ae_if) connect in_uops[2].bits.xcpt, _in_uops_2_bits_xcpt_T node _in_uops_2_bits_edge_inst_T = and(UInt<1>(0h0), io.enq.bits.edge_inst) connect in_uops[2].bits.edge_inst, _in_uops_2_bits_edge_inst_T node _in_uops_2_bits_xcpt_cause_T = mux(io.enq.bits.xcpt_pf_if, UInt<4>(0hc), UInt<1>(0h1)) connect in_uops[2].bits.xcpt_cause, _in_uops_2_bits_xcpt_cause_T node _rvc_T_3 = bits(io.enq.bits.insts[3], 1, 0) node rvc_3 = neq(_rvc_T_3, UInt<2>(0h3)) node _cond_br_T_48 = and(io.enq.bits.exp_insts[3], UInt<15>(0h707f)) node _cond_br_T_49 = eq(UInt<13>(0h1063), _cond_br_T_48) node _cond_br_T_50 = and(io.enq.bits.exp_insts[3], UInt<15>(0h707f)) node _cond_br_T_51 = eq(UInt<15>(0h5063), _cond_br_T_50) node _cond_br_T_52 = and(io.enq.bits.exp_insts[3], UInt<15>(0h707f)) node _cond_br_T_53 = eq(UInt<15>(0h7063), _cond_br_T_52) node _cond_br_T_54 = and(io.enq.bits.exp_insts[3], UInt<15>(0h707f)) node _cond_br_T_55 = eq(UInt<7>(0h63), _cond_br_T_54) node _cond_br_T_56 = and(io.enq.bits.exp_insts[3], UInt<15>(0h707f)) node _cond_br_T_57 = eq(UInt<15>(0h4063), _cond_br_T_56) node _cond_br_T_58 = and(io.enq.bits.exp_insts[3], UInt<15>(0h707f)) node _cond_br_T_59 = eq(UInt<15>(0h6063), _cond_br_T_58) node _cond_br_T_60 = or(_cond_br_T_49, _cond_br_T_51) node _cond_br_T_61 = or(_cond_br_T_60, _cond_br_T_53) node _cond_br_T_62 = or(_cond_br_T_61, _cond_br_T_55) node _cond_br_T_63 = or(_cond_br_T_62, _cond_br_T_57) node cond_br_3 = or(_cond_br_T_63, _cond_br_T_59) node _in_uops_3_valid_T = bits(io.enq.bits.mask, 3, 3) node _in_uops_3_valid_T_1 = and(io.enq.valid, _in_uops_3_valid_T) connect in_uops[3].valid, _in_uops_3_valid_T_1 invalidate in_uops[3].bits.flush_pipe invalidate in_uops[3].bits.mem_size invalidate in_uops[3].bits.fdivin.in3 invalidate in_uops[3].bits.fdivin.in2 invalidate in_uops[3].bits.fdivin.in1 invalidate in_uops[3].bits.fdivin.fmt invalidate in_uops[3].bits.fdivin.typ invalidate in_uops[3].bits.fdivin.fmaCmd invalidate in_uops[3].bits.fdivin.rm invalidate in_uops[3].bits.fdivin.vec invalidate in_uops[3].bits.fdivin.wflags invalidate in_uops[3].bits.fdivin.sqrt invalidate in_uops[3].bits.fdivin.div invalidate in_uops[3].bits.fdivin.fma invalidate in_uops[3].bits.fdivin.fastpipe invalidate in_uops[3].bits.fdivin.toint invalidate in_uops[3].bits.fdivin.fromint invalidate in_uops[3].bits.fdivin.typeTagOut invalidate in_uops[3].bits.fdivin.typeTagIn invalidate in_uops[3].bits.fdivin.swap23 invalidate in_uops[3].bits.fdivin.swap12 invalidate in_uops[3].bits.fdivin.ren3 invalidate in_uops[3].bits.fdivin.ren2 invalidate in_uops[3].bits.fdivin.ren1 invalidate in_uops[3].bits.fdivin.wen invalidate in_uops[3].bits.fdivin.ldst invalidate in_uops[3].bits.fexc invalidate in_uops[3].bits.fra3 invalidate in_uops[3].bits.fra2 invalidate in_uops[3].bits.fra1 invalidate in_uops[3].bits.wdata.bits invalidate in_uops[3].bits.wdata.valid invalidate in_uops[3].bits.uses_latealu invalidate in_uops[3].bits.uses_memalu invalidate in_uops[3].bits.rs3_data invalidate in_uops[3].bits.rs2_data invalidate in_uops[3].bits.rs1_data invalidate in_uops[3].bits.needs_replay invalidate in_uops[3].bits.xcpt_cause invalidate in_uops[3].bits.xcpt invalidate in_uops[3].bits.taken invalidate in_uops[3].bits.ras_head invalidate in_uops[3].bits.next_pc.bits invalidate in_uops[3].bits.next_pc.valid invalidate in_uops[3].bits.sfb_shadow invalidate in_uops[3].bits.sfb_br invalidate in_uops[3].bits.btb_resp.bits.bht.value invalidate in_uops[3].bits.btb_resp.bits.bht.history invalidate in_uops[3].bits.btb_resp.bits.entry invalidate in_uops[3].bits.btb_resp.bits.target invalidate in_uops[3].bits.btb_resp.bits.bridx invalidate in_uops[3].bits.btb_resp.bits.mask invalidate in_uops[3].bits.btb_resp.bits.taken invalidate in_uops[3].bits.btb_resp.bits.cfiType invalidate in_uops[3].bits.btb_resp.valid invalidate in_uops[3].bits.sets_vcfg invalidate in_uops[3].bits.rvc invalidate in_uops[3].bits.fp_ctrl.vec invalidate in_uops[3].bits.fp_ctrl.wflags invalidate in_uops[3].bits.fp_ctrl.sqrt invalidate in_uops[3].bits.fp_ctrl.div invalidate in_uops[3].bits.fp_ctrl.fma invalidate in_uops[3].bits.fp_ctrl.fastpipe invalidate in_uops[3].bits.fp_ctrl.toint invalidate in_uops[3].bits.fp_ctrl.fromint invalidate in_uops[3].bits.fp_ctrl.typeTagOut invalidate in_uops[3].bits.fp_ctrl.typeTagIn invalidate in_uops[3].bits.fp_ctrl.swap23 invalidate in_uops[3].bits.fp_ctrl.swap12 invalidate in_uops[3].bits.fp_ctrl.ren3 invalidate in_uops[3].bits.fp_ctrl.ren2 invalidate in_uops[3].bits.fp_ctrl.ren1 invalidate in_uops[3].bits.fp_ctrl.wen invalidate in_uops[3].bits.fp_ctrl.ldst invalidate in_uops[3].bits.ctrl.vec invalidate in_uops[3].bits.ctrl.dp invalidate in_uops[3].bits.ctrl.amo invalidate in_uops[3].bits.ctrl.fence invalidate in_uops[3].bits.ctrl.fence_i invalidate in_uops[3].bits.ctrl.csr invalidate in_uops[3].bits.ctrl.wxd invalidate in_uops[3].bits.ctrl.div invalidate in_uops[3].bits.ctrl.mul invalidate in_uops[3].bits.ctrl.wfd invalidate in_uops[3].bits.ctrl.rfs3 invalidate in_uops[3].bits.ctrl.rfs2 invalidate in_uops[3].bits.ctrl.rfs1 invalidate in_uops[3].bits.ctrl.mem_cmd invalidate in_uops[3].bits.ctrl.mem invalidate in_uops[3].bits.ctrl.alu_fn invalidate in_uops[3].bits.ctrl.alu_dw invalidate in_uops[3].bits.ctrl.sel_imm invalidate in_uops[3].bits.ctrl.sel_alu1 invalidate in_uops[3].bits.ctrl.sel_alu2 invalidate in_uops[3].bits.ctrl.rxs1 invalidate in_uops[3].bits.ctrl.rxs2 invalidate in_uops[3].bits.ctrl.jalr invalidate in_uops[3].bits.ctrl.jal invalidate in_uops[3].bits.ctrl.branch invalidate in_uops[3].bits.ctrl.rocc invalidate in_uops[3].bits.ctrl.fp invalidate in_uops[3].bits.ctrl.legal invalidate in_uops[3].bits.edge_inst invalidate in_uops[3].bits.pc invalidate in_uops[3].bits.raw_inst invalidate in_uops[3].bits.inst connect in_uops[3].bits.pc, io.enq.bits.pcs[3] invalidate in_uops[3].bits.ctrl.vec invalidate in_uops[3].bits.ctrl.dp invalidate in_uops[3].bits.ctrl.amo invalidate in_uops[3].bits.ctrl.fence invalidate in_uops[3].bits.ctrl.fence_i invalidate in_uops[3].bits.ctrl.csr invalidate in_uops[3].bits.ctrl.wxd invalidate in_uops[3].bits.ctrl.div invalidate in_uops[3].bits.ctrl.mul invalidate in_uops[3].bits.ctrl.wfd invalidate in_uops[3].bits.ctrl.rfs3 invalidate in_uops[3].bits.ctrl.rfs2 invalidate in_uops[3].bits.ctrl.rfs1 invalidate in_uops[3].bits.ctrl.mem_cmd invalidate in_uops[3].bits.ctrl.mem invalidate in_uops[3].bits.ctrl.alu_fn invalidate in_uops[3].bits.ctrl.alu_dw invalidate in_uops[3].bits.ctrl.sel_imm invalidate in_uops[3].bits.ctrl.sel_alu1 invalidate in_uops[3].bits.ctrl.sel_alu2 invalidate in_uops[3].bits.ctrl.rxs1 invalidate in_uops[3].bits.ctrl.rxs2 invalidate in_uops[3].bits.ctrl.jalr invalidate in_uops[3].bits.ctrl.jal invalidate in_uops[3].bits.ctrl.branch invalidate in_uops[3].bits.ctrl.rocc invalidate in_uops[3].bits.ctrl.fp invalidate in_uops[3].bits.ctrl.legal invalidate in_uops[3].bits.fp_ctrl.vec invalidate in_uops[3].bits.fp_ctrl.wflags invalidate in_uops[3].bits.fp_ctrl.sqrt invalidate in_uops[3].bits.fp_ctrl.div invalidate in_uops[3].bits.fp_ctrl.fma invalidate in_uops[3].bits.fp_ctrl.fastpipe invalidate in_uops[3].bits.fp_ctrl.toint invalidate in_uops[3].bits.fp_ctrl.fromint invalidate in_uops[3].bits.fp_ctrl.typeTagOut invalidate in_uops[3].bits.fp_ctrl.typeTagIn invalidate in_uops[3].bits.fp_ctrl.swap23 invalidate in_uops[3].bits.fp_ctrl.swap12 invalidate in_uops[3].bits.fp_ctrl.ren3 invalidate in_uops[3].bits.fp_ctrl.ren2 invalidate in_uops[3].bits.fp_ctrl.ren1 invalidate in_uops[3].bits.fp_ctrl.wen invalidate in_uops[3].bits.fp_ctrl.ldst connect in_uops[3].bits.inst, io.enq.bits.exp_insts[3] connect in_uops[3].bits.raw_inst, io.enq.bits.insts[3] node _in_uops_3_bits_rvc_T = bits(io.enq.bits.insts[3], 1, 0) node _in_uops_3_bits_rvc_T_1 = neq(_in_uops_3_bits_rvc_T, UInt<2>(0h3)) connect in_uops[3].bits.rvc, _in_uops_3_bits_rvc_T_1 node _in_uops_3_bits_sfb_br_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_3_bits_sfb_br_sign_T_1 = bits(io.enq.bits.exp_insts[3], 31, 31) node _in_uops_3_bits_sfb_br_sign_T_2 = asSInt(_in_uops_3_bits_sfb_br_sign_T_1) node in_uops_3_bits_sfb_br_sign = mux(_in_uops_3_bits_sfb_br_sign_T, asSInt(UInt<1>(0h0)), _in_uops_3_bits_sfb_br_sign_T_2) node _in_uops_3_bits_sfb_br_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_3_bits_sfb_br_b30_20_T_1 = bits(io.enq.bits.exp_insts[3], 30, 20) node _in_uops_3_bits_sfb_br_b30_20_T_2 = asSInt(_in_uops_3_bits_sfb_br_b30_20_T_1) node in_uops_3_bits_sfb_br_b30_20 = mux(_in_uops_3_bits_sfb_br_b30_20_T, _in_uops_3_bits_sfb_br_b30_20_T_2, in_uops_3_bits_sfb_br_sign) node _in_uops_3_bits_sfb_br_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_3_bits_sfb_br_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_3_bits_sfb_br_b19_12_T_2 = and(_in_uops_3_bits_sfb_br_b19_12_T, _in_uops_3_bits_sfb_br_b19_12_T_1) node _in_uops_3_bits_sfb_br_b19_12_T_3 = bits(io.enq.bits.exp_insts[3], 19, 12) node _in_uops_3_bits_sfb_br_b19_12_T_4 = asSInt(_in_uops_3_bits_sfb_br_b19_12_T_3) node in_uops_3_bits_sfb_br_b19_12 = mux(_in_uops_3_bits_sfb_br_b19_12_T_2, in_uops_3_bits_sfb_br_sign, _in_uops_3_bits_sfb_br_b19_12_T_4) node _in_uops_3_bits_sfb_br_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_3_bits_sfb_br_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_3_bits_sfb_br_b11_T_2 = or(_in_uops_3_bits_sfb_br_b11_T, _in_uops_3_bits_sfb_br_b11_T_1) node _in_uops_3_bits_sfb_br_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _in_uops_3_bits_sfb_br_b11_T_4 = bits(io.enq.bits.exp_insts[3], 20, 20) node _in_uops_3_bits_sfb_br_b11_T_5 = asSInt(_in_uops_3_bits_sfb_br_b11_T_4) node _in_uops_3_bits_sfb_br_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_3_bits_sfb_br_b11_T_7 = bits(io.enq.bits.exp_insts[3], 7, 7) node _in_uops_3_bits_sfb_br_b11_T_8 = asSInt(_in_uops_3_bits_sfb_br_b11_T_7) node _in_uops_3_bits_sfb_br_b11_T_9 = mux(_in_uops_3_bits_sfb_br_b11_T_6, _in_uops_3_bits_sfb_br_b11_T_8, in_uops_3_bits_sfb_br_sign) node _in_uops_3_bits_sfb_br_b11_T_10 = mux(_in_uops_3_bits_sfb_br_b11_T_3, _in_uops_3_bits_sfb_br_b11_T_5, _in_uops_3_bits_sfb_br_b11_T_9) node in_uops_3_bits_sfb_br_b11 = mux(_in_uops_3_bits_sfb_br_b11_T_2, asSInt(UInt<1>(0h0)), _in_uops_3_bits_sfb_br_b11_T_10) node _in_uops_3_bits_sfb_br_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_3_bits_sfb_br_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_3_bits_sfb_br_b10_5_T_2 = or(_in_uops_3_bits_sfb_br_b10_5_T, _in_uops_3_bits_sfb_br_b10_5_T_1) node _in_uops_3_bits_sfb_br_b10_5_T_3 = bits(io.enq.bits.exp_insts[3], 30, 25) node in_uops_3_bits_sfb_br_b10_5 = mux(_in_uops_3_bits_sfb_br_b10_5_T_2, UInt<1>(0h0), _in_uops_3_bits_sfb_br_b10_5_T_3) node _in_uops_3_bits_sfb_br_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _in_uops_3_bits_sfb_br_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_3_bits_sfb_br_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _in_uops_3_bits_sfb_br_b4_1_T_3 = or(_in_uops_3_bits_sfb_br_b4_1_T_1, _in_uops_3_bits_sfb_br_b4_1_T_2) node _in_uops_3_bits_sfb_br_b4_1_T_4 = bits(io.enq.bits.exp_insts[3], 11, 8) node _in_uops_3_bits_sfb_br_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_3_bits_sfb_br_b4_1_T_6 = bits(io.enq.bits.exp_insts[3], 19, 16) node _in_uops_3_bits_sfb_br_b4_1_T_7 = bits(io.enq.bits.exp_insts[3], 24, 21) node _in_uops_3_bits_sfb_br_b4_1_T_8 = mux(_in_uops_3_bits_sfb_br_b4_1_T_5, _in_uops_3_bits_sfb_br_b4_1_T_6, _in_uops_3_bits_sfb_br_b4_1_T_7) node _in_uops_3_bits_sfb_br_b4_1_T_9 = mux(_in_uops_3_bits_sfb_br_b4_1_T_3, _in_uops_3_bits_sfb_br_b4_1_T_4, _in_uops_3_bits_sfb_br_b4_1_T_8) node in_uops_3_bits_sfb_br_b4_1 = mux(_in_uops_3_bits_sfb_br_b4_1_T, UInt<1>(0h0), _in_uops_3_bits_sfb_br_b4_1_T_9) node _in_uops_3_bits_sfb_br_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) node _in_uops_3_bits_sfb_br_b0_T_1 = bits(io.enq.bits.exp_insts[3], 7, 7) node _in_uops_3_bits_sfb_br_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _in_uops_3_bits_sfb_br_b0_T_3 = bits(io.enq.bits.exp_insts[3], 20, 20) node _in_uops_3_bits_sfb_br_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _in_uops_3_bits_sfb_br_b0_T_5 = bits(io.enq.bits.exp_insts[3], 15, 15) node _in_uops_3_bits_sfb_br_b0_T_6 = mux(_in_uops_3_bits_sfb_br_b0_T_4, _in_uops_3_bits_sfb_br_b0_T_5, UInt<1>(0h0)) node _in_uops_3_bits_sfb_br_b0_T_7 = mux(_in_uops_3_bits_sfb_br_b0_T_2, _in_uops_3_bits_sfb_br_b0_T_3, _in_uops_3_bits_sfb_br_b0_T_6) node in_uops_3_bits_sfb_br_b0 = mux(_in_uops_3_bits_sfb_br_b0_T, _in_uops_3_bits_sfb_br_b0_T_1, _in_uops_3_bits_sfb_br_b0_T_7) node in_uops_3_bits_sfb_br_lo_hi = cat(in_uops_3_bits_sfb_br_b10_5, in_uops_3_bits_sfb_br_b4_1) node in_uops_3_bits_sfb_br_lo = cat(in_uops_3_bits_sfb_br_lo_hi, in_uops_3_bits_sfb_br_b0) node in_uops_3_bits_sfb_br_hi_lo_lo = asUInt(in_uops_3_bits_sfb_br_b11) node in_uops_3_bits_sfb_br_hi_lo_hi = asUInt(in_uops_3_bits_sfb_br_b19_12) node in_uops_3_bits_sfb_br_hi_lo = cat(in_uops_3_bits_sfb_br_hi_lo_hi, in_uops_3_bits_sfb_br_hi_lo_lo) node in_uops_3_bits_sfb_br_hi_hi_lo = asUInt(in_uops_3_bits_sfb_br_b30_20) node in_uops_3_bits_sfb_br_hi_hi_hi = asUInt(in_uops_3_bits_sfb_br_sign) node in_uops_3_bits_sfb_br_hi_hi = cat(in_uops_3_bits_sfb_br_hi_hi_hi, in_uops_3_bits_sfb_br_hi_hi_lo) node in_uops_3_bits_sfb_br_hi = cat(in_uops_3_bits_sfb_br_hi_hi, in_uops_3_bits_sfb_br_hi_lo) node _in_uops_3_bits_sfb_br_T = cat(in_uops_3_bits_sfb_br_hi, in_uops_3_bits_sfb_br_lo) node _in_uops_3_bits_sfb_br_T_1 = asSInt(_in_uops_3_bits_sfb_br_T) node _in_uops_3_bits_sfb_br_T_2 = mux(rvc_3, asSInt(UInt<4>(0h4)), asSInt(UInt<4>(0h6))) node _in_uops_3_bits_sfb_br_T_3 = eq(_in_uops_3_bits_sfb_br_T_1, _in_uops_3_bits_sfb_br_T_2) node _in_uops_3_bits_sfb_br_T_4 = and(cond_br_3, _in_uops_3_bits_sfb_br_T_3) node _in_uops_3_bits_sfb_br_T_5 = eq(io.enq.bits.next_pc.valid, UInt<1>(0h0)) node _in_uops_3_bits_sfb_br_T_6 = and(_in_uops_3_bits_sfb_br_T_4, _in_uops_3_bits_sfb_br_T_5) connect in_uops[3].bits.sfb_br, _in_uops_3_bits_sfb_br_T_6 connect in_uops[3].bits.btb_resp, io.enq.bits.btb_resp node _in_uops_3_bits_next_pc_valid_T = bits(maybe_cfi_mask, 3, 3) node _in_uops_3_bits_next_pc_valid_T_1 = and(io.enq.bits.next_pc.valid, _in_uops_3_bits_next_pc_valid_T) connect in_uops[3].bits.next_pc.valid, _in_uops_3_bits_next_pc_valid_T_1 connect in_uops[3].bits.next_pc.bits, io.enq.bits.next_pc.bits connect in_uops[3].bits.needs_replay, UInt<1>(0h0) node _in_uops_3_bits_mem_size_T = bits(io.enq.bits.exp_insts[3], 13, 12) connect in_uops[3].bits.mem_size, _in_uops_3_bits_mem_size_T connect in_uops[3].bits.ras_head, io.enq.bits.ras_head node _in_uops_3_bits_xcpt_T = or(io.enq.bits.xcpt_pf_if, io.enq.bits.xcpt_ae_if) connect in_uops[3].bits.xcpt, _in_uops_3_bits_xcpt_T node _in_uops_3_bits_edge_inst_T = and(UInt<1>(0h0), io.enq.bits.edge_inst) connect in_uops[3].bits.edge_inst, _in_uops_3_bits_edge_inst_T node _in_uops_3_bits_xcpt_cause_T = mux(io.enq.bits.xcpt_pf_if, UInt<4>(0hc), UInt<1>(0h1)) connect in_uops[3].bits.xcpt_cause, _in_uops_3_bits_xcpt_cause_T wire write_mask : UInt<1>[4][7] connect write_mask[0][0], UInt<1>(0h0) connect write_mask[0][1], UInt<1>(0h0) connect write_mask[0][2], UInt<1>(0h0) connect write_mask[0][3], UInt<1>(0h0) connect write_mask[1][0], UInt<1>(0h0) connect write_mask[1][1], UInt<1>(0h0) connect write_mask[1][2], UInt<1>(0h0) connect write_mask[1][3], UInt<1>(0h0) connect write_mask[2][0], UInt<1>(0h0) connect write_mask[2][1], UInt<1>(0h0) connect write_mask[2][2], UInt<1>(0h0) connect write_mask[2][3], UInt<1>(0h0) connect write_mask[3][0], UInt<1>(0h0) connect write_mask[3][1], UInt<1>(0h0) connect write_mask[3][2], UInt<1>(0h0) connect write_mask[3][3], UInt<1>(0h0) connect write_mask[4][0], UInt<1>(0h0) connect write_mask[4][1], UInt<1>(0h0) connect write_mask[4][2], UInt<1>(0h0) connect write_mask[4][3], UInt<1>(0h0) connect write_mask[5][0], UInt<1>(0h0) connect write_mask[5][1], UInt<1>(0h0) connect write_mask[5][2], UInt<1>(0h0) connect write_mask[5][3], UInt<1>(0h0) connect write_mask[6][0], UInt<1>(0h0) connect write_mask[6][1], UInt<1>(0h0) connect write_mask[6][2], UInt<1>(0h0) connect write_mask[6][3], UInt<1>(0h0) node _write_mask_0_0_T = bits(enq_ptr, 0, 0) node _write_mask_0_0_T_1 = and(_write_mask_0_0_T, in_uops[0].valid) connect write_mask[0][0], _write_mask_0_0_T_1 node _write_mask_1_0_T = bits(enq_ptr, 1, 1) node _write_mask_1_0_T_1 = and(_write_mask_1_0_T, in_uops[0].valid) connect write_mask[1][0], _write_mask_1_0_T_1 node _write_mask_2_0_T = bits(enq_ptr, 2, 2) node _write_mask_2_0_T_1 = and(_write_mask_2_0_T, in_uops[0].valid) connect write_mask[2][0], _write_mask_2_0_T_1 node _write_mask_3_0_T = bits(enq_ptr, 3, 3) node _write_mask_3_0_T_1 = and(_write_mask_3_0_T, in_uops[0].valid) connect write_mask[3][0], _write_mask_3_0_T_1 node _write_mask_4_0_T = bits(enq_ptr, 4, 4) node _write_mask_4_0_T_1 = and(_write_mask_4_0_T, in_uops[0].valid) connect write_mask[4][0], _write_mask_4_0_T_1 node _write_mask_5_0_T = bits(enq_ptr, 5, 5) node _write_mask_5_0_T_1 = and(_write_mask_5_0_T, in_uops[0].valid) connect write_mask[5][0], _write_mask_5_0_T_1 node _write_mask_6_0_T = bits(enq_ptr, 6, 6) node _write_mask_6_0_T_1 = and(_write_mask_6_0_T, in_uops[0].valid) connect write_mask[6][0], _write_mask_6_0_T_1 node _T = shl(enq_ptr, 1) node _T_1 = bits(enq_ptr, 6, 6) node _T_2 = or(_T, _T_1) node _T_3 = bits(_T_2, 6, 0) node _T_4 = mux(in_uops[0].valid, _T_3, enq_ptr) node _write_mask_0_1_T = bits(_T_4, 0, 0) node _write_mask_0_1_T_1 = and(_write_mask_0_1_T, in_uops[1].valid) connect write_mask[0][1], _write_mask_0_1_T_1 node _write_mask_1_1_T = bits(_T_4, 1, 1) node _write_mask_1_1_T_1 = and(_write_mask_1_1_T, in_uops[1].valid) connect write_mask[1][1], _write_mask_1_1_T_1 node _write_mask_2_1_T = bits(_T_4, 2, 2) node _write_mask_2_1_T_1 = and(_write_mask_2_1_T, in_uops[1].valid) connect write_mask[2][1], _write_mask_2_1_T_1 node _write_mask_3_1_T = bits(_T_4, 3, 3) node _write_mask_3_1_T_1 = and(_write_mask_3_1_T, in_uops[1].valid) connect write_mask[3][1], _write_mask_3_1_T_1 node _write_mask_4_1_T = bits(_T_4, 4, 4) node _write_mask_4_1_T_1 = and(_write_mask_4_1_T, in_uops[1].valid) connect write_mask[4][1], _write_mask_4_1_T_1 node _write_mask_5_1_T = bits(_T_4, 5, 5) node _write_mask_5_1_T_1 = and(_write_mask_5_1_T, in_uops[1].valid) connect write_mask[5][1], _write_mask_5_1_T_1 node _write_mask_6_1_T = bits(_T_4, 6, 6) node _write_mask_6_1_T_1 = and(_write_mask_6_1_T, in_uops[1].valid) connect write_mask[6][1], _write_mask_6_1_T_1 node _T_5 = shl(_T_4, 1) node _T_6 = bits(_T_4, 6, 6) node _T_7 = or(_T_5, _T_6) node _T_8 = bits(_T_7, 6, 0) node _T_9 = mux(in_uops[1].valid, _T_8, _T_4) node _write_mask_0_2_T = bits(_T_9, 0, 0) node _write_mask_0_2_T_1 = and(_write_mask_0_2_T, in_uops[2].valid) connect write_mask[0][2], _write_mask_0_2_T_1 node _write_mask_1_2_T = bits(_T_9, 1, 1) node _write_mask_1_2_T_1 = and(_write_mask_1_2_T, in_uops[2].valid) connect write_mask[1][2], _write_mask_1_2_T_1 node _write_mask_2_2_T = bits(_T_9, 2, 2) node _write_mask_2_2_T_1 = and(_write_mask_2_2_T, in_uops[2].valid) connect write_mask[2][2], _write_mask_2_2_T_1 node _write_mask_3_2_T = bits(_T_9, 3, 3) node _write_mask_3_2_T_1 = and(_write_mask_3_2_T, in_uops[2].valid) connect write_mask[3][2], _write_mask_3_2_T_1 node _write_mask_4_2_T = bits(_T_9, 4, 4) node _write_mask_4_2_T_1 = and(_write_mask_4_2_T, in_uops[2].valid) connect write_mask[4][2], _write_mask_4_2_T_1 node _write_mask_5_2_T = bits(_T_9, 5, 5) node _write_mask_5_2_T_1 = and(_write_mask_5_2_T, in_uops[2].valid) connect write_mask[5][2], _write_mask_5_2_T_1 node _write_mask_6_2_T = bits(_T_9, 6, 6) node _write_mask_6_2_T_1 = and(_write_mask_6_2_T, in_uops[2].valid) connect write_mask[6][2], _write_mask_6_2_T_1 node _T_10 = shl(_T_9, 1) node _T_11 = bits(_T_9, 6, 6) node _T_12 = or(_T_10, _T_11) node _T_13 = bits(_T_12, 6, 0) node _T_14 = mux(in_uops[2].valid, _T_13, _T_9) node _write_mask_0_3_T = bits(_T_14, 0, 0) node _write_mask_0_3_T_1 = and(_write_mask_0_3_T, in_uops[3].valid) connect write_mask[0][3], _write_mask_0_3_T_1 node _write_mask_1_3_T = bits(_T_14, 1, 1) node _write_mask_1_3_T_1 = and(_write_mask_1_3_T, in_uops[3].valid) connect write_mask[1][3], _write_mask_1_3_T_1 node _write_mask_2_3_T = bits(_T_14, 2, 2) node _write_mask_2_3_T_1 = and(_write_mask_2_3_T, in_uops[3].valid) connect write_mask[2][3], _write_mask_2_3_T_1 node _write_mask_3_3_T = bits(_T_14, 3, 3) node _write_mask_3_3_T_1 = and(_write_mask_3_3_T, in_uops[3].valid) connect write_mask[3][3], _write_mask_3_3_T_1 node _write_mask_4_3_T = bits(_T_14, 4, 4) node _write_mask_4_3_T_1 = and(_write_mask_4_3_T, in_uops[3].valid) connect write_mask[4][3], _write_mask_4_3_T_1 node _write_mask_5_3_T = bits(_T_14, 5, 5) node _write_mask_5_3_T_1 = and(_write_mask_5_3_T, in_uops[3].valid) connect write_mask[5][3], _write_mask_5_3_T_1 node _write_mask_6_3_T = bits(_T_14, 6, 6) node _write_mask_6_3_T_1 = and(_write_mask_6_3_T, in_uops[3].valid) connect write_mask[6][3], _write_mask_6_3_T_1 node _T_15 = shl(_T_14, 1) node _T_16 = bits(_T_14, 6, 6) node _T_17 = or(_T_15, _T_16) node _T_18 = bits(_T_17, 6, 0) node _T_19 = mux(in_uops[3].valid, _T_18, _T_14) node _T_20 = and(io.enq.ready, io.enq.valid) when _T_20 : node _enq_ptr_T = bits(io.enq.bits.mask, 0, 0) node _enq_ptr_T_1 = bits(io.enq.bits.mask, 1, 1) node _enq_ptr_T_2 = bits(io.enq.bits.mask, 2, 2) node _enq_ptr_T_3 = bits(io.enq.bits.mask, 3, 3) node _enq_ptr_T_4 = add(_enq_ptr_T, _enq_ptr_T_1) node _enq_ptr_T_5 = bits(_enq_ptr_T_4, 1, 0) node _enq_ptr_T_6 = add(_enq_ptr_T_2, _enq_ptr_T_3) node _enq_ptr_T_7 = bits(_enq_ptr_T_6, 1, 0) node _enq_ptr_T_8 = add(_enq_ptr_T_5, _enq_ptr_T_7) node _enq_ptr_T_9 = bits(_enq_ptr_T_8, 2, 0) wire enq_ptr_full : UInt<14> node _enq_ptr_full_T = dshl(enq_ptr, _enq_ptr_T_9) connect enq_ptr_full, _enq_ptr_full_T node _enq_ptr_T_10 = bits(enq_ptr_full, 6, 0) node _enq_ptr_T_11 = shr(enq_ptr_full, 7) node _enq_ptr_T_12 = or(_enq_ptr_T_10, _enq_ptr_T_11) node _enq_ptr_T_13 = bits(_enq_ptr_T_12, 6, 0) connect enq_ptr, _enq_ptr_T_13 node _T_21 = eq(ram[0].valid, UInt<1>(0h0)) when _T_21 : wire _ram_0_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_0_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_0_T = mux(write_mask[0][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_0_T_1 = mux(write_mask[0][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_0_T_2 = mux(write_mask[0][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_0_T_3 = mux(write_mask[0][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_0_T_4 = or(_ram_0_T, _ram_0_T_1) node _ram_0_T_5 = or(_ram_0_T_4, _ram_0_T_2) node _ram_0_T_6 = or(_ram_0_T_5, _ram_0_T_3) wire _ram_0_WIRE_2 : UInt<1> connect _ram_0_WIRE_2, _ram_0_T_6 connect _ram_0_WIRE_1.flush_pipe, _ram_0_WIRE_2 node _ram_0_T_7 = mux(write_mask[0][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_0_T_8 = mux(write_mask[0][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_0_T_9 = mux(write_mask[0][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_0_T_10 = mux(write_mask[0][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_0_T_11 = or(_ram_0_T_7, _ram_0_T_8) node _ram_0_T_12 = or(_ram_0_T_11, _ram_0_T_9) node _ram_0_T_13 = or(_ram_0_T_12, _ram_0_T_10) wire _ram_0_WIRE_3 : UInt<2> connect _ram_0_WIRE_3, _ram_0_T_13 connect _ram_0_WIRE_1.mem_size, _ram_0_WIRE_3 wire _ram_0_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_0_T_14 = mux(write_mask[0][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_0_T_15 = mux(write_mask[0][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_0_T_16 = mux(write_mask[0][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_0_T_17 = mux(write_mask[0][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_0_T_18 = or(_ram_0_T_14, _ram_0_T_15) node _ram_0_T_19 = or(_ram_0_T_18, _ram_0_T_16) node _ram_0_T_20 = or(_ram_0_T_19, _ram_0_T_17) wire _ram_0_WIRE_5 : UInt<65> connect _ram_0_WIRE_5, _ram_0_T_20 connect _ram_0_WIRE_4.in3, _ram_0_WIRE_5 node _ram_0_T_21 = mux(write_mask[0][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_0_T_22 = mux(write_mask[0][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_0_T_23 = mux(write_mask[0][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_0_T_24 = mux(write_mask[0][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_0_T_25 = or(_ram_0_T_21, _ram_0_T_22) node _ram_0_T_26 = or(_ram_0_T_25, _ram_0_T_23) node _ram_0_T_27 = or(_ram_0_T_26, _ram_0_T_24) wire _ram_0_WIRE_6 : UInt<65> connect _ram_0_WIRE_6, _ram_0_T_27 connect _ram_0_WIRE_4.in2, _ram_0_WIRE_6 node _ram_0_T_28 = mux(write_mask[0][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_0_T_29 = mux(write_mask[0][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_0_T_30 = mux(write_mask[0][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_0_T_31 = mux(write_mask[0][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_0_T_32 = or(_ram_0_T_28, _ram_0_T_29) node _ram_0_T_33 = or(_ram_0_T_32, _ram_0_T_30) node _ram_0_T_34 = or(_ram_0_T_33, _ram_0_T_31) wire _ram_0_WIRE_7 : UInt<65> connect _ram_0_WIRE_7, _ram_0_T_34 connect _ram_0_WIRE_4.in1, _ram_0_WIRE_7 node _ram_0_T_35 = mux(write_mask[0][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_0_T_36 = mux(write_mask[0][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_0_T_37 = mux(write_mask[0][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_0_T_38 = mux(write_mask[0][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_0_T_39 = or(_ram_0_T_35, _ram_0_T_36) node _ram_0_T_40 = or(_ram_0_T_39, _ram_0_T_37) node _ram_0_T_41 = or(_ram_0_T_40, _ram_0_T_38) wire _ram_0_WIRE_8 : UInt<2> connect _ram_0_WIRE_8, _ram_0_T_41 connect _ram_0_WIRE_4.fmt, _ram_0_WIRE_8 node _ram_0_T_42 = mux(write_mask[0][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_0_T_43 = mux(write_mask[0][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_0_T_44 = mux(write_mask[0][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_0_T_45 = mux(write_mask[0][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_0_T_46 = or(_ram_0_T_42, _ram_0_T_43) node _ram_0_T_47 = or(_ram_0_T_46, _ram_0_T_44) node _ram_0_T_48 = or(_ram_0_T_47, _ram_0_T_45) wire _ram_0_WIRE_9 : UInt<2> connect _ram_0_WIRE_9, _ram_0_T_48 connect _ram_0_WIRE_4.typ, _ram_0_WIRE_9 node _ram_0_T_49 = mux(write_mask[0][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_0_T_50 = mux(write_mask[0][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_0_T_51 = mux(write_mask[0][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_0_T_52 = mux(write_mask[0][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_0_T_53 = or(_ram_0_T_49, _ram_0_T_50) node _ram_0_T_54 = or(_ram_0_T_53, _ram_0_T_51) node _ram_0_T_55 = or(_ram_0_T_54, _ram_0_T_52) wire _ram_0_WIRE_10 : UInt<2> connect _ram_0_WIRE_10, _ram_0_T_55 connect _ram_0_WIRE_4.fmaCmd, _ram_0_WIRE_10 node _ram_0_T_56 = mux(write_mask[0][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_0_T_57 = mux(write_mask[0][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_0_T_58 = mux(write_mask[0][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_0_T_59 = mux(write_mask[0][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_0_T_60 = or(_ram_0_T_56, _ram_0_T_57) node _ram_0_T_61 = or(_ram_0_T_60, _ram_0_T_58) node _ram_0_T_62 = or(_ram_0_T_61, _ram_0_T_59) wire _ram_0_WIRE_11 : UInt<3> connect _ram_0_WIRE_11, _ram_0_T_62 connect _ram_0_WIRE_4.rm, _ram_0_WIRE_11 node _ram_0_T_63 = mux(write_mask[0][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_0_T_64 = mux(write_mask[0][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_0_T_65 = mux(write_mask[0][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_0_T_66 = mux(write_mask[0][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_0_T_67 = or(_ram_0_T_63, _ram_0_T_64) node _ram_0_T_68 = or(_ram_0_T_67, _ram_0_T_65) node _ram_0_T_69 = or(_ram_0_T_68, _ram_0_T_66) wire _ram_0_WIRE_12 : UInt<1> connect _ram_0_WIRE_12, _ram_0_T_69 connect _ram_0_WIRE_4.vec, _ram_0_WIRE_12 node _ram_0_T_70 = mux(write_mask[0][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_0_T_71 = mux(write_mask[0][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_0_T_72 = mux(write_mask[0][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_0_T_73 = mux(write_mask[0][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_0_T_74 = or(_ram_0_T_70, _ram_0_T_71) node _ram_0_T_75 = or(_ram_0_T_74, _ram_0_T_72) node _ram_0_T_76 = or(_ram_0_T_75, _ram_0_T_73) wire _ram_0_WIRE_13 : UInt<1> connect _ram_0_WIRE_13, _ram_0_T_76 connect _ram_0_WIRE_4.wflags, _ram_0_WIRE_13 node _ram_0_T_77 = mux(write_mask[0][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_0_T_78 = mux(write_mask[0][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_0_T_79 = mux(write_mask[0][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_0_T_80 = mux(write_mask[0][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_0_T_81 = or(_ram_0_T_77, _ram_0_T_78) node _ram_0_T_82 = or(_ram_0_T_81, _ram_0_T_79) node _ram_0_T_83 = or(_ram_0_T_82, _ram_0_T_80) wire _ram_0_WIRE_14 : UInt<1> connect _ram_0_WIRE_14, _ram_0_T_83 connect _ram_0_WIRE_4.sqrt, _ram_0_WIRE_14 node _ram_0_T_84 = mux(write_mask[0][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_0_T_85 = mux(write_mask[0][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_0_T_86 = mux(write_mask[0][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_0_T_87 = mux(write_mask[0][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_0_T_88 = or(_ram_0_T_84, _ram_0_T_85) node _ram_0_T_89 = or(_ram_0_T_88, _ram_0_T_86) node _ram_0_T_90 = or(_ram_0_T_89, _ram_0_T_87) wire _ram_0_WIRE_15 : UInt<1> connect _ram_0_WIRE_15, _ram_0_T_90 connect _ram_0_WIRE_4.div, _ram_0_WIRE_15 node _ram_0_T_91 = mux(write_mask[0][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_0_T_92 = mux(write_mask[0][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_0_T_93 = mux(write_mask[0][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_0_T_94 = mux(write_mask[0][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_0_T_95 = or(_ram_0_T_91, _ram_0_T_92) node _ram_0_T_96 = or(_ram_0_T_95, _ram_0_T_93) node _ram_0_T_97 = or(_ram_0_T_96, _ram_0_T_94) wire _ram_0_WIRE_16 : UInt<1> connect _ram_0_WIRE_16, _ram_0_T_97 connect _ram_0_WIRE_4.fma, _ram_0_WIRE_16 node _ram_0_T_98 = mux(write_mask[0][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_0_T_99 = mux(write_mask[0][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_0_T_100 = mux(write_mask[0][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_0_T_101 = mux(write_mask[0][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_0_T_102 = or(_ram_0_T_98, _ram_0_T_99) node _ram_0_T_103 = or(_ram_0_T_102, _ram_0_T_100) node _ram_0_T_104 = or(_ram_0_T_103, _ram_0_T_101) wire _ram_0_WIRE_17 : UInt<1> connect _ram_0_WIRE_17, _ram_0_T_104 connect _ram_0_WIRE_4.fastpipe, _ram_0_WIRE_17 node _ram_0_T_105 = mux(write_mask[0][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_0_T_106 = mux(write_mask[0][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_0_T_107 = mux(write_mask[0][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_0_T_108 = mux(write_mask[0][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_0_T_109 = or(_ram_0_T_105, _ram_0_T_106) node _ram_0_T_110 = or(_ram_0_T_109, _ram_0_T_107) node _ram_0_T_111 = or(_ram_0_T_110, _ram_0_T_108) wire _ram_0_WIRE_18 : UInt<1> connect _ram_0_WIRE_18, _ram_0_T_111 connect _ram_0_WIRE_4.toint, _ram_0_WIRE_18 node _ram_0_T_112 = mux(write_mask[0][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_0_T_113 = mux(write_mask[0][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_0_T_114 = mux(write_mask[0][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_0_T_115 = mux(write_mask[0][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_0_T_116 = or(_ram_0_T_112, _ram_0_T_113) node _ram_0_T_117 = or(_ram_0_T_116, _ram_0_T_114) node _ram_0_T_118 = or(_ram_0_T_117, _ram_0_T_115) wire _ram_0_WIRE_19 : UInt<1> connect _ram_0_WIRE_19, _ram_0_T_118 connect _ram_0_WIRE_4.fromint, _ram_0_WIRE_19 node _ram_0_T_119 = mux(write_mask[0][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_0_T_120 = mux(write_mask[0][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_0_T_121 = mux(write_mask[0][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_0_T_122 = mux(write_mask[0][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_0_T_123 = or(_ram_0_T_119, _ram_0_T_120) node _ram_0_T_124 = or(_ram_0_T_123, _ram_0_T_121) node _ram_0_T_125 = or(_ram_0_T_124, _ram_0_T_122) wire _ram_0_WIRE_20 : UInt<2> connect _ram_0_WIRE_20, _ram_0_T_125 connect _ram_0_WIRE_4.typeTagOut, _ram_0_WIRE_20 node _ram_0_T_126 = mux(write_mask[0][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_0_T_127 = mux(write_mask[0][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_0_T_128 = mux(write_mask[0][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_0_T_129 = mux(write_mask[0][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_0_T_130 = or(_ram_0_T_126, _ram_0_T_127) node _ram_0_T_131 = or(_ram_0_T_130, _ram_0_T_128) node _ram_0_T_132 = or(_ram_0_T_131, _ram_0_T_129) wire _ram_0_WIRE_21 : UInt<2> connect _ram_0_WIRE_21, _ram_0_T_132 connect _ram_0_WIRE_4.typeTagIn, _ram_0_WIRE_21 node _ram_0_T_133 = mux(write_mask[0][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_0_T_134 = mux(write_mask[0][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_0_T_135 = mux(write_mask[0][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_0_T_136 = mux(write_mask[0][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_0_T_137 = or(_ram_0_T_133, _ram_0_T_134) node _ram_0_T_138 = or(_ram_0_T_137, _ram_0_T_135) node _ram_0_T_139 = or(_ram_0_T_138, _ram_0_T_136) wire _ram_0_WIRE_22 : UInt<1> connect _ram_0_WIRE_22, _ram_0_T_139 connect _ram_0_WIRE_4.swap23, _ram_0_WIRE_22 node _ram_0_T_140 = mux(write_mask[0][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_0_T_141 = mux(write_mask[0][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_0_T_142 = mux(write_mask[0][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_0_T_143 = mux(write_mask[0][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_0_T_144 = or(_ram_0_T_140, _ram_0_T_141) node _ram_0_T_145 = or(_ram_0_T_144, _ram_0_T_142) node _ram_0_T_146 = or(_ram_0_T_145, _ram_0_T_143) wire _ram_0_WIRE_23 : UInt<1> connect _ram_0_WIRE_23, _ram_0_T_146 connect _ram_0_WIRE_4.swap12, _ram_0_WIRE_23 node _ram_0_T_147 = mux(write_mask[0][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_0_T_148 = mux(write_mask[0][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_0_T_149 = mux(write_mask[0][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_0_T_150 = mux(write_mask[0][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_0_T_151 = or(_ram_0_T_147, _ram_0_T_148) node _ram_0_T_152 = or(_ram_0_T_151, _ram_0_T_149) node _ram_0_T_153 = or(_ram_0_T_152, _ram_0_T_150) wire _ram_0_WIRE_24 : UInt<1> connect _ram_0_WIRE_24, _ram_0_T_153 connect _ram_0_WIRE_4.ren3, _ram_0_WIRE_24 node _ram_0_T_154 = mux(write_mask[0][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_0_T_155 = mux(write_mask[0][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_0_T_156 = mux(write_mask[0][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_0_T_157 = mux(write_mask[0][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_0_T_158 = or(_ram_0_T_154, _ram_0_T_155) node _ram_0_T_159 = or(_ram_0_T_158, _ram_0_T_156) node _ram_0_T_160 = or(_ram_0_T_159, _ram_0_T_157) wire _ram_0_WIRE_25 : UInt<1> connect _ram_0_WIRE_25, _ram_0_T_160 connect _ram_0_WIRE_4.ren2, _ram_0_WIRE_25 node _ram_0_T_161 = mux(write_mask[0][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_0_T_162 = mux(write_mask[0][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_0_T_163 = mux(write_mask[0][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_0_T_164 = mux(write_mask[0][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_0_T_165 = or(_ram_0_T_161, _ram_0_T_162) node _ram_0_T_166 = or(_ram_0_T_165, _ram_0_T_163) node _ram_0_T_167 = or(_ram_0_T_166, _ram_0_T_164) wire _ram_0_WIRE_26 : UInt<1> connect _ram_0_WIRE_26, _ram_0_T_167 connect _ram_0_WIRE_4.ren1, _ram_0_WIRE_26 node _ram_0_T_168 = mux(write_mask[0][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_0_T_169 = mux(write_mask[0][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_0_T_170 = mux(write_mask[0][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_0_T_171 = mux(write_mask[0][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_0_T_172 = or(_ram_0_T_168, _ram_0_T_169) node _ram_0_T_173 = or(_ram_0_T_172, _ram_0_T_170) node _ram_0_T_174 = or(_ram_0_T_173, _ram_0_T_171) wire _ram_0_WIRE_27 : UInt<1> connect _ram_0_WIRE_27, _ram_0_T_174 connect _ram_0_WIRE_4.wen, _ram_0_WIRE_27 node _ram_0_T_175 = mux(write_mask[0][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_0_T_176 = mux(write_mask[0][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_0_T_177 = mux(write_mask[0][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_0_T_178 = mux(write_mask[0][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_0_T_179 = or(_ram_0_T_175, _ram_0_T_176) node _ram_0_T_180 = or(_ram_0_T_179, _ram_0_T_177) node _ram_0_T_181 = or(_ram_0_T_180, _ram_0_T_178) wire _ram_0_WIRE_28 : UInt<1> connect _ram_0_WIRE_28, _ram_0_T_181 connect _ram_0_WIRE_4.ldst, _ram_0_WIRE_28 connect _ram_0_WIRE_1.fdivin, _ram_0_WIRE_4 node _ram_0_T_182 = mux(write_mask[0][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_0_T_183 = mux(write_mask[0][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_0_T_184 = mux(write_mask[0][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_0_T_185 = mux(write_mask[0][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_0_T_186 = or(_ram_0_T_182, _ram_0_T_183) node _ram_0_T_187 = or(_ram_0_T_186, _ram_0_T_184) node _ram_0_T_188 = or(_ram_0_T_187, _ram_0_T_185) wire _ram_0_WIRE_29 : UInt<5> connect _ram_0_WIRE_29, _ram_0_T_188 connect _ram_0_WIRE_1.fexc, _ram_0_WIRE_29 node _ram_0_T_189 = mux(write_mask[0][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_0_T_190 = mux(write_mask[0][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_0_T_191 = mux(write_mask[0][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_0_T_192 = mux(write_mask[0][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_0_T_193 = or(_ram_0_T_189, _ram_0_T_190) node _ram_0_T_194 = or(_ram_0_T_193, _ram_0_T_191) node _ram_0_T_195 = or(_ram_0_T_194, _ram_0_T_192) wire _ram_0_WIRE_30 : UInt<5> connect _ram_0_WIRE_30, _ram_0_T_195 connect _ram_0_WIRE_1.fra3, _ram_0_WIRE_30 node _ram_0_T_196 = mux(write_mask[0][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_0_T_197 = mux(write_mask[0][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_0_T_198 = mux(write_mask[0][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_0_T_199 = mux(write_mask[0][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_0_T_200 = or(_ram_0_T_196, _ram_0_T_197) node _ram_0_T_201 = or(_ram_0_T_200, _ram_0_T_198) node _ram_0_T_202 = or(_ram_0_T_201, _ram_0_T_199) wire _ram_0_WIRE_31 : UInt<5> connect _ram_0_WIRE_31, _ram_0_T_202 connect _ram_0_WIRE_1.fra2, _ram_0_WIRE_31 node _ram_0_T_203 = mux(write_mask[0][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_0_T_204 = mux(write_mask[0][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_0_T_205 = mux(write_mask[0][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_0_T_206 = mux(write_mask[0][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_0_T_207 = or(_ram_0_T_203, _ram_0_T_204) node _ram_0_T_208 = or(_ram_0_T_207, _ram_0_T_205) node _ram_0_T_209 = or(_ram_0_T_208, _ram_0_T_206) wire _ram_0_WIRE_32 : UInt<5> connect _ram_0_WIRE_32, _ram_0_T_209 connect _ram_0_WIRE_1.fra1, _ram_0_WIRE_32 wire _ram_0_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_0_T_210 = mux(write_mask[0][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_0_T_211 = mux(write_mask[0][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_0_T_212 = mux(write_mask[0][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_0_T_213 = mux(write_mask[0][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_0_T_214 = or(_ram_0_T_210, _ram_0_T_211) node _ram_0_T_215 = or(_ram_0_T_214, _ram_0_T_212) node _ram_0_T_216 = or(_ram_0_T_215, _ram_0_T_213) wire _ram_0_WIRE_34 : UInt<64> connect _ram_0_WIRE_34, _ram_0_T_216 connect _ram_0_WIRE_33.bits, _ram_0_WIRE_34 node _ram_0_T_217 = mux(write_mask[0][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_0_T_218 = mux(write_mask[0][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_0_T_219 = mux(write_mask[0][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_0_T_220 = mux(write_mask[0][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_0_T_221 = or(_ram_0_T_217, _ram_0_T_218) node _ram_0_T_222 = or(_ram_0_T_221, _ram_0_T_219) node _ram_0_T_223 = or(_ram_0_T_222, _ram_0_T_220) wire _ram_0_WIRE_35 : UInt<1> connect _ram_0_WIRE_35, _ram_0_T_223 connect _ram_0_WIRE_33.valid, _ram_0_WIRE_35 connect _ram_0_WIRE_1.wdata, _ram_0_WIRE_33 node _ram_0_T_224 = mux(write_mask[0][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_0_T_225 = mux(write_mask[0][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_0_T_226 = mux(write_mask[0][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_0_T_227 = mux(write_mask[0][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_0_T_228 = or(_ram_0_T_224, _ram_0_T_225) node _ram_0_T_229 = or(_ram_0_T_228, _ram_0_T_226) node _ram_0_T_230 = or(_ram_0_T_229, _ram_0_T_227) wire _ram_0_WIRE_36 : UInt<1> connect _ram_0_WIRE_36, _ram_0_T_230 connect _ram_0_WIRE_1.uses_latealu, _ram_0_WIRE_36 node _ram_0_T_231 = mux(write_mask[0][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_0_T_232 = mux(write_mask[0][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_0_T_233 = mux(write_mask[0][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_0_T_234 = mux(write_mask[0][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_0_T_235 = or(_ram_0_T_231, _ram_0_T_232) node _ram_0_T_236 = or(_ram_0_T_235, _ram_0_T_233) node _ram_0_T_237 = or(_ram_0_T_236, _ram_0_T_234) wire _ram_0_WIRE_37 : UInt<1> connect _ram_0_WIRE_37, _ram_0_T_237 connect _ram_0_WIRE_1.uses_memalu, _ram_0_WIRE_37 node _ram_0_T_238 = mux(write_mask[0][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_0_T_239 = mux(write_mask[0][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_0_T_240 = mux(write_mask[0][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_0_T_241 = mux(write_mask[0][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_0_T_242 = or(_ram_0_T_238, _ram_0_T_239) node _ram_0_T_243 = or(_ram_0_T_242, _ram_0_T_240) node _ram_0_T_244 = or(_ram_0_T_243, _ram_0_T_241) wire _ram_0_WIRE_38 : UInt<64> connect _ram_0_WIRE_38, _ram_0_T_244 connect _ram_0_WIRE_1.rs3_data, _ram_0_WIRE_38 node _ram_0_T_245 = mux(write_mask[0][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_0_T_246 = mux(write_mask[0][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_0_T_247 = mux(write_mask[0][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_0_T_248 = mux(write_mask[0][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_0_T_249 = or(_ram_0_T_245, _ram_0_T_246) node _ram_0_T_250 = or(_ram_0_T_249, _ram_0_T_247) node _ram_0_T_251 = or(_ram_0_T_250, _ram_0_T_248) wire _ram_0_WIRE_39 : UInt<64> connect _ram_0_WIRE_39, _ram_0_T_251 connect _ram_0_WIRE_1.rs2_data, _ram_0_WIRE_39 node _ram_0_T_252 = mux(write_mask[0][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_0_T_253 = mux(write_mask[0][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_0_T_254 = mux(write_mask[0][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_0_T_255 = mux(write_mask[0][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_0_T_256 = or(_ram_0_T_252, _ram_0_T_253) node _ram_0_T_257 = or(_ram_0_T_256, _ram_0_T_254) node _ram_0_T_258 = or(_ram_0_T_257, _ram_0_T_255) wire _ram_0_WIRE_40 : UInt<64> connect _ram_0_WIRE_40, _ram_0_T_258 connect _ram_0_WIRE_1.rs1_data, _ram_0_WIRE_40 node _ram_0_T_259 = mux(write_mask[0][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_0_T_260 = mux(write_mask[0][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_0_T_261 = mux(write_mask[0][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_0_T_262 = mux(write_mask[0][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_0_T_263 = or(_ram_0_T_259, _ram_0_T_260) node _ram_0_T_264 = or(_ram_0_T_263, _ram_0_T_261) node _ram_0_T_265 = or(_ram_0_T_264, _ram_0_T_262) wire _ram_0_WIRE_41 : UInt<1> connect _ram_0_WIRE_41, _ram_0_T_265 connect _ram_0_WIRE_1.needs_replay, _ram_0_WIRE_41 node _ram_0_T_266 = mux(write_mask[0][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_0_T_267 = mux(write_mask[0][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_0_T_268 = mux(write_mask[0][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_0_T_269 = mux(write_mask[0][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_0_T_270 = or(_ram_0_T_266, _ram_0_T_267) node _ram_0_T_271 = or(_ram_0_T_270, _ram_0_T_268) node _ram_0_T_272 = or(_ram_0_T_271, _ram_0_T_269) wire _ram_0_WIRE_42 : UInt<64> connect _ram_0_WIRE_42, _ram_0_T_272 connect _ram_0_WIRE_1.xcpt_cause, _ram_0_WIRE_42 node _ram_0_T_273 = mux(write_mask[0][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_0_T_274 = mux(write_mask[0][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_0_T_275 = mux(write_mask[0][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_0_T_276 = mux(write_mask[0][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_0_T_277 = or(_ram_0_T_273, _ram_0_T_274) node _ram_0_T_278 = or(_ram_0_T_277, _ram_0_T_275) node _ram_0_T_279 = or(_ram_0_T_278, _ram_0_T_276) wire _ram_0_WIRE_43 : UInt<1> connect _ram_0_WIRE_43, _ram_0_T_279 connect _ram_0_WIRE_1.xcpt, _ram_0_WIRE_43 node _ram_0_T_280 = mux(write_mask[0][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_0_T_281 = mux(write_mask[0][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_0_T_282 = mux(write_mask[0][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_0_T_283 = mux(write_mask[0][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_0_T_284 = or(_ram_0_T_280, _ram_0_T_281) node _ram_0_T_285 = or(_ram_0_T_284, _ram_0_T_282) node _ram_0_T_286 = or(_ram_0_T_285, _ram_0_T_283) wire _ram_0_WIRE_44 : UInt<1> connect _ram_0_WIRE_44, _ram_0_T_286 connect _ram_0_WIRE_1.taken, _ram_0_WIRE_44 node _ram_0_T_287 = mux(write_mask[0][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_0_T_288 = mux(write_mask[0][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_0_T_289 = mux(write_mask[0][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_0_T_290 = mux(write_mask[0][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_0_T_291 = or(_ram_0_T_287, _ram_0_T_288) node _ram_0_T_292 = or(_ram_0_T_291, _ram_0_T_289) node _ram_0_T_293 = or(_ram_0_T_292, _ram_0_T_290) wire _ram_0_WIRE_45 : UInt<3> connect _ram_0_WIRE_45, _ram_0_T_293 connect _ram_0_WIRE_1.ras_head, _ram_0_WIRE_45 wire _ram_0_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_0_T_294 = mux(write_mask[0][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_0_T_295 = mux(write_mask[0][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_0_T_296 = mux(write_mask[0][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_0_T_297 = mux(write_mask[0][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_0_T_298 = or(_ram_0_T_294, _ram_0_T_295) node _ram_0_T_299 = or(_ram_0_T_298, _ram_0_T_296) node _ram_0_T_300 = or(_ram_0_T_299, _ram_0_T_297) wire _ram_0_WIRE_47 : UInt<40> connect _ram_0_WIRE_47, _ram_0_T_300 connect _ram_0_WIRE_46.bits, _ram_0_WIRE_47 node _ram_0_T_301 = mux(write_mask[0][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_0_T_302 = mux(write_mask[0][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_0_T_303 = mux(write_mask[0][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_0_T_304 = mux(write_mask[0][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_0_T_305 = or(_ram_0_T_301, _ram_0_T_302) node _ram_0_T_306 = or(_ram_0_T_305, _ram_0_T_303) node _ram_0_T_307 = or(_ram_0_T_306, _ram_0_T_304) wire _ram_0_WIRE_48 : UInt<1> connect _ram_0_WIRE_48, _ram_0_T_307 connect _ram_0_WIRE_46.valid, _ram_0_WIRE_48 connect _ram_0_WIRE_1.next_pc, _ram_0_WIRE_46 node _ram_0_T_308 = mux(write_mask[0][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_0_T_309 = mux(write_mask[0][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_0_T_310 = mux(write_mask[0][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_0_T_311 = mux(write_mask[0][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_0_T_312 = or(_ram_0_T_308, _ram_0_T_309) node _ram_0_T_313 = or(_ram_0_T_312, _ram_0_T_310) node _ram_0_T_314 = or(_ram_0_T_313, _ram_0_T_311) wire _ram_0_WIRE_49 : UInt<1> connect _ram_0_WIRE_49, _ram_0_T_314 connect _ram_0_WIRE_1.sfb_shadow, _ram_0_WIRE_49 node _ram_0_T_315 = mux(write_mask[0][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_0_T_316 = mux(write_mask[0][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_0_T_317 = mux(write_mask[0][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_0_T_318 = mux(write_mask[0][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_0_T_319 = or(_ram_0_T_315, _ram_0_T_316) node _ram_0_T_320 = or(_ram_0_T_319, _ram_0_T_317) node _ram_0_T_321 = or(_ram_0_T_320, _ram_0_T_318) wire _ram_0_WIRE_50 : UInt<1> connect _ram_0_WIRE_50, _ram_0_T_321 connect _ram_0_WIRE_1.sfb_br, _ram_0_WIRE_50 wire _ram_0_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_0_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_0_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_0_T_322 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_0_T_323 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_0_T_324 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_0_T_325 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_0_T_326 = or(_ram_0_T_322, _ram_0_T_323) node _ram_0_T_327 = or(_ram_0_T_326, _ram_0_T_324) node _ram_0_T_328 = or(_ram_0_T_327, _ram_0_T_325) wire _ram_0_WIRE_54 : UInt<2> connect _ram_0_WIRE_54, _ram_0_T_328 connect _ram_0_WIRE_53.value, _ram_0_WIRE_54 node _ram_0_T_329 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_0_T_330 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_0_T_331 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_0_T_332 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_0_T_333 = or(_ram_0_T_329, _ram_0_T_330) node _ram_0_T_334 = or(_ram_0_T_333, _ram_0_T_331) node _ram_0_T_335 = or(_ram_0_T_334, _ram_0_T_332) wire _ram_0_WIRE_55 : UInt<8> connect _ram_0_WIRE_55, _ram_0_T_335 connect _ram_0_WIRE_53.history, _ram_0_WIRE_55 connect _ram_0_WIRE_52.bht, _ram_0_WIRE_53 node _ram_0_T_336 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_0_T_337 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_0_T_338 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_0_T_339 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_0_T_340 = or(_ram_0_T_336, _ram_0_T_337) node _ram_0_T_341 = or(_ram_0_T_340, _ram_0_T_338) node _ram_0_T_342 = or(_ram_0_T_341, _ram_0_T_339) wire _ram_0_WIRE_56 : UInt<6> connect _ram_0_WIRE_56, _ram_0_T_342 connect _ram_0_WIRE_52.entry, _ram_0_WIRE_56 node _ram_0_T_343 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_0_T_344 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_0_T_345 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_0_T_346 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_0_T_347 = or(_ram_0_T_343, _ram_0_T_344) node _ram_0_T_348 = or(_ram_0_T_347, _ram_0_T_345) node _ram_0_T_349 = or(_ram_0_T_348, _ram_0_T_346) wire _ram_0_WIRE_57 : UInt<39> connect _ram_0_WIRE_57, _ram_0_T_349 connect _ram_0_WIRE_52.target, _ram_0_WIRE_57 node _ram_0_T_350 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_0_T_351 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_0_T_352 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_0_T_353 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_0_T_354 = or(_ram_0_T_350, _ram_0_T_351) node _ram_0_T_355 = or(_ram_0_T_354, _ram_0_T_352) node _ram_0_T_356 = or(_ram_0_T_355, _ram_0_T_353) wire _ram_0_WIRE_58 : UInt<2> connect _ram_0_WIRE_58, _ram_0_T_356 connect _ram_0_WIRE_52.bridx, _ram_0_WIRE_58 node _ram_0_T_357 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_0_T_358 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_0_T_359 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_0_T_360 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_0_T_361 = or(_ram_0_T_357, _ram_0_T_358) node _ram_0_T_362 = or(_ram_0_T_361, _ram_0_T_359) node _ram_0_T_363 = or(_ram_0_T_362, _ram_0_T_360) wire _ram_0_WIRE_59 : UInt<4> connect _ram_0_WIRE_59, _ram_0_T_363 connect _ram_0_WIRE_52.mask, _ram_0_WIRE_59 node _ram_0_T_364 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_0_T_365 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_0_T_366 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_0_T_367 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_0_T_368 = or(_ram_0_T_364, _ram_0_T_365) node _ram_0_T_369 = or(_ram_0_T_368, _ram_0_T_366) node _ram_0_T_370 = or(_ram_0_T_369, _ram_0_T_367) wire _ram_0_WIRE_60 : UInt<1> connect _ram_0_WIRE_60, _ram_0_T_370 connect _ram_0_WIRE_52.taken, _ram_0_WIRE_60 node _ram_0_T_371 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_0_T_372 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_0_T_373 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_0_T_374 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_0_T_375 = or(_ram_0_T_371, _ram_0_T_372) node _ram_0_T_376 = or(_ram_0_T_375, _ram_0_T_373) node _ram_0_T_377 = or(_ram_0_T_376, _ram_0_T_374) wire _ram_0_WIRE_61 : UInt<2> connect _ram_0_WIRE_61, _ram_0_T_377 connect _ram_0_WIRE_52.cfiType, _ram_0_WIRE_61 connect _ram_0_WIRE_51.bits, _ram_0_WIRE_52 node _ram_0_T_378 = mux(write_mask[0][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_0_T_379 = mux(write_mask[0][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_0_T_380 = mux(write_mask[0][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_0_T_381 = mux(write_mask[0][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_0_T_382 = or(_ram_0_T_378, _ram_0_T_379) node _ram_0_T_383 = or(_ram_0_T_382, _ram_0_T_380) node _ram_0_T_384 = or(_ram_0_T_383, _ram_0_T_381) wire _ram_0_WIRE_62 : UInt<1> connect _ram_0_WIRE_62, _ram_0_T_384 connect _ram_0_WIRE_51.valid, _ram_0_WIRE_62 connect _ram_0_WIRE_1.btb_resp, _ram_0_WIRE_51 node _ram_0_T_385 = mux(write_mask[0][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_0_T_386 = mux(write_mask[0][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_0_T_387 = mux(write_mask[0][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_0_T_388 = mux(write_mask[0][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_0_T_389 = or(_ram_0_T_385, _ram_0_T_386) node _ram_0_T_390 = or(_ram_0_T_389, _ram_0_T_387) node _ram_0_T_391 = or(_ram_0_T_390, _ram_0_T_388) wire _ram_0_WIRE_63 : UInt<1> connect _ram_0_WIRE_63, _ram_0_T_391 connect _ram_0_WIRE_1.sets_vcfg, _ram_0_WIRE_63 node _ram_0_T_392 = mux(write_mask[0][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_0_T_393 = mux(write_mask[0][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_0_T_394 = mux(write_mask[0][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_0_T_395 = mux(write_mask[0][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_0_T_396 = or(_ram_0_T_392, _ram_0_T_393) node _ram_0_T_397 = or(_ram_0_T_396, _ram_0_T_394) node _ram_0_T_398 = or(_ram_0_T_397, _ram_0_T_395) wire _ram_0_WIRE_64 : UInt<1> connect _ram_0_WIRE_64, _ram_0_T_398 connect _ram_0_WIRE_1.rvc, _ram_0_WIRE_64 wire _ram_0_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_0_T_399 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_0_T_400 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_0_T_401 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_0_T_402 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_0_T_403 = or(_ram_0_T_399, _ram_0_T_400) node _ram_0_T_404 = or(_ram_0_T_403, _ram_0_T_401) node _ram_0_T_405 = or(_ram_0_T_404, _ram_0_T_402) wire _ram_0_WIRE_66 : UInt<1> connect _ram_0_WIRE_66, _ram_0_T_405 connect _ram_0_WIRE_65.vec, _ram_0_WIRE_66 node _ram_0_T_406 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_0_T_407 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_0_T_408 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_0_T_409 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_0_T_410 = or(_ram_0_T_406, _ram_0_T_407) node _ram_0_T_411 = or(_ram_0_T_410, _ram_0_T_408) node _ram_0_T_412 = or(_ram_0_T_411, _ram_0_T_409) wire _ram_0_WIRE_67 : UInt<1> connect _ram_0_WIRE_67, _ram_0_T_412 connect _ram_0_WIRE_65.wflags, _ram_0_WIRE_67 node _ram_0_T_413 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_0_T_414 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_0_T_415 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_0_T_416 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_0_T_417 = or(_ram_0_T_413, _ram_0_T_414) node _ram_0_T_418 = or(_ram_0_T_417, _ram_0_T_415) node _ram_0_T_419 = or(_ram_0_T_418, _ram_0_T_416) wire _ram_0_WIRE_68 : UInt<1> connect _ram_0_WIRE_68, _ram_0_T_419 connect _ram_0_WIRE_65.sqrt, _ram_0_WIRE_68 node _ram_0_T_420 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_0_T_421 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_0_T_422 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_0_T_423 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_0_T_424 = or(_ram_0_T_420, _ram_0_T_421) node _ram_0_T_425 = or(_ram_0_T_424, _ram_0_T_422) node _ram_0_T_426 = or(_ram_0_T_425, _ram_0_T_423) wire _ram_0_WIRE_69 : UInt<1> connect _ram_0_WIRE_69, _ram_0_T_426 connect _ram_0_WIRE_65.div, _ram_0_WIRE_69 node _ram_0_T_427 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_0_T_428 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_0_T_429 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_0_T_430 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_0_T_431 = or(_ram_0_T_427, _ram_0_T_428) node _ram_0_T_432 = or(_ram_0_T_431, _ram_0_T_429) node _ram_0_T_433 = or(_ram_0_T_432, _ram_0_T_430) wire _ram_0_WIRE_70 : UInt<1> connect _ram_0_WIRE_70, _ram_0_T_433 connect _ram_0_WIRE_65.fma, _ram_0_WIRE_70 node _ram_0_T_434 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_0_T_435 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_0_T_436 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_0_T_437 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_0_T_438 = or(_ram_0_T_434, _ram_0_T_435) node _ram_0_T_439 = or(_ram_0_T_438, _ram_0_T_436) node _ram_0_T_440 = or(_ram_0_T_439, _ram_0_T_437) wire _ram_0_WIRE_71 : UInt<1> connect _ram_0_WIRE_71, _ram_0_T_440 connect _ram_0_WIRE_65.fastpipe, _ram_0_WIRE_71 node _ram_0_T_441 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_0_T_442 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_0_T_443 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_0_T_444 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_0_T_445 = or(_ram_0_T_441, _ram_0_T_442) node _ram_0_T_446 = or(_ram_0_T_445, _ram_0_T_443) node _ram_0_T_447 = or(_ram_0_T_446, _ram_0_T_444) wire _ram_0_WIRE_72 : UInt<1> connect _ram_0_WIRE_72, _ram_0_T_447 connect _ram_0_WIRE_65.toint, _ram_0_WIRE_72 node _ram_0_T_448 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_0_T_449 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_0_T_450 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_0_T_451 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_0_T_452 = or(_ram_0_T_448, _ram_0_T_449) node _ram_0_T_453 = or(_ram_0_T_452, _ram_0_T_450) node _ram_0_T_454 = or(_ram_0_T_453, _ram_0_T_451) wire _ram_0_WIRE_73 : UInt<1> connect _ram_0_WIRE_73, _ram_0_T_454 connect _ram_0_WIRE_65.fromint, _ram_0_WIRE_73 node _ram_0_T_455 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_0_T_456 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_0_T_457 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_0_T_458 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_0_T_459 = or(_ram_0_T_455, _ram_0_T_456) node _ram_0_T_460 = or(_ram_0_T_459, _ram_0_T_457) node _ram_0_T_461 = or(_ram_0_T_460, _ram_0_T_458) wire _ram_0_WIRE_74 : UInt<2> connect _ram_0_WIRE_74, _ram_0_T_461 connect _ram_0_WIRE_65.typeTagOut, _ram_0_WIRE_74 node _ram_0_T_462 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_0_T_463 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_0_T_464 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_0_T_465 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_0_T_466 = or(_ram_0_T_462, _ram_0_T_463) node _ram_0_T_467 = or(_ram_0_T_466, _ram_0_T_464) node _ram_0_T_468 = or(_ram_0_T_467, _ram_0_T_465) wire _ram_0_WIRE_75 : UInt<2> connect _ram_0_WIRE_75, _ram_0_T_468 connect _ram_0_WIRE_65.typeTagIn, _ram_0_WIRE_75 node _ram_0_T_469 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_0_T_470 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_0_T_471 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_0_T_472 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_0_T_473 = or(_ram_0_T_469, _ram_0_T_470) node _ram_0_T_474 = or(_ram_0_T_473, _ram_0_T_471) node _ram_0_T_475 = or(_ram_0_T_474, _ram_0_T_472) wire _ram_0_WIRE_76 : UInt<1> connect _ram_0_WIRE_76, _ram_0_T_475 connect _ram_0_WIRE_65.swap23, _ram_0_WIRE_76 node _ram_0_T_476 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_0_T_477 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_0_T_478 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_0_T_479 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_0_T_480 = or(_ram_0_T_476, _ram_0_T_477) node _ram_0_T_481 = or(_ram_0_T_480, _ram_0_T_478) node _ram_0_T_482 = or(_ram_0_T_481, _ram_0_T_479) wire _ram_0_WIRE_77 : UInt<1> connect _ram_0_WIRE_77, _ram_0_T_482 connect _ram_0_WIRE_65.swap12, _ram_0_WIRE_77 node _ram_0_T_483 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_0_T_484 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_0_T_485 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_0_T_486 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_0_T_487 = or(_ram_0_T_483, _ram_0_T_484) node _ram_0_T_488 = or(_ram_0_T_487, _ram_0_T_485) node _ram_0_T_489 = or(_ram_0_T_488, _ram_0_T_486) wire _ram_0_WIRE_78 : UInt<1> connect _ram_0_WIRE_78, _ram_0_T_489 connect _ram_0_WIRE_65.ren3, _ram_0_WIRE_78 node _ram_0_T_490 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_0_T_491 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_0_T_492 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_0_T_493 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_0_T_494 = or(_ram_0_T_490, _ram_0_T_491) node _ram_0_T_495 = or(_ram_0_T_494, _ram_0_T_492) node _ram_0_T_496 = or(_ram_0_T_495, _ram_0_T_493) wire _ram_0_WIRE_79 : UInt<1> connect _ram_0_WIRE_79, _ram_0_T_496 connect _ram_0_WIRE_65.ren2, _ram_0_WIRE_79 node _ram_0_T_497 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_0_T_498 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_0_T_499 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_0_T_500 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_0_T_501 = or(_ram_0_T_497, _ram_0_T_498) node _ram_0_T_502 = or(_ram_0_T_501, _ram_0_T_499) node _ram_0_T_503 = or(_ram_0_T_502, _ram_0_T_500) wire _ram_0_WIRE_80 : UInt<1> connect _ram_0_WIRE_80, _ram_0_T_503 connect _ram_0_WIRE_65.ren1, _ram_0_WIRE_80 node _ram_0_T_504 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_0_T_505 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_0_T_506 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_0_T_507 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_0_T_508 = or(_ram_0_T_504, _ram_0_T_505) node _ram_0_T_509 = or(_ram_0_T_508, _ram_0_T_506) node _ram_0_T_510 = or(_ram_0_T_509, _ram_0_T_507) wire _ram_0_WIRE_81 : UInt<1> connect _ram_0_WIRE_81, _ram_0_T_510 connect _ram_0_WIRE_65.wen, _ram_0_WIRE_81 node _ram_0_T_511 = mux(write_mask[0][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_0_T_512 = mux(write_mask[0][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_0_T_513 = mux(write_mask[0][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_0_T_514 = mux(write_mask[0][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_0_T_515 = or(_ram_0_T_511, _ram_0_T_512) node _ram_0_T_516 = or(_ram_0_T_515, _ram_0_T_513) node _ram_0_T_517 = or(_ram_0_T_516, _ram_0_T_514) wire _ram_0_WIRE_82 : UInt<1> connect _ram_0_WIRE_82, _ram_0_T_517 connect _ram_0_WIRE_65.ldst, _ram_0_WIRE_82 connect _ram_0_WIRE_1.fp_ctrl, _ram_0_WIRE_65 wire _ram_0_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_0_T_518 = mux(write_mask[0][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_0_T_519 = mux(write_mask[0][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_0_T_520 = mux(write_mask[0][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_0_T_521 = mux(write_mask[0][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_0_T_522 = or(_ram_0_T_518, _ram_0_T_519) node _ram_0_T_523 = or(_ram_0_T_522, _ram_0_T_520) node _ram_0_T_524 = or(_ram_0_T_523, _ram_0_T_521) wire _ram_0_WIRE_84 : UInt<1> connect _ram_0_WIRE_84, _ram_0_T_524 connect _ram_0_WIRE_83.vec, _ram_0_WIRE_84 node _ram_0_T_525 = mux(write_mask[0][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_0_T_526 = mux(write_mask[0][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_0_T_527 = mux(write_mask[0][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_0_T_528 = mux(write_mask[0][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_0_T_529 = or(_ram_0_T_525, _ram_0_T_526) node _ram_0_T_530 = or(_ram_0_T_529, _ram_0_T_527) node _ram_0_T_531 = or(_ram_0_T_530, _ram_0_T_528) wire _ram_0_WIRE_85 : UInt<1> connect _ram_0_WIRE_85, _ram_0_T_531 connect _ram_0_WIRE_83.dp, _ram_0_WIRE_85 node _ram_0_T_532 = mux(write_mask[0][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_0_T_533 = mux(write_mask[0][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_0_T_534 = mux(write_mask[0][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_0_T_535 = mux(write_mask[0][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_0_T_536 = or(_ram_0_T_532, _ram_0_T_533) node _ram_0_T_537 = or(_ram_0_T_536, _ram_0_T_534) node _ram_0_T_538 = or(_ram_0_T_537, _ram_0_T_535) wire _ram_0_WIRE_86 : UInt<1> connect _ram_0_WIRE_86, _ram_0_T_538 connect _ram_0_WIRE_83.amo, _ram_0_WIRE_86 node _ram_0_T_539 = mux(write_mask[0][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_0_T_540 = mux(write_mask[0][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_0_T_541 = mux(write_mask[0][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_0_T_542 = mux(write_mask[0][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_0_T_543 = or(_ram_0_T_539, _ram_0_T_540) node _ram_0_T_544 = or(_ram_0_T_543, _ram_0_T_541) node _ram_0_T_545 = or(_ram_0_T_544, _ram_0_T_542) wire _ram_0_WIRE_87 : UInt<1> connect _ram_0_WIRE_87, _ram_0_T_545 connect _ram_0_WIRE_83.fence, _ram_0_WIRE_87 node _ram_0_T_546 = mux(write_mask[0][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_0_T_547 = mux(write_mask[0][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_0_T_548 = mux(write_mask[0][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_0_T_549 = mux(write_mask[0][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_0_T_550 = or(_ram_0_T_546, _ram_0_T_547) node _ram_0_T_551 = or(_ram_0_T_550, _ram_0_T_548) node _ram_0_T_552 = or(_ram_0_T_551, _ram_0_T_549) wire _ram_0_WIRE_88 : UInt<1> connect _ram_0_WIRE_88, _ram_0_T_552 connect _ram_0_WIRE_83.fence_i, _ram_0_WIRE_88 node _ram_0_T_553 = mux(write_mask[0][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_0_T_554 = mux(write_mask[0][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_0_T_555 = mux(write_mask[0][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_0_T_556 = mux(write_mask[0][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_0_T_557 = or(_ram_0_T_553, _ram_0_T_554) node _ram_0_T_558 = or(_ram_0_T_557, _ram_0_T_555) node _ram_0_T_559 = or(_ram_0_T_558, _ram_0_T_556) wire _ram_0_WIRE_89 : UInt<3> connect _ram_0_WIRE_89, _ram_0_T_559 connect _ram_0_WIRE_83.csr, _ram_0_WIRE_89 node _ram_0_T_560 = mux(write_mask[0][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_0_T_561 = mux(write_mask[0][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_0_T_562 = mux(write_mask[0][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_0_T_563 = mux(write_mask[0][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_0_T_564 = or(_ram_0_T_560, _ram_0_T_561) node _ram_0_T_565 = or(_ram_0_T_564, _ram_0_T_562) node _ram_0_T_566 = or(_ram_0_T_565, _ram_0_T_563) wire _ram_0_WIRE_90 : UInt<1> connect _ram_0_WIRE_90, _ram_0_T_566 connect _ram_0_WIRE_83.wxd, _ram_0_WIRE_90 node _ram_0_T_567 = mux(write_mask[0][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_0_T_568 = mux(write_mask[0][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_0_T_569 = mux(write_mask[0][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_0_T_570 = mux(write_mask[0][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_0_T_571 = or(_ram_0_T_567, _ram_0_T_568) node _ram_0_T_572 = or(_ram_0_T_571, _ram_0_T_569) node _ram_0_T_573 = or(_ram_0_T_572, _ram_0_T_570) wire _ram_0_WIRE_91 : UInt<1> connect _ram_0_WIRE_91, _ram_0_T_573 connect _ram_0_WIRE_83.div, _ram_0_WIRE_91 node _ram_0_T_574 = mux(write_mask[0][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_0_T_575 = mux(write_mask[0][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_0_T_576 = mux(write_mask[0][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_0_T_577 = mux(write_mask[0][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_0_T_578 = or(_ram_0_T_574, _ram_0_T_575) node _ram_0_T_579 = or(_ram_0_T_578, _ram_0_T_576) node _ram_0_T_580 = or(_ram_0_T_579, _ram_0_T_577) wire _ram_0_WIRE_92 : UInt<1> connect _ram_0_WIRE_92, _ram_0_T_580 connect _ram_0_WIRE_83.mul, _ram_0_WIRE_92 node _ram_0_T_581 = mux(write_mask[0][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_0_T_582 = mux(write_mask[0][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_0_T_583 = mux(write_mask[0][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_0_T_584 = mux(write_mask[0][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_0_T_585 = or(_ram_0_T_581, _ram_0_T_582) node _ram_0_T_586 = or(_ram_0_T_585, _ram_0_T_583) node _ram_0_T_587 = or(_ram_0_T_586, _ram_0_T_584) wire _ram_0_WIRE_93 : UInt<1> connect _ram_0_WIRE_93, _ram_0_T_587 connect _ram_0_WIRE_83.wfd, _ram_0_WIRE_93 node _ram_0_T_588 = mux(write_mask[0][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_0_T_589 = mux(write_mask[0][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_0_T_590 = mux(write_mask[0][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_0_T_591 = mux(write_mask[0][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_0_T_592 = or(_ram_0_T_588, _ram_0_T_589) node _ram_0_T_593 = or(_ram_0_T_592, _ram_0_T_590) node _ram_0_T_594 = or(_ram_0_T_593, _ram_0_T_591) wire _ram_0_WIRE_94 : UInt<1> connect _ram_0_WIRE_94, _ram_0_T_594 connect _ram_0_WIRE_83.rfs3, _ram_0_WIRE_94 node _ram_0_T_595 = mux(write_mask[0][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_0_T_596 = mux(write_mask[0][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_0_T_597 = mux(write_mask[0][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_0_T_598 = mux(write_mask[0][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_0_T_599 = or(_ram_0_T_595, _ram_0_T_596) node _ram_0_T_600 = or(_ram_0_T_599, _ram_0_T_597) node _ram_0_T_601 = or(_ram_0_T_600, _ram_0_T_598) wire _ram_0_WIRE_95 : UInt<1> connect _ram_0_WIRE_95, _ram_0_T_601 connect _ram_0_WIRE_83.rfs2, _ram_0_WIRE_95 node _ram_0_T_602 = mux(write_mask[0][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_0_T_603 = mux(write_mask[0][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_0_T_604 = mux(write_mask[0][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_0_T_605 = mux(write_mask[0][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_0_T_606 = or(_ram_0_T_602, _ram_0_T_603) node _ram_0_T_607 = or(_ram_0_T_606, _ram_0_T_604) node _ram_0_T_608 = or(_ram_0_T_607, _ram_0_T_605) wire _ram_0_WIRE_96 : UInt<1> connect _ram_0_WIRE_96, _ram_0_T_608 connect _ram_0_WIRE_83.rfs1, _ram_0_WIRE_96 node _ram_0_T_609 = mux(write_mask[0][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_0_T_610 = mux(write_mask[0][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_0_T_611 = mux(write_mask[0][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_0_T_612 = mux(write_mask[0][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_0_T_613 = or(_ram_0_T_609, _ram_0_T_610) node _ram_0_T_614 = or(_ram_0_T_613, _ram_0_T_611) node _ram_0_T_615 = or(_ram_0_T_614, _ram_0_T_612) wire _ram_0_WIRE_97 : UInt<5> connect _ram_0_WIRE_97, _ram_0_T_615 connect _ram_0_WIRE_83.mem_cmd, _ram_0_WIRE_97 node _ram_0_T_616 = mux(write_mask[0][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_0_T_617 = mux(write_mask[0][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_0_T_618 = mux(write_mask[0][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_0_T_619 = mux(write_mask[0][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_0_T_620 = or(_ram_0_T_616, _ram_0_T_617) node _ram_0_T_621 = or(_ram_0_T_620, _ram_0_T_618) node _ram_0_T_622 = or(_ram_0_T_621, _ram_0_T_619) wire _ram_0_WIRE_98 : UInt<1> connect _ram_0_WIRE_98, _ram_0_T_622 connect _ram_0_WIRE_83.mem, _ram_0_WIRE_98 node _ram_0_T_623 = mux(write_mask[0][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_0_T_624 = mux(write_mask[0][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_0_T_625 = mux(write_mask[0][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_0_T_626 = mux(write_mask[0][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_0_T_627 = or(_ram_0_T_623, _ram_0_T_624) node _ram_0_T_628 = or(_ram_0_T_627, _ram_0_T_625) node _ram_0_T_629 = or(_ram_0_T_628, _ram_0_T_626) wire _ram_0_WIRE_99 : UInt<5> connect _ram_0_WIRE_99, _ram_0_T_629 connect _ram_0_WIRE_83.alu_fn, _ram_0_WIRE_99 node _ram_0_T_630 = mux(write_mask[0][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_0_T_631 = mux(write_mask[0][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_0_T_632 = mux(write_mask[0][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_0_T_633 = mux(write_mask[0][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_0_T_634 = or(_ram_0_T_630, _ram_0_T_631) node _ram_0_T_635 = or(_ram_0_T_634, _ram_0_T_632) node _ram_0_T_636 = or(_ram_0_T_635, _ram_0_T_633) wire _ram_0_WIRE_100 : UInt<1> connect _ram_0_WIRE_100, _ram_0_T_636 connect _ram_0_WIRE_83.alu_dw, _ram_0_WIRE_100 node _ram_0_T_637 = mux(write_mask[0][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_0_T_638 = mux(write_mask[0][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_0_T_639 = mux(write_mask[0][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_0_T_640 = mux(write_mask[0][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_0_T_641 = or(_ram_0_T_637, _ram_0_T_638) node _ram_0_T_642 = or(_ram_0_T_641, _ram_0_T_639) node _ram_0_T_643 = or(_ram_0_T_642, _ram_0_T_640) wire _ram_0_WIRE_101 : UInt<3> connect _ram_0_WIRE_101, _ram_0_T_643 connect _ram_0_WIRE_83.sel_imm, _ram_0_WIRE_101 node _ram_0_T_644 = mux(write_mask[0][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_0_T_645 = mux(write_mask[0][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_0_T_646 = mux(write_mask[0][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_0_T_647 = mux(write_mask[0][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_0_T_648 = or(_ram_0_T_644, _ram_0_T_645) node _ram_0_T_649 = or(_ram_0_T_648, _ram_0_T_646) node _ram_0_T_650 = or(_ram_0_T_649, _ram_0_T_647) wire _ram_0_WIRE_102 : UInt<2> connect _ram_0_WIRE_102, _ram_0_T_650 connect _ram_0_WIRE_83.sel_alu1, _ram_0_WIRE_102 node _ram_0_T_651 = mux(write_mask[0][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_0_T_652 = mux(write_mask[0][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_0_T_653 = mux(write_mask[0][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_0_T_654 = mux(write_mask[0][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_0_T_655 = or(_ram_0_T_651, _ram_0_T_652) node _ram_0_T_656 = or(_ram_0_T_655, _ram_0_T_653) node _ram_0_T_657 = or(_ram_0_T_656, _ram_0_T_654) wire _ram_0_WIRE_103 : UInt<3> connect _ram_0_WIRE_103, _ram_0_T_657 connect _ram_0_WIRE_83.sel_alu2, _ram_0_WIRE_103 node _ram_0_T_658 = mux(write_mask[0][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_0_T_659 = mux(write_mask[0][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_0_T_660 = mux(write_mask[0][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_0_T_661 = mux(write_mask[0][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_0_T_662 = or(_ram_0_T_658, _ram_0_T_659) node _ram_0_T_663 = or(_ram_0_T_662, _ram_0_T_660) node _ram_0_T_664 = or(_ram_0_T_663, _ram_0_T_661) wire _ram_0_WIRE_104 : UInt<1> connect _ram_0_WIRE_104, _ram_0_T_664 connect _ram_0_WIRE_83.rxs1, _ram_0_WIRE_104 node _ram_0_T_665 = mux(write_mask[0][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_0_T_666 = mux(write_mask[0][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_0_T_667 = mux(write_mask[0][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_0_T_668 = mux(write_mask[0][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_0_T_669 = or(_ram_0_T_665, _ram_0_T_666) node _ram_0_T_670 = or(_ram_0_T_669, _ram_0_T_667) node _ram_0_T_671 = or(_ram_0_T_670, _ram_0_T_668) wire _ram_0_WIRE_105 : UInt<1> connect _ram_0_WIRE_105, _ram_0_T_671 connect _ram_0_WIRE_83.rxs2, _ram_0_WIRE_105 node _ram_0_T_672 = mux(write_mask[0][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_0_T_673 = mux(write_mask[0][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_0_T_674 = mux(write_mask[0][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_0_T_675 = mux(write_mask[0][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_0_T_676 = or(_ram_0_T_672, _ram_0_T_673) node _ram_0_T_677 = or(_ram_0_T_676, _ram_0_T_674) node _ram_0_T_678 = or(_ram_0_T_677, _ram_0_T_675) wire _ram_0_WIRE_106 : UInt<1> connect _ram_0_WIRE_106, _ram_0_T_678 connect _ram_0_WIRE_83.jalr, _ram_0_WIRE_106 node _ram_0_T_679 = mux(write_mask[0][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_0_T_680 = mux(write_mask[0][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_0_T_681 = mux(write_mask[0][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_0_T_682 = mux(write_mask[0][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_0_T_683 = or(_ram_0_T_679, _ram_0_T_680) node _ram_0_T_684 = or(_ram_0_T_683, _ram_0_T_681) node _ram_0_T_685 = or(_ram_0_T_684, _ram_0_T_682) wire _ram_0_WIRE_107 : UInt<1> connect _ram_0_WIRE_107, _ram_0_T_685 connect _ram_0_WIRE_83.jal, _ram_0_WIRE_107 node _ram_0_T_686 = mux(write_mask[0][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_0_T_687 = mux(write_mask[0][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_0_T_688 = mux(write_mask[0][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_0_T_689 = mux(write_mask[0][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_0_T_690 = or(_ram_0_T_686, _ram_0_T_687) node _ram_0_T_691 = or(_ram_0_T_690, _ram_0_T_688) node _ram_0_T_692 = or(_ram_0_T_691, _ram_0_T_689) wire _ram_0_WIRE_108 : UInt<1> connect _ram_0_WIRE_108, _ram_0_T_692 connect _ram_0_WIRE_83.branch, _ram_0_WIRE_108 node _ram_0_T_693 = mux(write_mask[0][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_0_T_694 = mux(write_mask[0][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_0_T_695 = mux(write_mask[0][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_0_T_696 = mux(write_mask[0][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_0_T_697 = or(_ram_0_T_693, _ram_0_T_694) node _ram_0_T_698 = or(_ram_0_T_697, _ram_0_T_695) node _ram_0_T_699 = or(_ram_0_T_698, _ram_0_T_696) wire _ram_0_WIRE_109 : UInt<1> connect _ram_0_WIRE_109, _ram_0_T_699 connect _ram_0_WIRE_83.rocc, _ram_0_WIRE_109 node _ram_0_T_700 = mux(write_mask[0][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_0_T_701 = mux(write_mask[0][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_0_T_702 = mux(write_mask[0][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_0_T_703 = mux(write_mask[0][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_0_T_704 = or(_ram_0_T_700, _ram_0_T_701) node _ram_0_T_705 = or(_ram_0_T_704, _ram_0_T_702) node _ram_0_T_706 = or(_ram_0_T_705, _ram_0_T_703) wire _ram_0_WIRE_110 : UInt<1> connect _ram_0_WIRE_110, _ram_0_T_706 connect _ram_0_WIRE_83.fp, _ram_0_WIRE_110 node _ram_0_T_707 = mux(write_mask[0][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_0_T_708 = mux(write_mask[0][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_0_T_709 = mux(write_mask[0][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_0_T_710 = mux(write_mask[0][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_0_T_711 = or(_ram_0_T_707, _ram_0_T_708) node _ram_0_T_712 = or(_ram_0_T_711, _ram_0_T_709) node _ram_0_T_713 = or(_ram_0_T_712, _ram_0_T_710) wire _ram_0_WIRE_111 : UInt<1> connect _ram_0_WIRE_111, _ram_0_T_713 connect _ram_0_WIRE_83.legal, _ram_0_WIRE_111 connect _ram_0_WIRE_1.ctrl, _ram_0_WIRE_83 node _ram_0_T_714 = mux(write_mask[0][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_0_T_715 = mux(write_mask[0][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_0_T_716 = mux(write_mask[0][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_0_T_717 = mux(write_mask[0][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_0_T_718 = or(_ram_0_T_714, _ram_0_T_715) node _ram_0_T_719 = or(_ram_0_T_718, _ram_0_T_716) node _ram_0_T_720 = or(_ram_0_T_719, _ram_0_T_717) wire _ram_0_WIRE_112 : UInt<1> connect _ram_0_WIRE_112, _ram_0_T_720 connect _ram_0_WIRE_1.edge_inst, _ram_0_WIRE_112 node _ram_0_T_721 = mux(write_mask[0][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_0_T_722 = mux(write_mask[0][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_0_T_723 = mux(write_mask[0][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_0_T_724 = mux(write_mask[0][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_0_T_725 = or(_ram_0_T_721, _ram_0_T_722) node _ram_0_T_726 = or(_ram_0_T_725, _ram_0_T_723) node _ram_0_T_727 = or(_ram_0_T_726, _ram_0_T_724) wire _ram_0_WIRE_113 : UInt<40> connect _ram_0_WIRE_113, _ram_0_T_727 connect _ram_0_WIRE_1.pc, _ram_0_WIRE_113 node _ram_0_T_728 = mux(write_mask[0][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_0_T_729 = mux(write_mask[0][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_0_T_730 = mux(write_mask[0][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_0_T_731 = mux(write_mask[0][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_0_T_732 = or(_ram_0_T_728, _ram_0_T_729) node _ram_0_T_733 = or(_ram_0_T_732, _ram_0_T_730) node _ram_0_T_734 = or(_ram_0_T_733, _ram_0_T_731) wire _ram_0_WIRE_114 : UInt<32> connect _ram_0_WIRE_114, _ram_0_T_734 connect _ram_0_WIRE_1.raw_inst, _ram_0_WIRE_114 node _ram_0_T_735 = mux(write_mask[0][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_0_T_736 = mux(write_mask[0][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_0_T_737 = mux(write_mask[0][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_0_T_738 = mux(write_mask[0][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_0_T_739 = or(_ram_0_T_735, _ram_0_T_736) node _ram_0_T_740 = or(_ram_0_T_739, _ram_0_T_737) node _ram_0_T_741 = or(_ram_0_T_740, _ram_0_T_738) wire _ram_0_WIRE_115 : UInt<32> connect _ram_0_WIRE_115, _ram_0_T_741 connect _ram_0_WIRE_1.inst, _ram_0_WIRE_115 connect _ram_0_WIRE.bits, _ram_0_WIRE_1 node _ram_0_T_742 = mux(write_mask[0][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_0_T_743 = mux(write_mask[0][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_0_T_744 = mux(write_mask[0][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_0_T_745 = mux(write_mask[0][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_0_T_746 = or(_ram_0_T_742, _ram_0_T_743) node _ram_0_T_747 = or(_ram_0_T_746, _ram_0_T_744) node _ram_0_T_748 = or(_ram_0_T_747, _ram_0_T_745) wire _ram_0_WIRE_116 : UInt<1> connect _ram_0_WIRE_116, _ram_0_T_748 connect _ram_0_WIRE.valid, _ram_0_WIRE_116 connect ram[0], _ram_0_WIRE node _T_22 = eq(ram[1].valid, UInt<1>(0h0)) when _T_22 : wire _ram_1_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_1_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_1_T = mux(write_mask[1][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_1_T_1 = mux(write_mask[1][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_1_T_2 = mux(write_mask[1][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_1_T_3 = mux(write_mask[1][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_1_T_4 = or(_ram_1_T, _ram_1_T_1) node _ram_1_T_5 = or(_ram_1_T_4, _ram_1_T_2) node _ram_1_T_6 = or(_ram_1_T_5, _ram_1_T_3) wire _ram_1_WIRE_2 : UInt<1> connect _ram_1_WIRE_2, _ram_1_T_6 connect _ram_1_WIRE_1.flush_pipe, _ram_1_WIRE_2 node _ram_1_T_7 = mux(write_mask[1][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_1_T_8 = mux(write_mask[1][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_1_T_9 = mux(write_mask[1][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_1_T_10 = mux(write_mask[1][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_1_T_11 = or(_ram_1_T_7, _ram_1_T_8) node _ram_1_T_12 = or(_ram_1_T_11, _ram_1_T_9) node _ram_1_T_13 = or(_ram_1_T_12, _ram_1_T_10) wire _ram_1_WIRE_3 : UInt<2> connect _ram_1_WIRE_3, _ram_1_T_13 connect _ram_1_WIRE_1.mem_size, _ram_1_WIRE_3 wire _ram_1_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_1_T_14 = mux(write_mask[1][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_1_T_15 = mux(write_mask[1][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_1_T_16 = mux(write_mask[1][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_1_T_17 = mux(write_mask[1][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_1_T_18 = or(_ram_1_T_14, _ram_1_T_15) node _ram_1_T_19 = or(_ram_1_T_18, _ram_1_T_16) node _ram_1_T_20 = or(_ram_1_T_19, _ram_1_T_17) wire _ram_1_WIRE_5 : UInt<65> connect _ram_1_WIRE_5, _ram_1_T_20 connect _ram_1_WIRE_4.in3, _ram_1_WIRE_5 node _ram_1_T_21 = mux(write_mask[1][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_1_T_22 = mux(write_mask[1][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_1_T_23 = mux(write_mask[1][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_1_T_24 = mux(write_mask[1][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_1_T_25 = or(_ram_1_T_21, _ram_1_T_22) node _ram_1_T_26 = or(_ram_1_T_25, _ram_1_T_23) node _ram_1_T_27 = or(_ram_1_T_26, _ram_1_T_24) wire _ram_1_WIRE_6 : UInt<65> connect _ram_1_WIRE_6, _ram_1_T_27 connect _ram_1_WIRE_4.in2, _ram_1_WIRE_6 node _ram_1_T_28 = mux(write_mask[1][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_1_T_29 = mux(write_mask[1][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_1_T_30 = mux(write_mask[1][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_1_T_31 = mux(write_mask[1][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_1_T_32 = or(_ram_1_T_28, _ram_1_T_29) node _ram_1_T_33 = or(_ram_1_T_32, _ram_1_T_30) node _ram_1_T_34 = or(_ram_1_T_33, _ram_1_T_31) wire _ram_1_WIRE_7 : UInt<65> connect _ram_1_WIRE_7, _ram_1_T_34 connect _ram_1_WIRE_4.in1, _ram_1_WIRE_7 node _ram_1_T_35 = mux(write_mask[1][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_1_T_36 = mux(write_mask[1][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_1_T_37 = mux(write_mask[1][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_1_T_38 = mux(write_mask[1][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_1_T_39 = or(_ram_1_T_35, _ram_1_T_36) node _ram_1_T_40 = or(_ram_1_T_39, _ram_1_T_37) node _ram_1_T_41 = or(_ram_1_T_40, _ram_1_T_38) wire _ram_1_WIRE_8 : UInt<2> connect _ram_1_WIRE_8, _ram_1_T_41 connect _ram_1_WIRE_4.fmt, _ram_1_WIRE_8 node _ram_1_T_42 = mux(write_mask[1][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_1_T_43 = mux(write_mask[1][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_1_T_44 = mux(write_mask[1][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_1_T_45 = mux(write_mask[1][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_1_T_46 = or(_ram_1_T_42, _ram_1_T_43) node _ram_1_T_47 = or(_ram_1_T_46, _ram_1_T_44) node _ram_1_T_48 = or(_ram_1_T_47, _ram_1_T_45) wire _ram_1_WIRE_9 : UInt<2> connect _ram_1_WIRE_9, _ram_1_T_48 connect _ram_1_WIRE_4.typ, _ram_1_WIRE_9 node _ram_1_T_49 = mux(write_mask[1][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_1_T_50 = mux(write_mask[1][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_1_T_51 = mux(write_mask[1][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_1_T_52 = mux(write_mask[1][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_1_T_53 = or(_ram_1_T_49, _ram_1_T_50) node _ram_1_T_54 = or(_ram_1_T_53, _ram_1_T_51) node _ram_1_T_55 = or(_ram_1_T_54, _ram_1_T_52) wire _ram_1_WIRE_10 : UInt<2> connect _ram_1_WIRE_10, _ram_1_T_55 connect _ram_1_WIRE_4.fmaCmd, _ram_1_WIRE_10 node _ram_1_T_56 = mux(write_mask[1][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_1_T_57 = mux(write_mask[1][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_1_T_58 = mux(write_mask[1][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_1_T_59 = mux(write_mask[1][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_1_T_60 = or(_ram_1_T_56, _ram_1_T_57) node _ram_1_T_61 = or(_ram_1_T_60, _ram_1_T_58) node _ram_1_T_62 = or(_ram_1_T_61, _ram_1_T_59) wire _ram_1_WIRE_11 : UInt<3> connect _ram_1_WIRE_11, _ram_1_T_62 connect _ram_1_WIRE_4.rm, _ram_1_WIRE_11 node _ram_1_T_63 = mux(write_mask[1][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_1_T_64 = mux(write_mask[1][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_1_T_65 = mux(write_mask[1][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_1_T_66 = mux(write_mask[1][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_1_T_67 = or(_ram_1_T_63, _ram_1_T_64) node _ram_1_T_68 = or(_ram_1_T_67, _ram_1_T_65) node _ram_1_T_69 = or(_ram_1_T_68, _ram_1_T_66) wire _ram_1_WIRE_12 : UInt<1> connect _ram_1_WIRE_12, _ram_1_T_69 connect _ram_1_WIRE_4.vec, _ram_1_WIRE_12 node _ram_1_T_70 = mux(write_mask[1][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_1_T_71 = mux(write_mask[1][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_1_T_72 = mux(write_mask[1][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_1_T_73 = mux(write_mask[1][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_1_T_74 = or(_ram_1_T_70, _ram_1_T_71) node _ram_1_T_75 = or(_ram_1_T_74, _ram_1_T_72) node _ram_1_T_76 = or(_ram_1_T_75, _ram_1_T_73) wire _ram_1_WIRE_13 : UInt<1> connect _ram_1_WIRE_13, _ram_1_T_76 connect _ram_1_WIRE_4.wflags, _ram_1_WIRE_13 node _ram_1_T_77 = mux(write_mask[1][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_1_T_78 = mux(write_mask[1][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_1_T_79 = mux(write_mask[1][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_1_T_80 = mux(write_mask[1][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_1_T_81 = or(_ram_1_T_77, _ram_1_T_78) node _ram_1_T_82 = or(_ram_1_T_81, _ram_1_T_79) node _ram_1_T_83 = or(_ram_1_T_82, _ram_1_T_80) wire _ram_1_WIRE_14 : UInt<1> connect _ram_1_WIRE_14, _ram_1_T_83 connect _ram_1_WIRE_4.sqrt, _ram_1_WIRE_14 node _ram_1_T_84 = mux(write_mask[1][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_1_T_85 = mux(write_mask[1][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_1_T_86 = mux(write_mask[1][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_1_T_87 = mux(write_mask[1][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_1_T_88 = or(_ram_1_T_84, _ram_1_T_85) node _ram_1_T_89 = or(_ram_1_T_88, _ram_1_T_86) node _ram_1_T_90 = or(_ram_1_T_89, _ram_1_T_87) wire _ram_1_WIRE_15 : UInt<1> connect _ram_1_WIRE_15, _ram_1_T_90 connect _ram_1_WIRE_4.div, _ram_1_WIRE_15 node _ram_1_T_91 = mux(write_mask[1][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_1_T_92 = mux(write_mask[1][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_1_T_93 = mux(write_mask[1][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_1_T_94 = mux(write_mask[1][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_1_T_95 = or(_ram_1_T_91, _ram_1_T_92) node _ram_1_T_96 = or(_ram_1_T_95, _ram_1_T_93) node _ram_1_T_97 = or(_ram_1_T_96, _ram_1_T_94) wire _ram_1_WIRE_16 : UInt<1> connect _ram_1_WIRE_16, _ram_1_T_97 connect _ram_1_WIRE_4.fma, _ram_1_WIRE_16 node _ram_1_T_98 = mux(write_mask[1][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_1_T_99 = mux(write_mask[1][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_1_T_100 = mux(write_mask[1][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_1_T_101 = mux(write_mask[1][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_1_T_102 = or(_ram_1_T_98, _ram_1_T_99) node _ram_1_T_103 = or(_ram_1_T_102, _ram_1_T_100) node _ram_1_T_104 = or(_ram_1_T_103, _ram_1_T_101) wire _ram_1_WIRE_17 : UInt<1> connect _ram_1_WIRE_17, _ram_1_T_104 connect _ram_1_WIRE_4.fastpipe, _ram_1_WIRE_17 node _ram_1_T_105 = mux(write_mask[1][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_1_T_106 = mux(write_mask[1][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_1_T_107 = mux(write_mask[1][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_1_T_108 = mux(write_mask[1][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_1_T_109 = or(_ram_1_T_105, _ram_1_T_106) node _ram_1_T_110 = or(_ram_1_T_109, _ram_1_T_107) node _ram_1_T_111 = or(_ram_1_T_110, _ram_1_T_108) wire _ram_1_WIRE_18 : UInt<1> connect _ram_1_WIRE_18, _ram_1_T_111 connect _ram_1_WIRE_4.toint, _ram_1_WIRE_18 node _ram_1_T_112 = mux(write_mask[1][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_1_T_113 = mux(write_mask[1][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_1_T_114 = mux(write_mask[1][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_1_T_115 = mux(write_mask[1][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_1_T_116 = or(_ram_1_T_112, _ram_1_T_113) node _ram_1_T_117 = or(_ram_1_T_116, _ram_1_T_114) node _ram_1_T_118 = or(_ram_1_T_117, _ram_1_T_115) wire _ram_1_WIRE_19 : UInt<1> connect _ram_1_WIRE_19, _ram_1_T_118 connect _ram_1_WIRE_4.fromint, _ram_1_WIRE_19 node _ram_1_T_119 = mux(write_mask[1][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_1_T_120 = mux(write_mask[1][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_1_T_121 = mux(write_mask[1][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_1_T_122 = mux(write_mask[1][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_1_T_123 = or(_ram_1_T_119, _ram_1_T_120) node _ram_1_T_124 = or(_ram_1_T_123, _ram_1_T_121) node _ram_1_T_125 = or(_ram_1_T_124, _ram_1_T_122) wire _ram_1_WIRE_20 : UInt<2> connect _ram_1_WIRE_20, _ram_1_T_125 connect _ram_1_WIRE_4.typeTagOut, _ram_1_WIRE_20 node _ram_1_T_126 = mux(write_mask[1][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_1_T_127 = mux(write_mask[1][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_1_T_128 = mux(write_mask[1][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_1_T_129 = mux(write_mask[1][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_1_T_130 = or(_ram_1_T_126, _ram_1_T_127) node _ram_1_T_131 = or(_ram_1_T_130, _ram_1_T_128) node _ram_1_T_132 = or(_ram_1_T_131, _ram_1_T_129) wire _ram_1_WIRE_21 : UInt<2> connect _ram_1_WIRE_21, _ram_1_T_132 connect _ram_1_WIRE_4.typeTagIn, _ram_1_WIRE_21 node _ram_1_T_133 = mux(write_mask[1][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_1_T_134 = mux(write_mask[1][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_1_T_135 = mux(write_mask[1][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_1_T_136 = mux(write_mask[1][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_1_T_137 = or(_ram_1_T_133, _ram_1_T_134) node _ram_1_T_138 = or(_ram_1_T_137, _ram_1_T_135) node _ram_1_T_139 = or(_ram_1_T_138, _ram_1_T_136) wire _ram_1_WIRE_22 : UInt<1> connect _ram_1_WIRE_22, _ram_1_T_139 connect _ram_1_WIRE_4.swap23, _ram_1_WIRE_22 node _ram_1_T_140 = mux(write_mask[1][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_1_T_141 = mux(write_mask[1][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_1_T_142 = mux(write_mask[1][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_1_T_143 = mux(write_mask[1][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_1_T_144 = or(_ram_1_T_140, _ram_1_T_141) node _ram_1_T_145 = or(_ram_1_T_144, _ram_1_T_142) node _ram_1_T_146 = or(_ram_1_T_145, _ram_1_T_143) wire _ram_1_WIRE_23 : UInt<1> connect _ram_1_WIRE_23, _ram_1_T_146 connect _ram_1_WIRE_4.swap12, _ram_1_WIRE_23 node _ram_1_T_147 = mux(write_mask[1][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_1_T_148 = mux(write_mask[1][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_1_T_149 = mux(write_mask[1][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_1_T_150 = mux(write_mask[1][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_1_T_151 = or(_ram_1_T_147, _ram_1_T_148) node _ram_1_T_152 = or(_ram_1_T_151, _ram_1_T_149) node _ram_1_T_153 = or(_ram_1_T_152, _ram_1_T_150) wire _ram_1_WIRE_24 : UInt<1> connect _ram_1_WIRE_24, _ram_1_T_153 connect _ram_1_WIRE_4.ren3, _ram_1_WIRE_24 node _ram_1_T_154 = mux(write_mask[1][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_1_T_155 = mux(write_mask[1][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_1_T_156 = mux(write_mask[1][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_1_T_157 = mux(write_mask[1][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_1_T_158 = or(_ram_1_T_154, _ram_1_T_155) node _ram_1_T_159 = or(_ram_1_T_158, _ram_1_T_156) node _ram_1_T_160 = or(_ram_1_T_159, _ram_1_T_157) wire _ram_1_WIRE_25 : UInt<1> connect _ram_1_WIRE_25, _ram_1_T_160 connect _ram_1_WIRE_4.ren2, _ram_1_WIRE_25 node _ram_1_T_161 = mux(write_mask[1][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_1_T_162 = mux(write_mask[1][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_1_T_163 = mux(write_mask[1][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_1_T_164 = mux(write_mask[1][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_1_T_165 = or(_ram_1_T_161, _ram_1_T_162) node _ram_1_T_166 = or(_ram_1_T_165, _ram_1_T_163) node _ram_1_T_167 = or(_ram_1_T_166, _ram_1_T_164) wire _ram_1_WIRE_26 : UInt<1> connect _ram_1_WIRE_26, _ram_1_T_167 connect _ram_1_WIRE_4.ren1, _ram_1_WIRE_26 node _ram_1_T_168 = mux(write_mask[1][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_1_T_169 = mux(write_mask[1][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_1_T_170 = mux(write_mask[1][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_1_T_171 = mux(write_mask[1][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_1_T_172 = or(_ram_1_T_168, _ram_1_T_169) node _ram_1_T_173 = or(_ram_1_T_172, _ram_1_T_170) node _ram_1_T_174 = or(_ram_1_T_173, _ram_1_T_171) wire _ram_1_WIRE_27 : UInt<1> connect _ram_1_WIRE_27, _ram_1_T_174 connect _ram_1_WIRE_4.wen, _ram_1_WIRE_27 node _ram_1_T_175 = mux(write_mask[1][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_1_T_176 = mux(write_mask[1][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_1_T_177 = mux(write_mask[1][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_1_T_178 = mux(write_mask[1][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_1_T_179 = or(_ram_1_T_175, _ram_1_T_176) node _ram_1_T_180 = or(_ram_1_T_179, _ram_1_T_177) node _ram_1_T_181 = or(_ram_1_T_180, _ram_1_T_178) wire _ram_1_WIRE_28 : UInt<1> connect _ram_1_WIRE_28, _ram_1_T_181 connect _ram_1_WIRE_4.ldst, _ram_1_WIRE_28 connect _ram_1_WIRE_1.fdivin, _ram_1_WIRE_4 node _ram_1_T_182 = mux(write_mask[1][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_1_T_183 = mux(write_mask[1][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_1_T_184 = mux(write_mask[1][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_1_T_185 = mux(write_mask[1][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_1_T_186 = or(_ram_1_T_182, _ram_1_T_183) node _ram_1_T_187 = or(_ram_1_T_186, _ram_1_T_184) node _ram_1_T_188 = or(_ram_1_T_187, _ram_1_T_185) wire _ram_1_WIRE_29 : UInt<5> connect _ram_1_WIRE_29, _ram_1_T_188 connect _ram_1_WIRE_1.fexc, _ram_1_WIRE_29 node _ram_1_T_189 = mux(write_mask[1][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_1_T_190 = mux(write_mask[1][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_1_T_191 = mux(write_mask[1][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_1_T_192 = mux(write_mask[1][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_1_T_193 = or(_ram_1_T_189, _ram_1_T_190) node _ram_1_T_194 = or(_ram_1_T_193, _ram_1_T_191) node _ram_1_T_195 = or(_ram_1_T_194, _ram_1_T_192) wire _ram_1_WIRE_30 : UInt<5> connect _ram_1_WIRE_30, _ram_1_T_195 connect _ram_1_WIRE_1.fra3, _ram_1_WIRE_30 node _ram_1_T_196 = mux(write_mask[1][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_1_T_197 = mux(write_mask[1][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_1_T_198 = mux(write_mask[1][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_1_T_199 = mux(write_mask[1][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_1_T_200 = or(_ram_1_T_196, _ram_1_T_197) node _ram_1_T_201 = or(_ram_1_T_200, _ram_1_T_198) node _ram_1_T_202 = or(_ram_1_T_201, _ram_1_T_199) wire _ram_1_WIRE_31 : UInt<5> connect _ram_1_WIRE_31, _ram_1_T_202 connect _ram_1_WIRE_1.fra2, _ram_1_WIRE_31 node _ram_1_T_203 = mux(write_mask[1][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_1_T_204 = mux(write_mask[1][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_1_T_205 = mux(write_mask[1][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_1_T_206 = mux(write_mask[1][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_1_T_207 = or(_ram_1_T_203, _ram_1_T_204) node _ram_1_T_208 = or(_ram_1_T_207, _ram_1_T_205) node _ram_1_T_209 = or(_ram_1_T_208, _ram_1_T_206) wire _ram_1_WIRE_32 : UInt<5> connect _ram_1_WIRE_32, _ram_1_T_209 connect _ram_1_WIRE_1.fra1, _ram_1_WIRE_32 wire _ram_1_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_1_T_210 = mux(write_mask[1][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_1_T_211 = mux(write_mask[1][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_1_T_212 = mux(write_mask[1][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_1_T_213 = mux(write_mask[1][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_1_T_214 = or(_ram_1_T_210, _ram_1_T_211) node _ram_1_T_215 = or(_ram_1_T_214, _ram_1_T_212) node _ram_1_T_216 = or(_ram_1_T_215, _ram_1_T_213) wire _ram_1_WIRE_34 : UInt<64> connect _ram_1_WIRE_34, _ram_1_T_216 connect _ram_1_WIRE_33.bits, _ram_1_WIRE_34 node _ram_1_T_217 = mux(write_mask[1][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_1_T_218 = mux(write_mask[1][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_1_T_219 = mux(write_mask[1][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_1_T_220 = mux(write_mask[1][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_1_T_221 = or(_ram_1_T_217, _ram_1_T_218) node _ram_1_T_222 = or(_ram_1_T_221, _ram_1_T_219) node _ram_1_T_223 = or(_ram_1_T_222, _ram_1_T_220) wire _ram_1_WIRE_35 : UInt<1> connect _ram_1_WIRE_35, _ram_1_T_223 connect _ram_1_WIRE_33.valid, _ram_1_WIRE_35 connect _ram_1_WIRE_1.wdata, _ram_1_WIRE_33 node _ram_1_T_224 = mux(write_mask[1][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_1_T_225 = mux(write_mask[1][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_1_T_226 = mux(write_mask[1][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_1_T_227 = mux(write_mask[1][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_1_T_228 = or(_ram_1_T_224, _ram_1_T_225) node _ram_1_T_229 = or(_ram_1_T_228, _ram_1_T_226) node _ram_1_T_230 = or(_ram_1_T_229, _ram_1_T_227) wire _ram_1_WIRE_36 : UInt<1> connect _ram_1_WIRE_36, _ram_1_T_230 connect _ram_1_WIRE_1.uses_latealu, _ram_1_WIRE_36 node _ram_1_T_231 = mux(write_mask[1][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_1_T_232 = mux(write_mask[1][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_1_T_233 = mux(write_mask[1][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_1_T_234 = mux(write_mask[1][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_1_T_235 = or(_ram_1_T_231, _ram_1_T_232) node _ram_1_T_236 = or(_ram_1_T_235, _ram_1_T_233) node _ram_1_T_237 = or(_ram_1_T_236, _ram_1_T_234) wire _ram_1_WIRE_37 : UInt<1> connect _ram_1_WIRE_37, _ram_1_T_237 connect _ram_1_WIRE_1.uses_memalu, _ram_1_WIRE_37 node _ram_1_T_238 = mux(write_mask[1][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_1_T_239 = mux(write_mask[1][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_1_T_240 = mux(write_mask[1][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_1_T_241 = mux(write_mask[1][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_1_T_242 = or(_ram_1_T_238, _ram_1_T_239) node _ram_1_T_243 = or(_ram_1_T_242, _ram_1_T_240) node _ram_1_T_244 = or(_ram_1_T_243, _ram_1_T_241) wire _ram_1_WIRE_38 : UInt<64> connect _ram_1_WIRE_38, _ram_1_T_244 connect _ram_1_WIRE_1.rs3_data, _ram_1_WIRE_38 node _ram_1_T_245 = mux(write_mask[1][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_1_T_246 = mux(write_mask[1][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_1_T_247 = mux(write_mask[1][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_1_T_248 = mux(write_mask[1][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_1_T_249 = or(_ram_1_T_245, _ram_1_T_246) node _ram_1_T_250 = or(_ram_1_T_249, _ram_1_T_247) node _ram_1_T_251 = or(_ram_1_T_250, _ram_1_T_248) wire _ram_1_WIRE_39 : UInt<64> connect _ram_1_WIRE_39, _ram_1_T_251 connect _ram_1_WIRE_1.rs2_data, _ram_1_WIRE_39 node _ram_1_T_252 = mux(write_mask[1][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_1_T_253 = mux(write_mask[1][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_1_T_254 = mux(write_mask[1][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_1_T_255 = mux(write_mask[1][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_1_T_256 = or(_ram_1_T_252, _ram_1_T_253) node _ram_1_T_257 = or(_ram_1_T_256, _ram_1_T_254) node _ram_1_T_258 = or(_ram_1_T_257, _ram_1_T_255) wire _ram_1_WIRE_40 : UInt<64> connect _ram_1_WIRE_40, _ram_1_T_258 connect _ram_1_WIRE_1.rs1_data, _ram_1_WIRE_40 node _ram_1_T_259 = mux(write_mask[1][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_1_T_260 = mux(write_mask[1][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_1_T_261 = mux(write_mask[1][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_1_T_262 = mux(write_mask[1][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_1_T_263 = or(_ram_1_T_259, _ram_1_T_260) node _ram_1_T_264 = or(_ram_1_T_263, _ram_1_T_261) node _ram_1_T_265 = or(_ram_1_T_264, _ram_1_T_262) wire _ram_1_WIRE_41 : UInt<1> connect _ram_1_WIRE_41, _ram_1_T_265 connect _ram_1_WIRE_1.needs_replay, _ram_1_WIRE_41 node _ram_1_T_266 = mux(write_mask[1][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_1_T_267 = mux(write_mask[1][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_1_T_268 = mux(write_mask[1][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_1_T_269 = mux(write_mask[1][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_1_T_270 = or(_ram_1_T_266, _ram_1_T_267) node _ram_1_T_271 = or(_ram_1_T_270, _ram_1_T_268) node _ram_1_T_272 = or(_ram_1_T_271, _ram_1_T_269) wire _ram_1_WIRE_42 : UInt<64> connect _ram_1_WIRE_42, _ram_1_T_272 connect _ram_1_WIRE_1.xcpt_cause, _ram_1_WIRE_42 node _ram_1_T_273 = mux(write_mask[1][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_1_T_274 = mux(write_mask[1][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_1_T_275 = mux(write_mask[1][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_1_T_276 = mux(write_mask[1][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_1_T_277 = or(_ram_1_T_273, _ram_1_T_274) node _ram_1_T_278 = or(_ram_1_T_277, _ram_1_T_275) node _ram_1_T_279 = or(_ram_1_T_278, _ram_1_T_276) wire _ram_1_WIRE_43 : UInt<1> connect _ram_1_WIRE_43, _ram_1_T_279 connect _ram_1_WIRE_1.xcpt, _ram_1_WIRE_43 node _ram_1_T_280 = mux(write_mask[1][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_1_T_281 = mux(write_mask[1][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_1_T_282 = mux(write_mask[1][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_1_T_283 = mux(write_mask[1][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_1_T_284 = or(_ram_1_T_280, _ram_1_T_281) node _ram_1_T_285 = or(_ram_1_T_284, _ram_1_T_282) node _ram_1_T_286 = or(_ram_1_T_285, _ram_1_T_283) wire _ram_1_WIRE_44 : UInt<1> connect _ram_1_WIRE_44, _ram_1_T_286 connect _ram_1_WIRE_1.taken, _ram_1_WIRE_44 node _ram_1_T_287 = mux(write_mask[1][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_1_T_288 = mux(write_mask[1][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_1_T_289 = mux(write_mask[1][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_1_T_290 = mux(write_mask[1][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_1_T_291 = or(_ram_1_T_287, _ram_1_T_288) node _ram_1_T_292 = or(_ram_1_T_291, _ram_1_T_289) node _ram_1_T_293 = or(_ram_1_T_292, _ram_1_T_290) wire _ram_1_WIRE_45 : UInt<3> connect _ram_1_WIRE_45, _ram_1_T_293 connect _ram_1_WIRE_1.ras_head, _ram_1_WIRE_45 wire _ram_1_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_1_T_294 = mux(write_mask[1][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_1_T_295 = mux(write_mask[1][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_1_T_296 = mux(write_mask[1][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_1_T_297 = mux(write_mask[1][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_1_T_298 = or(_ram_1_T_294, _ram_1_T_295) node _ram_1_T_299 = or(_ram_1_T_298, _ram_1_T_296) node _ram_1_T_300 = or(_ram_1_T_299, _ram_1_T_297) wire _ram_1_WIRE_47 : UInt<40> connect _ram_1_WIRE_47, _ram_1_T_300 connect _ram_1_WIRE_46.bits, _ram_1_WIRE_47 node _ram_1_T_301 = mux(write_mask[1][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_1_T_302 = mux(write_mask[1][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_1_T_303 = mux(write_mask[1][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_1_T_304 = mux(write_mask[1][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_1_T_305 = or(_ram_1_T_301, _ram_1_T_302) node _ram_1_T_306 = or(_ram_1_T_305, _ram_1_T_303) node _ram_1_T_307 = or(_ram_1_T_306, _ram_1_T_304) wire _ram_1_WIRE_48 : UInt<1> connect _ram_1_WIRE_48, _ram_1_T_307 connect _ram_1_WIRE_46.valid, _ram_1_WIRE_48 connect _ram_1_WIRE_1.next_pc, _ram_1_WIRE_46 node _ram_1_T_308 = mux(write_mask[1][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_1_T_309 = mux(write_mask[1][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_1_T_310 = mux(write_mask[1][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_1_T_311 = mux(write_mask[1][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_1_T_312 = or(_ram_1_T_308, _ram_1_T_309) node _ram_1_T_313 = or(_ram_1_T_312, _ram_1_T_310) node _ram_1_T_314 = or(_ram_1_T_313, _ram_1_T_311) wire _ram_1_WIRE_49 : UInt<1> connect _ram_1_WIRE_49, _ram_1_T_314 connect _ram_1_WIRE_1.sfb_shadow, _ram_1_WIRE_49 node _ram_1_T_315 = mux(write_mask[1][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_1_T_316 = mux(write_mask[1][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_1_T_317 = mux(write_mask[1][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_1_T_318 = mux(write_mask[1][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_1_T_319 = or(_ram_1_T_315, _ram_1_T_316) node _ram_1_T_320 = or(_ram_1_T_319, _ram_1_T_317) node _ram_1_T_321 = or(_ram_1_T_320, _ram_1_T_318) wire _ram_1_WIRE_50 : UInt<1> connect _ram_1_WIRE_50, _ram_1_T_321 connect _ram_1_WIRE_1.sfb_br, _ram_1_WIRE_50 wire _ram_1_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_1_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_1_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_1_T_322 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_1_T_323 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_1_T_324 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_1_T_325 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_1_T_326 = or(_ram_1_T_322, _ram_1_T_323) node _ram_1_T_327 = or(_ram_1_T_326, _ram_1_T_324) node _ram_1_T_328 = or(_ram_1_T_327, _ram_1_T_325) wire _ram_1_WIRE_54 : UInt<2> connect _ram_1_WIRE_54, _ram_1_T_328 connect _ram_1_WIRE_53.value, _ram_1_WIRE_54 node _ram_1_T_329 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_1_T_330 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_1_T_331 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_1_T_332 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_1_T_333 = or(_ram_1_T_329, _ram_1_T_330) node _ram_1_T_334 = or(_ram_1_T_333, _ram_1_T_331) node _ram_1_T_335 = or(_ram_1_T_334, _ram_1_T_332) wire _ram_1_WIRE_55 : UInt<8> connect _ram_1_WIRE_55, _ram_1_T_335 connect _ram_1_WIRE_53.history, _ram_1_WIRE_55 connect _ram_1_WIRE_52.bht, _ram_1_WIRE_53 node _ram_1_T_336 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_1_T_337 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_1_T_338 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_1_T_339 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_1_T_340 = or(_ram_1_T_336, _ram_1_T_337) node _ram_1_T_341 = or(_ram_1_T_340, _ram_1_T_338) node _ram_1_T_342 = or(_ram_1_T_341, _ram_1_T_339) wire _ram_1_WIRE_56 : UInt<6> connect _ram_1_WIRE_56, _ram_1_T_342 connect _ram_1_WIRE_52.entry, _ram_1_WIRE_56 node _ram_1_T_343 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_1_T_344 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_1_T_345 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_1_T_346 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_1_T_347 = or(_ram_1_T_343, _ram_1_T_344) node _ram_1_T_348 = or(_ram_1_T_347, _ram_1_T_345) node _ram_1_T_349 = or(_ram_1_T_348, _ram_1_T_346) wire _ram_1_WIRE_57 : UInt<39> connect _ram_1_WIRE_57, _ram_1_T_349 connect _ram_1_WIRE_52.target, _ram_1_WIRE_57 node _ram_1_T_350 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_1_T_351 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_1_T_352 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_1_T_353 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_1_T_354 = or(_ram_1_T_350, _ram_1_T_351) node _ram_1_T_355 = or(_ram_1_T_354, _ram_1_T_352) node _ram_1_T_356 = or(_ram_1_T_355, _ram_1_T_353) wire _ram_1_WIRE_58 : UInt<2> connect _ram_1_WIRE_58, _ram_1_T_356 connect _ram_1_WIRE_52.bridx, _ram_1_WIRE_58 node _ram_1_T_357 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_1_T_358 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_1_T_359 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_1_T_360 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_1_T_361 = or(_ram_1_T_357, _ram_1_T_358) node _ram_1_T_362 = or(_ram_1_T_361, _ram_1_T_359) node _ram_1_T_363 = or(_ram_1_T_362, _ram_1_T_360) wire _ram_1_WIRE_59 : UInt<4> connect _ram_1_WIRE_59, _ram_1_T_363 connect _ram_1_WIRE_52.mask, _ram_1_WIRE_59 node _ram_1_T_364 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_1_T_365 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_1_T_366 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_1_T_367 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_1_T_368 = or(_ram_1_T_364, _ram_1_T_365) node _ram_1_T_369 = or(_ram_1_T_368, _ram_1_T_366) node _ram_1_T_370 = or(_ram_1_T_369, _ram_1_T_367) wire _ram_1_WIRE_60 : UInt<1> connect _ram_1_WIRE_60, _ram_1_T_370 connect _ram_1_WIRE_52.taken, _ram_1_WIRE_60 node _ram_1_T_371 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_1_T_372 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_1_T_373 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_1_T_374 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_1_T_375 = or(_ram_1_T_371, _ram_1_T_372) node _ram_1_T_376 = or(_ram_1_T_375, _ram_1_T_373) node _ram_1_T_377 = or(_ram_1_T_376, _ram_1_T_374) wire _ram_1_WIRE_61 : UInt<2> connect _ram_1_WIRE_61, _ram_1_T_377 connect _ram_1_WIRE_52.cfiType, _ram_1_WIRE_61 connect _ram_1_WIRE_51.bits, _ram_1_WIRE_52 node _ram_1_T_378 = mux(write_mask[1][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_1_T_379 = mux(write_mask[1][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_1_T_380 = mux(write_mask[1][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_1_T_381 = mux(write_mask[1][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_1_T_382 = or(_ram_1_T_378, _ram_1_T_379) node _ram_1_T_383 = or(_ram_1_T_382, _ram_1_T_380) node _ram_1_T_384 = or(_ram_1_T_383, _ram_1_T_381) wire _ram_1_WIRE_62 : UInt<1> connect _ram_1_WIRE_62, _ram_1_T_384 connect _ram_1_WIRE_51.valid, _ram_1_WIRE_62 connect _ram_1_WIRE_1.btb_resp, _ram_1_WIRE_51 node _ram_1_T_385 = mux(write_mask[1][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_1_T_386 = mux(write_mask[1][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_1_T_387 = mux(write_mask[1][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_1_T_388 = mux(write_mask[1][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_1_T_389 = or(_ram_1_T_385, _ram_1_T_386) node _ram_1_T_390 = or(_ram_1_T_389, _ram_1_T_387) node _ram_1_T_391 = or(_ram_1_T_390, _ram_1_T_388) wire _ram_1_WIRE_63 : UInt<1> connect _ram_1_WIRE_63, _ram_1_T_391 connect _ram_1_WIRE_1.sets_vcfg, _ram_1_WIRE_63 node _ram_1_T_392 = mux(write_mask[1][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_1_T_393 = mux(write_mask[1][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_1_T_394 = mux(write_mask[1][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_1_T_395 = mux(write_mask[1][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_1_T_396 = or(_ram_1_T_392, _ram_1_T_393) node _ram_1_T_397 = or(_ram_1_T_396, _ram_1_T_394) node _ram_1_T_398 = or(_ram_1_T_397, _ram_1_T_395) wire _ram_1_WIRE_64 : UInt<1> connect _ram_1_WIRE_64, _ram_1_T_398 connect _ram_1_WIRE_1.rvc, _ram_1_WIRE_64 wire _ram_1_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_1_T_399 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_1_T_400 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_1_T_401 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_1_T_402 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_1_T_403 = or(_ram_1_T_399, _ram_1_T_400) node _ram_1_T_404 = or(_ram_1_T_403, _ram_1_T_401) node _ram_1_T_405 = or(_ram_1_T_404, _ram_1_T_402) wire _ram_1_WIRE_66 : UInt<1> connect _ram_1_WIRE_66, _ram_1_T_405 connect _ram_1_WIRE_65.vec, _ram_1_WIRE_66 node _ram_1_T_406 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_1_T_407 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_1_T_408 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_1_T_409 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_1_T_410 = or(_ram_1_T_406, _ram_1_T_407) node _ram_1_T_411 = or(_ram_1_T_410, _ram_1_T_408) node _ram_1_T_412 = or(_ram_1_T_411, _ram_1_T_409) wire _ram_1_WIRE_67 : UInt<1> connect _ram_1_WIRE_67, _ram_1_T_412 connect _ram_1_WIRE_65.wflags, _ram_1_WIRE_67 node _ram_1_T_413 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_1_T_414 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_1_T_415 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_1_T_416 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_1_T_417 = or(_ram_1_T_413, _ram_1_T_414) node _ram_1_T_418 = or(_ram_1_T_417, _ram_1_T_415) node _ram_1_T_419 = or(_ram_1_T_418, _ram_1_T_416) wire _ram_1_WIRE_68 : UInt<1> connect _ram_1_WIRE_68, _ram_1_T_419 connect _ram_1_WIRE_65.sqrt, _ram_1_WIRE_68 node _ram_1_T_420 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_1_T_421 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_1_T_422 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_1_T_423 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_1_T_424 = or(_ram_1_T_420, _ram_1_T_421) node _ram_1_T_425 = or(_ram_1_T_424, _ram_1_T_422) node _ram_1_T_426 = or(_ram_1_T_425, _ram_1_T_423) wire _ram_1_WIRE_69 : UInt<1> connect _ram_1_WIRE_69, _ram_1_T_426 connect _ram_1_WIRE_65.div, _ram_1_WIRE_69 node _ram_1_T_427 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_1_T_428 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_1_T_429 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_1_T_430 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_1_T_431 = or(_ram_1_T_427, _ram_1_T_428) node _ram_1_T_432 = or(_ram_1_T_431, _ram_1_T_429) node _ram_1_T_433 = or(_ram_1_T_432, _ram_1_T_430) wire _ram_1_WIRE_70 : UInt<1> connect _ram_1_WIRE_70, _ram_1_T_433 connect _ram_1_WIRE_65.fma, _ram_1_WIRE_70 node _ram_1_T_434 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_1_T_435 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_1_T_436 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_1_T_437 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_1_T_438 = or(_ram_1_T_434, _ram_1_T_435) node _ram_1_T_439 = or(_ram_1_T_438, _ram_1_T_436) node _ram_1_T_440 = or(_ram_1_T_439, _ram_1_T_437) wire _ram_1_WIRE_71 : UInt<1> connect _ram_1_WIRE_71, _ram_1_T_440 connect _ram_1_WIRE_65.fastpipe, _ram_1_WIRE_71 node _ram_1_T_441 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_1_T_442 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_1_T_443 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_1_T_444 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_1_T_445 = or(_ram_1_T_441, _ram_1_T_442) node _ram_1_T_446 = or(_ram_1_T_445, _ram_1_T_443) node _ram_1_T_447 = or(_ram_1_T_446, _ram_1_T_444) wire _ram_1_WIRE_72 : UInt<1> connect _ram_1_WIRE_72, _ram_1_T_447 connect _ram_1_WIRE_65.toint, _ram_1_WIRE_72 node _ram_1_T_448 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_1_T_449 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_1_T_450 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_1_T_451 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_1_T_452 = or(_ram_1_T_448, _ram_1_T_449) node _ram_1_T_453 = or(_ram_1_T_452, _ram_1_T_450) node _ram_1_T_454 = or(_ram_1_T_453, _ram_1_T_451) wire _ram_1_WIRE_73 : UInt<1> connect _ram_1_WIRE_73, _ram_1_T_454 connect _ram_1_WIRE_65.fromint, _ram_1_WIRE_73 node _ram_1_T_455 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_1_T_456 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_1_T_457 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_1_T_458 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_1_T_459 = or(_ram_1_T_455, _ram_1_T_456) node _ram_1_T_460 = or(_ram_1_T_459, _ram_1_T_457) node _ram_1_T_461 = or(_ram_1_T_460, _ram_1_T_458) wire _ram_1_WIRE_74 : UInt<2> connect _ram_1_WIRE_74, _ram_1_T_461 connect _ram_1_WIRE_65.typeTagOut, _ram_1_WIRE_74 node _ram_1_T_462 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_1_T_463 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_1_T_464 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_1_T_465 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_1_T_466 = or(_ram_1_T_462, _ram_1_T_463) node _ram_1_T_467 = or(_ram_1_T_466, _ram_1_T_464) node _ram_1_T_468 = or(_ram_1_T_467, _ram_1_T_465) wire _ram_1_WIRE_75 : UInt<2> connect _ram_1_WIRE_75, _ram_1_T_468 connect _ram_1_WIRE_65.typeTagIn, _ram_1_WIRE_75 node _ram_1_T_469 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_1_T_470 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_1_T_471 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_1_T_472 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_1_T_473 = or(_ram_1_T_469, _ram_1_T_470) node _ram_1_T_474 = or(_ram_1_T_473, _ram_1_T_471) node _ram_1_T_475 = or(_ram_1_T_474, _ram_1_T_472) wire _ram_1_WIRE_76 : UInt<1> connect _ram_1_WIRE_76, _ram_1_T_475 connect _ram_1_WIRE_65.swap23, _ram_1_WIRE_76 node _ram_1_T_476 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_1_T_477 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_1_T_478 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_1_T_479 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_1_T_480 = or(_ram_1_T_476, _ram_1_T_477) node _ram_1_T_481 = or(_ram_1_T_480, _ram_1_T_478) node _ram_1_T_482 = or(_ram_1_T_481, _ram_1_T_479) wire _ram_1_WIRE_77 : UInt<1> connect _ram_1_WIRE_77, _ram_1_T_482 connect _ram_1_WIRE_65.swap12, _ram_1_WIRE_77 node _ram_1_T_483 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_1_T_484 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_1_T_485 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_1_T_486 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_1_T_487 = or(_ram_1_T_483, _ram_1_T_484) node _ram_1_T_488 = or(_ram_1_T_487, _ram_1_T_485) node _ram_1_T_489 = or(_ram_1_T_488, _ram_1_T_486) wire _ram_1_WIRE_78 : UInt<1> connect _ram_1_WIRE_78, _ram_1_T_489 connect _ram_1_WIRE_65.ren3, _ram_1_WIRE_78 node _ram_1_T_490 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_1_T_491 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_1_T_492 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_1_T_493 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_1_T_494 = or(_ram_1_T_490, _ram_1_T_491) node _ram_1_T_495 = or(_ram_1_T_494, _ram_1_T_492) node _ram_1_T_496 = or(_ram_1_T_495, _ram_1_T_493) wire _ram_1_WIRE_79 : UInt<1> connect _ram_1_WIRE_79, _ram_1_T_496 connect _ram_1_WIRE_65.ren2, _ram_1_WIRE_79 node _ram_1_T_497 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_1_T_498 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_1_T_499 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_1_T_500 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_1_T_501 = or(_ram_1_T_497, _ram_1_T_498) node _ram_1_T_502 = or(_ram_1_T_501, _ram_1_T_499) node _ram_1_T_503 = or(_ram_1_T_502, _ram_1_T_500) wire _ram_1_WIRE_80 : UInt<1> connect _ram_1_WIRE_80, _ram_1_T_503 connect _ram_1_WIRE_65.ren1, _ram_1_WIRE_80 node _ram_1_T_504 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_1_T_505 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_1_T_506 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_1_T_507 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_1_T_508 = or(_ram_1_T_504, _ram_1_T_505) node _ram_1_T_509 = or(_ram_1_T_508, _ram_1_T_506) node _ram_1_T_510 = or(_ram_1_T_509, _ram_1_T_507) wire _ram_1_WIRE_81 : UInt<1> connect _ram_1_WIRE_81, _ram_1_T_510 connect _ram_1_WIRE_65.wen, _ram_1_WIRE_81 node _ram_1_T_511 = mux(write_mask[1][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_1_T_512 = mux(write_mask[1][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_1_T_513 = mux(write_mask[1][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_1_T_514 = mux(write_mask[1][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_1_T_515 = or(_ram_1_T_511, _ram_1_T_512) node _ram_1_T_516 = or(_ram_1_T_515, _ram_1_T_513) node _ram_1_T_517 = or(_ram_1_T_516, _ram_1_T_514) wire _ram_1_WIRE_82 : UInt<1> connect _ram_1_WIRE_82, _ram_1_T_517 connect _ram_1_WIRE_65.ldst, _ram_1_WIRE_82 connect _ram_1_WIRE_1.fp_ctrl, _ram_1_WIRE_65 wire _ram_1_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_1_T_518 = mux(write_mask[1][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_1_T_519 = mux(write_mask[1][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_1_T_520 = mux(write_mask[1][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_1_T_521 = mux(write_mask[1][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_1_T_522 = or(_ram_1_T_518, _ram_1_T_519) node _ram_1_T_523 = or(_ram_1_T_522, _ram_1_T_520) node _ram_1_T_524 = or(_ram_1_T_523, _ram_1_T_521) wire _ram_1_WIRE_84 : UInt<1> connect _ram_1_WIRE_84, _ram_1_T_524 connect _ram_1_WIRE_83.vec, _ram_1_WIRE_84 node _ram_1_T_525 = mux(write_mask[1][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_1_T_526 = mux(write_mask[1][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_1_T_527 = mux(write_mask[1][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_1_T_528 = mux(write_mask[1][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_1_T_529 = or(_ram_1_T_525, _ram_1_T_526) node _ram_1_T_530 = or(_ram_1_T_529, _ram_1_T_527) node _ram_1_T_531 = or(_ram_1_T_530, _ram_1_T_528) wire _ram_1_WIRE_85 : UInt<1> connect _ram_1_WIRE_85, _ram_1_T_531 connect _ram_1_WIRE_83.dp, _ram_1_WIRE_85 node _ram_1_T_532 = mux(write_mask[1][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_1_T_533 = mux(write_mask[1][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_1_T_534 = mux(write_mask[1][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_1_T_535 = mux(write_mask[1][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_1_T_536 = or(_ram_1_T_532, _ram_1_T_533) node _ram_1_T_537 = or(_ram_1_T_536, _ram_1_T_534) node _ram_1_T_538 = or(_ram_1_T_537, _ram_1_T_535) wire _ram_1_WIRE_86 : UInt<1> connect _ram_1_WIRE_86, _ram_1_T_538 connect _ram_1_WIRE_83.amo, _ram_1_WIRE_86 node _ram_1_T_539 = mux(write_mask[1][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_1_T_540 = mux(write_mask[1][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_1_T_541 = mux(write_mask[1][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_1_T_542 = mux(write_mask[1][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_1_T_543 = or(_ram_1_T_539, _ram_1_T_540) node _ram_1_T_544 = or(_ram_1_T_543, _ram_1_T_541) node _ram_1_T_545 = or(_ram_1_T_544, _ram_1_T_542) wire _ram_1_WIRE_87 : UInt<1> connect _ram_1_WIRE_87, _ram_1_T_545 connect _ram_1_WIRE_83.fence, _ram_1_WIRE_87 node _ram_1_T_546 = mux(write_mask[1][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_1_T_547 = mux(write_mask[1][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_1_T_548 = mux(write_mask[1][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_1_T_549 = mux(write_mask[1][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_1_T_550 = or(_ram_1_T_546, _ram_1_T_547) node _ram_1_T_551 = or(_ram_1_T_550, _ram_1_T_548) node _ram_1_T_552 = or(_ram_1_T_551, _ram_1_T_549) wire _ram_1_WIRE_88 : UInt<1> connect _ram_1_WIRE_88, _ram_1_T_552 connect _ram_1_WIRE_83.fence_i, _ram_1_WIRE_88 node _ram_1_T_553 = mux(write_mask[1][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_1_T_554 = mux(write_mask[1][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_1_T_555 = mux(write_mask[1][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_1_T_556 = mux(write_mask[1][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_1_T_557 = or(_ram_1_T_553, _ram_1_T_554) node _ram_1_T_558 = or(_ram_1_T_557, _ram_1_T_555) node _ram_1_T_559 = or(_ram_1_T_558, _ram_1_T_556) wire _ram_1_WIRE_89 : UInt<3> connect _ram_1_WIRE_89, _ram_1_T_559 connect _ram_1_WIRE_83.csr, _ram_1_WIRE_89 node _ram_1_T_560 = mux(write_mask[1][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_1_T_561 = mux(write_mask[1][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_1_T_562 = mux(write_mask[1][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_1_T_563 = mux(write_mask[1][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_1_T_564 = or(_ram_1_T_560, _ram_1_T_561) node _ram_1_T_565 = or(_ram_1_T_564, _ram_1_T_562) node _ram_1_T_566 = or(_ram_1_T_565, _ram_1_T_563) wire _ram_1_WIRE_90 : UInt<1> connect _ram_1_WIRE_90, _ram_1_T_566 connect _ram_1_WIRE_83.wxd, _ram_1_WIRE_90 node _ram_1_T_567 = mux(write_mask[1][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_1_T_568 = mux(write_mask[1][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_1_T_569 = mux(write_mask[1][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_1_T_570 = mux(write_mask[1][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_1_T_571 = or(_ram_1_T_567, _ram_1_T_568) node _ram_1_T_572 = or(_ram_1_T_571, _ram_1_T_569) node _ram_1_T_573 = or(_ram_1_T_572, _ram_1_T_570) wire _ram_1_WIRE_91 : UInt<1> connect _ram_1_WIRE_91, _ram_1_T_573 connect _ram_1_WIRE_83.div, _ram_1_WIRE_91 node _ram_1_T_574 = mux(write_mask[1][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_1_T_575 = mux(write_mask[1][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_1_T_576 = mux(write_mask[1][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_1_T_577 = mux(write_mask[1][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_1_T_578 = or(_ram_1_T_574, _ram_1_T_575) node _ram_1_T_579 = or(_ram_1_T_578, _ram_1_T_576) node _ram_1_T_580 = or(_ram_1_T_579, _ram_1_T_577) wire _ram_1_WIRE_92 : UInt<1> connect _ram_1_WIRE_92, _ram_1_T_580 connect _ram_1_WIRE_83.mul, _ram_1_WIRE_92 node _ram_1_T_581 = mux(write_mask[1][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_1_T_582 = mux(write_mask[1][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_1_T_583 = mux(write_mask[1][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_1_T_584 = mux(write_mask[1][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_1_T_585 = or(_ram_1_T_581, _ram_1_T_582) node _ram_1_T_586 = or(_ram_1_T_585, _ram_1_T_583) node _ram_1_T_587 = or(_ram_1_T_586, _ram_1_T_584) wire _ram_1_WIRE_93 : UInt<1> connect _ram_1_WIRE_93, _ram_1_T_587 connect _ram_1_WIRE_83.wfd, _ram_1_WIRE_93 node _ram_1_T_588 = mux(write_mask[1][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_1_T_589 = mux(write_mask[1][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_1_T_590 = mux(write_mask[1][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_1_T_591 = mux(write_mask[1][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_1_T_592 = or(_ram_1_T_588, _ram_1_T_589) node _ram_1_T_593 = or(_ram_1_T_592, _ram_1_T_590) node _ram_1_T_594 = or(_ram_1_T_593, _ram_1_T_591) wire _ram_1_WIRE_94 : UInt<1> connect _ram_1_WIRE_94, _ram_1_T_594 connect _ram_1_WIRE_83.rfs3, _ram_1_WIRE_94 node _ram_1_T_595 = mux(write_mask[1][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_1_T_596 = mux(write_mask[1][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_1_T_597 = mux(write_mask[1][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_1_T_598 = mux(write_mask[1][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_1_T_599 = or(_ram_1_T_595, _ram_1_T_596) node _ram_1_T_600 = or(_ram_1_T_599, _ram_1_T_597) node _ram_1_T_601 = or(_ram_1_T_600, _ram_1_T_598) wire _ram_1_WIRE_95 : UInt<1> connect _ram_1_WIRE_95, _ram_1_T_601 connect _ram_1_WIRE_83.rfs2, _ram_1_WIRE_95 node _ram_1_T_602 = mux(write_mask[1][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_1_T_603 = mux(write_mask[1][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_1_T_604 = mux(write_mask[1][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_1_T_605 = mux(write_mask[1][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_1_T_606 = or(_ram_1_T_602, _ram_1_T_603) node _ram_1_T_607 = or(_ram_1_T_606, _ram_1_T_604) node _ram_1_T_608 = or(_ram_1_T_607, _ram_1_T_605) wire _ram_1_WIRE_96 : UInt<1> connect _ram_1_WIRE_96, _ram_1_T_608 connect _ram_1_WIRE_83.rfs1, _ram_1_WIRE_96 node _ram_1_T_609 = mux(write_mask[1][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_1_T_610 = mux(write_mask[1][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_1_T_611 = mux(write_mask[1][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_1_T_612 = mux(write_mask[1][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_1_T_613 = or(_ram_1_T_609, _ram_1_T_610) node _ram_1_T_614 = or(_ram_1_T_613, _ram_1_T_611) node _ram_1_T_615 = or(_ram_1_T_614, _ram_1_T_612) wire _ram_1_WIRE_97 : UInt<5> connect _ram_1_WIRE_97, _ram_1_T_615 connect _ram_1_WIRE_83.mem_cmd, _ram_1_WIRE_97 node _ram_1_T_616 = mux(write_mask[1][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_1_T_617 = mux(write_mask[1][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_1_T_618 = mux(write_mask[1][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_1_T_619 = mux(write_mask[1][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_1_T_620 = or(_ram_1_T_616, _ram_1_T_617) node _ram_1_T_621 = or(_ram_1_T_620, _ram_1_T_618) node _ram_1_T_622 = or(_ram_1_T_621, _ram_1_T_619) wire _ram_1_WIRE_98 : UInt<1> connect _ram_1_WIRE_98, _ram_1_T_622 connect _ram_1_WIRE_83.mem, _ram_1_WIRE_98 node _ram_1_T_623 = mux(write_mask[1][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_1_T_624 = mux(write_mask[1][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_1_T_625 = mux(write_mask[1][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_1_T_626 = mux(write_mask[1][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_1_T_627 = or(_ram_1_T_623, _ram_1_T_624) node _ram_1_T_628 = or(_ram_1_T_627, _ram_1_T_625) node _ram_1_T_629 = or(_ram_1_T_628, _ram_1_T_626) wire _ram_1_WIRE_99 : UInt<5> connect _ram_1_WIRE_99, _ram_1_T_629 connect _ram_1_WIRE_83.alu_fn, _ram_1_WIRE_99 node _ram_1_T_630 = mux(write_mask[1][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_1_T_631 = mux(write_mask[1][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_1_T_632 = mux(write_mask[1][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_1_T_633 = mux(write_mask[1][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_1_T_634 = or(_ram_1_T_630, _ram_1_T_631) node _ram_1_T_635 = or(_ram_1_T_634, _ram_1_T_632) node _ram_1_T_636 = or(_ram_1_T_635, _ram_1_T_633) wire _ram_1_WIRE_100 : UInt<1> connect _ram_1_WIRE_100, _ram_1_T_636 connect _ram_1_WIRE_83.alu_dw, _ram_1_WIRE_100 node _ram_1_T_637 = mux(write_mask[1][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_1_T_638 = mux(write_mask[1][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_1_T_639 = mux(write_mask[1][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_1_T_640 = mux(write_mask[1][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_1_T_641 = or(_ram_1_T_637, _ram_1_T_638) node _ram_1_T_642 = or(_ram_1_T_641, _ram_1_T_639) node _ram_1_T_643 = or(_ram_1_T_642, _ram_1_T_640) wire _ram_1_WIRE_101 : UInt<3> connect _ram_1_WIRE_101, _ram_1_T_643 connect _ram_1_WIRE_83.sel_imm, _ram_1_WIRE_101 node _ram_1_T_644 = mux(write_mask[1][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_1_T_645 = mux(write_mask[1][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_1_T_646 = mux(write_mask[1][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_1_T_647 = mux(write_mask[1][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_1_T_648 = or(_ram_1_T_644, _ram_1_T_645) node _ram_1_T_649 = or(_ram_1_T_648, _ram_1_T_646) node _ram_1_T_650 = or(_ram_1_T_649, _ram_1_T_647) wire _ram_1_WIRE_102 : UInt<2> connect _ram_1_WIRE_102, _ram_1_T_650 connect _ram_1_WIRE_83.sel_alu1, _ram_1_WIRE_102 node _ram_1_T_651 = mux(write_mask[1][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_1_T_652 = mux(write_mask[1][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_1_T_653 = mux(write_mask[1][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_1_T_654 = mux(write_mask[1][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_1_T_655 = or(_ram_1_T_651, _ram_1_T_652) node _ram_1_T_656 = or(_ram_1_T_655, _ram_1_T_653) node _ram_1_T_657 = or(_ram_1_T_656, _ram_1_T_654) wire _ram_1_WIRE_103 : UInt<3> connect _ram_1_WIRE_103, _ram_1_T_657 connect _ram_1_WIRE_83.sel_alu2, _ram_1_WIRE_103 node _ram_1_T_658 = mux(write_mask[1][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_1_T_659 = mux(write_mask[1][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_1_T_660 = mux(write_mask[1][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_1_T_661 = mux(write_mask[1][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_1_T_662 = or(_ram_1_T_658, _ram_1_T_659) node _ram_1_T_663 = or(_ram_1_T_662, _ram_1_T_660) node _ram_1_T_664 = or(_ram_1_T_663, _ram_1_T_661) wire _ram_1_WIRE_104 : UInt<1> connect _ram_1_WIRE_104, _ram_1_T_664 connect _ram_1_WIRE_83.rxs1, _ram_1_WIRE_104 node _ram_1_T_665 = mux(write_mask[1][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_1_T_666 = mux(write_mask[1][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_1_T_667 = mux(write_mask[1][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_1_T_668 = mux(write_mask[1][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_1_T_669 = or(_ram_1_T_665, _ram_1_T_666) node _ram_1_T_670 = or(_ram_1_T_669, _ram_1_T_667) node _ram_1_T_671 = or(_ram_1_T_670, _ram_1_T_668) wire _ram_1_WIRE_105 : UInt<1> connect _ram_1_WIRE_105, _ram_1_T_671 connect _ram_1_WIRE_83.rxs2, _ram_1_WIRE_105 node _ram_1_T_672 = mux(write_mask[1][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_1_T_673 = mux(write_mask[1][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_1_T_674 = mux(write_mask[1][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_1_T_675 = mux(write_mask[1][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_1_T_676 = or(_ram_1_T_672, _ram_1_T_673) node _ram_1_T_677 = or(_ram_1_T_676, _ram_1_T_674) node _ram_1_T_678 = or(_ram_1_T_677, _ram_1_T_675) wire _ram_1_WIRE_106 : UInt<1> connect _ram_1_WIRE_106, _ram_1_T_678 connect _ram_1_WIRE_83.jalr, _ram_1_WIRE_106 node _ram_1_T_679 = mux(write_mask[1][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_1_T_680 = mux(write_mask[1][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_1_T_681 = mux(write_mask[1][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_1_T_682 = mux(write_mask[1][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_1_T_683 = or(_ram_1_T_679, _ram_1_T_680) node _ram_1_T_684 = or(_ram_1_T_683, _ram_1_T_681) node _ram_1_T_685 = or(_ram_1_T_684, _ram_1_T_682) wire _ram_1_WIRE_107 : UInt<1> connect _ram_1_WIRE_107, _ram_1_T_685 connect _ram_1_WIRE_83.jal, _ram_1_WIRE_107 node _ram_1_T_686 = mux(write_mask[1][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_1_T_687 = mux(write_mask[1][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_1_T_688 = mux(write_mask[1][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_1_T_689 = mux(write_mask[1][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_1_T_690 = or(_ram_1_T_686, _ram_1_T_687) node _ram_1_T_691 = or(_ram_1_T_690, _ram_1_T_688) node _ram_1_T_692 = or(_ram_1_T_691, _ram_1_T_689) wire _ram_1_WIRE_108 : UInt<1> connect _ram_1_WIRE_108, _ram_1_T_692 connect _ram_1_WIRE_83.branch, _ram_1_WIRE_108 node _ram_1_T_693 = mux(write_mask[1][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_1_T_694 = mux(write_mask[1][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_1_T_695 = mux(write_mask[1][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_1_T_696 = mux(write_mask[1][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_1_T_697 = or(_ram_1_T_693, _ram_1_T_694) node _ram_1_T_698 = or(_ram_1_T_697, _ram_1_T_695) node _ram_1_T_699 = or(_ram_1_T_698, _ram_1_T_696) wire _ram_1_WIRE_109 : UInt<1> connect _ram_1_WIRE_109, _ram_1_T_699 connect _ram_1_WIRE_83.rocc, _ram_1_WIRE_109 node _ram_1_T_700 = mux(write_mask[1][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_1_T_701 = mux(write_mask[1][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_1_T_702 = mux(write_mask[1][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_1_T_703 = mux(write_mask[1][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_1_T_704 = or(_ram_1_T_700, _ram_1_T_701) node _ram_1_T_705 = or(_ram_1_T_704, _ram_1_T_702) node _ram_1_T_706 = or(_ram_1_T_705, _ram_1_T_703) wire _ram_1_WIRE_110 : UInt<1> connect _ram_1_WIRE_110, _ram_1_T_706 connect _ram_1_WIRE_83.fp, _ram_1_WIRE_110 node _ram_1_T_707 = mux(write_mask[1][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_1_T_708 = mux(write_mask[1][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_1_T_709 = mux(write_mask[1][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_1_T_710 = mux(write_mask[1][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_1_T_711 = or(_ram_1_T_707, _ram_1_T_708) node _ram_1_T_712 = or(_ram_1_T_711, _ram_1_T_709) node _ram_1_T_713 = or(_ram_1_T_712, _ram_1_T_710) wire _ram_1_WIRE_111 : UInt<1> connect _ram_1_WIRE_111, _ram_1_T_713 connect _ram_1_WIRE_83.legal, _ram_1_WIRE_111 connect _ram_1_WIRE_1.ctrl, _ram_1_WIRE_83 node _ram_1_T_714 = mux(write_mask[1][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_1_T_715 = mux(write_mask[1][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_1_T_716 = mux(write_mask[1][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_1_T_717 = mux(write_mask[1][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_1_T_718 = or(_ram_1_T_714, _ram_1_T_715) node _ram_1_T_719 = or(_ram_1_T_718, _ram_1_T_716) node _ram_1_T_720 = or(_ram_1_T_719, _ram_1_T_717) wire _ram_1_WIRE_112 : UInt<1> connect _ram_1_WIRE_112, _ram_1_T_720 connect _ram_1_WIRE_1.edge_inst, _ram_1_WIRE_112 node _ram_1_T_721 = mux(write_mask[1][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_1_T_722 = mux(write_mask[1][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_1_T_723 = mux(write_mask[1][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_1_T_724 = mux(write_mask[1][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_1_T_725 = or(_ram_1_T_721, _ram_1_T_722) node _ram_1_T_726 = or(_ram_1_T_725, _ram_1_T_723) node _ram_1_T_727 = or(_ram_1_T_726, _ram_1_T_724) wire _ram_1_WIRE_113 : UInt<40> connect _ram_1_WIRE_113, _ram_1_T_727 connect _ram_1_WIRE_1.pc, _ram_1_WIRE_113 node _ram_1_T_728 = mux(write_mask[1][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_1_T_729 = mux(write_mask[1][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_1_T_730 = mux(write_mask[1][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_1_T_731 = mux(write_mask[1][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_1_T_732 = or(_ram_1_T_728, _ram_1_T_729) node _ram_1_T_733 = or(_ram_1_T_732, _ram_1_T_730) node _ram_1_T_734 = or(_ram_1_T_733, _ram_1_T_731) wire _ram_1_WIRE_114 : UInt<32> connect _ram_1_WIRE_114, _ram_1_T_734 connect _ram_1_WIRE_1.raw_inst, _ram_1_WIRE_114 node _ram_1_T_735 = mux(write_mask[1][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_1_T_736 = mux(write_mask[1][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_1_T_737 = mux(write_mask[1][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_1_T_738 = mux(write_mask[1][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_1_T_739 = or(_ram_1_T_735, _ram_1_T_736) node _ram_1_T_740 = or(_ram_1_T_739, _ram_1_T_737) node _ram_1_T_741 = or(_ram_1_T_740, _ram_1_T_738) wire _ram_1_WIRE_115 : UInt<32> connect _ram_1_WIRE_115, _ram_1_T_741 connect _ram_1_WIRE_1.inst, _ram_1_WIRE_115 connect _ram_1_WIRE.bits, _ram_1_WIRE_1 node _ram_1_T_742 = mux(write_mask[1][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_1_T_743 = mux(write_mask[1][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_1_T_744 = mux(write_mask[1][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_1_T_745 = mux(write_mask[1][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_1_T_746 = or(_ram_1_T_742, _ram_1_T_743) node _ram_1_T_747 = or(_ram_1_T_746, _ram_1_T_744) node _ram_1_T_748 = or(_ram_1_T_747, _ram_1_T_745) wire _ram_1_WIRE_116 : UInt<1> connect _ram_1_WIRE_116, _ram_1_T_748 connect _ram_1_WIRE.valid, _ram_1_WIRE_116 connect ram[1], _ram_1_WIRE node _T_23 = eq(ram[2].valid, UInt<1>(0h0)) when _T_23 : wire _ram_2_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_2_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_2_T = mux(write_mask[2][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_2_T_1 = mux(write_mask[2][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_2_T_2 = mux(write_mask[2][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_2_T_3 = mux(write_mask[2][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_2_T_4 = or(_ram_2_T, _ram_2_T_1) node _ram_2_T_5 = or(_ram_2_T_4, _ram_2_T_2) node _ram_2_T_6 = or(_ram_2_T_5, _ram_2_T_3) wire _ram_2_WIRE_2 : UInt<1> connect _ram_2_WIRE_2, _ram_2_T_6 connect _ram_2_WIRE_1.flush_pipe, _ram_2_WIRE_2 node _ram_2_T_7 = mux(write_mask[2][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_2_T_8 = mux(write_mask[2][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_2_T_9 = mux(write_mask[2][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_2_T_10 = mux(write_mask[2][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_2_T_11 = or(_ram_2_T_7, _ram_2_T_8) node _ram_2_T_12 = or(_ram_2_T_11, _ram_2_T_9) node _ram_2_T_13 = or(_ram_2_T_12, _ram_2_T_10) wire _ram_2_WIRE_3 : UInt<2> connect _ram_2_WIRE_3, _ram_2_T_13 connect _ram_2_WIRE_1.mem_size, _ram_2_WIRE_3 wire _ram_2_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_2_T_14 = mux(write_mask[2][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_2_T_15 = mux(write_mask[2][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_2_T_16 = mux(write_mask[2][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_2_T_17 = mux(write_mask[2][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_2_T_18 = or(_ram_2_T_14, _ram_2_T_15) node _ram_2_T_19 = or(_ram_2_T_18, _ram_2_T_16) node _ram_2_T_20 = or(_ram_2_T_19, _ram_2_T_17) wire _ram_2_WIRE_5 : UInt<65> connect _ram_2_WIRE_5, _ram_2_T_20 connect _ram_2_WIRE_4.in3, _ram_2_WIRE_5 node _ram_2_T_21 = mux(write_mask[2][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_2_T_22 = mux(write_mask[2][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_2_T_23 = mux(write_mask[2][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_2_T_24 = mux(write_mask[2][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_2_T_25 = or(_ram_2_T_21, _ram_2_T_22) node _ram_2_T_26 = or(_ram_2_T_25, _ram_2_T_23) node _ram_2_T_27 = or(_ram_2_T_26, _ram_2_T_24) wire _ram_2_WIRE_6 : UInt<65> connect _ram_2_WIRE_6, _ram_2_T_27 connect _ram_2_WIRE_4.in2, _ram_2_WIRE_6 node _ram_2_T_28 = mux(write_mask[2][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_2_T_29 = mux(write_mask[2][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_2_T_30 = mux(write_mask[2][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_2_T_31 = mux(write_mask[2][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_2_T_32 = or(_ram_2_T_28, _ram_2_T_29) node _ram_2_T_33 = or(_ram_2_T_32, _ram_2_T_30) node _ram_2_T_34 = or(_ram_2_T_33, _ram_2_T_31) wire _ram_2_WIRE_7 : UInt<65> connect _ram_2_WIRE_7, _ram_2_T_34 connect _ram_2_WIRE_4.in1, _ram_2_WIRE_7 node _ram_2_T_35 = mux(write_mask[2][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_2_T_36 = mux(write_mask[2][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_2_T_37 = mux(write_mask[2][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_2_T_38 = mux(write_mask[2][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_2_T_39 = or(_ram_2_T_35, _ram_2_T_36) node _ram_2_T_40 = or(_ram_2_T_39, _ram_2_T_37) node _ram_2_T_41 = or(_ram_2_T_40, _ram_2_T_38) wire _ram_2_WIRE_8 : UInt<2> connect _ram_2_WIRE_8, _ram_2_T_41 connect _ram_2_WIRE_4.fmt, _ram_2_WIRE_8 node _ram_2_T_42 = mux(write_mask[2][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_2_T_43 = mux(write_mask[2][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_2_T_44 = mux(write_mask[2][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_2_T_45 = mux(write_mask[2][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_2_T_46 = or(_ram_2_T_42, _ram_2_T_43) node _ram_2_T_47 = or(_ram_2_T_46, _ram_2_T_44) node _ram_2_T_48 = or(_ram_2_T_47, _ram_2_T_45) wire _ram_2_WIRE_9 : UInt<2> connect _ram_2_WIRE_9, _ram_2_T_48 connect _ram_2_WIRE_4.typ, _ram_2_WIRE_9 node _ram_2_T_49 = mux(write_mask[2][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_2_T_50 = mux(write_mask[2][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_2_T_51 = mux(write_mask[2][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_2_T_52 = mux(write_mask[2][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_2_T_53 = or(_ram_2_T_49, _ram_2_T_50) node _ram_2_T_54 = or(_ram_2_T_53, _ram_2_T_51) node _ram_2_T_55 = or(_ram_2_T_54, _ram_2_T_52) wire _ram_2_WIRE_10 : UInt<2> connect _ram_2_WIRE_10, _ram_2_T_55 connect _ram_2_WIRE_4.fmaCmd, _ram_2_WIRE_10 node _ram_2_T_56 = mux(write_mask[2][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_2_T_57 = mux(write_mask[2][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_2_T_58 = mux(write_mask[2][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_2_T_59 = mux(write_mask[2][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_2_T_60 = or(_ram_2_T_56, _ram_2_T_57) node _ram_2_T_61 = or(_ram_2_T_60, _ram_2_T_58) node _ram_2_T_62 = or(_ram_2_T_61, _ram_2_T_59) wire _ram_2_WIRE_11 : UInt<3> connect _ram_2_WIRE_11, _ram_2_T_62 connect _ram_2_WIRE_4.rm, _ram_2_WIRE_11 node _ram_2_T_63 = mux(write_mask[2][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_2_T_64 = mux(write_mask[2][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_2_T_65 = mux(write_mask[2][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_2_T_66 = mux(write_mask[2][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_2_T_67 = or(_ram_2_T_63, _ram_2_T_64) node _ram_2_T_68 = or(_ram_2_T_67, _ram_2_T_65) node _ram_2_T_69 = or(_ram_2_T_68, _ram_2_T_66) wire _ram_2_WIRE_12 : UInt<1> connect _ram_2_WIRE_12, _ram_2_T_69 connect _ram_2_WIRE_4.vec, _ram_2_WIRE_12 node _ram_2_T_70 = mux(write_mask[2][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_2_T_71 = mux(write_mask[2][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_2_T_72 = mux(write_mask[2][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_2_T_73 = mux(write_mask[2][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_2_T_74 = or(_ram_2_T_70, _ram_2_T_71) node _ram_2_T_75 = or(_ram_2_T_74, _ram_2_T_72) node _ram_2_T_76 = or(_ram_2_T_75, _ram_2_T_73) wire _ram_2_WIRE_13 : UInt<1> connect _ram_2_WIRE_13, _ram_2_T_76 connect _ram_2_WIRE_4.wflags, _ram_2_WIRE_13 node _ram_2_T_77 = mux(write_mask[2][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_2_T_78 = mux(write_mask[2][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_2_T_79 = mux(write_mask[2][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_2_T_80 = mux(write_mask[2][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_2_T_81 = or(_ram_2_T_77, _ram_2_T_78) node _ram_2_T_82 = or(_ram_2_T_81, _ram_2_T_79) node _ram_2_T_83 = or(_ram_2_T_82, _ram_2_T_80) wire _ram_2_WIRE_14 : UInt<1> connect _ram_2_WIRE_14, _ram_2_T_83 connect _ram_2_WIRE_4.sqrt, _ram_2_WIRE_14 node _ram_2_T_84 = mux(write_mask[2][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_2_T_85 = mux(write_mask[2][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_2_T_86 = mux(write_mask[2][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_2_T_87 = mux(write_mask[2][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_2_T_88 = or(_ram_2_T_84, _ram_2_T_85) node _ram_2_T_89 = or(_ram_2_T_88, _ram_2_T_86) node _ram_2_T_90 = or(_ram_2_T_89, _ram_2_T_87) wire _ram_2_WIRE_15 : UInt<1> connect _ram_2_WIRE_15, _ram_2_T_90 connect _ram_2_WIRE_4.div, _ram_2_WIRE_15 node _ram_2_T_91 = mux(write_mask[2][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_2_T_92 = mux(write_mask[2][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_2_T_93 = mux(write_mask[2][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_2_T_94 = mux(write_mask[2][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_2_T_95 = or(_ram_2_T_91, _ram_2_T_92) node _ram_2_T_96 = or(_ram_2_T_95, _ram_2_T_93) node _ram_2_T_97 = or(_ram_2_T_96, _ram_2_T_94) wire _ram_2_WIRE_16 : UInt<1> connect _ram_2_WIRE_16, _ram_2_T_97 connect _ram_2_WIRE_4.fma, _ram_2_WIRE_16 node _ram_2_T_98 = mux(write_mask[2][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_2_T_99 = mux(write_mask[2][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_2_T_100 = mux(write_mask[2][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_2_T_101 = mux(write_mask[2][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_2_T_102 = or(_ram_2_T_98, _ram_2_T_99) node _ram_2_T_103 = or(_ram_2_T_102, _ram_2_T_100) node _ram_2_T_104 = or(_ram_2_T_103, _ram_2_T_101) wire _ram_2_WIRE_17 : UInt<1> connect _ram_2_WIRE_17, _ram_2_T_104 connect _ram_2_WIRE_4.fastpipe, _ram_2_WIRE_17 node _ram_2_T_105 = mux(write_mask[2][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_2_T_106 = mux(write_mask[2][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_2_T_107 = mux(write_mask[2][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_2_T_108 = mux(write_mask[2][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_2_T_109 = or(_ram_2_T_105, _ram_2_T_106) node _ram_2_T_110 = or(_ram_2_T_109, _ram_2_T_107) node _ram_2_T_111 = or(_ram_2_T_110, _ram_2_T_108) wire _ram_2_WIRE_18 : UInt<1> connect _ram_2_WIRE_18, _ram_2_T_111 connect _ram_2_WIRE_4.toint, _ram_2_WIRE_18 node _ram_2_T_112 = mux(write_mask[2][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_2_T_113 = mux(write_mask[2][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_2_T_114 = mux(write_mask[2][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_2_T_115 = mux(write_mask[2][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_2_T_116 = or(_ram_2_T_112, _ram_2_T_113) node _ram_2_T_117 = or(_ram_2_T_116, _ram_2_T_114) node _ram_2_T_118 = or(_ram_2_T_117, _ram_2_T_115) wire _ram_2_WIRE_19 : UInt<1> connect _ram_2_WIRE_19, _ram_2_T_118 connect _ram_2_WIRE_4.fromint, _ram_2_WIRE_19 node _ram_2_T_119 = mux(write_mask[2][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_2_T_120 = mux(write_mask[2][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_2_T_121 = mux(write_mask[2][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_2_T_122 = mux(write_mask[2][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_2_T_123 = or(_ram_2_T_119, _ram_2_T_120) node _ram_2_T_124 = or(_ram_2_T_123, _ram_2_T_121) node _ram_2_T_125 = or(_ram_2_T_124, _ram_2_T_122) wire _ram_2_WIRE_20 : UInt<2> connect _ram_2_WIRE_20, _ram_2_T_125 connect _ram_2_WIRE_4.typeTagOut, _ram_2_WIRE_20 node _ram_2_T_126 = mux(write_mask[2][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_2_T_127 = mux(write_mask[2][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_2_T_128 = mux(write_mask[2][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_2_T_129 = mux(write_mask[2][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_2_T_130 = or(_ram_2_T_126, _ram_2_T_127) node _ram_2_T_131 = or(_ram_2_T_130, _ram_2_T_128) node _ram_2_T_132 = or(_ram_2_T_131, _ram_2_T_129) wire _ram_2_WIRE_21 : UInt<2> connect _ram_2_WIRE_21, _ram_2_T_132 connect _ram_2_WIRE_4.typeTagIn, _ram_2_WIRE_21 node _ram_2_T_133 = mux(write_mask[2][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_2_T_134 = mux(write_mask[2][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_2_T_135 = mux(write_mask[2][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_2_T_136 = mux(write_mask[2][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_2_T_137 = or(_ram_2_T_133, _ram_2_T_134) node _ram_2_T_138 = or(_ram_2_T_137, _ram_2_T_135) node _ram_2_T_139 = or(_ram_2_T_138, _ram_2_T_136) wire _ram_2_WIRE_22 : UInt<1> connect _ram_2_WIRE_22, _ram_2_T_139 connect _ram_2_WIRE_4.swap23, _ram_2_WIRE_22 node _ram_2_T_140 = mux(write_mask[2][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_2_T_141 = mux(write_mask[2][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_2_T_142 = mux(write_mask[2][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_2_T_143 = mux(write_mask[2][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_2_T_144 = or(_ram_2_T_140, _ram_2_T_141) node _ram_2_T_145 = or(_ram_2_T_144, _ram_2_T_142) node _ram_2_T_146 = or(_ram_2_T_145, _ram_2_T_143) wire _ram_2_WIRE_23 : UInt<1> connect _ram_2_WIRE_23, _ram_2_T_146 connect _ram_2_WIRE_4.swap12, _ram_2_WIRE_23 node _ram_2_T_147 = mux(write_mask[2][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_2_T_148 = mux(write_mask[2][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_2_T_149 = mux(write_mask[2][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_2_T_150 = mux(write_mask[2][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_2_T_151 = or(_ram_2_T_147, _ram_2_T_148) node _ram_2_T_152 = or(_ram_2_T_151, _ram_2_T_149) node _ram_2_T_153 = or(_ram_2_T_152, _ram_2_T_150) wire _ram_2_WIRE_24 : UInt<1> connect _ram_2_WIRE_24, _ram_2_T_153 connect _ram_2_WIRE_4.ren3, _ram_2_WIRE_24 node _ram_2_T_154 = mux(write_mask[2][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_2_T_155 = mux(write_mask[2][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_2_T_156 = mux(write_mask[2][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_2_T_157 = mux(write_mask[2][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_2_T_158 = or(_ram_2_T_154, _ram_2_T_155) node _ram_2_T_159 = or(_ram_2_T_158, _ram_2_T_156) node _ram_2_T_160 = or(_ram_2_T_159, _ram_2_T_157) wire _ram_2_WIRE_25 : UInt<1> connect _ram_2_WIRE_25, _ram_2_T_160 connect _ram_2_WIRE_4.ren2, _ram_2_WIRE_25 node _ram_2_T_161 = mux(write_mask[2][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_2_T_162 = mux(write_mask[2][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_2_T_163 = mux(write_mask[2][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_2_T_164 = mux(write_mask[2][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_2_T_165 = or(_ram_2_T_161, _ram_2_T_162) node _ram_2_T_166 = or(_ram_2_T_165, _ram_2_T_163) node _ram_2_T_167 = or(_ram_2_T_166, _ram_2_T_164) wire _ram_2_WIRE_26 : UInt<1> connect _ram_2_WIRE_26, _ram_2_T_167 connect _ram_2_WIRE_4.ren1, _ram_2_WIRE_26 node _ram_2_T_168 = mux(write_mask[2][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_2_T_169 = mux(write_mask[2][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_2_T_170 = mux(write_mask[2][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_2_T_171 = mux(write_mask[2][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_2_T_172 = or(_ram_2_T_168, _ram_2_T_169) node _ram_2_T_173 = or(_ram_2_T_172, _ram_2_T_170) node _ram_2_T_174 = or(_ram_2_T_173, _ram_2_T_171) wire _ram_2_WIRE_27 : UInt<1> connect _ram_2_WIRE_27, _ram_2_T_174 connect _ram_2_WIRE_4.wen, _ram_2_WIRE_27 node _ram_2_T_175 = mux(write_mask[2][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_2_T_176 = mux(write_mask[2][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_2_T_177 = mux(write_mask[2][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_2_T_178 = mux(write_mask[2][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_2_T_179 = or(_ram_2_T_175, _ram_2_T_176) node _ram_2_T_180 = or(_ram_2_T_179, _ram_2_T_177) node _ram_2_T_181 = or(_ram_2_T_180, _ram_2_T_178) wire _ram_2_WIRE_28 : UInt<1> connect _ram_2_WIRE_28, _ram_2_T_181 connect _ram_2_WIRE_4.ldst, _ram_2_WIRE_28 connect _ram_2_WIRE_1.fdivin, _ram_2_WIRE_4 node _ram_2_T_182 = mux(write_mask[2][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_2_T_183 = mux(write_mask[2][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_2_T_184 = mux(write_mask[2][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_2_T_185 = mux(write_mask[2][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_2_T_186 = or(_ram_2_T_182, _ram_2_T_183) node _ram_2_T_187 = or(_ram_2_T_186, _ram_2_T_184) node _ram_2_T_188 = or(_ram_2_T_187, _ram_2_T_185) wire _ram_2_WIRE_29 : UInt<5> connect _ram_2_WIRE_29, _ram_2_T_188 connect _ram_2_WIRE_1.fexc, _ram_2_WIRE_29 node _ram_2_T_189 = mux(write_mask[2][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_2_T_190 = mux(write_mask[2][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_2_T_191 = mux(write_mask[2][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_2_T_192 = mux(write_mask[2][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_2_T_193 = or(_ram_2_T_189, _ram_2_T_190) node _ram_2_T_194 = or(_ram_2_T_193, _ram_2_T_191) node _ram_2_T_195 = or(_ram_2_T_194, _ram_2_T_192) wire _ram_2_WIRE_30 : UInt<5> connect _ram_2_WIRE_30, _ram_2_T_195 connect _ram_2_WIRE_1.fra3, _ram_2_WIRE_30 node _ram_2_T_196 = mux(write_mask[2][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_2_T_197 = mux(write_mask[2][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_2_T_198 = mux(write_mask[2][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_2_T_199 = mux(write_mask[2][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_2_T_200 = or(_ram_2_T_196, _ram_2_T_197) node _ram_2_T_201 = or(_ram_2_T_200, _ram_2_T_198) node _ram_2_T_202 = or(_ram_2_T_201, _ram_2_T_199) wire _ram_2_WIRE_31 : UInt<5> connect _ram_2_WIRE_31, _ram_2_T_202 connect _ram_2_WIRE_1.fra2, _ram_2_WIRE_31 node _ram_2_T_203 = mux(write_mask[2][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_2_T_204 = mux(write_mask[2][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_2_T_205 = mux(write_mask[2][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_2_T_206 = mux(write_mask[2][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_2_T_207 = or(_ram_2_T_203, _ram_2_T_204) node _ram_2_T_208 = or(_ram_2_T_207, _ram_2_T_205) node _ram_2_T_209 = or(_ram_2_T_208, _ram_2_T_206) wire _ram_2_WIRE_32 : UInt<5> connect _ram_2_WIRE_32, _ram_2_T_209 connect _ram_2_WIRE_1.fra1, _ram_2_WIRE_32 wire _ram_2_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_2_T_210 = mux(write_mask[2][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_2_T_211 = mux(write_mask[2][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_2_T_212 = mux(write_mask[2][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_2_T_213 = mux(write_mask[2][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_2_T_214 = or(_ram_2_T_210, _ram_2_T_211) node _ram_2_T_215 = or(_ram_2_T_214, _ram_2_T_212) node _ram_2_T_216 = or(_ram_2_T_215, _ram_2_T_213) wire _ram_2_WIRE_34 : UInt<64> connect _ram_2_WIRE_34, _ram_2_T_216 connect _ram_2_WIRE_33.bits, _ram_2_WIRE_34 node _ram_2_T_217 = mux(write_mask[2][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_2_T_218 = mux(write_mask[2][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_2_T_219 = mux(write_mask[2][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_2_T_220 = mux(write_mask[2][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_2_T_221 = or(_ram_2_T_217, _ram_2_T_218) node _ram_2_T_222 = or(_ram_2_T_221, _ram_2_T_219) node _ram_2_T_223 = or(_ram_2_T_222, _ram_2_T_220) wire _ram_2_WIRE_35 : UInt<1> connect _ram_2_WIRE_35, _ram_2_T_223 connect _ram_2_WIRE_33.valid, _ram_2_WIRE_35 connect _ram_2_WIRE_1.wdata, _ram_2_WIRE_33 node _ram_2_T_224 = mux(write_mask[2][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_2_T_225 = mux(write_mask[2][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_2_T_226 = mux(write_mask[2][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_2_T_227 = mux(write_mask[2][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_2_T_228 = or(_ram_2_T_224, _ram_2_T_225) node _ram_2_T_229 = or(_ram_2_T_228, _ram_2_T_226) node _ram_2_T_230 = or(_ram_2_T_229, _ram_2_T_227) wire _ram_2_WIRE_36 : UInt<1> connect _ram_2_WIRE_36, _ram_2_T_230 connect _ram_2_WIRE_1.uses_latealu, _ram_2_WIRE_36 node _ram_2_T_231 = mux(write_mask[2][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_2_T_232 = mux(write_mask[2][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_2_T_233 = mux(write_mask[2][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_2_T_234 = mux(write_mask[2][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_2_T_235 = or(_ram_2_T_231, _ram_2_T_232) node _ram_2_T_236 = or(_ram_2_T_235, _ram_2_T_233) node _ram_2_T_237 = or(_ram_2_T_236, _ram_2_T_234) wire _ram_2_WIRE_37 : UInt<1> connect _ram_2_WIRE_37, _ram_2_T_237 connect _ram_2_WIRE_1.uses_memalu, _ram_2_WIRE_37 node _ram_2_T_238 = mux(write_mask[2][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_2_T_239 = mux(write_mask[2][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_2_T_240 = mux(write_mask[2][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_2_T_241 = mux(write_mask[2][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_2_T_242 = or(_ram_2_T_238, _ram_2_T_239) node _ram_2_T_243 = or(_ram_2_T_242, _ram_2_T_240) node _ram_2_T_244 = or(_ram_2_T_243, _ram_2_T_241) wire _ram_2_WIRE_38 : UInt<64> connect _ram_2_WIRE_38, _ram_2_T_244 connect _ram_2_WIRE_1.rs3_data, _ram_2_WIRE_38 node _ram_2_T_245 = mux(write_mask[2][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_2_T_246 = mux(write_mask[2][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_2_T_247 = mux(write_mask[2][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_2_T_248 = mux(write_mask[2][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_2_T_249 = or(_ram_2_T_245, _ram_2_T_246) node _ram_2_T_250 = or(_ram_2_T_249, _ram_2_T_247) node _ram_2_T_251 = or(_ram_2_T_250, _ram_2_T_248) wire _ram_2_WIRE_39 : UInt<64> connect _ram_2_WIRE_39, _ram_2_T_251 connect _ram_2_WIRE_1.rs2_data, _ram_2_WIRE_39 node _ram_2_T_252 = mux(write_mask[2][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_2_T_253 = mux(write_mask[2][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_2_T_254 = mux(write_mask[2][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_2_T_255 = mux(write_mask[2][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_2_T_256 = or(_ram_2_T_252, _ram_2_T_253) node _ram_2_T_257 = or(_ram_2_T_256, _ram_2_T_254) node _ram_2_T_258 = or(_ram_2_T_257, _ram_2_T_255) wire _ram_2_WIRE_40 : UInt<64> connect _ram_2_WIRE_40, _ram_2_T_258 connect _ram_2_WIRE_1.rs1_data, _ram_2_WIRE_40 node _ram_2_T_259 = mux(write_mask[2][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_2_T_260 = mux(write_mask[2][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_2_T_261 = mux(write_mask[2][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_2_T_262 = mux(write_mask[2][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_2_T_263 = or(_ram_2_T_259, _ram_2_T_260) node _ram_2_T_264 = or(_ram_2_T_263, _ram_2_T_261) node _ram_2_T_265 = or(_ram_2_T_264, _ram_2_T_262) wire _ram_2_WIRE_41 : UInt<1> connect _ram_2_WIRE_41, _ram_2_T_265 connect _ram_2_WIRE_1.needs_replay, _ram_2_WIRE_41 node _ram_2_T_266 = mux(write_mask[2][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_2_T_267 = mux(write_mask[2][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_2_T_268 = mux(write_mask[2][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_2_T_269 = mux(write_mask[2][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_2_T_270 = or(_ram_2_T_266, _ram_2_T_267) node _ram_2_T_271 = or(_ram_2_T_270, _ram_2_T_268) node _ram_2_T_272 = or(_ram_2_T_271, _ram_2_T_269) wire _ram_2_WIRE_42 : UInt<64> connect _ram_2_WIRE_42, _ram_2_T_272 connect _ram_2_WIRE_1.xcpt_cause, _ram_2_WIRE_42 node _ram_2_T_273 = mux(write_mask[2][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_2_T_274 = mux(write_mask[2][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_2_T_275 = mux(write_mask[2][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_2_T_276 = mux(write_mask[2][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_2_T_277 = or(_ram_2_T_273, _ram_2_T_274) node _ram_2_T_278 = or(_ram_2_T_277, _ram_2_T_275) node _ram_2_T_279 = or(_ram_2_T_278, _ram_2_T_276) wire _ram_2_WIRE_43 : UInt<1> connect _ram_2_WIRE_43, _ram_2_T_279 connect _ram_2_WIRE_1.xcpt, _ram_2_WIRE_43 node _ram_2_T_280 = mux(write_mask[2][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_2_T_281 = mux(write_mask[2][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_2_T_282 = mux(write_mask[2][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_2_T_283 = mux(write_mask[2][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_2_T_284 = or(_ram_2_T_280, _ram_2_T_281) node _ram_2_T_285 = or(_ram_2_T_284, _ram_2_T_282) node _ram_2_T_286 = or(_ram_2_T_285, _ram_2_T_283) wire _ram_2_WIRE_44 : UInt<1> connect _ram_2_WIRE_44, _ram_2_T_286 connect _ram_2_WIRE_1.taken, _ram_2_WIRE_44 node _ram_2_T_287 = mux(write_mask[2][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_2_T_288 = mux(write_mask[2][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_2_T_289 = mux(write_mask[2][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_2_T_290 = mux(write_mask[2][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_2_T_291 = or(_ram_2_T_287, _ram_2_T_288) node _ram_2_T_292 = or(_ram_2_T_291, _ram_2_T_289) node _ram_2_T_293 = or(_ram_2_T_292, _ram_2_T_290) wire _ram_2_WIRE_45 : UInt<3> connect _ram_2_WIRE_45, _ram_2_T_293 connect _ram_2_WIRE_1.ras_head, _ram_2_WIRE_45 wire _ram_2_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_2_T_294 = mux(write_mask[2][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_2_T_295 = mux(write_mask[2][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_2_T_296 = mux(write_mask[2][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_2_T_297 = mux(write_mask[2][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_2_T_298 = or(_ram_2_T_294, _ram_2_T_295) node _ram_2_T_299 = or(_ram_2_T_298, _ram_2_T_296) node _ram_2_T_300 = or(_ram_2_T_299, _ram_2_T_297) wire _ram_2_WIRE_47 : UInt<40> connect _ram_2_WIRE_47, _ram_2_T_300 connect _ram_2_WIRE_46.bits, _ram_2_WIRE_47 node _ram_2_T_301 = mux(write_mask[2][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_2_T_302 = mux(write_mask[2][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_2_T_303 = mux(write_mask[2][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_2_T_304 = mux(write_mask[2][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_2_T_305 = or(_ram_2_T_301, _ram_2_T_302) node _ram_2_T_306 = or(_ram_2_T_305, _ram_2_T_303) node _ram_2_T_307 = or(_ram_2_T_306, _ram_2_T_304) wire _ram_2_WIRE_48 : UInt<1> connect _ram_2_WIRE_48, _ram_2_T_307 connect _ram_2_WIRE_46.valid, _ram_2_WIRE_48 connect _ram_2_WIRE_1.next_pc, _ram_2_WIRE_46 node _ram_2_T_308 = mux(write_mask[2][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_2_T_309 = mux(write_mask[2][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_2_T_310 = mux(write_mask[2][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_2_T_311 = mux(write_mask[2][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_2_T_312 = or(_ram_2_T_308, _ram_2_T_309) node _ram_2_T_313 = or(_ram_2_T_312, _ram_2_T_310) node _ram_2_T_314 = or(_ram_2_T_313, _ram_2_T_311) wire _ram_2_WIRE_49 : UInt<1> connect _ram_2_WIRE_49, _ram_2_T_314 connect _ram_2_WIRE_1.sfb_shadow, _ram_2_WIRE_49 node _ram_2_T_315 = mux(write_mask[2][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_2_T_316 = mux(write_mask[2][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_2_T_317 = mux(write_mask[2][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_2_T_318 = mux(write_mask[2][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_2_T_319 = or(_ram_2_T_315, _ram_2_T_316) node _ram_2_T_320 = or(_ram_2_T_319, _ram_2_T_317) node _ram_2_T_321 = or(_ram_2_T_320, _ram_2_T_318) wire _ram_2_WIRE_50 : UInt<1> connect _ram_2_WIRE_50, _ram_2_T_321 connect _ram_2_WIRE_1.sfb_br, _ram_2_WIRE_50 wire _ram_2_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_2_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_2_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_2_T_322 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_2_T_323 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_2_T_324 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_2_T_325 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_2_T_326 = or(_ram_2_T_322, _ram_2_T_323) node _ram_2_T_327 = or(_ram_2_T_326, _ram_2_T_324) node _ram_2_T_328 = or(_ram_2_T_327, _ram_2_T_325) wire _ram_2_WIRE_54 : UInt<2> connect _ram_2_WIRE_54, _ram_2_T_328 connect _ram_2_WIRE_53.value, _ram_2_WIRE_54 node _ram_2_T_329 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_2_T_330 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_2_T_331 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_2_T_332 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_2_T_333 = or(_ram_2_T_329, _ram_2_T_330) node _ram_2_T_334 = or(_ram_2_T_333, _ram_2_T_331) node _ram_2_T_335 = or(_ram_2_T_334, _ram_2_T_332) wire _ram_2_WIRE_55 : UInt<8> connect _ram_2_WIRE_55, _ram_2_T_335 connect _ram_2_WIRE_53.history, _ram_2_WIRE_55 connect _ram_2_WIRE_52.bht, _ram_2_WIRE_53 node _ram_2_T_336 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_2_T_337 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_2_T_338 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_2_T_339 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_2_T_340 = or(_ram_2_T_336, _ram_2_T_337) node _ram_2_T_341 = or(_ram_2_T_340, _ram_2_T_338) node _ram_2_T_342 = or(_ram_2_T_341, _ram_2_T_339) wire _ram_2_WIRE_56 : UInt<6> connect _ram_2_WIRE_56, _ram_2_T_342 connect _ram_2_WIRE_52.entry, _ram_2_WIRE_56 node _ram_2_T_343 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_2_T_344 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_2_T_345 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_2_T_346 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_2_T_347 = or(_ram_2_T_343, _ram_2_T_344) node _ram_2_T_348 = or(_ram_2_T_347, _ram_2_T_345) node _ram_2_T_349 = or(_ram_2_T_348, _ram_2_T_346) wire _ram_2_WIRE_57 : UInt<39> connect _ram_2_WIRE_57, _ram_2_T_349 connect _ram_2_WIRE_52.target, _ram_2_WIRE_57 node _ram_2_T_350 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_2_T_351 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_2_T_352 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_2_T_353 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_2_T_354 = or(_ram_2_T_350, _ram_2_T_351) node _ram_2_T_355 = or(_ram_2_T_354, _ram_2_T_352) node _ram_2_T_356 = or(_ram_2_T_355, _ram_2_T_353) wire _ram_2_WIRE_58 : UInt<2> connect _ram_2_WIRE_58, _ram_2_T_356 connect _ram_2_WIRE_52.bridx, _ram_2_WIRE_58 node _ram_2_T_357 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_2_T_358 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_2_T_359 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_2_T_360 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_2_T_361 = or(_ram_2_T_357, _ram_2_T_358) node _ram_2_T_362 = or(_ram_2_T_361, _ram_2_T_359) node _ram_2_T_363 = or(_ram_2_T_362, _ram_2_T_360) wire _ram_2_WIRE_59 : UInt<4> connect _ram_2_WIRE_59, _ram_2_T_363 connect _ram_2_WIRE_52.mask, _ram_2_WIRE_59 node _ram_2_T_364 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_2_T_365 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_2_T_366 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_2_T_367 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_2_T_368 = or(_ram_2_T_364, _ram_2_T_365) node _ram_2_T_369 = or(_ram_2_T_368, _ram_2_T_366) node _ram_2_T_370 = or(_ram_2_T_369, _ram_2_T_367) wire _ram_2_WIRE_60 : UInt<1> connect _ram_2_WIRE_60, _ram_2_T_370 connect _ram_2_WIRE_52.taken, _ram_2_WIRE_60 node _ram_2_T_371 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_2_T_372 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_2_T_373 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_2_T_374 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_2_T_375 = or(_ram_2_T_371, _ram_2_T_372) node _ram_2_T_376 = or(_ram_2_T_375, _ram_2_T_373) node _ram_2_T_377 = or(_ram_2_T_376, _ram_2_T_374) wire _ram_2_WIRE_61 : UInt<2> connect _ram_2_WIRE_61, _ram_2_T_377 connect _ram_2_WIRE_52.cfiType, _ram_2_WIRE_61 connect _ram_2_WIRE_51.bits, _ram_2_WIRE_52 node _ram_2_T_378 = mux(write_mask[2][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_2_T_379 = mux(write_mask[2][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_2_T_380 = mux(write_mask[2][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_2_T_381 = mux(write_mask[2][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_2_T_382 = or(_ram_2_T_378, _ram_2_T_379) node _ram_2_T_383 = or(_ram_2_T_382, _ram_2_T_380) node _ram_2_T_384 = or(_ram_2_T_383, _ram_2_T_381) wire _ram_2_WIRE_62 : UInt<1> connect _ram_2_WIRE_62, _ram_2_T_384 connect _ram_2_WIRE_51.valid, _ram_2_WIRE_62 connect _ram_2_WIRE_1.btb_resp, _ram_2_WIRE_51 node _ram_2_T_385 = mux(write_mask[2][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_2_T_386 = mux(write_mask[2][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_2_T_387 = mux(write_mask[2][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_2_T_388 = mux(write_mask[2][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_2_T_389 = or(_ram_2_T_385, _ram_2_T_386) node _ram_2_T_390 = or(_ram_2_T_389, _ram_2_T_387) node _ram_2_T_391 = or(_ram_2_T_390, _ram_2_T_388) wire _ram_2_WIRE_63 : UInt<1> connect _ram_2_WIRE_63, _ram_2_T_391 connect _ram_2_WIRE_1.sets_vcfg, _ram_2_WIRE_63 node _ram_2_T_392 = mux(write_mask[2][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_2_T_393 = mux(write_mask[2][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_2_T_394 = mux(write_mask[2][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_2_T_395 = mux(write_mask[2][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_2_T_396 = or(_ram_2_T_392, _ram_2_T_393) node _ram_2_T_397 = or(_ram_2_T_396, _ram_2_T_394) node _ram_2_T_398 = or(_ram_2_T_397, _ram_2_T_395) wire _ram_2_WIRE_64 : UInt<1> connect _ram_2_WIRE_64, _ram_2_T_398 connect _ram_2_WIRE_1.rvc, _ram_2_WIRE_64 wire _ram_2_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_2_T_399 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_2_T_400 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_2_T_401 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_2_T_402 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_2_T_403 = or(_ram_2_T_399, _ram_2_T_400) node _ram_2_T_404 = or(_ram_2_T_403, _ram_2_T_401) node _ram_2_T_405 = or(_ram_2_T_404, _ram_2_T_402) wire _ram_2_WIRE_66 : UInt<1> connect _ram_2_WIRE_66, _ram_2_T_405 connect _ram_2_WIRE_65.vec, _ram_2_WIRE_66 node _ram_2_T_406 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_2_T_407 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_2_T_408 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_2_T_409 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_2_T_410 = or(_ram_2_T_406, _ram_2_T_407) node _ram_2_T_411 = or(_ram_2_T_410, _ram_2_T_408) node _ram_2_T_412 = or(_ram_2_T_411, _ram_2_T_409) wire _ram_2_WIRE_67 : UInt<1> connect _ram_2_WIRE_67, _ram_2_T_412 connect _ram_2_WIRE_65.wflags, _ram_2_WIRE_67 node _ram_2_T_413 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_2_T_414 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_2_T_415 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_2_T_416 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_2_T_417 = or(_ram_2_T_413, _ram_2_T_414) node _ram_2_T_418 = or(_ram_2_T_417, _ram_2_T_415) node _ram_2_T_419 = or(_ram_2_T_418, _ram_2_T_416) wire _ram_2_WIRE_68 : UInt<1> connect _ram_2_WIRE_68, _ram_2_T_419 connect _ram_2_WIRE_65.sqrt, _ram_2_WIRE_68 node _ram_2_T_420 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_2_T_421 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_2_T_422 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_2_T_423 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_2_T_424 = or(_ram_2_T_420, _ram_2_T_421) node _ram_2_T_425 = or(_ram_2_T_424, _ram_2_T_422) node _ram_2_T_426 = or(_ram_2_T_425, _ram_2_T_423) wire _ram_2_WIRE_69 : UInt<1> connect _ram_2_WIRE_69, _ram_2_T_426 connect _ram_2_WIRE_65.div, _ram_2_WIRE_69 node _ram_2_T_427 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_2_T_428 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_2_T_429 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_2_T_430 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_2_T_431 = or(_ram_2_T_427, _ram_2_T_428) node _ram_2_T_432 = or(_ram_2_T_431, _ram_2_T_429) node _ram_2_T_433 = or(_ram_2_T_432, _ram_2_T_430) wire _ram_2_WIRE_70 : UInt<1> connect _ram_2_WIRE_70, _ram_2_T_433 connect _ram_2_WIRE_65.fma, _ram_2_WIRE_70 node _ram_2_T_434 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_2_T_435 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_2_T_436 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_2_T_437 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_2_T_438 = or(_ram_2_T_434, _ram_2_T_435) node _ram_2_T_439 = or(_ram_2_T_438, _ram_2_T_436) node _ram_2_T_440 = or(_ram_2_T_439, _ram_2_T_437) wire _ram_2_WIRE_71 : UInt<1> connect _ram_2_WIRE_71, _ram_2_T_440 connect _ram_2_WIRE_65.fastpipe, _ram_2_WIRE_71 node _ram_2_T_441 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_2_T_442 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_2_T_443 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_2_T_444 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_2_T_445 = or(_ram_2_T_441, _ram_2_T_442) node _ram_2_T_446 = or(_ram_2_T_445, _ram_2_T_443) node _ram_2_T_447 = or(_ram_2_T_446, _ram_2_T_444) wire _ram_2_WIRE_72 : UInt<1> connect _ram_2_WIRE_72, _ram_2_T_447 connect _ram_2_WIRE_65.toint, _ram_2_WIRE_72 node _ram_2_T_448 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_2_T_449 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_2_T_450 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_2_T_451 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_2_T_452 = or(_ram_2_T_448, _ram_2_T_449) node _ram_2_T_453 = or(_ram_2_T_452, _ram_2_T_450) node _ram_2_T_454 = or(_ram_2_T_453, _ram_2_T_451) wire _ram_2_WIRE_73 : UInt<1> connect _ram_2_WIRE_73, _ram_2_T_454 connect _ram_2_WIRE_65.fromint, _ram_2_WIRE_73 node _ram_2_T_455 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_2_T_456 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_2_T_457 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_2_T_458 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_2_T_459 = or(_ram_2_T_455, _ram_2_T_456) node _ram_2_T_460 = or(_ram_2_T_459, _ram_2_T_457) node _ram_2_T_461 = or(_ram_2_T_460, _ram_2_T_458) wire _ram_2_WIRE_74 : UInt<2> connect _ram_2_WIRE_74, _ram_2_T_461 connect _ram_2_WIRE_65.typeTagOut, _ram_2_WIRE_74 node _ram_2_T_462 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_2_T_463 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_2_T_464 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_2_T_465 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_2_T_466 = or(_ram_2_T_462, _ram_2_T_463) node _ram_2_T_467 = or(_ram_2_T_466, _ram_2_T_464) node _ram_2_T_468 = or(_ram_2_T_467, _ram_2_T_465) wire _ram_2_WIRE_75 : UInt<2> connect _ram_2_WIRE_75, _ram_2_T_468 connect _ram_2_WIRE_65.typeTagIn, _ram_2_WIRE_75 node _ram_2_T_469 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_2_T_470 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_2_T_471 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_2_T_472 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_2_T_473 = or(_ram_2_T_469, _ram_2_T_470) node _ram_2_T_474 = or(_ram_2_T_473, _ram_2_T_471) node _ram_2_T_475 = or(_ram_2_T_474, _ram_2_T_472) wire _ram_2_WIRE_76 : UInt<1> connect _ram_2_WIRE_76, _ram_2_T_475 connect _ram_2_WIRE_65.swap23, _ram_2_WIRE_76 node _ram_2_T_476 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_2_T_477 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_2_T_478 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_2_T_479 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_2_T_480 = or(_ram_2_T_476, _ram_2_T_477) node _ram_2_T_481 = or(_ram_2_T_480, _ram_2_T_478) node _ram_2_T_482 = or(_ram_2_T_481, _ram_2_T_479) wire _ram_2_WIRE_77 : UInt<1> connect _ram_2_WIRE_77, _ram_2_T_482 connect _ram_2_WIRE_65.swap12, _ram_2_WIRE_77 node _ram_2_T_483 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_2_T_484 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_2_T_485 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_2_T_486 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_2_T_487 = or(_ram_2_T_483, _ram_2_T_484) node _ram_2_T_488 = or(_ram_2_T_487, _ram_2_T_485) node _ram_2_T_489 = or(_ram_2_T_488, _ram_2_T_486) wire _ram_2_WIRE_78 : UInt<1> connect _ram_2_WIRE_78, _ram_2_T_489 connect _ram_2_WIRE_65.ren3, _ram_2_WIRE_78 node _ram_2_T_490 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_2_T_491 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_2_T_492 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_2_T_493 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_2_T_494 = or(_ram_2_T_490, _ram_2_T_491) node _ram_2_T_495 = or(_ram_2_T_494, _ram_2_T_492) node _ram_2_T_496 = or(_ram_2_T_495, _ram_2_T_493) wire _ram_2_WIRE_79 : UInt<1> connect _ram_2_WIRE_79, _ram_2_T_496 connect _ram_2_WIRE_65.ren2, _ram_2_WIRE_79 node _ram_2_T_497 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_2_T_498 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_2_T_499 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_2_T_500 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_2_T_501 = or(_ram_2_T_497, _ram_2_T_498) node _ram_2_T_502 = or(_ram_2_T_501, _ram_2_T_499) node _ram_2_T_503 = or(_ram_2_T_502, _ram_2_T_500) wire _ram_2_WIRE_80 : UInt<1> connect _ram_2_WIRE_80, _ram_2_T_503 connect _ram_2_WIRE_65.ren1, _ram_2_WIRE_80 node _ram_2_T_504 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_2_T_505 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_2_T_506 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_2_T_507 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_2_T_508 = or(_ram_2_T_504, _ram_2_T_505) node _ram_2_T_509 = or(_ram_2_T_508, _ram_2_T_506) node _ram_2_T_510 = or(_ram_2_T_509, _ram_2_T_507) wire _ram_2_WIRE_81 : UInt<1> connect _ram_2_WIRE_81, _ram_2_T_510 connect _ram_2_WIRE_65.wen, _ram_2_WIRE_81 node _ram_2_T_511 = mux(write_mask[2][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_2_T_512 = mux(write_mask[2][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_2_T_513 = mux(write_mask[2][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_2_T_514 = mux(write_mask[2][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_2_T_515 = or(_ram_2_T_511, _ram_2_T_512) node _ram_2_T_516 = or(_ram_2_T_515, _ram_2_T_513) node _ram_2_T_517 = or(_ram_2_T_516, _ram_2_T_514) wire _ram_2_WIRE_82 : UInt<1> connect _ram_2_WIRE_82, _ram_2_T_517 connect _ram_2_WIRE_65.ldst, _ram_2_WIRE_82 connect _ram_2_WIRE_1.fp_ctrl, _ram_2_WIRE_65 wire _ram_2_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_2_T_518 = mux(write_mask[2][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_2_T_519 = mux(write_mask[2][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_2_T_520 = mux(write_mask[2][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_2_T_521 = mux(write_mask[2][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_2_T_522 = or(_ram_2_T_518, _ram_2_T_519) node _ram_2_T_523 = or(_ram_2_T_522, _ram_2_T_520) node _ram_2_T_524 = or(_ram_2_T_523, _ram_2_T_521) wire _ram_2_WIRE_84 : UInt<1> connect _ram_2_WIRE_84, _ram_2_T_524 connect _ram_2_WIRE_83.vec, _ram_2_WIRE_84 node _ram_2_T_525 = mux(write_mask[2][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_2_T_526 = mux(write_mask[2][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_2_T_527 = mux(write_mask[2][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_2_T_528 = mux(write_mask[2][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_2_T_529 = or(_ram_2_T_525, _ram_2_T_526) node _ram_2_T_530 = or(_ram_2_T_529, _ram_2_T_527) node _ram_2_T_531 = or(_ram_2_T_530, _ram_2_T_528) wire _ram_2_WIRE_85 : UInt<1> connect _ram_2_WIRE_85, _ram_2_T_531 connect _ram_2_WIRE_83.dp, _ram_2_WIRE_85 node _ram_2_T_532 = mux(write_mask[2][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_2_T_533 = mux(write_mask[2][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_2_T_534 = mux(write_mask[2][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_2_T_535 = mux(write_mask[2][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_2_T_536 = or(_ram_2_T_532, _ram_2_T_533) node _ram_2_T_537 = or(_ram_2_T_536, _ram_2_T_534) node _ram_2_T_538 = or(_ram_2_T_537, _ram_2_T_535) wire _ram_2_WIRE_86 : UInt<1> connect _ram_2_WIRE_86, _ram_2_T_538 connect _ram_2_WIRE_83.amo, _ram_2_WIRE_86 node _ram_2_T_539 = mux(write_mask[2][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_2_T_540 = mux(write_mask[2][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_2_T_541 = mux(write_mask[2][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_2_T_542 = mux(write_mask[2][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_2_T_543 = or(_ram_2_T_539, _ram_2_T_540) node _ram_2_T_544 = or(_ram_2_T_543, _ram_2_T_541) node _ram_2_T_545 = or(_ram_2_T_544, _ram_2_T_542) wire _ram_2_WIRE_87 : UInt<1> connect _ram_2_WIRE_87, _ram_2_T_545 connect _ram_2_WIRE_83.fence, _ram_2_WIRE_87 node _ram_2_T_546 = mux(write_mask[2][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_2_T_547 = mux(write_mask[2][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_2_T_548 = mux(write_mask[2][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_2_T_549 = mux(write_mask[2][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_2_T_550 = or(_ram_2_T_546, _ram_2_T_547) node _ram_2_T_551 = or(_ram_2_T_550, _ram_2_T_548) node _ram_2_T_552 = or(_ram_2_T_551, _ram_2_T_549) wire _ram_2_WIRE_88 : UInt<1> connect _ram_2_WIRE_88, _ram_2_T_552 connect _ram_2_WIRE_83.fence_i, _ram_2_WIRE_88 node _ram_2_T_553 = mux(write_mask[2][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_2_T_554 = mux(write_mask[2][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_2_T_555 = mux(write_mask[2][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_2_T_556 = mux(write_mask[2][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_2_T_557 = or(_ram_2_T_553, _ram_2_T_554) node _ram_2_T_558 = or(_ram_2_T_557, _ram_2_T_555) node _ram_2_T_559 = or(_ram_2_T_558, _ram_2_T_556) wire _ram_2_WIRE_89 : UInt<3> connect _ram_2_WIRE_89, _ram_2_T_559 connect _ram_2_WIRE_83.csr, _ram_2_WIRE_89 node _ram_2_T_560 = mux(write_mask[2][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_2_T_561 = mux(write_mask[2][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_2_T_562 = mux(write_mask[2][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_2_T_563 = mux(write_mask[2][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_2_T_564 = or(_ram_2_T_560, _ram_2_T_561) node _ram_2_T_565 = or(_ram_2_T_564, _ram_2_T_562) node _ram_2_T_566 = or(_ram_2_T_565, _ram_2_T_563) wire _ram_2_WIRE_90 : UInt<1> connect _ram_2_WIRE_90, _ram_2_T_566 connect _ram_2_WIRE_83.wxd, _ram_2_WIRE_90 node _ram_2_T_567 = mux(write_mask[2][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_2_T_568 = mux(write_mask[2][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_2_T_569 = mux(write_mask[2][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_2_T_570 = mux(write_mask[2][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_2_T_571 = or(_ram_2_T_567, _ram_2_T_568) node _ram_2_T_572 = or(_ram_2_T_571, _ram_2_T_569) node _ram_2_T_573 = or(_ram_2_T_572, _ram_2_T_570) wire _ram_2_WIRE_91 : UInt<1> connect _ram_2_WIRE_91, _ram_2_T_573 connect _ram_2_WIRE_83.div, _ram_2_WIRE_91 node _ram_2_T_574 = mux(write_mask[2][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_2_T_575 = mux(write_mask[2][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_2_T_576 = mux(write_mask[2][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_2_T_577 = mux(write_mask[2][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_2_T_578 = or(_ram_2_T_574, _ram_2_T_575) node _ram_2_T_579 = or(_ram_2_T_578, _ram_2_T_576) node _ram_2_T_580 = or(_ram_2_T_579, _ram_2_T_577) wire _ram_2_WIRE_92 : UInt<1> connect _ram_2_WIRE_92, _ram_2_T_580 connect _ram_2_WIRE_83.mul, _ram_2_WIRE_92 node _ram_2_T_581 = mux(write_mask[2][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_2_T_582 = mux(write_mask[2][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_2_T_583 = mux(write_mask[2][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_2_T_584 = mux(write_mask[2][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_2_T_585 = or(_ram_2_T_581, _ram_2_T_582) node _ram_2_T_586 = or(_ram_2_T_585, _ram_2_T_583) node _ram_2_T_587 = or(_ram_2_T_586, _ram_2_T_584) wire _ram_2_WIRE_93 : UInt<1> connect _ram_2_WIRE_93, _ram_2_T_587 connect _ram_2_WIRE_83.wfd, _ram_2_WIRE_93 node _ram_2_T_588 = mux(write_mask[2][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_2_T_589 = mux(write_mask[2][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_2_T_590 = mux(write_mask[2][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_2_T_591 = mux(write_mask[2][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_2_T_592 = or(_ram_2_T_588, _ram_2_T_589) node _ram_2_T_593 = or(_ram_2_T_592, _ram_2_T_590) node _ram_2_T_594 = or(_ram_2_T_593, _ram_2_T_591) wire _ram_2_WIRE_94 : UInt<1> connect _ram_2_WIRE_94, _ram_2_T_594 connect _ram_2_WIRE_83.rfs3, _ram_2_WIRE_94 node _ram_2_T_595 = mux(write_mask[2][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_2_T_596 = mux(write_mask[2][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_2_T_597 = mux(write_mask[2][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_2_T_598 = mux(write_mask[2][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_2_T_599 = or(_ram_2_T_595, _ram_2_T_596) node _ram_2_T_600 = or(_ram_2_T_599, _ram_2_T_597) node _ram_2_T_601 = or(_ram_2_T_600, _ram_2_T_598) wire _ram_2_WIRE_95 : UInt<1> connect _ram_2_WIRE_95, _ram_2_T_601 connect _ram_2_WIRE_83.rfs2, _ram_2_WIRE_95 node _ram_2_T_602 = mux(write_mask[2][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_2_T_603 = mux(write_mask[2][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_2_T_604 = mux(write_mask[2][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_2_T_605 = mux(write_mask[2][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_2_T_606 = or(_ram_2_T_602, _ram_2_T_603) node _ram_2_T_607 = or(_ram_2_T_606, _ram_2_T_604) node _ram_2_T_608 = or(_ram_2_T_607, _ram_2_T_605) wire _ram_2_WIRE_96 : UInt<1> connect _ram_2_WIRE_96, _ram_2_T_608 connect _ram_2_WIRE_83.rfs1, _ram_2_WIRE_96 node _ram_2_T_609 = mux(write_mask[2][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_2_T_610 = mux(write_mask[2][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_2_T_611 = mux(write_mask[2][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_2_T_612 = mux(write_mask[2][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_2_T_613 = or(_ram_2_T_609, _ram_2_T_610) node _ram_2_T_614 = or(_ram_2_T_613, _ram_2_T_611) node _ram_2_T_615 = or(_ram_2_T_614, _ram_2_T_612) wire _ram_2_WIRE_97 : UInt<5> connect _ram_2_WIRE_97, _ram_2_T_615 connect _ram_2_WIRE_83.mem_cmd, _ram_2_WIRE_97 node _ram_2_T_616 = mux(write_mask[2][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_2_T_617 = mux(write_mask[2][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_2_T_618 = mux(write_mask[2][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_2_T_619 = mux(write_mask[2][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_2_T_620 = or(_ram_2_T_616, _ram_2_T_617) node _ram_2_T_621 = or(_ram_2_T_620, _ram_2_T_618) node _ram_2_T_622 = or(_ram_2_T_621, _ram_2_T_619) wire _ram_2_WIRE_98 : UInt<1> connect _ram_2_WIRE_98, _ram_2_T_622 connect _ram_2_WIRE_83.mem, _ram_2_WIRE_98 node _ram_2_T_623 = mux(write_mask[2][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_2_T_624 = mux(write_mask[2][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_2_T_625 = mux(write_mask[2][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_2_T_626 = mux(write_mask[2][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_2_T_627 = or(_ram_2_T_623, _ram_2_T_624) node _ram_2_T_628 = or(_ram_2_T_627, _ram_2_T_625) node _ram_2_T_629 = or(_ram_2_T_628, _ram_2_T_626) wire _ram_2_WIRE_99 : UInt<5> connect _ram_2_WIRE_99, _ram_2_T_629 connect _ram_2_WIRE_83.alu_fn, _ram_2_WIRE_99 node _ram_2_T_630 = mux(write_mask[2][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_2_T_631 = mux(write_mask[2][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_2_T_632 = mux(write_mask[2][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_2_T_633 = mux(write_mask[2][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_2_T_634 = or(_ram_2_T_630, _ram_2_T_631) node _ram_2_T_635 = or(_ram_2_T_634, _ram_2_T_632) node _ram_2_T_636 = or(_ram_2_T_635, _ram_2_T_633) wire _ram_2_WIRE_100 : UInt<1> connect _ram_2_WIRE_100, _ram_2_T_636 connect _ram_2_WIRE_83.alu_dw, _ram_2_WIRE_100 node _ram_2_T_637 = mux(write_mask[2][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_2_T_638 = mux(write_mask[2][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_2_T_639 = mux(write_mask[2][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_2_T_640 = mux(write_mask[2][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_2_T_641 = or(_ram_2_T_637, _ram_2_T_638) node _ram_2_T_642 = or(_ram_2_T_641, _ram_2_T_639) node _ram_2_T_643 = or(_ram_2_T_642, _ram_2_T_640) wire _ram_2_WIRE_101 : UInt<3> connect _ram_2_WIRE_101, _ram_2_T_643 connect _ram_2_WIRE_83.sel_imm, _ram_2_WIRE_101 node _ram_2_T_644 = mux(write_mask[2][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_2_T_645 = mux(write_mask[2][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_2_T_646 = mux(write_mask[2][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_2_T_647 = mux(write_mask[2][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_2_T_648 = or(_ram_2_T_644, _ram_2_T_645) node _ram_2_T_649 = or(_ram_2_T_648, _ram_2_T_646) node _ram_2_T_650 = or(_ram_2_T_649, _ram_2_T_647) wire _ram_2_WIRE_102 : UInt<2> connect _ram_2_WIRE_102, _ram_2_T_650 connect _ram_2_WIRE_83.sel_alu1, _ram_2_WIRE_102 node _ram_2_T_651 = mux(write_mask[2][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_2_T_652 = mux(write_mask[2][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_2_T_653 = mux(write_mask[2][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_2_T_654 = mux(write_mask[2][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_2_T_655 = or(_ram_2_T_651, _ram_2_T_652) node _ram_2_T_656 = or(_ram_2_T_655, _ram_2_T_653) node _ram_2_T_657 = or(_ram_2_T_656, _ram_2_T_654) wire _ram_2_WIRE_103 : UInt<3> connect _ram_2_WIRE_103, _ram_2_T_657 connect _ram_2_WIRE_83.sel_alu2, _ram_2_WIRE_103 node _ram_2_T_658 = mux(write_mask[2][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_2_T_659 = mux(write_mask[2][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_2_T_660 = mux(write_mask[2][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_2_T_661 = mux(write_mask[2][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_2_T_662 = or(_ram_2_T_658, _ram_2_T_659) node _ram_2_T_663 = or(_ram_2_T_662, _ram_2_T_660) node _ram_2_T_664 = or(_ram_2_T_663, _ram_2_T_661) wire _ram_2_WIRE_104 : UInt<1> connect _ram_2_WIRE_104, _ram_2_T_664 connect _ram_2_WIRE_83.rxs1, _ram_2_WIRE_104 node _ram_2_T_665 = mux(write_mask[2][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_2_T_666 = mux(write_mask[2][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_2_T_667 = mux(write_mask[2][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_2_T_668 = mux(write_mask[2][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_2_T_669 = or(_ram_2_T_665, _ram_2_T_666) node _ram_2_T_670 = or(_ram_2_T_669, _ram_2_T_667) node _ram_2_T_671 = or(_ram_2_T_670, _ram_2_T_668) wire _ram_2_WIRE_105 : UInt<1> connect _ram_2_WIRE_105, _ram_2_T_671 connect _ram_2_WIRE_83.rxs2, _ram_2_WIRE_105 node _ram_2_T_672 = mux(write_mask[2][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_2_T_673 = mux(write_mask[2][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_2_T_674 = mux(write_mask[2][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_2_T_675 = mux(write_mask[2][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_2_T_676 = or(_ram_2_T_672, _ram_2_T_673) node _ram_2_T_677 = or(_ram_2_T_676, _ram_2_T_674) node _ram_2_T_678 = or(_ram_2_T_677, _ram_2_T_675) wire _ram_2_WIRE_106 : UInt<1> connect _ram_2_WIRE_106, _ram_2_T_678 connect _ram_2_WIRE_83.jalr, _ram_2_WIRE_106 node _ram_2_T_679 = mux(write_mask[2][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_2_T_680 = mux(write_mask[2][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_2_T_681 = mux(write_mask[2][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_2_T_682 = mux(write_mask[2][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_2_T_683 = or(_ram_2_T_679, _ram_2_T_680) node _ram_2_T_684 = or(_ram_2_T_683, _ram_2_T_681) node _ram_2_T_685 = or(_ram_2_T_684, _ram_2_T_682) wire _ram_2_WIRE_107 : UInt<1> connect _ram_2_WIRE_107, _ram_2_T_685 connect _ram_2_WIRE_83.jal, _ram_2_WIRE_107 node _ram_2_T_686 = mux(write_mask[2][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_2_T_687 = mux(write_mask[2][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_2_T_688 = mux(write_mask[2][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_2_T_689 = mux(write_mask[2][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_2_T_690 = or(_ram_2_T_686, _ram_2_T_687) node _ram_2_T_691 = or(_ram_2_T_690, _ram_2_T_688) node _ram_2_T_692 = or(_ram_2_T_691, _ram_2_T_689) wire _ram_2_WIRE_108 : UInt<1> connect _ram_2_WIRE_108, _ram_2_T_692 connect _ram_2_WIRE_83.branch, _ram_2_WIRE_108 node _ram_2_T_693 = mux(write_mask[2][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_2_T_694 = mux(write_mask[2][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_2_T_695 = mux(write_mask[2][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_2_T_696 = mux(write_mask[2][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_2_T_697 = or(_ram_2_T_693, _ram_2_T_694) node _ram_2_T_698 = or(_ram_2_T_697, _ram_2_T_695) node _ram_2_T_699 = or(_ram_2_T_698, _ram_2_T_696) wire _ram_2_WIRE_109 : UInt<1> connect _ram_2_WIRE_109, _ram_2_T_699 connect _ram_2_WIRE_83.rocc, _ram_2_WIRE_109 node _ram_2_T_700 = mux(write_mask[2][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_2_T_701 = mux(write_mask[2][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_2_T_702 = mux(write_mask[2][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_2_T_703 = mux(write_mask[2][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_2_T_704 = or(_ram_2_T_700, _ram_2_T_701) node _ram_2_T_705 = or(_ram_2_T_704, _ram_2_T_702) node _ram_2_T_706 = or(_ram_2_T_705, _ram_2_T_703) wire _ram_2_WIRE_110 : UInt<1> connect _ram_2_WIRE_110, _ram_2_T_706 connect _ram_2_WIRE_83.fp, _ram_2_WIRE_110 node _ram_2_T_707 = mux(write_mask[2][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_2_T_708 = mux(write_mask[2][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_2_T_709 = mux(write_mask[2][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_2_T_710 = mux(write_mask[2][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_2_T_711 = or(_ram_2_T_707, _ram_2_T_708) node _ram_2_T_712 = or(_ram_2_T_711, _ram_2_T_709) node _ram_2_T_713 = or(_ram_2_T_712, _ram_2_T_710) wire _ram_2_WIRE_111 : UInt<1> connect _ram_2_WIRE_111, _ram_2_T_713 connect _ram_2_WIRE_83.legal, _ram_2_WIRE_111 connect _ram_2_WIRE_1.ctrl, _ram_2_WIRE_83 node _ram_2_T_714 = mux(write_mask[2][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_2_T_715 = mux(write_mask[2][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_2_T_716 = mux(write_mask[2][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_2_T_717 = mux(write_mask[2][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_2_T_718 = or(_ram_2_T_714, _ram_2_T_715) node _ram_2_T_719 = or(_ram_2_T_718, _ram_2_T_716) node _ram_2_T_720 = or(_ram_2_T_719, _ram_2_T_717) wire _ram_2_WIRE_112 : UInt<1> connect _ram_2_WIRE_112, _ram_2_T_720 connect _ram_2_WIRE_1.edge_inst, _ram_2_WIRE_112 node _ram_2_T_721 = mux(write_mask[2][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_2_T_722 = mux(write_mask[2][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_2_T_723 = mux(write_mask[2][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_2_T_724 = mux(write_mask[2][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_2_T_725 = or(_ram_2_T_721, _ram_2_T_722) node _ram_2_T_726 = or(_ram_2_T_725, _ram_2_T_723) node _ram_2_T_727 = or(_ram_2_T_726, _ram_2_T_724) wire _ram_2_WIRE_113 : UInt<40> connect _ram_2_WIRE_113, _ram_2_T_727 connect _ram_2_WIRE_1.pc, _ram_2_WIRE_113 node _ram_2_T_728 = mux(write_mask[2][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_2_T_729 = mux(write_mask[2][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_2_T_730 = mux(write_mask[2][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_2_T_731 = mux(write_mask[2][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_2_T_732 = or(_ram_2_T_728, _ram_2_T_729) node _ram_2_T_733 = or(_ram_2_T_732, _ram_2_T_730) node _ram_2_T_734 = or(_ram_2_T_733, _ram_2_T_731) wire _ram_2_WIRE_114 : UInt<32> connect _ram_2_WIRE_114, _ram_2_T_734 connect _ram_2_WIRE_1.raw_inst, _ram_2_WIRE_114 node _ram_2_T_735 = mux(write_mask[2][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_2_T_736 = mux(write_mask[2][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_2_T_737 = mux(write_mask[2][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_2_T_738 = mux(write_mask[2][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_2_T_739 = or(_ram_2_T_735, _ram_2_T_736) node _ram_2_T_740 = or(_ram_2_T_739, _ram_2_T_737) node _ram_2_T_741 = or(_ram_2_T_740, _ram_2_T_738) wire _ram_2_WIRE_115 : UInt<32> connect _ram_2_WIRE_115, _ram_2_T_741 connect _ram_2_WIRE_1.inst, _ram_2_WIRE_115 connect _ram_2_WIRE.bits, _ram_2_WIRE_1 node _ram_2_T_742 = mux(write_mask[2][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_2_T_743 = mux(write_mask[2][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_2_T_744 = mux(write_mask[2][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_2_T_745 = mux(write_mask[2][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_2_T_746 = or(_ram_2_T_742, _ram_2_T_743) node _ram_2_T_747 = or(_ram_2_T_746, _ram_2_T_744) node _ram_2_T_748 = or(_ram_2_T_747, _ram_2_T_745) wire _ram_2_WIRE_116 : UInt<1> connect _ram_2_WIRE_116, _ram_2_T_748 connect _ram_2_WIRE.valid, _ram_2_WIRE_116 connect ram[2], _ram_2_WIRE node _T_24 = eq(ram[3].valid, UInt<1>(0h0)) when _T_24 : wire _ram_3_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_3_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_3_T = mux(write_mask[3][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_3_T_1 = mux(write_mask[3][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_3_T_2 = mux(write_mask[3][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_3_T_3 = mux(write_mask[3][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_3_T_4 = or(_ram_3_T, _ram_3_T_1) node _ram_3_T_5 = or(_ram_3_T_4, _ram_3_T_2) node _ram_3_T_6 = or(_ram_3_T_5, _ram_3_T_3) wire _ram_3_WIRE_2 : UInt<1> connect _ram_3_WIRE_2, _ram_3_T_6 connect _ram_3_WIRE_1.flush_pipe, _ram_3_WIRE_2 node _ram_3_T_7 = mux(write_mask[3][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_3_T_8 = mux(write_mask[3][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_3_T_9 = mux(write_mask[3][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_3_T_10 = mux(write_mask[3][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_3_T_11 = or(_ram_3_T_7, _ram_3_T_8) node _ram_3_T_12 = or(_ram_3_T_11, _ram_3_T_9) node _ram_3_T_13 = or(_ram_3_T_12, _ram_3_T_10) wire _ram_3_WIRE_3 : UInt<2> connect _ram_3_WIRE_3, _ram_3_T_13 connect _ram_3_WIRE_1.mem_size, _ram_3_WIRE_3 wire _ram_3_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_3_T_14 = mux(write_mask[3][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_3_T_15 = mux(write_mask[3][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_3_T_16 = mux(write_mask[3][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_3_T_17 = mux(write_mask[3][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_3_T_18 = or(_ram_3_T_14, _ram_3_T_15) node _ram_3_T_19 = or(_ram_3_T_18, _ram_3_T_16) node _ram_3_T_20 = or(_ram_3_T_19, _ram_3_T_17) wire _ram_3_WIRE_5 : UInt<65> connect _ram_3_WIRE_5, _ram_3_T_20 connect _ram_3_WIRE_4.in3, _ram_3_WIRE_5 node _ram_3_T_21 = mux(write_mask[3][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_3_T_22 = mux(write_mask[3][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_3_T_23 = mux(write_mask[3][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_3_T_24 = mux(write_mask[3][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_3_T_25 = or(_ram_3_T_21, _ram_3_T_22) node _ram_3_T_26 = or(_ram_3_T_25, _ram_3_T_23) node _ram_3_T_27 = or(_ram_3_T_26, _ram_3_T_24) wire _ram_3_WIRE_6 : UInt<65> connect _ram_3_WIRE_6, _ram_3_T_27 connect _ram_3_WIRE_4.in2, _ram_3_WIRE_6 node _ram_3_T_28 = mux(write_mask[3][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_3_T_29 = mux(write_mask[3][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_3_T_30 = mux(write_mask[3][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_3_T_31 = mux(write_mask[3][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_3_T_32 = or(_ram_3_T_28, _ram_3_T_29) node _ram_3_T_33 = or(_ram_3_T_32, _ram_3_T_30) node _ram_3_T_34 = or(_ram_3_T_33, _ram_3_T_31) wire _ram_3_WIRE_7 : UInt<65> connect _ram_3_WIRE_7, _ram_3_T_34 connect _ram_3_WIRE_4.in1, _ram_3_WIRE_7 node _ram_3_T_35 = mux(write_mask[3][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_3_T_36 = mux(write_mask[3][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_3_T_37 = mux(write_mask[3][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_3_T_38 = mux(write_mask[3][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_3_T_39 = or(_ram_3_T_35, _ram_3_T_36) node _ram_3_T_40 = or(_ram_3_T_39, _ram_3_T_37) node _ram_3_T_41 = or(_ram_3_T_40, _ram_3_T_38) wire _ram_3_WIRE_8 : UInt<2> connect _ram_3_WIRE_8, _ram_3_T_41 connect _ram_3_WIRE_4.fmt, _ram_3_WIRE_8 node _ram_3_T_42 = mux(write_mask[3][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_3_T_43 = mux(write_mask[3][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_3_T_44 = mux(write_mask[3][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_3_T_45 = mux(write_mask[3][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_3_T_46 = or(_ram_3_T_42, _ram_3_T_43) node _ram_3_T_47 = or(_ram_3_T_46, _ram_3_T_44) node _ram_3_T_48 = or(_ram_3_T_47, _ram_3_T_45) wire _ram_3_WIRE_9 : UInt<2> connect _ram_3_WIRE_9, _ram_3_T_48 connect _ram_3_WIRE_4.typ, _ram_3_WIRE_9 node _ram_3_T_49 = mux(write_mask[3][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_3_T_50 = mux(write_mask[3][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_3_T_51 = mux(write_mask[3][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_3_T_52 = mux(write_mask[3][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_3_T_53 = or(_ram_3_T_49, _ram_3_T_50) node _ram_3_T_54 = or(_ram_3_T_53, _ram_3_T_51) node _ram_3_T_55 = or(_ram_3_T_54, _ram_3_T_52) wire _ram_3_WIRE_10 : UInt<2> connect _ram_3_WIRE_10, _ram_3_T_55 connect _ram_3_WIRE_4.fmaCmd, _ram_3_WIRE_10 node _ram_3_T_56 = mux(write_mask[3][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_3_T_57 = mux(write_mask[3][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_3_T_58 = mux(write_mask[3][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_3_T_59 = mux(write_mask[3][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_3_T_60 = or(_ram_3_T_56, _ram_3_T_57) node _ram_3_T_61 = or(_ram_3_T_60, _ram_3_T_58) node _ram_3_T_62 = or(_ram_3_T_61, _ram_3_T_59) wire _ram_3_WIRE_11 : UInt<3> connect _ram_3_WIRE_11, _ram_3_T_62 connect _ram_3_WIRE_4.rm, _ram_3_WIRE_11 node _ram_3_T_63 = mux(write_mask[3][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_3_T_64 = mux(write_mask[3][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_3_T_65 = mux(write_mask[3][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_3_T_66 = mux(write_mask[3][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_3_T_67 = or(_ram_3_T_63, _ram_3_T_64) node _ram_3_T_68 = or(_ram_3_T_67, _ram_3_T_65) node _ram_3_T_69 = or(_ram_3_T_68, _ram_3_T_66) wire _ram_3_WIRE_12 : UInt<1> connect _ram_3_WIRE_12, _ram_3_T_69 connect _ram_3_WIRE_4.vec, _ram_3_WIRE_12 node _ram_3_T_70 = mux(write_mask[3][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_3_T_71 = mux(write_mask[3][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_3_T_72 = mux(write_mask[3][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_3_T_73 = mux(write_mask[3][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_3_T_74 = or(_ram_3_T_70, _ram_3_T_71) node _ram_3_T_75 = or(_ram_3_T_74, _ram_3_T_72) node _ram_3_T_76 = or(_ram_3_T_75, _ram_3_T_73) wire _ram_3_WIRE_13 : UInt<1> connect _ram_3_WIRE_13, _ram_3_T_76 connect _ram_3_WIRE_4.wflags, _ram_3_WIRE_13 node _ram_3_T_77 = mux(write_mask[3][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_3_T_78 = mux(write_mask[3][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_3_T_79 = mux(write_mask[3][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_3_T_80 = mux(write_mask[3][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_3_T_81 = or(_ram_3_T_77, _ram_3_T_78) node _ram_3_T_82 = or(_ram_3_T_81, _ram_3_T_79) node _ram_3_T_83 = or(_ram_3_T_82, _ram_3_T_80) wire _ram_3_WIRE_14 : UInt<1> connect _ram_3_WIRE_14, _ram_3_T_83 connect _ram_3_WIRE_4.sqrt, _ram_3_WIRE_14 node _ram_3_T_84 = mux(write_mask[3][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_3_T_85 = mux(write_mask[3][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_3_T_86 = mux(write_mask[3][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_3_T_87 = mux(write_mask[3][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_3_T_88 = or(_ram_3_T_84, _ram_3_T_85) node _ram_3_T_89 = or(_ram_3_T_88, _ram_3_T_86) node _ram_3_T_90 = or(_ram_3_T_89, _ram_3_T_87) wire _ram_3_WIRE_15 : UInt<1> connect _ram_3_WIRE_15, _ram_3_T_90 connect _ram_3_WIRE_4.div, _ram_3_WIRE_15 node _ram_3_T_91 = mux(write_mask[3][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_3_T_92 = mux(write_mask[3][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_3_T_93 = mux(write_mask[3][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_3_T_94 = mux(write_mask[3][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_3_T_95 = or(_ram_3_T_91, _ram_3_T_92) node _ram_3_T_96 = or(_ram_3_T_95, _ram_3_T_93) node _ram_3_T_97 = or(_ram_3_T_96, _ram_3_T_94) wire _ram_3_WIRE_16 : UInt<1> connect _ram_3_WIRE_16, _ram_3_T_97 connect _ram_3_WIRE_4.fma, _ram_3_WIRE_16 node _ram_3_T_98 = mux(write_mask[3][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_3_T_99 = mux(write_mask[3][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_3_T_100 = mux(write_mask[3][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_3_T_101 = mux(write_mask[3][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_3_T_102 = or(_ram_3_T_98, _ram_3_T_99) node _ram_3_T_103 = or(_ram_3_T_102, _ram_3_T_100) node _ram_3_T_104 = or(_ram_3_T_103, _ram_3_T_101) wire _ram_3_WIRE_17 : UInt<1> connect _ram_3_WIRE_17, _ram_3_T_104 connect _ram_3_WIRE_4.fastpipe, _ram_3_WIRE_17 node _ram_3_T_105 = mux(write_mask[3][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_3_T_106 = mux(write_mask[3][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_3_T_107 = mux(write_mask[3][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_3_T_108 = mux(write_mask[3][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_3_T_109 = or(_ram_3_T_105, _ram_3_T_106) node _ram_3_T_110 = or(_ram_3_T_109, _ram_3_T_107) node _ram_3_T_111 = or(_ram_3_T_110, _ram_3_T_108) wire _ram_3_WIRE_18 : UInt<1> connect _ram_3_WIRE_18, _ram_3_T_111 connect _ram_3_WIRE_4.toint, _ram_3_WIRE_18 node _ram_3_T_112 = mux(write_mask[3][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_3_T_113 = mux(write_mask[3][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_3_T_114 = mux(write_mask[3][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_3_T_115 = mux(write_mask[3][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_3_T_116 = or(_ram_3_T_112, _ram_3_T_113) node _ram_3_T_117 = or(_ram_3_T_116, _ram_3_T_114) node _ram_3_T_118 = or(_ram_3_T_117, _ram_3_T_115) wire _ram_3_WIRE_19 : UInt<1> connect _ram_3_WIRE_19, _ram_3_T_118 connect _ram_3_WIRE_4.fromint, _ram_3_WIRE_19 node _ram_3_T_119 = mux(write_mask[3][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_3_T_120 = mux(write_mask[3][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_3_T_121 = mux(write_mask[3][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_3_T_122 = mux(write_mask[3][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_3_T_123 = or(_ram_3_T_119, _ram_3_T_120) node _ram_3_T_124 = or(_ram_3_T_123, _ram_3_T_121) node _ram_3_T_125 = or(_ram_3_T_124, _ram_3_T_122) wire _ram_3_WIRE_20 : UInt<2> connect _ram_3_WIRE_20, _ram_3_T_125 connect _ram_3_WIRE_4.typeTagOut, _ram_3_WIRE_20 node _ram_3_T_126 = mux(write_mask[3][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_3_T_127 = mux(write_mask[3][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_3_T_128 = mux(write_mask[3][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_3_T_129 = mux(write_mask[3][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_3_T_130 = or(_ram_3_T_126, _ram_3_T_127) node _ram_3_T_131 = or(_ram_3_T_130, _ram_3_T_128) node _ram_3_T_132 = or(_ram_3_T_131, _ram_3_T_129) wire _ram_3_WIRE_21 : UInt<2> connect _ram_3_WIRE_21, _ram_3_T_132 connect _ram_3_WIRE_4.typeTagIn, _ram_3_WIRE_21 node _ram_3_T_133 = mux(write_mask[3][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_3_T_134 = mux(write_mask[3][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_3_T_135 = mux(write_mask[3][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_3_T_136 = mux(write_mask[3][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_3_T_137 = or(_ram_3_T_133, _ram_3_T_134) node _ram_3_T_138 = or(_ram_3_T_137, _ram_3_T_135) node _ram_3_T_139 = or(_ram_3_T_138, _ram_3_T_136) wire _ram_3_WIRE_22 : UInt<1> connect _ram_3_WIRE_22, _ram_3_T_139 connect _ram_3_WIRE_4.swap23, _ram_3_WIRE_22 node _ram_3_T_140 = mux(write_mask[3][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_3_T_141 = mux(write_mask[3][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_3_T_142 = mux(write_mask[3][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_3_T_143 = mux(write_mask[3][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_3_T_144 = or(_ram_3_T_140, _ram_3_T_141) node _ram_3_T_145 = or(_ram_3_T_144, _ram_3_T_142) node _ram_3_T_146 = or(_ram_3_T_145, _ram_3_T_143) wire _ram_3_WIRE_23 : UInt<1> connect _ram_3_WIRE_23, _ram_3_T_146 connect _ram_3_WIRE_4.swap12, _ram_3_WIRE_23 node _ram_3_T_147 = mux(write_mask[3][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_3_T_148 = mux(write_mask[3][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_3_T_149 = mux(write_mask[3][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_3_T_150 = mux(write_mask[3][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_3_T_151 = or(_ram_3_T_147, _ram_3_T_148) node _ram_3_T_152 = or(_ram_3_T_151, _ram_3_T_149) node _ram_3_T_153 = or(_ram_3_T_152, _ram_3_T_150) wire _ram_3_WIRE_24 : UInt<1> connect _ram_3_WIRE_24, _ram_3_T_153 connect _ram_3_WIRE_4.ren3, _ram_3_WIRE_24 node _ram_3_T_154 = mux(write_mask[3][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_3_T_155 = mux(write_mask[3][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_3_T_156 = mux(write_mask[3][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_3_T_157 = mux(write_mask[3][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_3_T_158 = or(_ram_3_T_154, _ram_3_T_155) node _ram_3_T_159 = or(_ram_3_T_158, _ram_3_T_156) node _ram_3_T_160 = or(_ram_3_T_159, _ram_3_T_157) wire _ram_3_WIRE_25 : UInt<1> connect _ram_3_WIRE_25, _ram_3_T_160 connect _ram_3_WIRE_4.ren2, _ram_3_WIRE_25 node _ram_3_T_161 = mux(write_mask[3][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_3_T_162 = mux(write_mask[3][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_3_T_163 = mux(write_mask[3][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_3_T_164 = mux(write_mask[3][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_3_T_165 = or(_ram_3_T_161, _ram_3_T_162) node _ram_3_T_166 = or(_ram_3_T_165, _ram_3_T_163) node _ram_3_T_167 = or(_ram_3_T_166, _ram_3_T_164) wire _ram_3_WIRE_26 : UInt<1> connect _ram_3_WIRE_26, _ram_3_T_167 connect _ram_3_WIRE_4.ren1, _ram_3_WIRE_26 node _ram_3_T_168 = mux(write_mask[3][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_3_T_169 = mux(write_mask[3][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_3_T_170 = mux(write_mask[3][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_3_T_171 = mux(write_mask[3][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_3_T_172 = or(_ram_3_T_168, _ram_3_T_169) node _ram_3_T_173 = or(_ram_3_T_172, _ram_3_T_170) node _ram_3_T_174 = or(_ram_3_T_173, _ram_3_T_171) wire _ram_3_WIRE_27 : UInt<1> connect _ram_3_WIRE_27, _ram_3_T_174 connect _ram_3_WIRE_4.wen, _ram_3_WIRE_27 node _ram_3_T_175 = mux(write_mask[3][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_3_T_176 = mux(write_mask[3][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_3_T_177 = mux(write_mask[3][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_3_T_178 = mux(write_mask[3][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_3_T_179 = or(_ram_3_T_175, _ram_3_T_176) node _ram_3_T_180 = or(_ram_3_T_179, _ram_3_T_177) node _ram_3_T_181 = or(_ram_3_T_180, _ram_3_T_178) wire _ram_3_WIRE_28 : UInt<1> connect _ram_3_WIRE_28, _ram_3_T_181 connect _ram_3_WIRE_4.ldst, _ram_3_WIRE_28 connect _ram_3_WIRE_1.fdivin, _ram_3_WIRE_4 node _ram_3_T_182 = mux(write_mask[3][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_3_T_183 = mux(write_mask[3][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_3_T_184 = mux(write_mask[3][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_3_T_185 = mux(write_mask[3][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_3_T_186 = or(_ram_3_T_182, _ram_3_T_183) node _ram_3_T_187 = or(_ram_3_T_186, _ram_3_T_184) node _ram_3_T_188 = or(_ram_3_T_187, _ram_3_T_185) wire _ram_3_WIRE_29 : UInt<5> connect _ram_3_WIRE_29, _ram_3_T_188 connect _ram_3_WIRE_1.fexc, _ram_3_WIRE_29 node _ram_3_T_189 = mux(write_mask[3][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_3_T_190 = mux(write_mask[3][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_3_T_191 = mux(write_mask[3][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_3_T_192 = mux(write_mask[3][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_3_T_193 = or(_ram_3_T_189, _ram_3_T_190) node _ram_3_T_194 = or(_ram_3_T_193, _ram_3_T_191) node _ram_3_T_195 = or(_ram_3_T_194, _ram_3_T_192) wire _ram_3_WIRE_30 : UInt<5> connect _ram_3_WIRE_30, _ram_3_T_195 connect _ram_3_WIRE_1.fra3, _ram_3_WIRE_30 node _ram_3_T_196 = mux(write_mask[3][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_3_T_197 = mux(write_mask[3][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_3_T_198 = mux(write_mask[3][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_3_T_199 = mux(write_mask[3][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_3_T_200 = or(_ram_3_T_196, _ram_3_T_197) node _ram_3_T_201 = or(_ram_3_T_200, _ram_3_T_198) node _ram_3_T_202 = or(_ram_3_T_201, _ram_3_T_199) wire _ram_3_WIRE_31 : UInt<5> connect _ram_3_WIRE_31, _ram_3_T_202 connect _ram_3_WIRE_1.fra2, _ram_3_WIRE_31 node _ram_3_T_203 = mux(write_mask[3][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_3_T_204 = mux(write_mask[3][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_3_T_205 = mux(write_mask[3][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_3_T_206 = mux(write_mask[3][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_3_T_207 = or(_ram_3_T_203, _ram_3_T_204) node _ram_3_T_208 = or(_ram_3_T_207, _ram_3_T_205) node _ram_3_T_209 = or(_ram_3_T_208, _ram_3_T_206) wire _ram_3_WIRE_32 : UInt<5> connect _ram_3_WIRE_32, _ram_3_T_209 connect _ram_3_WIRE_1.fra1, _ram_3_WIRE_32 wire _ram_3_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_3_T_210 = mux(write_mask[3][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_3_T_211 = mux(write_mask[3][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_3_T_212 = mux(write_mask[3][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_3_T_213 = mux(write_mask[3][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_3_T_214 = or(_ram_3_T_210, _ram_3_T_211) node _ram_3_T_215 = or(_ram_3_T_214, _ram_3_T_212) node _ram_3_T_216 = or(_ram_3_T_215, _ram_3_T_213) wire _ram_3_WIRE_34 : UInt<64> connect _ram_3_WIRE_34, _ram_3_T_216 connect _ram_3_WIRE_33.bits, _ram_3_WIRE_34 node _ram_3_T_217 = mux(write_mask[3][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_3_T_218 = mux(write_mask[3][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_3_T_219 = mux(write_mask[3][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_3_T_220 = mux(write_mask[3][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_3_T_221 = or(_ram_3_T_217, _ram_3_T_218) node _ram_3_T_222 = or(_ram_3_T_221, _ram_3_T_219) node _ram_3_T_223 = or(_ram_3_T_222, _ram_3_T_220) wire _ram_3_WIRE_35 : UInt<1> connect _ram_3_WIRE_35, _ram_3_T_223 connect _ram_3_WIRE_33.valid, _ram_3_WIRE_35 connect _ram_3_WIRE_1.wdata, _ram_3_WIRE_33 node _ram_3_T_224 = mux(write_mask[3][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_3_T_225 = mux(write_mask[3][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_3_T_226 = mux(write_mask[3][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_3_T_227 = mux(write_mask[3][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_3_T_228 = or(_ram_3_T_224, _ram_3_T_225) node _ram_3_T_229 = or(_ram_3_T_228, _ram_3_T_226) node _ram_3_T_230 = or(_ram_3_T_229, _ram_3_T_227) wire _ram_3_WIRE_36 : UInt<1> connect _ram_3_WIRE_36, _ram_3_T_230 connect _ram_3_WIRE_1.uses_latealu, _ram_3_WIRE_36 node _ram_3_T_231 = mux(write_mask[3][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_3_T_232 = mux(write_mask[3][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_3_T_233 = mux(write_mask[3][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_3_T_234 = mux(write_mask[3][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_3_T_235 = or(_ram_3_T_231, _ram_3_T_232) node _ram_3_T_236 = or(_ram_3_T_235, _ram_3_T_233) node _ram_3_T_237 = or(_ram_3_T_236, _ram_3_T_234) wire _ram_3_WIRE_37 : UInt<1> connect _ram_3_WIRE_37, _ram_3_T_237 connect _ram_3_WIRE_1.uses_memalu, _ram_3_WIRE_37 node _ram_3_T_238 = mux(write_mask[3][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_3_T_239 = mux(write_mask[3][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_3_T_240 = mux(write_mask[3][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_3_T_241 = mux(write_mask[3][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_3_T_242 = or(_ram_3_T_238, _ram_3_T_239) node _ram_3_T_243 = or(_ram_3_T_242, _ram_3_T_240) node _ram_3_T_244 = or(_ram_3_T_243, _ram_3_T_241) wire _ram_3_WIRE_38 : UInt<64> connect _ram_3_WIRE_38, _ram_3_T_244 connect _ram_3_WIRE_1.rs3_data, _ram_3_WIRE_38 node _ram_3_T_245 = mux(write_mask[3][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_3_T_246 = mux(write_mask[3][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_3_T_247 = mux(write_mask[3][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_3_T_248 = mux(write_mask[3][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_3_T_249 = or(_ram_3_T_245, _ram_3_T_246) node _ram_3_T_250 = or(_ram_3_T_249, _ram_3_T_247) node _ram_3_T_251 = or(_ram_3_T_250, _ram_3_T_248) wire _ram_3_WIRE_39 : UInt<64> connect _ram_3_WIRE_39, _ram_3_T_251 connect _ram_3_WIRE_1.rs2_data, _ram_3_WIRE_39 node _ram_3_T_252 = mux(write_mask[3][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_3_T_253 = mux(write_mask[3][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_3_T_254 = mux(write_mask[3][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_3_T_255 = mux(write_mask[3][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_3_T_256 = or(_ram_3_T_252, _ram_3_T_253) node _ram_3_T_257 = or(_ram_3_T_256, _ram_3_T_254) node _ram_3_T_258 = or(_ram_3_T_257, _ram_3_T_255) wire _ram_3_WIRE_40 : UInt<64> connect _ram_3_WIRE_40, _ram_3_T_258 connect _ram_3_WIRE_1.rs1_data, _ram_3_WIRE_40 node _ram_3_T_259 = mux(write_mask[3][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_3_T_260 = mux(write_mask[3][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_3_T_261 = mux(write_mask[3][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_3_T_262 = mux(write_mask[3][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_3_T_263 = or(_ram_3_T_259, _ram_3_T_260) node _ram_3_T_264 = or(_ram_3_T_263, _ram_3_T_261) node _ram_3_T_265 = or(_ram_3_T_264, _ram_3_T_262) wire _ram_3_WIRE_41 : UInt<1> connect _ram_3_WIRE_41, _ram_3_T_265 connect _ram_3_WIRE_1.needs_replay, _ram_3_WIRE_41 node _ram_3_T_266 = mux(write_mask[3][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_3_T_267 = mux(write_mask[3][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_3_T_268 = mux(write_mask[3][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_3_T_269 = mux(write_mask[3][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_3_T_270 = or(_ram_3_T_266, _ram_3_T_267) node _ram_3_T_271 = or(_ram_3_T_270, _ram_3_T_268) node _ram_3_T_272 = or(_ram_3_T_271, _ram_3_T_269) wire _ram_3_WIRE_42 : UInt<64> connect _ram_3_WIRE_42, _ram_3_T_272 connect _ram_3_WIRE_1.xcpt_cause, _ram_3_WIRE_42 node _ram_3_T_273 = mux(write_mask[3][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_3_T_274 = mux(write_mask[3][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_3_T_275 = mux(write_mask[3][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_3_T_276 = mux(write_mask[3][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_3_T_277 = or(_ram_3_T_273, _ram_3_T_274) node _ram_3_T_278 = or(_ram_3_T_277, _ram_3_T_275) node _ram_3_T_279 = or(_ram_3_T_278, _ram_3_T_276) wire _ram_3_WIRE_43 : UInt<1> connect _ram_3_WIRE_43, _ram_3_T_279 connect _ram_3_WIRE_1.xcpt, _ram_3_WIRE_43 node _ram_3_T_280 = mux(write_mask[3][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_3_T_281 = mux(write_mask[3][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_3_T_282 = mux(write_mask[3][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_3_T_283 = mux(write_mask[3][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_3_T_284 = or(_ram_3_T_280, _ram_3_T_281) node _ram_3_T_285 = or(_ram_3_T_284, _ram_3_T_282) node _ram_3_T_286 = or(_ram_3_T_285, _ram_3_T_283) wire _ram_3_WIRE_44 : UInt<1> connect _ram_3_WIRE_44, _ram_3_T_286 connect _ram_3_WIRE_1.taken, _ram_3_WIRE_44 node _ram_3_T_287 = mux(write_mask[3][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_3_T_288 = mux(write_mask[3][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_3_T_289 = mux(write_mask[3][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_3_T_290 = mux(write_mask[3][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_3_T_291 = or(_ram_3_T_287, _ram_3_T_288) node _ram_3_T_292 = or(_ram_3_T_291, _ram_3_T_289) node _ram_3_T_293 = or(_ram_3_T_292, _ram_3_T_290) wire _ram_3_WIRE_45 : UInt<3> connect _ram_3_WIRE_45, _ram_3_T_293 connect _ram_3_WIRE_1.ras_head, _ram_3_WIRE_45 wire _ram_3_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_3_T_294 = mux(write_mask[3][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_3_T_295 = mux(write_mask[3][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_3_T_296 = mux(write_mask[3][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_3_T_297 = mux(write_mask[3][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_3_T_298 = or(_ram_3_T_294, _ram_3_T_295) node _ram_3_T_299 = or(_ram_3_T_298, _ram_3_T_296) node _ram_3_T_300 = or(_ram_3_T_299, _ram_3_T_297) wire _ram_3_WIRE_47 : UInt<40> connect _ram_3_WIRE_47, _ram_3_T_300 connect _ram_3_WIRE_46.bits, _ram_3_WIRE_47 node _ram_3_T_301 = mux(write_mask[3][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_3_T_302 = mux(write_mask[3][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_3_T_303 = mux(write_mask[3][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_3_T_304 = mux(write_mask[3][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_3_T_305 = or(_ram_3_T_301, _ram_3_T_302) node _ram_3_T_306 = or(_ram_3_T_305, _ram_3_T_303) node _ram_3_T_307 = or(_ram_3_T_306, _ram_3_T_304) wire _ram_3_WIRE_48 : UInt<1> connect _ram_3_WIRE_48, _ram_3_T_307 connect _ram_3_WIRE_46.valid, _ram_3_WIRE_48 connect _ram_3_WIRE_1.next_pc, _ram_3_WIRE_46 node _ram_3_T_308 = mux(write_mask[3][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_3_T_309 = mux(write_mask[3][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_3_T_310 = mux(write_mask[3][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_3_T_311 = mux(write_mask[3][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_3_T_312 = or(_ram_3_T_308, _ram_3_T_309) node _ram_3_T_313 = or(_ram_3_T_312, _ram_3_T_310) node _ram_3_T_314 = or(_ram_3_T_313, _ram_3_T_311) wire _ram_3_WIRE_49 : UInt<1> connect _ram_3_WIRE_49, _ram_3_T_314 connect _ram_3_WIRE_1.sfb_shadow, _ram_3_WIRE_49 node _ram_3_T_315 = mux(write_mask[3][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_3_T_316 = mux(write_mask[3][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_3_T_317 = mux(write_mask[3][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_3_T_318 = mux(write_mask[3][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_3_T_319 = or(_ram_3_T_315, _ram_3_T_316) node _ram_3_T_320 = or(_ram_3_T_319, _ram_3_T_317) node _ram_3_T_321 = or(_ram_3_T_320, _ram_3_T_318) wire _ram_3_WIRE_50 : UInt<1> connect _ram_3_WIRE_50, _ram_3_T_321 connect _ram_3_WIRE_1.sfb_br, _ram_3_WIRE_50 wire _ram_3_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_3_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_3_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_3_T_322 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_3_T_323 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_3_T_324 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_3_T_325 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_3_T_326 = or(_ram_3_T_322, _ram_3_T_323) node _ram_3_T_327 = or(_ram_3_T_326, _ram_3_T_324) node _ram_3_T_328 = or(_ram_3_T_327, _ram_3_T_325) wire _ram_3_WIRE_54 : UInt<2> connect _ram_3_WIRE_54, _ram_3_T_328 connect _ram_3_WIRE_53.value, _ram_3_WIRE_54 node _ram_3_T_329 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_3_T_330 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_3_T_331 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_3_T_332 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_3_T_333 = or(_ram_3_T_329, _ram_3_T_330) node _ram_3_T_334 = or(_ram_3_T_333, _ram_3_T_331) node _ram_3_T_335 = or(_ram_3_T_334, _ram_3_T_332) wire _ram_3_WIRE_55 : UInt<8> connect _ram_3_WIRE_55, _ram_3_T_335 connect _ram_3_WIRE_53.history, _ram_3_WIRE_55 connect _ram_3_WIRE_52.bht, _ram_3_WIRE_53 node _ram_3_T_336 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_3_T_337 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_3_T_338 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_3_T_339 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_3_T_340 = or(_ram_3_T_336, _ram_3_T_337) node _ram_3_T_341 = or(_ram_3_T_340, _ram_3_T_338) node _ram_3_T_342 = or(_ram_3_T_341, _ram_3_T_339) wire _ram_3_WIRE_56 : UInt<6> connect _ram_3_WIRE_56, _ram_3_T_342 connect _ram_3_WIRE_52.entry, _ram_3_WIRE_56 node _ram_3_T_343 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_3_T_344 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_3_T_345 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_3_T_346 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_3_T_347 = or(_ram_3_T_343, _ram_3_T_344) node _ram_3_T_348 = or(_ram_3_T_347, _ram_3_T_345) node _ram_3_T_349 = or(_ram_3_T_348, _ram_3_T_346) wire _ram_3_WIRE_57 : UInt<39> connect _ram_3_WIRE_57, _ram_3_T_349 connect _ram_3_WIRE_52.target, _ram_3_WIRE_57 node _ram_3_T_350 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_3_T_351 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_3_T_352 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_3_T_353 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_3_T_354 = or(_ram_3_T_350, _ram_3_T_351) node _ram_3_T_355 = or(_ram_3_T_354, _ram_3_T_352) node _ram_3_T_356 = or(_ram_3_T_355, _ram_3_T_353) wire _ram_3_WIRE_58 : UInt<2> connect _ram_3_WIRE_58, _ram_3_T_356 connect _ram_3_WIRE_52.bridx, _ram_3_WIRE_58 node _ram_3_T_357 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_3_T_358 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_3_T_359 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_3_T_360 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_3_T_361 = or(_ram_3_T_357, _ram_3_T_358) node _ram_3_T_362 = or(_ram_3_T_361, _ram_3_T_359) node _ram_3_T_363 = or(_ram_3_T_362, _ram_3_T_360) wire _ram_3_WIRE_59 : UInt<4> connect _ram_3_WIRE_59, _ram_3_T_363 connect _ram_3_WIRE_52.mask, _ram_3_WIRE_59 node _ram_3_T_364 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_3_T_365 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_3_T_366 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_3_T_367 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_3_T_368 = or(_ram_3_T_364, _ram_3_T_365) node _ram_3_T_369 = or(_ram_3_T_368, _ram_3_T_366) node _ram_3_T_370 = or(_ram_3_T_369, _ram_3_T_367) wire _ram_3_WIRE_60 : UInt<1> connect _ram_3_WIRE_60, _ram_3_T_370 connect _ram_3_WIRE_52.taken, _ram_3_WIRE_60 node _ram_3_T_371 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_3_T_372 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_3_T_373 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_3_T_374 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_3_T_375 = or(_ram_3_T_371, _ram_3_T_372) node _ram_3_T_376 = or(_ram_3_T_375, _ram_3_T_373) node _ram_3_T_377 = or(_ram_3_T_376, _ram_3_T_374) wire _ram_3_WIRE_61 : UInt<2> connect _ram_3_WIRE_61, _ram_3_T_377 connect _ram_3_WIRE_52.cfiType, _ram_3_WIRE_61 connect _ram_3_WIRE_51.bits, _ram_3_WIRE_52 node _ram_3_T_378 = mux(write_mask[3][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_3_T_379 = mux(write_mask[3][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_3_T_380 = mux(write_mask[3][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_3_T_381 = mux(write_mask[3][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_3_T_382 = or(_ram_3_T_378, _ram_3_T_379) node _ram_3_T_383 = or(_ram_3_T_382, _ram_3_T_380) node _ram_3_T_384 = or(_ram_3_T_383, _ram_3_T_381) wire _ram_3_WIRE_62 : UInt<1> connect _ram_3_WIRE_62, _ram_3_T_384 connect _ram_3_WIRE_51.valid, _ram_3_WIRE_62 connect _ram_3_WIRE_1.btb_resp, _ram_3_WIRE_51 node _ram_3_T_385 = mux(write_mask[3][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_3_T_386 = mux(write_mask[3][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_3_T_387 = mux(write_mask[3][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_3_T_388 = mux(write_mask[3][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_3_T_389 = or(_ram_3_T_385, _ram_3_T_386) node _ram_3_T_390 = or(_ram_3_T_389, _ram_3_T_387) node _ram_3_T_391 = or(_ram_3_T_390, _ram_3_T_388) wire _ram_3_WIRE_63 : UInt<1> connect _ram_3_WIRE_63, _ram_3_T_391 connect _ram_3_WIRE_1.sets_vcfg, _ram_3_WIRE_63 node _ram_3_T_392 = mux(write_mask[3][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_3_T_393 = mux(write_mask[3][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_3_T_394 = mux(write_mask[3][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_3_T_395 = mux(write_mask[3][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_3_T_396 = or(_ram_3_T_392, _ram_3_T_393) node _ram_3_T_397 = or(_ram_3_T_396, _ram_3_T_394) node _ram_3_T_398 = or(_ram_3_T_397, _ram_3_T_395) wire _ram_3_WIRE_64 : UInt<1> connect _ram_3_WIRE_64, _ram_3_T_398 connect _ram_3_WIRE_1.rvc, _ram_3_WIRE_64 wire _ram_3_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_3_T_399 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_3_T_400 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_3_T_401 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_3_T_402 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_3_T_403 = or(_ram_3_T_399, _ram_3_T_400) node _ram_3_T_404 = or(_ram_3_T_403, _ram_3_T_401) node _ram_3_T_405 = or(_ram_3_T_404, _ram_3_T_402) wire _ram_3_WIRE_66 : UInt<1> connect _ram_3_WIRE_66, _ram_3_T_405 connect _ram_3_WIRE_65.vec, _ram_3_WIRE_66 node _ram_3_T_406 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_3_T_407 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_3_T_408 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_3_T_409 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_3_T_410 = or(_ram_3_T_406, _ram_3_T_407) node _ram_3_T_411 = or(_ram_3_T_410, _ram_3_T_408) node _ram_3_T_412 = or(_ram_3_T_411, _ram_3_T_409) wire _ram_3_WIRE_67 : UInt<1> connect _ram_3_WIRE_67, _ram_3_T_412 connect _ram_3_WIRE_65.wflags, _ram_3_WIRE_67 node _ram_3_T_413 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_3_T_414 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_3_T_415 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_3_T_416 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_3_T_417 = or(_ram_3_T_413, _ram_3_T_414) node _ram_3_T_418 = or(_ram_3_T_417, _ram_3_T_415) node _ram_3_T_419 = or(_ram_3_T_418, _ram_3_T_416) wire _ram_3_WIRE_68 : UInt<1> connect _ram_3_WIRE_68, _ram_3_T_419 connect _ram_3_WIRE_65.sqrt, _ram_3_WIRE_68 node _ram_3_T_420 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_3_T_421 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_3_T_422 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_3_T_423 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_3_T_424 = or(_ram_3_T_420, _ram_3_T_421) node _ram_3_T_425 = or(_ram_3_T_424, _ram_3_T_422) node _ram_3_T_426 = or(_ram_3_T_425, _ram_3_T_423) wire _ram_3_WIRE_69 : UInt<1> connect _ram_3_WIRE_69, _ram_3_T_426 connect _ram_3_WIRE_65.div, _ram_3_WIRE_69 node _ram_3_T_427 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_3_T_428 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_3_T_429 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_3_T_430 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_3_T_431 = or(_ram_3_T_427, _ram_3_T_428) node _ram_3_T_432 = or(_ram_3_T_431, _ram_3_T_429) node _ram_3_T_433 = or(_ram_3_T_432, _ram_3_T_430) wire _ram_3_WIRE_70 : UInt<1> connect _ram_3_WIRE_70, _ram_3_T_433 connect _ram_3_WIRE_65.fma, _ram_3_WIRE_70 node _ram_3_T_434 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_3_T_435 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_3_T_436 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_3_T_437 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_3_T_438 = or(_ram_3_T_434, _ram_3_T_435) node _ram_3_T_439 = or(_ram_3_T_438, _ram_3_T_436) node _ram_3_T_440 = or(_ram_3_T_439, _ram_3_T_437) wire _ram_3_WIRE_71 : UInt<1> connect _ram_3_WIRE_71, _ram_3_T_440 connect _ram_3_WIRE_65.fastpipe, _ram_3_WIRE_71 node _ram_3_T_441 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_3_T_442 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_3_T_443 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_3_T_444 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_3_T_445 = or(_ram_3_T_441, _ram_3_T_442) node _ram_3_T_446 = or(_ram_3_T_445, _ram_3_T_443) node _ram_3_T_447 = or(_ram_3_T_446, _ram_3_T_444) wire _ram_3_WIRE_72 : UInt<1> connect _ram_3_WIRE_72, _ram_3_T_447 connect _ram_3_WIRE_65.toint, _ram_3_WIRE_72 node _ram_3_T_448 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_3_T_449 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_3_T_450 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_3_T_451 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_3_T_452 = or(_ram_3_T_448, _ram_3_T_449) node _ram_3_T_453 = or(_ram_3_T_452, _ram_3_T_450) node _ram_3_T_454 = or(_ram_3_T_453, _ram_3_T_451) wire _ram_3_WIRE_73 : UInt<1> connect _ram_3_WIRE_73, _ram_3_T_454 connect _ram_3_WIRE_65.fromint, _ram_3_WIRE_73 node _ram_3_T_455 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_3_T_456 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_3_T_457 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_3_T_458 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_3_T_459 = or(_ram_3_T_455, _ram_3_T_456) node _ram_3_T_460 = or(_ram_3_T_459, _ram_3_T_457) node _ram_3_T_461 = or(_ram_3_T_460, _ram_3_T_458) wire _ram_3_WIRE_74 : UInt<2> connect _ram_3_WIRE_74, _ram_3_T_461 connect _ram_3_WIRE_65.typeTagOut, _ram_3_WIRE_74 node _ram_3_T_462 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_3_T_463 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_3_T_464 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_3_T_465 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_3_T_466 = or(_ram_3_T_462, _ram_3_T_463) node _ram_3_T_467 = or(_ram_3_T_466, _ram_3_T_464) node _ram_3_T_468 = or(_ram_3_T_467, _ram_3_T_465) wire _ram_3_WIRE_75 : UInt<2> connect _ram_3_WIRE_75, _ram_3_T_468 connect _ram_3_WIRE_65.typeTagIn, _ram_3_WIRE_75 node _ram_3_T_469 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_3_T_470 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_3_T_471 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_3_T_472 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_3_T_473 = or(_ram_3_T_469, _ram_3_T_470) node _ram_3_T_474 = or(_ram_3_T_473, _ram_3_T_471) node _ram_3_T_475 = or(_ram_3_T_474, _ram_3_T_472) wire _ram_3_WIRE_76 : UInt<1> connect _ram_3_WIRE_76, _ram_3_T_475 connect _ram_3_WIRE_65.swap23, _ram_3_WIRE_76 node _ram_3_T_476 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_3_T_477 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_3_T_478 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_3_T_479 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_3_T_480 = or(_ram_3_T_476, _ram_3_T_477) node _ram_3_T_481 = or(_ram_3_T_480, _ram_3_T_478) node _ram_3_T_482 = or(_ram_3_T_481, _ram_3_T_479) wire _ram_3_WIRE_77 : UInt<1> connect _ram_3_WIRE_77, _ram_3_T_482 connect _ram_3_WIRE_65.swap12, _ram_3_WIRE_77 node _ram_3_T_483 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_3_T_484 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_3_T_485 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_3_T_486 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_3_T_487 = or(_ram_3_T_483, _ram_3_T_484) node _ram_3_T_488 = or(_ram_3_T_487, _ram_3_T_485) node _ram_3_T_489 = or(_ram_3_T_488, _ram_3_T_486) wire _ram_3_WIRE_78 : UInt<1> connect _ram_3_WIRE_78, _ram_3_T_489 connect _ram_3_WIRE_65.ren3, _ram_3_WIRE_78 node _ram_3_T_490 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_3_T_491 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_3_T_492 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_3_T_493 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_3_T_494 = or(_ram_3_T_490, _ram_3_T_491) node _ram_3_T_495 = or(_ram_3_T_494, _ram_3_T_492) node _ram_3_T_496 = or(_ram_3_T_495, _ram_3_T_493) wire _ram_3_WIRE_79 : UInt<1> connect _ram_3_WIRE_79, _ram_3_T_496 connect _ram_3_WIRE_65.ren2, _ram_3_WIRE_79 node _ram_3_T_497 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_3_T_498 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_3_T_499 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_3_T_500 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_3_T_501 = or(_ram_3_T_497, _ram_3_T_498) node _ram_3_T_502 = or(_ram_3_T_501, _ram_3_T_499) node _ram_3_T_503 = or(_ram_3_T_502, _ram_3_T_500) wire _ram_3_WIRE_80 : UInt<1> connect _ram_3_WIRE_80, _ram_3_T_503 connect _ram_3_WIRE_65.ren1, _ram_3_WIRE_80 node _ram_3_T_504 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_3_T_505 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_3_T_506 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_3_T_507 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_3_T_508 = or(_ram_3_T_504, _ram_3_T_505) node _ram_3_T_509 = or(_ram_3_T_508, _ram_3_T_506) node _ram_3_T_510 = or(_ram_3_T_509, _ram_3_T_507) wire _ram_3_WIRE_81 : UInt<1> connect _ram_3_WIRE_81, _ram_3_T_510 connect _ram_3_WIRE_65.wen, _ram_3_WIRE_81 node _ram_3_T_511 = mux(write_mask[3][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_3_T_512 = mux(write_mask[3][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_3_T_513 = mux(write_mask[3][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_3_T_514 = mux(write_mask[3][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_3_T_515 = or(_ram_3_T_511, _ram_3_T_512) node _ram_3_T_516 = or(_ram_3_T_515, _ram_3_T_513) node _ram_3_T_517 = or(_ram_3_T_516, _ram_3_T_514) wire _ram_3_WIRE_82 : UInt<1> connect _ram_3_WIRE_82, _ram_3_T_517 connect _ram_3_WIRE_65.ldst, _ram_3_WIRE_82 connect _ram_3_WIRE_1.fp_ctrl, _ram_3_WIRE_65 wire _ram_3_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_3_T_518 = mux(write_mask[3][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_3_T_519 = mux(write_mask[3][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_3_T_520 = mux(write_mask[3][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_3_T_521 = mux(write_mask[3][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_3_T_522 = or(_ram_3_T_518, _ram_3_T_519) node _ram_3_T_523 = or(_ram_3_T_522, _ram_3_T_520) node _ram_3_T_524 = or(_ram_3_T_523, _ram_3_T_521) wire _ram_3_WIRE_84 : UInt<1> connect _ram_3_WIRE_84, _ram_3_T_524 connect _ram_3_WIRE_83.vec, _ram_3_WIRE_84 node _ram_3_T_525 = mux(write_mask[3][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_3_T_526 = mux(write_mask[3][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_3_T_527 = mux(write_mask[3][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_3_T_528 = mux(write_mask[3][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_3_T_529 = or(_ram_3_T_525, _ram_3_T_526) node _ram_3_T_530 = or(_ram_3_T_529, _ram_3_T_527) node _ram_3_T_531 = or(_ram_3_T_530, _ram_3_T_528) wire _ram_3_WIRE_85 : UInt<1> connect _ram_3_WIRE_85, _ram_3_T_531 connect _ram_3_WIRE_83.dp, _ram_3_WIRE_85 node _ram_3_T_532 = mux(write_mask[3][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_3_T_533 = mux(write_mask[3][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_3_T_534 = mux(write_mask[3][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_3_T_535 = mux(write_mask[3][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_3_T_536 = or(_ram_3_T_532, _ram_3_T_533) node _ram_3_T_537 = or(_ram_3_T_536, _ram_3_T_534) node _ram_3_T_538 = or(_ram_3_T_537, _ram_3_T_535) wire _ram_3_WIRE_86 : UInt<1> connect _ram_3_WIRE_86, _ram_3_T_538 connect _ram_3_WIRE_83.amo, _ram_3_WIRE_86 node _ram_3_T_539 = mux(write_mask[3][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_3_T_540 = mux(write_mask[3][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_3_T_541 = mux(write_mask[3][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_3_T_542 = mux(write_mask[3][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_3_T_543 = or(_ram_3_T_539, _ram_3_T_540) node _ram_3_T_544 = or(_ram_3_T_543, _ram_3_T_541) node _ram_3_T_545 = or(_ram_3_T_544, _ram_3_T_542) wire _ram_3_WIRE_87 : UInt<1> connect _ram_3_WIRE_87, _ram_3_T_545 connect _ram_3_WIRE_83.fence, _ram_3_WIRE_87 node _ram_3_T_546 = mux(write_mask[3][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_3_T_547 = mux(write_mask[3][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_3_T_548 = mux(write_mask[3][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_3_T_549 = mux(write_mask[3][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_3_T_550 = or(_ram_3_T_546, _ram_3_T_547) node _ram_3_T_551 = or(_ram_3_T_550, _ram_3_T_548) node _ram_3_T_552 = or(_ram_3_T_551, _ram_3_T_549) wire _ram_3_WIRE_88 : UInt<1> connect _ram_3_WIRE_88, _ram_3_T_552 connect _ram_3_WIRE_83.fence_i, _ram_3_WIRE_88 node _ram_3_T_553 = mux(write_mask[3][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_3_T_554 = mux(write_mask[3][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_3_T_555 = mux(write_mask[3][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_3_T_556 = mux(write_mask[3][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_3_T_557 = or(_ram_3_T_553, _ram_3_T_554) node _ram_3_T_558 = or(_ram_3_T_557, _ram_3_T_555) node _ram_3_T_559 = or(_ram_3_T_558, _ram_3_T_556) wire _ram_3_WIRE_89 : UInt<3> connect _ram_3_WIRE_89, _ram_3_T_559 connect _ram_3_WIRE_83.csr, _ram_3_WIRE_89 node _ram_3_T_560 = mux(write_mask[3][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_3_T_561 = mux(write_mask[3][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_3_T_562 = mux(write_mask[3][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_3_T_563 = mux(write_mask[3][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_3_T_564 = or(_ram_3_T_560, _ram_3_T_561) node _ram_3_T_565 = or(_ram_3_T_564, _ram_3_T_562) node _ram_3_T_566 = or(_ram_3_T_565, _ram_3_T_563) wire _ram_3_WIRE_90 : UInt<1> connect _ram_3_WIRE_90, _ram_3_T_566 connect _ram_3_WIRE_83.wxd, _ram_3_WIRE_90 node _ram_3_T_567 = mux(write_mask[3][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_3_T_568 = mux(write_mask[3][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_3_T_569 = mux(write_mask[3][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_3_T_570 = mux(write_mask[3][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_3_T_571 = or(_ram_3_T_567, _ram_3_T_568) node _ram_3_T_572 = or(_ram_3_T_571, _ram_3_T_569) node _ram_3_T_573 = or(_ram_3_T_572, _ram_3_T_570) wire _ram_3_WIRE_91 : UInt<1> connect _ram_3_WIRE_91, _ram_3_T_573 connect _ram_3_WIRE_83.div, _ram_3_WIRE_91 node _ram_3_T_574 = mux(write_mask[3][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_3_T_575 = mux(write_mask[3][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_3_T_576 = mux(write_mask[3][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_3_T_577 = mux(write_mask[3][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_3_T_578 = or(_ram_3_T_574, _ram_3_T_575) node _ram_3_T_579 = or(_ram_3_T_578, _ram_3_T_576) node _ram_3_T_580 = or(_ram_3_T_579, _ram_3_T_577) wire _ram_3_WIRE_92 : UInt<1> connect _ram_3_WIRE_92, _ram_3_T_580 connect _ram_3_WIRE_83.mul, _ram_3_WIRE_92 node _ram_3_T_581 = mux(write_mask[3][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_3_T_582 = mux(write_mask[3][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_3_T_583 = mux(write_mask[3][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_3_T_584 = mux(write_mask[3][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_3_T_585 = or(_ram_3_T_581, _ram_3_T_582) node _ram_3_T_586 = or(_ram_3_T_585, _ram_3_T_583) node _ram_3_T_587 = or(_ram_3_T_586, _ram_3_T_584) wire _ram_3_WIRE_93 : UInt<1> connect _ram_3_WIRE_93, _ram_3_T_587 connect _ram_3_WIRE_83.wfd, _ram_3_WIRE_93 node _ram_3_T_588 = mux(write_mask[3][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_3_T_589 = mux(write_mask[3][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_3_T_590 = mux(write_mask[3][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_3_T_591 = mux(write_mask[3][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_3_T_592 = or(_ram_3_T_588, _ram_3_T_589) node _ram_3_T_593 = or(_ram_3_T_592, _ram_3_T_590) node _ram_3_T_594 = or(_ram_3_T_593, _ram_3_T_591) wire _ram_3_WIRE_94 : UInt<1> connect _ram_3_WIRE_94, _ram_3_T_594 connect _ram_3_WIRE_83.rfs3, _ram_3_WIRE_94 node _ram_3_T_595 = mux(write_mask[3][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_3_T_596 = mux(write_mask[3][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_3_T_597 = mux(write_mask[3][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_3_T_598 = mux(write_mask[3][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_3_T_599 = or(_ram_3_T_595, _ram_3_T_596) node _ram_3_T_600 = or(_ram_3_T_599, _ram_3_T_597) node _ram_3_T_601 = or(_ram_3_T_600, _ram_3_T_598) wire _ram_3_WIRE_95 : UInt<1> connect _ram_3_WIRE_95, _ram_3_T_601 connect _ram_3_WIRE_83.rfs2, _ram_3_WIRE_95 node _ram_3_T_602 = mux(write_mask[3][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_3_T_603 = mux(write_mask[3][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_3_T_604 = mux(write_mask[3][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_3_T_605 = mux(write_mask[3][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_3_T_606 = or(_ram_3_T_602, _ram_3_T_603) node _ram_3_T_607 = or(_ram_3_T_606, _ram_3_T_604) node _ram_3_T_608 = or(_ram_3_T_607, _ram_3_T_605) wire _ram_3_WIRE_96 : UInt<1> connect _ram_3_WIRE_96, _ram_3_T_608 connect _ram_3_WIRE_83.rfs1, _ram_3_WIRE_96 node _ram_3_T_609 = mux(write_mask[3][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_3_T_610 = mux(write_mask[3][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_3_T_611 = mux(write_mask[3][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_3_T_612 = mux(write_mask[3][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_3_T_613 = or(_ram_3_T_609, _ram_3_T_610) node _ram_3_T_614 = or(_ram_3_T_613, _ram_3_T_611) node _ram_3_T_615 = or(_ram_3_T_614, _ram_3_T_612) wire _ram_3_WIRE_97 : UInt<5> connect _ram_3_WIRE_97, _ram_3_T_615 connect _ram_3_WIRE_83.mem_cmd, _ram_3_WIRE_97 node _ram_3_T_616 = mux(write_mask[3][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_3_T_617 = mux(write_mask[3][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_3_T_618 = mux(write_mask[3][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_3_T_619 = mux(write_mask[3][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_3_T_620 = or(_ram_3_T_616, _ram_3_T_617) node _ram_3_T_621 = or(_ram_3_T_620, _ram_3_T_618) node _ram_3_T_622 = or(_ram_3_T_621, _ram_3_T_619) wire _ram_3_WIRE_98 : UInt<1> connect _ram_3_WIRE_98, _ram_3_T_622 connect _ram_3_WIRE_83.mem, _ram_3_WIRE_98 node _ram_3_T_623 = mux(write_mask[3][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_3_T_624 = mux(write_mask[3][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_3_T_625 = mux(write_mask[3][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_3_T_626 = mux(write_mask[3][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_3_T_627 = or(_ram_3_T_623, _ram_3_T_624) node _ram_3_T_628 = or(_ram_3_T_627, _ram_3_T_625) node _ram_3_T_629 = or(_ram_3_T_628, _ram_3_T_626) wire _ram_3_WIRE_99 : UInt<5> connect _ram_3_WIRE_99, _ram_3_T_629 connect _ram_3_WIRE_83.alu_fn, _ram_3_WIRE_99 node _ram_3_T_630 = mux(write_mask[3][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_3_T_631 = mux(write_mask[3][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_3_T_632 = mux(write_mask[3][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_3_T_633 = mux(write_mask[3][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_3_T_634 = or(_ram_3_T_630, _ram_3_T_631) node _ram_3_T_635 = or(_ram_3_T_634, _ram_3_T_632) node _ram_3_T_636 = or(_ram_3_T_635, _ram_3_T_633) wire _ram_3_WIRE_100 : UInt<1> connect _ram_3_WIRE_100, _ram_3_T_636 connect _ram_3_WIRE_83.alu_dw, _ram_3_WIRE_100 node _ram_3_T_637 = mux(write_mask[3][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_3_T_638 = mux(write_mask[3][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_3_T_639 = mux(write_mask[3][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_3_T_640 = mux(write_mask[3][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_3_T_641 = or(_ram_3_T_637, _ram_3_T_638) node _ram_3_T_642 = or(_ram_3_T_641, _ram_3_T_639) node _ram_3_T_643 = or(_ram_3_T_642, _ram_3_T_640) wire _ram_3_WIRE_101 : UInt<3> connect _ram_3_WIRE_101, _ram_3_T_643 connect _ram_3_WIRE_83.sel_imm, _ram_3_WIRE_101 node _ram_3_T_644 = mux(write_mask[3][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_3_T_645 = mux(write_mask[3][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_3_T_646 = mux(write_mask[3][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_3_T_647 = mux(write_mask[3][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_3_T_648 = or(_ram_3_T_644, _ram_3_T_645) node _ram_3_T_649 = or(_ram_3_T_648, _ram_3_T_646) node _ram_3_T_650 = or(_ram_3_T_649, _ram_3_T_647) wire _ram_3_WIRE_102 : UInt<2> connect _ram_3_WIRE_102, _ram_3_T_650 connect _ram_3_WIRE_83.sel_alu1, _ram_3_WIRE_102 node _ram_3_T_651 = mux(write_mask[3][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_3_T_652 = mux(write_mask[3][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_3_T_653 = mux(write_mask[3][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_3_T_654 = mux(write_mask[3][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_3_T_655 = or(_ram_3_T_651, _ram_3_T_652) node _ram_3_T_656 = or(_ram_3_T_655, _ram_3_T_653) node _ram_3_T_657 = or(_ram_3_T_656, _ram_3_T_654) wire _ram_3_WIRE_103 : UInt<3> connect _ram_3_WIRE_103, _ram_3_T_657 connect _ram_3_WIRE_83.sel_alu2, _ram_3_WIRE_103 node _ram_3_T_658 = mux(write_mask[3][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_3_T_659 = mux(write_mask[3][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_3_T_660 = mux(write_mask[3][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_3_T_661 = mux(write_mask[3][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_3_T_662 = or(_ram_3_T_658, _ram_3_T_659) node _ram_3_T_663 = or(_ram_3_T_662, _ram_3_T_660) node _ram_3_T_664 = or(_ram_3_T_663, _ram_3_T_661) wire _ram_3_WIRE_104 : UInt<1> connect _ram_3_WIRE_104, _ram_3_T_664 connect _ram_3_WIRE_83.rxs1, _ram_3_WIRE_104 node _ram_3_T_665 = mux(write_mask[3][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_3_T_666 = mux(write_mask[3][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_3_T_667 = mux(write_mask[3][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_3_T_668 = mux(write_mask[3][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_3_T_669 = or(_ram_3_T_665, _ram_3_T_666) node _ram_3_T_670 = or(_ram_3_T_669, _ram_3_T_667) node _ram_3_T_671 = or(_ram_3_T_670, _ram_3_T_668) wire _ram_3_WIRE_105 : UInt<1> connect _ram_3_WIRE_105, _ram_3_T_671 connect _ram_3_WIRE_83.rxs2, _ram_3_WIRE_105 node _ram_3_T_672 = mux(write_mask[3][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_3_T_673 = mux(write_mask[3][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_3_T_674 = mux(write_mask[3][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_3_T_675 = mux(write_mask[3][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_3_T_676 = or(_ram_3_T_672, _ram_3_T_673) node _ram_3_T_677 = or(_ram_3_T_676, _ram_3_T_674) node _ram_3_T_678 = or(_ram_3_T_677, _ram_3_T_675) wire _ram_3_WIRE_106 : UInt<1> connect _ram_3_WIRE_106, _ram_3_T_678 connect _ram_3_WIRE_83.jalr, _ram_3_WIRE_106 node _ram_3_T_679 = mux(write_mask[3][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_3_T_680 = mux(write_mask[3][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_3_T_681 = mux(write_mask[3][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_3_T_682 = mux(write_mask[3][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_3_T_683 = or(_ram_3_T_679, _ram_3_T_680) node _ram_3_T_684 = or(_ram_3_T_683, _ram_3_T_681) node _ram_3_T_685 = or(_ram_3_T_684, _ram_3_T_682) wire _ram_3_WIRE_107 : UInt<1> connect _ram_3_WIRE_107, _ram_3_T_685 connect _ram_3_WIRE_83.jal, _ram_3_WIRE_107 node _ram_3_T_686 = mux(write_mask[3][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_3_T_687 = mux(write_mask[3][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_3_T_688 = mux(write_mask[3][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_3_T_689 = mux(write_mask[3][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_3_T_690 = or(_ram_3_T_686, _ram_3_T_687) node _ram_3_T_691 = or(_ram_3_T_690, _ram_3_T_688) node _ram_3_T_692 = or(_ram_3_T_691, _ram_3_T_689) wire _ram_3_WIRE_108 : UInt<1> connect _ram_3_WIRE_108, _ram_3_T_692 connect _ram_3_WIRE_83.branch, _ram_3_WIRE_108 node _ram_3_T_693 = mux(write_mask[3][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_3_T_694 = mux(write_mask[3][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_3_T_695 = mux(write_mask[3][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_3_T_696 = mux(write_mask[3][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_3_T_697 = or(_ram_3_T_693, _ram_3_T_694) node _ram_3_T_698 = or(_ram_3_T_697, _ram_3_T_695) node _ram_3_T_699 = or(_ram_3_T_698, _ram_3_T_696) wire _ram_3_WIRE_109 : UInt<1> connect _ram_3_WIRE_109, _ram_3_T_699 connect _ram_3_WIRE_83.rocc, _ram_3_WIRE_109 node _ram_3_T_700 = mux(write_mask[3][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_3_T_701 = mux(write_mask[3][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_3_T_702 = mux(write_mask[3][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_3_T_703 = mux(write_mask[3][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_3_T_704 = or(_ram_3_T_700, _ram_3_T_701) node _ram_3_T_705 = or(_ram_3_T_704, _ram_3_T_702) node _ram_3_T_706 = or(_ram_3_T_705, _ram_3_T_703) wire _ram_3_WIRE_110 : UInt<1> connect _ram_3_WIRE_110, _ram_3_T_706 connect _ram_3_WIRE_83.fp, _ram_3_WIRE_110 node _ram_3_T_707 = mux(write_mask[3][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_3_T_708 = mux(write_mask[3][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_3_T_709 = mux(write_mask[3][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_3_T_710 = mux(write_mask[3][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_3_T_711 = or(_ram_3_T_707, _ram_3_T_708) node _ram_3_T_712 = or(_ram_3_T_711, _ram_3_T_709) node _ram_3_T_713 = or(_ram_3_T_712, _ram_3_T_710) wire _ram_3_WIRE_111 : UInt<1> connect _ram_3_WIRE_111, _ram_3_T_713 connect _ram_3_WIRE_83.legal, _ram_3_WIRE_111 connect _ram_3_WIRE_1.ctrl, _ram_3_WIRE_83 node _ram_3_T_714 = mux(write_mask[3][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_3_T_715 = mux(write_mask[3][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_3_T_716 = mux(write_mask[3][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_3_T_717 = mux(write_mask[3][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_3_T_718 = or(_ram_3_T_714, _ram_3_T_715) node _ram_3_T_719 = or(_ram_3_T_718, _ram_3_T_716) node _ram_3_T_720 = or(_ram_3_T_719, _ram_3_T_717) wire _ram_3_WIRE_112 : UInt<1> connect _ram_3_WIRE_112, _ram_3_T_720 connect _ram_3_WIRE_1.edge_inst, _ram_3_WIRE_112 node _ram_3_T_721 = mux(write_mask[3][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_3_T_722 = mux(write_mask[3][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_3_T_723 = mux(write_mask[3][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_3_T_724 = mux(write_mask[3][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_3_T_725 = or(_ram_3_T_721, _ram_3_T_722) node _ram_3_T_726 = or(_ram_3_T_725, _ram_3_T_723) node _ram_3_T_727 = or(_ram_3_T_726, _ram_3_T_724) wire _ram_3_WIRE_113 : UInt<40> connect _ram_3_WIRE_113, _ram_3_T_727 connect _ram_3_WIRE_1.pc, _ram_3_WIRE_113 node _ram_3_T_728 = mux(write_mask[3][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_3_T_729 = mux(write_mask[3][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_3_T_730 = mux(write_mask[3][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_3_T_731 = mux(write_mask[3][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_3_T_732 = or(_ram_3_T_728, _ram_3_T_729) node _ram_3_T_733 = or(_ram_3_T_732, _ram_3_T_730) node _ram_3_T_734 = or(_ram_3_T_733, _ram_3_T_731) wire _ram_3_WIRE_114 : UInt<32> connect _ram_3_WIRE_114, _ram_3_T_734 connect _ram_3_WIRE_1.raw_inst, _ram_3_WIRE_114 node _ram_3_T_735 = mux(write_mask[3][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_3_T_736 = mux(write_mask[3][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_3_T_737 = mux(write_mask[3][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_3_T_738 = mux(write_mask[3][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_3_T_739 = or(_ram_3_T_735, _ram_3_T_736) node _ram_3_T_740 = or(_ram_3_T_739, _ram_3_T_737) node _ram_3_T_741 = or(_ram_3_T_740, _ram_3_T_738) wire _ram_3_WIRE_115 : UInt<32> connect _ram_3_WIRE_115, _ram_3_T_741 connect _ram_3_WIRE_1.inst, _ram_3_WIRE_115 connect _ram_3_WIRE.bits, _ram_3_WIRE_1 node _ram_3_T_742 = mux(write_mask[3][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_3_T_743 = mux(write_mask[3][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_3_T_744 = mux(write_mask[3][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_3_T_745 = mux(write_mask[3][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_3_T_746 = or(_ram_3_T_742, _ram_3_T_743) node _ram_3_T_747 = or(_ram_3_T_746, _ram_3_T_744) node _ram_3_T_748 = or(_ram_3_T_747, _ram_3_T_745) wire _ram_3_WIRE_116 : UInt<1> connect _ram_3_WIRE_116, _ram_3_T_748 connect _ram_3_WIRE.valid, _ram_3_WIRE_116 connect ram[3], _ram_3_WIRE node _T_25 = eq(ram[4].valid, UInt<1>(0h0)) when _T_25 : wire _ram_4_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_4_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_4_T = mux(write_mask[4][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_4_T_1 = mux(write_mask[4][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_4_T_2 = mux(write_mask[4][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_4_T_3 = mux(write_mask[4][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_4_T_4 = or(_ram_4_T, _ram_4_T_1) node _ram_4_T_5 = or(_ram_4_T_4, _ram_4_T_2) node _ram_4_T_6 = or(_ram_4_T_5, _ram_4_T_3) wire _ram_4_WIRE_2 : UInt<1> connect _ram_4_WIRE_2, _ram_4_T_6 connect _ram_4_WIRE_1.flush_pipe, _ram_4_WIRE_2 node _ram_4_T_7 = mux(write_mask[4][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_4_T_8 = mux(write_mask[4][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_4_T_9 = mux(write_mask[4][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_4_T_10 = mux(write_mask[4][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_4_T_11 = or(_ram_4_T_7, _ram_4_T_8) node _ram_4_T_12 = or(_ram_4_T_11, _ram_4_T_9) node _ram_4_T_13 = or(_ram_4_T_12, _ram_4_T_10) wire _ram_4_WIRE_3 : UInt<2> connect _ram_4_WIRE_3, _ram_4_T_13 connect _ram_4_WIRE_1.mem_size, _ram_4_WIRE_3 wire _ram_4_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_4_T_14 = mux(write_mask[4][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_4_T_15 = mux(write_mask[4][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_4_T_16 = mux(write_mask[4][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_4_T_17 = mux(write_mask[4][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_4_T_18 = or(_ram_4_T_14, _ram_4_T_15) node _ram_4_T_19 = or(_ram_4_T_18, _ram_4_T_16) node _ram_4_T_20 = or(_ram_4_T_19, _ram_4_T_17) wire _ram_4_WIRE_5 : UInt<65> connect _ram_4_WIRE_5, _ram_4_T_20 connect _ram_4_WIRE_4.in3, _ram_4_WIRE_5 node _ram_4_T_21 = mux(write_mask[4][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_4_T_22 = mux(write_mask[4][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_4_T_23 = mux(write_mask[4][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_4_T_24 = mux(write_mask[4][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_4_T_25 = or(_ram_4_T_21, _ram_4_T_22) node _ram_4_T_26 = or(_ram_4_T_25, _ram_4_T_23) node _ram_4_T_27 = or(_ram_4_T_26, _ram_4_T_24) wire _ram_4_WIRE_6 : UInt<65> connect _ram_4_WIRE_6, _ram_4_T_27 connect _ram_4_WIRE_4.in2, _ram_4_WIRE_6 node _ram_4_T_28 = mux(write_mask[4][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_4_T_29 = mux(write_mask[4][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_4_T_30 = mux(write_mask[4][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_4_T_31 = mux(write_mask[4][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_4_T_32 = or(_ram_4_T_28, _ram_4_T_29) node _ram_4_T_33 = or(_ram_4_T_32, _ram_4_T_30) node _ram_4_T_34 = or(_ram_4_T_33, _ram_4_T_31) wire _ram_4_WIRE_7 : UInt<65> connect _ram_4_WIRE_7, _ram_4_T_34 connect _ram_4_WIRE_4.in1, _ram_4_WIRE_7 node _ram_4_T_35 = mux(write_mask[4][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_4_T_36 = mux(write_mask[4][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_4_T_37 = mux(write_mask[4][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_4_T_38 = mux(write_mask[4][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_4_T_39 = or(_ram_4_T_35, _ram_4_T_36) node _ram_4_T_40 = or(_ram_4_T_39, _ram_4_T_37) node _ram_4_T_41 = or(_ram_4_T_40, _ram_4_T_38) wire _ram_4_WIRE_8 : UInt<2> connect _ram_4_WIRE_8, _ram_4_T_41 connect _ram_4_WIRE_4.fmt, _ram_4_WIRE_8 node _ram_4_T_42 = mux(write_mask[4][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_4_T_43 = mux(write_mask[4][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_4_T_44 = mux(write_mask[4][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_4_T_45 = mux(write_mask[4][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_4_T_46 = or(_ram_4_T_42, _ram_4_T_43) node _ram_4_T_47 = or(_ram_4_T_46, _ram_4_T_44) node _ram_4_T_48 = or(_ram_4_T_47, _ram_4_T_45) wire _ram_4_WIRE_9 : UInt<2> connect _ram_4_WIRE_9, _ram_4_T_48 connect _ram_4_WIRE_4.typ, _ram_4_WIRE_9 node _ram_4_T_49 = mux(write_mask[4][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_4_T_50 = mux(write_mask[4][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_4_T_51 = mux(write_mask[4][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_4_T_52 = mux(write_mask[4][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_4_T_53 = or(_ram_4_T_49, _ram_4_T_50) node _ram_4_T_54 = or(_ram_4_T_53, _ram_4_T_51) node _ram_4_T_55 = or(_ram_4_T_54, _ram_4_T_52) wire _ram_4_WIRE_10 : UInt<2> connect _ram_4_WIRE_10, _ram_4_T_55 connect _ram_4_WIRE_4.fmaCmd, _ram_4_WIRE_10 node _ram_4_T_56 = mux(write_mask[4][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_4_T_57 = mux(write_mask[4][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_4_T_58 = mux(write_mask[4][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_4_T_59 = mux(write_mask[4][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_4_T_60 = or(_ram_4_T_56, _ram_4_T_57) node _ram_4_T_61 = or(_ram_4_T_60, _ram_4_T_58) node _ram_4_T_62 = or(_ram_4_T_61, _ram_4_T_59) wire _ram_4_WIRE_11 : UInt<3> connect _ram_4_WIRE_11, _ram_4_T_62 connect _ram_4_WIRE_4.rm, _ram_4_WIRE_11 node _ram_4_T_63 = mux(write_mask[4][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_4_T_64 = mux(write_mask[4][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_4_T_65 = mux(write_mask[4][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_4_T_66 = mux(write_mask[4][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_4_T_67 = or(_ram_4_T_63, _ram_4_T_64) node _ram_4_T_68 = or(_ram_4_T_67, _ram_4_T_65) node _ram_4_T_69 = or(_ram_4_T_68, _ram_4_T_66) wire _ram_4_WIRE_12 : UInt<1> connect _ram_4_WIRE_12, _ram_4_T_69 connect _ram_4_WIRE_4.vec, _ram_4_WIRE_12 node _ram_4_T_70 = mux(write_mask[4][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_4_T_71 = mux(write_mask[4][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_4_T_72 = mux(write_mask[4][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_4_T_73 = mux(write_mask[4][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_4_T_74 = or(_ram_4_T_70, _ram_4_T_71) node _ram_4_T_75 = or(_ram_4_T_74, _ram_4_T_72) node _ram_4_T_76 = or(_ram_4_T_75, _ram_4_T_73) wire _ram_4_WIRE_13 : UInt<1> connect _ram_4_WIRE_13, _ram_4_T_76 connect _ram_4_WIRE_4.wflags, _ram_4_WIRE_13 node _ram_4_T_77 = mux(write_mask[4][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_4_T_78 = mux(write_mask[4][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_4_T_79 = mux(write_mask[4][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_4_T_80 = mux(write_mask[4][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_4_T_81 = or(_ram_4_T_77, _ram_4_T_78) node _ram_4_T_82 = or(_ram_4_T_81, _ram_4_T_79) node _ram_4_T_83 = or(_ram_4_T_82, _ram_4_T_80) wire _ram_4_WIRE_14 : UInt<1> connect _ram_4_WIRE_14, _ram_4_T_83 connect _ram_4_WIRE_4.sqrt, _ram_4_WIRE_14 node _ram_4_T_84 = mux(write_mask[4][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_4_T_85 = mux(write_mask[4][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_4_T_86 = mux(write_mask[4][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_4_T_87 = mux(write_mask[4][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_4_T_88 = or(_ram_4_T_84, _ram_4_T_85) node _ram_4_T_89 = or(_ram_4_T_88, _ram_4_T_86) node _ram_4_T_90 = or(_ram_4_T_89, _ram_4_T_87) wire _ram_4_WIRE_15 : UInt<1> connect _ram_4_WIRE_15, _ram_4_T_90 connect _ram_4_WIRE_4.div, _ram_4_WIRE_15 node _ram_4_T_91 = mux(write_mask[4][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_4_T_92 = mux(write_mask[4][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_4_T_93 = mux(write_mask[4][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_4_T_94 = mux(write_mask[4][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_4_T_95 = or(_ram_4_T_91, _ram_4_T_92) node _ram_4_T_96 = or(_ram_4_T_95, _ram_4_T_93) node _ram_4_T_97 = or(_ram_4_T_96, _ram_4_T_94) wire _ram_4_WIRE_16 : UInt<1> connect _ram_4_WIRE_16, _ram_4_T_97 connect _ram_4_WIRE_4.fma, _ram_4_WIRE_16 node _ram_4_T_98 = mux(write_mask[4][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_4_T_99 = mux(write_mask[4][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_4_T_100 = mux(write_mask[4][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_4_T_101 = mux(write_mask[4][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_4_T_102 = or(_ram_4_T_98, _ram_4_T_99) node _ram_4_T_103 = or(_ram_4_T_102, _ram_4_T_100) node _ram_4_T_104 = or(_ram_4_T_103, _ram_4_T_101) wire _ram_4_WIRE_17 : UInt<1> connect _ram_4_WIRE_17, _ram_4_T_104 connect _ram_4_WIRE_4.fastpipe, _ram_4_WIRE_17 node _ram_4_T_105 = mux(write_mask[4][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_4_T_106 = mux(write_mask[4][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_4_T_107 = mux(write_mask[4][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_4_T_108 = mux(write_mask[4][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_4_T_109 = or(_ram_4_T_105, _ram_4_T_106) node _ram_4_T_110 = or(_ram_4_T_109, _ram_4_T_107) node _ram_4_T_111 = or(_ram_4_T_110, _ram_4_T_108) wire _ram_4_WIRE_18 : UInt<1> connect _ram_4_WIRE_18, _ram_4_T_111 connect _ram_4_WIRE_4.toint, _ram_4_WIRE_18 node _ram_4_T_112 = mux(write_mask[4][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_4_T_113 = mux(write_mask[4][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_4_T_114 = mux(write_mask[4][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_4_T_115 = mux(write_mask[4][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_4_T_116 = or(_ram_4_T_112, _ram_4_T_113) node _ram_4_T_117 = or(_ram_4_T_116, _ram_4_T_114) node _ram_4_T_118 = or(_ram_4_T_117, _ram_4_T_115) wire _ram_4_WIRE_19 : UInt<1> connect _ram_4_WIRE_19, _ram_4_T_118 connect _ram_4_WIRE_4.fromint, _ram_4_WIRE_19 node _ram_4_T_119 = mux(write_mask[4][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_4_T_120 = mux(write_mask[4][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_4_T_121 = mux(write_mask[4][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_4_T_122 = mux(write_mask[4][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_4_T_123 = or(_ram_4_T_119, _ram_4_T_120) node _ram_4_T_124 = or(_ram_4_T_123, _ram_4_T_121) node _ram_4_T_125 = or(_ram_4_T_124, _ram_4_T_122) wire _ram_4_WIRE_20 : UInt<2> connect _ram_4_WIRE_20, _ram_4_T_125 connect _ram_4_WIRE_4.typeTagOut, _ram_4_WIRE_20 node _ram_4_T_126 = mux(write_mask[4][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_4_T_127 = mux(write_mask[4][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_4_T_128 = mux(write_mask[4][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_4_T_129 = mux(write_mask[4][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_4_T_130 = or(_ram_4_T_126, _ram_4_T_127) node _ram_4_T_131 = or(_ram_4_T_130, _ram_4_T_128) node _ram_4_T_132 = or(_ram_4_T_131, _ram_4_T_129) wire _ram_4_WIRE_21 : UInt<2> connect _ram_4_WIRE_21, _ram_4_T_132 connect _ram_4_WIRE_4.typeTagIn, _ram_4_WIRE_21 node _ram_4_T_133 = mux(write_mask[4][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_4_T_134 = mux(write_mask[4][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_4_T_135 = mux(write_mask[4][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_4_T_136 = mux(write_mask[4][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_4_T_137 = or(_ram_4_T_133, _ram_4_T_134) node _ram_4_T_138 = or(_ram_4_T_137, _ram_4_T_135) node _ram_4_T_139 = or(_ram_4_T_138, _ram_4_T_136) wire _ram_4_WIRE_22 : UInt<1> connect _ram_4_WIRE_22, _ram_4_T_139 connect _ram_4_WIRE_4.swap23, _ram_4_WIRE_22 node _ram_4_T_140 = mux(write_mask[4][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_4_T_141 = mux(write_mask[4][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_4_T_142 = mux(write_mask[4][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_4_T_143 = mux(write_mask[4][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_4_T_144 = or(_ram_4_T_140, _ram_4_T_141) node _ram_4_T_145 = or(_ram_4_T_144, _ram_4_T_142) node _ram_4_T_146 = or(_ram_4_T_145, _ram_4_T_143) wire _ram_4_WIRE_23 : UInt<1> connect _ram_4_WIRE_23, _ram_4_T_146 connect _ram_4_WIRE_4.swap12, _ram_4_WIRE_23 node _ram_4_T_147 = mux(write_mask[4][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_4_T_148 = mux(write_mask[4][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_4_T_149 = mux(write_mask[4][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_4_T_150 = mux(write_mask[4][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_4_T_151 = or(_ram_4_T_147, _ram_4_T_148) node _ram_4_T_152 = or(_ram_4_T_151, _ram_4_T_149) node _ram_4_T_153 = or(_ram_4_T_152, _ram_4_T_150) wire _ram_4_WIRE_24 : UInt<1> connect _ram_4_WIRE_24, _ram_4_T_153 connect _ram_4_WIRE_4.ren3, _ram_4_WIRE_24 node _ram_4_T_154 = mux(write_mask[4][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_4_T_155 = mux(write_mask[4][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_4_T_156 = mux(write_mask[4][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_4_T_157 = mux(write_mask[4][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_4_T_158 = or(_ram_4_T_154, _ram_4_T_155) node _ram_4_T_159 = or(_ram_4_T_158, _ram_4_T_156) node _ram_4_T_160 = or(_ram_4_T_159, _ram_4_T_157) wire _ram_4_WIRE_25 : UInt<1> connect _ram_4_WIRE_25, _ram_4_T_160 connect _ram_4_WIRE_4.ren2, _ram_4_WIRE_25 node _ram_4_T_161 = mux(write_mask[4][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_4_T_162 = mux(write_mask[4][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_4_T_163 = mux(write_mask[4][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_4_T_164 = mux(write_mask[4][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_4_T_165 = or(_ram_4_T_161, _ram_4_T_162) node _ram_4_T_166 = or(_ram_4_T_165, _ram_4_T_163) node _ram_4_T_167 = or(_ram_4_T_166, _ram_4_T_164) wire _ram_4_WIRE_26 : UInt<1> connect _ram_4_WIRE_26, _ram_4_T_167 connect _ram_4_WIRE_4.ren1, _ram_4_WIRE_26 node _ram_4_T_168 = mux(write_mask[4][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_4_T_169 = mux(write_mask[4][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_4_T_170 = mux(write_mask[4][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_4_T_171 = mux(write_mask[4][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_4_T_172 = or(_ram_4_T_168, _ram_4_T_169) node _ram_4_T_173 = or(_ram_4_T_172, _ram_4_T_170) node _ram_4_T_174 = or(_ram_4_T_173, _ram_4_T_171) wire _ram_4_WIRE_27 : UInt<1> connect _ram_4_WIRE_27, _ram_4_T_174 connect _ram_4_WIRE_4.wen, _ram_4_WIRE_27 node _ram_4_T_175 = mux(write_mask[4][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_4_T_176 = mux(write_mask[4][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_4_T_177 = mux(write_mask[4][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_4_T_178 = mux(write_mask[4][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_4_T_179 = or(_ram_4_T_175, _ram_4_T_176) node _ram_4_T_180 = or(_ram_4_T_179, _ram_4_T_177) node _ram_4_T_181 = or(_ram_4_T_180, _ram_4_T_178) wire _ram_4_WIRE_28 : UInt<1> connect _ram_4_WIRE_28, _ram_4_T_181 connect _ram_4_WIRE_4.ldst, _ram_4_WIRE_28 connect _ram_4_WIRE_1.fdivin, _ram_4_WIRE_4 node _ram_4_T_182 = mux(write_mask[4][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_4_T_183 = mux(write_mask[4][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_4_T_184 = mux(write_mask[4][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_4_T_185 = mux(write_mask[4][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_4_T_186 = or(_ram_4_T_182, _ram_4_T_183) node _ram_4_T_187 = or(_ram_4_T_186, _ram_4_T_184) node _ram_4_T_188 = or(_ram_4_T_187, _ram_4_T_185) wire _ram_4_WIRE_29 : UInt<5> connect _ram_4_WIRE_29, _ram_4_T_188 connect _ram_4_WIRE_1.fexc, _ram_4_WIRE_29 node _ram_4_T_189 = mux(write_mask[4][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_4_T_190 = mux(write_mask[4][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_4_T_191 = mux(write_mask[4][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_4_T_192 = mux(write_mask[4][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_4_T_193 = or(_ram_4_T_189, _ram_4_T_190) node _ram_4_T_194 = or(_ram_4_T_193, _ram_4_T_191) node _ram_4_T_195 = or(_ram_4_T_194, _ram_4_T_192) wire _ram_4_WIRE_30 : UInt<5> connect _ram_4_WIRE_30, _ram_4_T_195 connect _ram_4_WIRE_1.fra3, _ram_4_WIRE_30 node _ram_4_T_196 = mux(write_mask[4][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_4_T_197 = mux(write_mask[4][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_4_T_198 = mux(write_mask[4][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_4_T_199 = mux(write_mask[4][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_4_T_200 = or(_ram_4_T_196, _ram_4_T_197) node _ram_4_T_201 = or(_ram_4_T_200, _ram_4_T_198) node _ram_4_T_202 = or(_ram_4_T_201, _ram_4_T_199) wire _ram_4_WIRE_31 : UInt<5> connect _ram_4_WIRE_31, _ram_4_T_202 connect _ram_4_WIRE_1.fra2, _ram_4_WIRE_31 node _ram_4_T_203 = mux(write_mask[4][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_4_T_204 = mux(write_mask[4][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_4_T_205 = mux(write_mask[4][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_4_T_206 = mux(write_mask[4][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_4_T_207 = or(_ram_4_T_203, _ram_4_T_204) node _ram_4_T_208 = or(_ram_4_T_207, _ram_4_T_205) node _ram_4_T_209 = or(_ram_4_T_208, _ram_4_T_206) wire _ram_4_WIRE_32 : UInt<5> connect _ram_4_WIRE_32, _ram_4_T_209 connect _ram_4_WIRE_1.fra1, _ram_4_WIRE_32 wire _ram_4_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_4_T_210 = mux(write_mask[4][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_4_T_211 = mux(write_mask[4][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_4_T_212 = mux(write_mask[4][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_4_T_213 = mux(write_mask[4][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_4_T_214 = or(_ram_4_T_210, _ram_4_T_211) node _ram_4_T_215 = or(_ram_4_T_214, _ram_4_T_212) node _ram_4_T_216 = or(_ram_4_T_215, _ram_4_T_213) wire _ram_4_WIRE_34 : UInt<64> connect _ram_4_WIRE_34, _ram_4_T_216 connect _ram_4_WIRE_33.bits, _ram_4_WIRE_34 node _ram_4_T_217 = mux(write_mask[4][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_4_T_218 = mux(write_mask[4][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_4_T_219 = mux(write_mask[4][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_4_T_220 = mux(write_mask[4][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_4_T_221 = or(_ram_4_T_217, _ram_4_T_218) node _ram_4_T_222 = or(_ram_4_T_221, _ram_4_T_219) node _ram_4_T_223 = or(_ram_4_T_222, _ram_4_T_220) wire _ram_4_WIRE_35 : UInt<1> connect _ram_4_WIRE_35, _ram_4_T_223 connect _ram_4_WIRE_33.valid, _ram_4_WIRE_35 connect _ram_4_WIRE_1.wdata, _ram_4_WIRE_33 node _ram_4_T_224 = mux(write_mask[4][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_4_T_225 = mux(write_mask[4][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_4_T_226 = mux(write_mask[4][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_4_T_227 = mux(write_mask[4][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_4_T_228 = or(_ram_4_T_224, _ram_4_T_225) node _ram_4_T_229 = or(_ram_4_T_228, _ram_4_T_226) node _ram_4_T_230 = or(_ram_4_T_229, _ram_4_T_227) wire _ram_4_WIRE_36 : UInt<1> connect _ram_4_WIRE_36, _ram_4_T_230 connect _ram_4_WIRE_1.uses_latealu, _ram_4_WIRE_36 node _ram_4_T_231 = mux(write_mask[4][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_4_T_232 = mux(write_mask[4][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_4_T_233 = mux(write_mask[4][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_4_T_234 = mux(write_mask[4][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_4_T_235 = or(_ram_4_T_231, _ram_4_T_232) node _ram_4_T_236 = or(_ram_4_T_235, _ram_4_T_233) node _ram_4_T_237 = or(_ram_4_T_236, _ram_4_T_234) wire _ram_4_WIRE_37 : UInt<1> connect _ram_4_WIRE_37, _ram_4_T_237 connect _ram_4_WIRE_1.uses_memalu, _ram_4_WIRE_37 node _ram_4_T_238 = mux(write_mask[4][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_4_T_239 = mux(write_mask[4][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_4_T_240 = mux(write_mask[4][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_4_T_241 = mux(write_mask[4][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_4_T_242 = or(_ram_4_T_238, _ram_4_T_239) node _ram_4_T_243 = or(_ram_4_T_242, _ram_4_T_240) node _ram_4_T_244 = or(_ram_4_T_243, _ram_4_T_241) wire _ram_4_WIRE_38 : UInt<64> connect _ram_4_WIRE_38, _ram_4_T_244 connect _ram_4_WIRE_1.rs3_data, _ram_4_WIRE_38 node _ram_4_T_245 = mux(write_mask[4][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_4_T_246 = mux(write_mask[4][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_4_T_247 = mux(write_mask[4][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_4_T_248 = mux(write_mask[4][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_4_T_249 = or(_ram_4_T_245, _ram_4_T_246) node _ram_4_T_250 = or(_ram_4_T_249, _ram_4_T_247) node _ram_4_T_251 = or(_ram_4_T_250, _ram_4_T_248) wire _ram_4_WIRE_39 : UInt<64> connect _ram_4_WIRE_39, _ram_4_T_251 connect _ram_4_WIRE_1.rs2_data, _ram_4_WIRE_39 node _ram_4_T_252 = mux(write_mask[4][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_4_T_253 = mux(write_mask[4][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_4_T_254 = mux(write_mask[4][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_4_T_255 = mux(write_mask[4][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_4_T_256 = or(_ram_4_T_252, _ram_4_T_253) node _ram_4_T_257 = or(_ram_4_T_256, _ram_4_T_254) node _ram_4_T_258 = or(_ram_4_T_257, _ram_4_T_255) wire _ram_4_WIRE_40 : UInt<64> connect _ram_4_WIRE_40, _ram_4_T_258 connect _ram_4_WIRE_1.rs1_data, _ram_4_WIRE_40 node _ram_4_T_259 = mux(write_mask[4][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_4_T_260 = mux(write_mask[4][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_4_T_261 = mux(write_mask[4][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_4_T_262 = mux(write_mask[4][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_4_T_263 = or(_ram_4_T_259, _ram_4_T_260) node _ram_4_T_264 = or(_ram_4_T_263, _ram_4_T_261) node _ram_4_T_265 = or(_ram_4_T_264, _ram_4_T_262) wire _ram_4_WIRE_41 : UInt<1> connect _ram_4_WIRE_41, _ram_4_T_265 connect _ram_4_WIRE_1.needs_replay, _ram_4_WIRE_41 node _ram_4_T_266 = mux(write_mask[4][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_4_T_267 = mux(write_mask[4][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_4_T_268 = mux(write_mask[4][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_4_T_269 = mux(write_mask[4][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_4_T_270 = or(_ram_4_T_266, _ram_4_T_267) node _ram_4_T_271 = or(_ram_4_T_270, _ram_4_T_268) node _ram_4_T_272 = or(_ram_4_T_271, _ram_4_T_269) wire _ram_4_WIRE_42 : UInt<64> connect _ram_4_WIRE_42, _ram_4_T_272 connect _ram_4_WIRE_1.xcpt_cause, _ram_4_WIRE_42 node _ram_4_T_273 = mux(write_mask[4][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_4_T_274 = mux(write_mask[4][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_4_T_275 = mux(write_mask[4][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_4_T_276 = mux(write_mask[4][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_4_T_277 = or(_ram_4_T_273, _ram_4_T_274) node _ram_4_T_278 = or(_ram_4_T_277, _ram_4_T_275) node _ram_4_T_279 = or(_ram_4_T_278, _ram_4_T_276) wire _ram_4_WIRE_43 : UInt<1> connect _ram_4_WIRE_43, _ram_4_T_279 connect _ram_4_WIRE_1.xcpt, _ram_4_WIRE_43 node _ram_4_T_280 = mux(write_mask[4][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_4_T_281 = mux(write_mask[4][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_4_T_282 = mux(write_mask[4][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_4_T_283 = mux(write_mask[4][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_4_T_284 = or(_ram_4_T_280, _ram_4_T_281) node _ram_4_T_285 = or(_ram_4_T_284, _ram_4_T_282) node _ram_4_T_286 = or(_ram_4_T_285, _ram_4_T_283) wire _ram_4_WIRE_44 : UInt<1> connect _ram_4_WIRE_44, _ram_4_T_286 connect _ram_4_WIRE_1.taken, _ram_4_WIRE_44 node _ram_4_T_287 = mux(write_mask[4][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_4_T_288 = mux(write_mask[4][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_4_T_289 = mux(write_mask[4][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_4_T_290 = mux(write_mask[4][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_4_T_291 = or(_ram_4_T_287, _ram_4_T_288) node _ram_4_T_292 = or(_ram_4_T_291, _ram_4_T_289) node _ram_4_T_293 = or(_ram_4_T_292, _ram_4_T_290) wire _ram_4_WIRE_45 : UInt<3> connect _ram_4_WIRE_45, _ram_4_T_293 connect _ram_4_WIRE_1.ras_head, _ram_4_WIRE_45 wire _ram_4_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_4_T_294 = mux(write_mask[4][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_4_T_295 = mux(write_mask[4][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_4_T_296 = mux(write_mask[4][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_4_T_297 = mux(write_mask[4][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_4_T_298 = or(_ram_4_T_294, _ram_4_T_295) node _ram_4_T_299 = or(_ram_4_T_298, _ram_4_T_296) node _ram_4_T_300 = or(_ram_4_T_299, _ram_4_T_297) wire _ram_4_WIRE_47 : UInt<40> connect _ram_4_WIRE_47, _ram_4_T_300 connect _ram_4_WIRE_46.bits, _ram_4_WIRE_47 node _ram_4_T_301 = mux(write_mask[4][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_4_T_302 = mux(write_mask[4][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_4_T_303 = mux(write_mask[4][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_4_T_304 = mux(write_mask[4][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_4_T_305 = or(_ram_4_T_301, _ram_4_T_302) node _ram_4_T_306 = or(_ram_4_T_305, _ram_4_T_303) node _ram_4_T_307 = or(_ram_4_T_306, _ram_4_T_304) wire _ram_4_WIRE_48 : UInt<1> connect _ram_4_WIRE_48, _ram_4_T_307 connect _ram_4_WIRE_46.valid, _ram_4_WIRE_48 connect _ram_4_WIRE_1.next_pc, _ram_4_WIRE_46 node _ram_4_T_308 = mux(write_mask[4][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_4_T_309 = mux(write_mask[4][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_4_T_310 = mux(write_mask[4][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_4_T_311 = mux(write_mask[4][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_4_T_312 = or(_ram_4_T_308, _ram_4_T_309) node _ram_4_T_313 = or(_ram_4_T_312, _ram_4_T_310) node _ram_4_T_314 = or(_ram_4_T_313, _ram_4_T_311) wire _ram_4_WIRE_49 : UInt<1> connect _ram_4_WIRE_49, _ram_4_T_314 connect _ram_4_WIRE_1.sfb_shadow, _ram_4_WIRE_49 node _ram_4_T_315 = mux(write_mask[4][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_4_T_316 = mux(write_mask[4][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_4_T_317 = mux(write_mask[4][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_4_T_318 = mux(write_mask[4][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_4_T_319 = or(_ram_4_T_315, _ram_4_T_316) node _ram_4_T_320 = or(_ram_4_T_319, _ram_4_T_317) node _ram_4_T_321 = or(_ram_4_T_320, _ram_4_T_318) wire _ram_4_WIRE_50 : UInt<1> connect _ram_4_WIRE_50, _ram_4_T_321 connect _ram_4_WIRE_1.sfb_br, _ram_4_WIRE_50 wire _ram_4_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_4_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_4_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_4_T_322 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_4_T_323 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_4_T_324 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_4_T_325 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_4_T_326 = or(_ram_4_T_322, _ram_4_T_323) node _ram_4_T_327 = or(_ram_4_T_326, _ram_4_T_324) node _ram_4_T_328 = or(_ram_4_T_327, _ram_4_T_325) wire _ram_4_WIRE_54 : UInt<2> connect _ram_4_WIRE_54, _ram_4_T_328 connect _ram_4_WIRE_53.value, _ram_4_WIRE_54 node _ram_4_T_329 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_4_T_330 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_4_T_331 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_4_T_332 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_4_T_333 = or(_ram_4_T_329, _ram_4_T_330) node _ram_4_T_334 = or(_ram_4_T_333, _ram_4_T_331) node _ram_4_T_335 = or(_ram_4_T_334, _ram_4_T_332) wire _ram_4_WIRE_55 : UInt<8> connect _ram_4_WIRE_55, _ram_4_T_335 connect _ram_4_WIRE_53.history, _ram_4_WIRE_55 connect _ram_4_WIRE_52.bht, _ram_4_WIRE_53 node _ram_4_T_336 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_4_T_337 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_4_T_338 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_4_T_339 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_4_T_340 = or(_ram_4_T_336, _ram_4_T_337) node _ram_4_T_341 = or(_ram_4_T_340, _ram_4_T_338) node _ram_4_T_342 = or(_ram_4_T_341, _ram_4_T_339) wire _ram_4_WIRE_56 : UInt<6> connect _ram_4_WIRE_56, _ram_4_T_342 connect _ram_4_WIRE_52.entry, _ram_4_WIRE_56 node _ram_4_T_343 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_4_T_344 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_4_T_345 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_4_T_346 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_4_T_347 = or(_ram_4_T_343, _ram_4_T_344) node _ram_4_T_348 = or(_ram_4_T_347, _ram_4_T_345) node _ram_4_T_349 = or(_ram_4_T_348, _ram_4_T_346) wire _ram_4_WIRE_57 : UInt<39> connect _ram_4_WIRE_57, _ram_4_T_349 connect _ram_4_WIRE_52.target, _ram_4_WIRE_57 node _ram_4_T_350 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_4_T_351 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_4_T_352 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_4_T_353 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_4_T_354 = or(_ram_4_T_350, _ram_4_T_351) node _ram_4_T_355 = or(_ram_4_T_354, _ram_4_T_352) node _ram_4_T_356 = or(_ram_4_T_355, _ram_4_T_353) wire _ram_4_WIRE_58 : UInt<2> connect _ram_4_WIRE_58, _ram_4_T_356 connect _ram_4_WIRE_52.bridx, _ram_4_WIRE_58 node _ram_4_T_357 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_4_T_358 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_4_T_359 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_4_T_360 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_4_T_361 = or(_ram_4_T_357, _ram_4_T_358) node _ram_4_T_362 = or(_ram_4_T_361, _ram_4_T_359) node _ram_4_T_363 = or(_ram_4_T_362, _ram_4_T_360) wire _ram_4_WIRE_59 : UInt<4> connect _ram_4_WIRE_59, _ram_4_T_363 connect _ram_4_WIRE_52.mask, _ram_4_WIRE_59 node _ram_4_T_364 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_4_T_365 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_4_T_366 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_4_T_367 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_4_T_368 = or(_ram_4_T_364, _ram_4_T_365) node _ram_4_T_369 = or(_ram_4_T_368, _ram_4_T_366) node _ram_4_T_370 = or(_ram_4_T_369, _ram_4_T_367) wire _ram_4_WIRE_60 : UInt<1> connect _ram_4_WIRE_60, _ram_4_T_370 connect _ram_4_WIRE_52.taken, _ram_4_WIRE_60 node _ram_4_T_371 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_4_T_372 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_4_T_373 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_4_T_374 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_4_T_375 = or(_ram_4_T_371, _ram_4_T_372) node _ram_4_T_376 = or(_ram_4_T_375, _ram_4_T_373) node _ram_4_T_377 = or(_ram_4_T_376, _ram_4_T_374) wire _ram_4_WIRE_61 : UInt<2> connect _ram_4_WIRE_61, _ram_4_T_377 connect _ram_4_WIRE_52.cfiType, _ram_4_WIRE_61 connect _ram_4_WIRE_51.bits, _ram_4_WIRE_52 node _ram_4_T_378 = mux(write_mask[4][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_4_T_379 = mux(write_mask[4][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_4_T_380 = mux(write_mask[4][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_4_T_381 = mux(write_mask[4][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_4_T_382 = or(_ram_4_T_378, _ram_4_T_379) node _ram_4_T_383 = or(_ram_4_T_382, _ram_4_T_380) node _ram_4_T_384 = or(_ram_4_T_383, _ram_4_T_381) wire _ram_4_WIRE_62 : UInt<1> connect _ram_4_WIRE_62, _ram_4_T_384 connect _ram_4_WIRE_51.valid, _ram_4_WIRE_62 connect _ram_4_WIRE_1.btb_resp, _ram_4_WIRE_51 node _ram_4_T_385 = mux(write_mask[4][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_4_T_386 = mux(write_mask[4][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_4_T_387 = mux(write_mask[4][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_4_T_388 = mux(write_mask[4][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_4_T_389 = or(_ram_4_T_385, _ram_4_T_386) node _ram_4_T_390 = or(_ram_4_T_389, _ram_4_T_387) node _ram_4_T_391 = or(_ram_4_T_390, _ram_4_T_388) wire _ram_4_WIRE_63 : UInt<1> connect _ram_4_WIRE_63, _ram_4_T_391 connect _ram_4_WIRE_1.sets_vcfg, _ram_4_WIRE_63 node _ram_4_T_392 = mux(write_mask[4][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_4_T_393 = mux(write_mask[4][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_4_T_394 = mux(write_mask[4][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_4_T_395 = mux(write_mask[4][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_4_T_396 = or(_ram_4_T_392, _ram_4_T_393) node _ram_4_T_397 = or(_ram_4_T_396, _ram_4_T_394) node _ram_4_T_398 = or(_ram_4_T_397, _ram_4_T_395) wire _ram_4_WIRE_64 : UInt<1> connect _ram_4_WIRE_64, _ram_4_T_398 connect _ram_4_WIRE_1.rvc, _ram_4_WIRE_64 wire _ram_4_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_4_T_399 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_4_T_400 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_4_T_401 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_4_T_402 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_4_T_403 = or(_ram_4_T_399, _ram_4_T_400) node _ram_4_T_404 = or(_ram_4_T_403, _ram_4_T_401) node _ram_4_T_405 = or(_ram_4_T_404, _ram_4_T_402) wire _ram_4_WIRE_66 : UInt<1> connect _ram_4_WIRE_66, _ram_4_T_405 connect _ram_4_WIRE_65.vec, _ram_4_WIRE_66 node _ram_4_T_406 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_4_T_407 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_4_T_408 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_4_T_409 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_4_T_410 = or(_ram_4_T_406, _ram_4_T_407) node _ram_4_T_411 = or(_ram_4_T_410, _ram_4_T_408) node _ram_4_T_412 = or(_ram_4_T_411, _ram_4_T_409) wire _ram_4_WIRE_67 : UInt<1> connect _ram_4_WIRE_67, _ram_4_T_412 connect _ram_4_WIRE_65.wflags, _ram_4_WIRE_67 node _ram_4_T_413 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_4_T_414 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_4_T_415 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_4_T_416 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_4_T_417 = or(_ram_4_T_413, _ram_4_T_414) node _ram_4_T_418 = or(_ram_4_T_417, _ram_4_T_415) node _ram_4_T_419 = or(_ram_4_T_418, _ram_4_T_416) wire _ram_4_WIRE_68 : UInt<1> connect _ram_4_WIRE_68, _ram_4_T_419 connect _ram_4_WIRE_65.sqrt, _ram_4_WIRE_68 node _ram_4_T_420 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_4_T_421 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_4_T_422 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_4_T_423 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_4_T_424 = or(_ram_4_T_420, _ram_4_T_421) node _ram_4_T_425 = or(_ram_4_T_424, _ram_4_T_422) node _ram_4_T_426 = or(_ram_4_T_425, _ram_4_T_423) wire _ram_4_WIRE_69 : UInt<1> connect _ram_4_WIRE_69, _ram_4_T_426 connect _ram_4_WIRE_65.div, _ram_4_WIRE_69 node _ram_4_T_427 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_4_T_428 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_4_T_429 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_4_T_430 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_4_T_431 = or(_ram_4_T_427, _ram_4_T_428) node _ram_4_T_432 = or(_ram_4_T_431, _ram_4_T_429) node _ram_4_T_433 = or(_ram_4_T_432, _ram_4_T_430) wire _ram_4_WIRE_70 : UInt<1> connect _ram_4_WIRE_70, _ram_4_T_433 connect _ram_4_WIRE_65.fma, _ram_4_WIRE_70 node _ram_4_T_434 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_4_T_435 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_4_T_436 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_4_T_437 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_4_T_438 = or(_ram_4_T_434, _ram_4_T_435) node _ram_4_T_439 = or(_ram_4_T_438, _ram_4_T_436) node _ram_4_T_440 = or(_ram_4_T_439, _ram_4_T_437) wire _ram_4_WIRE_71 : UInt<1> connect _ram_4_WIRE_71, _ram_4_T_440 connect _ram_4_WIRE_65.fastpipe, _ram_4_WIRE_71 node _ram_4_T_441 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_4_T_442 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_4_T_443 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_4_T_444 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_4_T_445 = or(_ram_4_T_441, _ram_4_T_442) node _ram_4_T_446 = or(_ram_4_T_445, _ram_4_T_443) node _ram_4_T_447 = or(_ram_4_T_446, _ram_4_T_444) wire _ram_4_WIRE_72 : UInt<1> connect _ram_4_WIRE_72, _ram_4_T_447 connect _ram_4_WIRE_65.toint, _ram_4_WIRE_72 node _ram_4_T_448 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_4_T_449 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_4_T_450 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_4_T_451 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_4_T_452 = or(_ram_4_T_448, _ram_4_T_449) node _ram_4_T_453 = or(_ram_4_T_452, _ram_4_T_450) node _ram_4_T_454 = or(_ram_4_T_453, _ram_4_T_451) wire _ram_4_WIRE_73 : UInt<1> connect _ram_4_WIRE_73, _ram_4_T_454 connect _ram_4_WIRE_65.fromint, _ram_4_WIRE_73 node _ram_4_T_455 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_4_T_456 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_4_T_457 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_4_T_458 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_4_T_459 = or(_ram_4_T_455, _ram_4_T_456) node _ram_4_T_460 = or(_ram_4_T_459, _ram_4_T_457) node _ram_4_T_461 = or(_ram_4_T_460, _ram_4_T_458) wire _ram_4_WIRE_74 : UInt<2> connect _ram_4_WIRE_74, _ram_4_T_461 connect _ram_4_WIRE_65.typeTagOut, _ram_4_WIRE_74 node _ram_4_T_462 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_4_T_463 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_4_T_464 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_4_T_465 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_4_T_466 = or(_ram_4_T_462, _ram_4_T_463) node _ram_4_T_467 = or(_ram_4_T_466, _ram_4_T_464) node _ram_4_T_468 = or(_ram_4_T_467, _ram_4_T_465) wire _ram_4_WIRE_75 : UInt<2> connect _ram_4_WIRE_75, _ram_4_T_468 connect _ram_4_WIRE_65.typeTagIn, _ram_4_WIRE_75 node _ram_4_T_469 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_4_T_470 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_4_T_471 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_4_T_472 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_4_T_473 = or(_ram_4_T_469, _ram_4_T_470) node _ram_4_T_474 = or(_ram_4_T_473, _ram_4_T_471) node _ram_4_T_475 = or(_ram_4_T_474, _ram_4_T_472) wire _ram_4_WIRE_76 : UInt<1> connect _ram_4_WIRE_76, _ram_4_T_475 connect _ram_4_WIRE_65.swap23, _ram_4_WIRE_76 node _ram_4_T_476 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_4_T_477 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_4_T_478 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_4_T_479 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_4_T_480 = or(_ram_4_T_476, _ram_4_T_477) node _ram_4_T_481 = or(_ram_4_T_480, _ram_4_T_478) node _ram_4_T_482 = or(_ram_4_T_481, _ram_4_T_479) wire _ram_4_WIRE_77 : UInt<1> connect _ram_4_WIRE_77, _ram_4_T_482 connect _ram_4_WIRE_65.swap12, _ram_4_WIRE_77 node _ram_4_T_483 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_4_T_484 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_4_T_485 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_4_T_486 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_4_T_487 = or(_ram_4_T_483, _ram_4_T_484) node _ram_4_T_488 = or(_ram_4_T_487, _ram_4_T_485) node _ram_4_T_489 = or(_ram_4_T_488, _ram_4_T_486) wire _ram_4_WIRE_78 : UInt<1> connect _ram_4_WIRE_78, _ram_4_T_489 connect _ram_4_WIRE_65.ren3, _ram_4_WIRE_78 node _ram_4_T_490 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_4_T_491 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_4_T_492 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_4_T_493 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_4_T_494 = or(_ram_4_T_490, _ram_4_T_491) node _ram_4_T_495 = or(_ram_4_T_494, _ram_4_T_492) node _ram_4_T_496 = or(_ram_4_T_495, _ram_4_T_493) wire _ram_4_WIRE_79 : UInt<1> connect _ram_4_WIRE_79, _ram_4_T_496 connect _ram_4_WIRE_65.ren2, _ram_4_WIRE_79 node _ram_4_T_497 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_4_T_498 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_4_T_499 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_4_T_500 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_4_T_501 = or(_ram_4_T_497, _ram_4_T_498) node _ram_4_T_502 = or(_ram_4_T_501, _ram_4_T_499) node _ram_4_T_503 = or(_ram_4_T_502, _ram_4_T_500) wire _ram_4_WIRE_80 : UInt<1> connect _ram_4_WIRE_80, _ram_4_T_503 connect _ram_4_WIRE_65.ren1, _ram_4_WIRE_80 node _ram_4_T_504 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_4_T_505 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_4_T_506 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_4_T_507 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_4_T_508 = or(_ram_4_T_504, _ram_4_T_505) node _ram_4_T_509 = or(_ram_4_T_508, _ram_4_T_506) node _ram_4_T_510 = or(_ram_4_T_509, _ram_4_T_507) wire _ram_4_WIRE_81 : UInt<1> connect _ram_4_WIRE_81, _ram_4_T_510 connect _ram_4_WIRE_65.wen, _ram_4_WIRE_81 node _ram_4_T_511 = mux(write_mask[4][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_4_T_512 = mux(write_mask[4][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_4_T_513 = mux(write_mask[4][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_4_T_514 = mux(write_mask[4][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_4_T_515 = or(_ram_4_T_511, _ram_4_T_512) node _ram_4_T_516 = or(_ram_4_T_515, _ram_4_T_513) node _ram_4_T_517 = or(_ram_4_T_516, _ram_4_T_514) wire _ram_4_WIRE_82 : UInt<1> connect _ram_4_WIRE_82, _ram_4_T_517 connect _ram_4_WIRE_65.ldst, _ram_4_WIRE_82 connect _ram_4_WIRE_1.fp_ctrl, _ram_4_WIRE_65 wire _ram_4_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_4_T_518 = mux(write_mask[4][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_4_T_519 = mux(write_mask[4][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_4_T_520 = mux(write_mask[4][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_4_T_521 = mux(write_mask[4][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_4_T_522 = or(_ram_4_T_518, _ram_4_T_519) node _ram_4_T_523 = or(_ram_4_T_522, _ram_4_T_520) node _ram_4_T_524 = or(_ram_4_T_523, _ram_4_T_521) wire _ram_4_WIRE_84 : UInt<1> connect _ram_4_WIRE_84, _ram_4_T_524 connect _ram_4_WIRE_83.vec, _ram_4_WIRE_84 node _ram_4_T_525 = mux(write_mask[4][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_4_T_526 = mux(write_mask[4][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_4_T_527 = mux(write_mask[4][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_4_T_528 = mux(write_mask[4][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_4_T_529 = or(_ram_4_T_525, _ram_4_T_526) node _ram_4_T_530 = or(_ram_4_T_529, _ram_4_T_527) node _ram_4_T_531 = or(_ram_4_T_530, _ram_4_T_528) wire _ram_4_WIRE_85 : UInt<1> connect _ram_4_WIRE_85, _ram_4_T_531 connect _ram_4_WIRE_83.dp, _ram_4_WIRE_85 node _ram_4_T_532 = mux(write_mask[4][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_4_T_533 = mux(write_mask[4][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_4_T_534 = mux(write_mask[4][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_4_T_535 = mux(write_mask[4][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_4_T_536 = or(_ram_4_T_532, _ram_4_T_533) node _ram_4_T_537 = or(_ram_4_T_536, _ram_4_T_534) node _ram_4_T_538 = or(_ram_4_T_537, _ram_4_T_535) wire _ram_4_WIRE_86 : UInt<1> connect _ram_4_WIRE_86, _ram_4_T_538 connect _ram_4_WIRE_83.amo, _ram_4_WIRE_86 node _ram_4_T_539 = mux(write_mask[4][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_4_T_540 = mux(write_mask[4][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_4_T_541 = mux(write_mask[4][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_4_T_542 = mux(write_mask[4][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_4_T_543 = or(_ram_4_T_539, _ram_4_T_540) node _ram_4_T_544 = or(_ram_4_T_543, _ram_4_T_541) node _ram_4_T_545 = or(_ram_4_T_544, _ram_4_T_542) wire _ram_4_WIRE_87 : UInt<1> connect _ram_4_WIRE_87, _ram_4_T_545 connect _ram_4_WIRE_83.fence, _ram_4_WIRE_87 node _ram_4_T_546 = mux(write_mask[4][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_4_T_547 = mux(write_mask[4][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_4_T_548 = mux(write_mask[4][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_4_T_549 = mux(write_mask[4][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_4_T_550 = or(_ram_4_T_546, _ram_4_T_547) node _ram_4_T_551 = or(_ram_4_T_550, _ram_4_T_548) node _ram_4_T_552 = or(_ram_4_T_551, _ram_4_T_549) wire _ram_4_WIRE_88 : UInt<1> connect _ram_4_WIRE_88, _ram_4_T_552 connect _ram_4_WIRE_83.fence_i, _ram_4_WIRE_88 node _ram_4_T_553 = mux(write_mask[4][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_4_T_554 = mux(write_mask[4][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_4_T_555 = mux(write_mask[4][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_4_T_556 = mux(write_mask[4][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_4_T_557 = or(_ram_4_T_553, _ram_4_T_554) node _ram_4_T_558 = or(_ram_4_T_557, _ram_4_T_555) node _ram_4_T_559 = or(_ram_4_T_558, _ram_4_T_556) wire _ram_4_WIRE_89 : UInt<3> connect _ram_4_WIRE_89, _ram_4_T_559 connect _ram_4_WIRE_83.csr, _ram_4_WIRE_89 node _ram_4_T_560 = mux(write_mask[4][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_4_T_561 = mux(write_mask[4][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_4_T_562 = mux(write_mask[4][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_4_T_563 = mux(write_mask[4][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_4_T_564 = or(_ram_4_T_560, _ram_4_T_561) node _ram_4_T_565 = or(_ram_4_T_564, _ram_4_T_562) node _ram_4_T_566 = or(_ram_4_T_565, _ram_4_T_563) wire _ram_4_WIRE_90 : UInt<1> connect _ram_4_WIRE_90, _ram_4_T_566 connect _ram_4_WIRE_83.wxd, _ram_4_WIRE_90 node _ram_4_T_567 = mux(write_mask[4][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_4_T_568 = mux(write_mask[4][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_4_T_569 = mux(write_mask[4][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_4_T_570 = mux(write_mask[4][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_4_T_571 = or(_ram_4_T_567, _ram_4_T_568) node _ram_4_T_572 = or(_ram_4_T_571, _ram_4_T_569) node _ram_4_T_573 = or(_ram_4_T_572, _ram_4_T_570) wire _ram_4_WIRE_91 : UInt<1> connect _ram_4_WIRE_91, _ram_4_T_573 connect _ram_4_WIRE_83.div, _ram_4_WIRE_91 node _ram_4_T_574 = mux(write_mask[4][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_4_T_575 = mux(write_mask[4][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_4_T_576 = mux(write_mask[4][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_4_T_577 = mux(write_mask[4][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_4_T_578 = or(_ram_4_T_574, _ram_4_T_575) node _ram_4_T_579 = or(_ram_4_T_578, _ram_4_T_576) node _ram_4_T_580 = or(_ram_4_T_579, _ram_4_T_577) wire _ram_4_WIRE_92 : UInt<1> connect _ram_4_WIRE_92, _ram_4_T_580 connect _ram_4_WIRE_83.mul, _ram_4_WIRE_92 node _ram_4_T_581 = mux(write_mask[4][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_4_T_582 = mux(write_mask[4][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_4_T_583 = mux(write_mask[4][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_4_T_584 = mux(write_mask[4][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_4_T_585 = or(_ram_4_T_581, _ram_4_T_582) node _ram_4_T_586 = or(_ram_4_T_585, _ram_4_T_583) node _ram_4_T_587 = or(_ram_4_T_586, _ram_4_T_584) wire _ram_4_WIRE_93 : UInt<1> connect _ram_4_WIRE_93, _ram_4_T_587 connect _ram_4_WIRE_83.wfd, _ram_4_WIRE_93 node _ram_4_T_588 = mux(write_mask[4][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_4_T_589 = mux(write_mask[4][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_4_T_590 = mux(write_mask[4][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_4_T_591 = mux(write_mask[4][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_4_T_592 = or(_ram_4_T_588, _ram_4_T_589) node _ram_4_T_593 = or(_ram_4_T_592, _ram_4_T_590) node _ram_4_T_594 = or(_ram_4_T_593, _ram_4_T_591) wire _ram_4_WIRE_94 : UInt<1> connect _ram_4_WIRE_94, _ram_4_T_594 connect _ram_4_WIRE_83.rfs3, _ram_4_WIRE_94 node _ram_4_T_595 = mux(write_mask[4][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_4_T_596 = mux(write_mask[4][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_4_T_597 = mux(write_mask[4][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_4_T_598 = mux(write_mask[4][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_4_T_599 = or(_ram_4_T_595, _ram_4_T_596) node _ram_4_T_600 = or(_ram_4_T_599, _ram_4_T_597) node _ram_4_T_601 = or(_ram_4_T_600, _ram_4_T_598) wire _ram_4_WIRE_95 : UInt<1> connect _ram_4_WIRE_95, _ram_4_T_601 connect _ram_4_WIRE_83.rfs2, _ram_4_WIRE_95 node _ram_4_T_602 = mux(write_mask[4][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_4_T_603 = mux(write_mask[4][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_4_T_604 = mux(write_mask[4][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_4_T_605 = mux(write_mask[4][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_4_T_606 = or(_ram_4_T_602, _ram_4_T_603) node _ram_4_T_607 = or(_ram_4_T_606, _ram_4_T_604) node _ram_4_T_608 = or(_ram_4_T_607, _ram_4_T_605) wire _ram_4_WIRE_96 : UInt<1> connect _ram_4_WIRE_96, _ram_4_T_608 connect _ram_4_WIRE_83.rfs1, _ram_4_WIRE_96 node _ram_4_T_609 = mux(write_mask[4][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_4_T_610 = mux(write_mask[4][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_4_T_611 = mux(write_mask[4][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_4_T_612 = mux(write_mask[4][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_4_T_613 = or(_ram_4_T_609, _ram_4_T_610) node _ram_4_T_614 = or(_ram_4_T_613, _ram_4_T_611) node _ram_4_T_615 = or(_ram_4_T_614, _ram_4_T_612) wire _ram_4_WIRE_97 : UInt<5> connect _ram_4_WIRE_97, _ram_4_T_615 connect _ram_4_WIRE_83.mem_cmd, _ram_4_WIRE_97 node _ram_4_T_616 = mux(write_mask[4][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_4_T_617 = mux(write_mask[4][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_4_T_618 = mux(write_mask[4][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_4_T_619 = mux(write_mask[4][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_4_T_620 = or(_ram_4_T_616, _ram_4_T_617) node _ram_4_T_621 = or(_ram_4_T_620, _ram_4_T_618) node _ram_4_T_622 = or(_ram_4_T_621, _ram_4_T_619) wire _ram_4_WIRE_98 : UInt<1> connect _ram_4_WIRE_98, _ram_4_T_622 connect _ram_4_WIRE_83.mem, _ram_4_WIRE_98 node _ram_4_T_623 = mux(write_mask[4][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_4_T_624 = mux(write_mask[4][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_4_T_625 = mux(write_mask[4][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_4_T_626 = mux(write_mask[4][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_4_T_627 = or(_ram_4_T_623, _ram_4_T_624) node _ram_4_T_628 = or(_ram_4_T_627, _ram_4_T_625) node _ram_4_T_629 = or(_ram_4_T_628, _ram_4_T_626) wire _ram_4_WIRE_99 : UInt<5> connect _ram_4_WIRE_99, _ram_4_T_629 connect _ram_4_WIRE_83.alu_fn, _ram_4_WIRE_99 node _ram_4_T_630 = mux(write_mask[4][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_4_T_631 = mux(write_mask[4][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_4_T_632 = mux(write_mask[4][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_4_T_633 = mux(write_mask[4][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_4_T_634 = or(_ram_4_T_630, _ram_4_T_631) node _ram_4_T_635 = or(_ram_4_T_634, _ram_4_T_632) node _ram_4_T_636 = or(_ram_4_T_635, _ram_4_T_633) wire _ram_4_WIRE_100 : UInt<1> connect _ram_4_WIRE_100, _ram_4_T_636 connect _ram_4_WIRE_83.alu_dw, _ram_4_WIRE_100 node _ram_4_T_637 = mux(write_mask[4][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_4_T_638 = mux(write_mask[4][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_4_T_639 = mux(write_mask[4][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_4_T_640 = mux(write_mask[4][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_4_T_641 = or(_ram_4_T_637, _ram_4_T_638) node _ram_4_T_642 = or(_ram_4_T_641, _ram_4_T_639) node _ram_4_T_643 = or(_ram_4_T_642, _ram_4_T_640) wire _ram_4_WIRE_101 : UInt<3> connect _ram_4_WIRE_101, _ram_4_T_643 connect _ram_4_WIRE_83.sel_imm, _ram_4_WIRE_101 node _ram_4_T_644 = mux(write_mask[4][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_4_T_645 = mux(write_mask[4][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_4_T_646 = mux(write_mask[4][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_4_T_647 = mux(write_mask[4][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_4_T_648 = or(_ram_4_T_644, _ram_4_T_645) node _ram_4_T_649 = or(_ram_4_T_648, _ram_4_T_646) node _ram_4_T_650 = or(_ram_4_T_649, _ram_4_T_647) wire _ram_4_WIRE_102 : UInt<2> connect _ram_4_WIRE_102, _ram_4_T_650 connect _ram_4_WIRE_83.sel_alu1, _ram_4_WIRE_102 node _ram_4_T_651 = mux(write_mask[4][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_4_T_652 = mux(write_mask[4][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_4_T_653 = mux(write_mask[4][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_4_T_654 = mux(write_mask[4][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_4_T_655 = or(_ram_4_T_651, _ram_4_T_652) node _ram_4_T_656 = or(_ram_4_T_655, _ram_4_T_653) node _ram_4_T_657 = or(_ram_4_T_656, _ram_4_T_654) wire _ram_4_WIRE_103 : UInt<3> connect _ram_4_WIRE_103, _ram_4_T_657 connect _ram_4_WIRE_83.sel_alu2, _ram_4_WIRE_103 node _ram_4_T_658 = mux(write_mask[4][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_4_T_659 = mux(write_mask[4][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_4_T_660 = mux(write_mask[4][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_4_T_661 = mux(write_mask[4][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_4_T_662 = or(_ram_4_T_658, _ram_4_T_659) node _ram_4_T_663 = or(_ram_4_T_662, _ram_4_T_660) node _ram_4_T_664 = or(_ram_4_T_663, _ram_4_T_661) wire _ram_4_WIRE_104 : UInt<1> connect _ram_4_WIRE_104, _ram_4_T_664 connect _ram_4_WIRE_83.rxs1, _ram_4_WIRE_104 node _ram_4_T_665 = mux(write_mask[4][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_4_T_666 = mux(write_mask[4][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_4_T_667 = mux(write_mask[4][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_4_T_668 = mux(write_mask[4][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_4_T_669 = or(_ram_4_T_665, _ram_4_T_666) node _ram_4_T_670 = or(_ram_4_T_669, _ram_4_T_667) node _ram_4_T_671 = or(_ram_4_T_670, _ram_4_T_668) wire _ram_4_WIRE_105 : UInt<1> connect _ram_4_WIRE_105, _ram_4_T_671 connect _ram_4_WIRE_83.rxs2, _ram_4_WIRE_105 node _ram_4_T_672 = mux(write_mask[4][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_4_T_673 = mux(write_mask[4][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_4_T_674 = mux(write_mask[4][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_4_T_675 = mux(write_mask[4][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_4_T_676 = or(_ram_4_T_672, _ram_4_T_673) node _ram_4_T_677 = or(_ram_4_T_676, _ram_4_T_674) node _ram_4_T_678 = or(_ram_4_T_677, _ram_4_T_675) wire _ram_4_WIRE_106 : UInt<1> connect _ram_4_WIRE_106, _ram_4_T_678 connect _ram_4_WIRE_83.jalr, _ram_4_WIRE_106 node _ram_4_T_679 = mux(write_mask[4][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_4_T_680 = mux(write_mask[4][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_4_T_681 = mux(write_mask[4][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_4_T_682 = mux(write_mask[4][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_4_T_683 = or(_ram_4_T_679, _ram_4_T_680) node _ram_4_T_684 = or(_ram_4_T_683, _ram_4_T_681) node _ram_4_T_685 = or(_ram_4_T_684, _ram_4_T_682) wire _ram_4_WIRE_107 : UInt<1> connect _ram_4_WIRE_107, _ram_4_T_685 connect _ram_4_WIRE_83.jal, _ram_4_WIRE_107 node _ram_4_T_686 = mux(write_mask[4][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_4_T_687 = mux(write_mask[4][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_4_T_688 = mux(write_mask[4][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_4_T_689 = mux(write_mask[4][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_4_T_690 = or(_ram_4_T_686, _ram_4_T_687) node _ram_4_T_691 = or(_ram_4_T_690, _ram_4_T_688) node _ram_4_T_692 = or(_ram_4_T_691, _ram_4_T_689) wire _ram_4_WIRE_108 : UInt<1> connect _ram_4_WIRE_108, _ram_4_T_692 connect _ram_4_WIRE_83.branch, _ram_4_WIRE_108 node _ram_4_T_693 = mux(write_mask[4][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_4_T_694 = mux(write_mask[4][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_4_T_695 = mux(write_mask[4][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_4_T_696 = mux(write_mask[4][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_4_T_697 = or(_ram_4_T_693, _ram_4_T_694) node _ram_4_T_698 = or(_ram_4_T_697, _ram_4_T_695) node _ram_4_T_699 = or(_ram_4_T_698, _ram_4_T_696) wire _ram_4_WIRE_109 : UInt<1> connect _ram_4_WIRE_109, _ram_4_T_699 connect _ram_4_WIRE_83.rocc, _ram_4_WIRE_109 node _ram_4_T_700 = mux(write_mask[4][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_4_T_701 = mux(write_mask[4][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_4_T_702 = mux(write_mask[4][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_4_T_703 = mux(write_mask[4][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_4_T_704 = or(_ram_4_T_700, _ram_4_T_701) node _ram_4_T_705 = or(_ram_4_T_704, _ram_4_T_702) node _ram_4_T_706 = or(_ram_4_T_705, _ram_4_T_703) wire _ram_4_WIRE_110 : UInt<1> connect _ram_4_WIRE_110, _ram_4_T_706 connect _ram_4_WIRE_83.fp, _ram_4_WIRE_110 node _ram_4_T_707 = mux(write_mask[4][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_4_T_708 = mux(write_mask[4][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_4_T_709 = mux(write_mask[4][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_4_T_710 = mux(write_mask[4][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_4_T_711 = or(_ram_4_T_707, _ram_4_T_708) node _ram_4_T_712 = or(_ram_4_T_711, _ram_4_T_709) node _ram_4_T_713 = or(_ram_4_T_712, _ram_4_T_710) wire _ram_4_WIRE_111 : UInt<1> connect _ram_4_WIRE_111, _ram_4_T_713 connect _ram_4_WIRE_83.legal, _ram_4_WIRE_111 connect _ram_4_WIRE_1.ctrl, _ram_4_WIRE_83 node _ram_4_T_714 = mux(write_mask[4][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_4_T_715 = mux(write_mask[4][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_4_T_716 = mux(write_mask[4][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_4_T_717 = mux(write_mask[4][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_4_T_718 = or(_ram_4_T_714, _ram_4_T_715) node _ram_4_T_719 = or(_ram_4_T_718, _ram_4_T_716) node _ram_4_T_720 = or(_ram_4_T_719, _ram_4_T_717) wire _ram_4_WIRE_112 : UInt<1> connect _ram_4_WIRE_112, _ram_4_T_720 connect _ram_4_WIRE_1.edge_inst, _ram_4_WIRE_112 node _ram_4_T_721 = mux(write_mask[4][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_4_T_722 = mux(write_mask[4][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_4_T_723 = mux(write_mask[4][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_4_T_724 = mux(write_mask[4][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_4_T_725 = or(_ram_4_T_721, _ram_4_T_722) node _ram_4_T_726 = or(_ram_4_T_725, _ram_4_T_723) node _ram_4_T_727 = or(_ram_4_T_726, _ram_4_T_724) wire _ram_4_WIRE_113 : UInt<40> connect _ram_4_WIRE_113, _ram_4_T_727 connect _ram_4_WIRE_1.pc, _ram_4_WIRE_113 node _ram_4_T_728 = mux(write_mask[4][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_4_T_729 = mux(write_mask[4][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_4_T_730 = mux(write_mask[4][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_4_T_731 = mux(write_mask[4][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_4_T_732 = or(_ram_4_T_728, _ram_4_T_729) node _ram_4_T_733 = or(_ram_4_T_732, _ram_4_T_730) node _ram_4_T_734 = or(_ram_4_T_733, _ram_4_T_731) wire _ram_4_WIRE_114 : UInt<32> connect _ram_4_WIRE_114, _ram_4_T_734 connect _ram_4_WIRE_1.raw_inst, _ram_4_WIRE_114 node _ram_4_T_735 = mux(write_mask[4][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_4_T_736 = mux(write_mask[4][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_4_T_737 = mux(write_mask[4][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_4_T_738 = mux(write_mask[4][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_4_T_739 = or(_ram_4_T_735, _ram_4_T_736) node _ram_4_T_740 = or(_ram_4_T_739, _ram_4_T_737) node _ram_4_T_741 = or(_ram_4_T_740, _ram_4_T_738) wire _ram_4_WIRE_115 : UInt<32> connect _ram_4_WIRE_115, _ram_4_T_741 connect _ram_4_WIRE_1.inst, _ram_4_WIRE_115 connect _ram_4_WIRE.bits, _ram_4_WIRE_1 node _ram_4_T_742 = mux(write_mask[4][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_4_T_743 = mux(write_mask[4][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_4_T_744 = mux(write_mask[4][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_4_T_745 = mux(write_mask[4][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_4_T_746 = or(_ram_4_T_742, _ram_4_T_743) node _ram_4_T_747 = or(_ram_4_T_746, _ram_4_T_744) node _ram_4_T_748 = or(_ram_4_T_747, _ram_4_T_745) wire _ram_4_WIRE_116 : UInt<1> connect _ram_4_WIRE_116, _ram_4_T_748 connect _ram_4_WIRE.valid, _ram_4_WIRE_116 connect ram[4], _ram_4_WIRE node _T_26 = eq(ram[5].valid, UInt<1>(0h0)) when _T_26 : wire _ram_5_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_5_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_5_T = mux(write_mask[5][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_5_T_1 = mux(write_mask[5][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_5_T_2 = mux(write_mask[5][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_5_T_3 = mux(write_mask[5][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_5_T_4 = or(_ram_5_T, _ram_5_T_1) node _ram_5_T_5 = or(_ram_5_T_4, _ram_5_T_2) node _ram_5_T_6 = or(_ram_5_T_5, _ram_5_T_3) wire _ram_5_WIRE_2 : UInt<1> connect _ram_5_WIRE_2, _ram_5_T_6 connect _ram_5_WIRE_1.flush_pipe, _ram_5_WIRE_2 node _ram_5_T_7 = mux(write_mask[5][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_5_T_8 = mux(write_mask[5][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_5_T_9 = mux(write_mask[5][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_5_T_10 = mux(write_mask[5][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_5_T_11 = or(_ram_5_T_7, _ram_5_T_8) node _ram_5_T_12 = or(_ram_5_T_11, _ram_5_T_9) node _ram_5_T_13 = or(_ram_5_T_12, _ram_5_T_10) wire _ram_5_WIRE_3 : UInt<2> connect _ram_5_WIRE_3, _ram_5_T_13 connect _ram_5_WIRE_1.mem_size, _ram_5_WIRE_3 wire _ram_5_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_5_T_14 = mux(write_mask[5][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_5_T_15 = mux(write_mask[5][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_5_T_16 = mux(write_mask[5][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_5_T_17 = mux(write_mask[5][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_5_T_18 = or(_ram_5_T_14, _ram_5_T_15) node _ram_5_T_19 = or(_ram_5_T_18, _ram_5_T_16) node _ram_5_T_20 = or(_ram_5_T_19, _ram_5_T_17) wire _ram_5_WIRE_5 : UInt<65> connect _ram_5_WIRE_5, _ram_5_T_20 connect _ram_5_WIRE_4.in3, _ram_5_WIRE_5 node _ram_5_T_21 = mux(write_mask[5][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_5_T_22 = mux(write_mask[5][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_5_T_23 = mux(write_mask[5][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_5_T_24 = mux(write_mask[5][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_5_T_25 = or(_ram_5_T_21, _ram_5_T_22) node _ram_5_T_26 = or(_ram_5_T_25, _ram_5_T_23) node _ram_5_T_27 = or(_ram_5_T_26, _ram_5_T_24) wire _ram_5_WIRE_6 : UInt<65> connect _ram_5_WIRE_6, _ram_5_T_27 connect _ram_5_WIRE_4.in2, _ram_5_WIRE_6 node _ram_5_T_28 = mux(write_mask[5][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_5_T_29 = mux(write_mask[5][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_5_T_30 = mux(write_mask[5][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_5_T_31 = mux(write_mask[5][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_5_T_32 = or(_ram_5_T_28, _ram_5_T_29) node _ram_5_T_33 = or(_ram_5_T_32, _ram_5_T_30) node _ram_5_T_34 = or(_ram_5_T_33, _ram_5_T_31) wire _ram_5_WIRE_7 : UInt<65> connect _ram_5_WIRE_7, _ram_5_T_34 connect _ram_5_WIRE_4.in1, _ram_5_WIRE_7 node _ram_5_T_35 = mux(write_mask[5][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_5_T_36 = mux(write_mask[5][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_5_T_37 = mux(write_mask[5][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_5_T_38 = mux(write_mask[5][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_5_T_39 = or(_ram_5_T_35, _ram_5_T_36) node _ram_5_T_40 = or(_ram_5_T_39, _ram_5_T_37) node _ram_5_T_41 = or(_ram_5_T_40, _ram_5_T_38) wire _ram_5_WIRE_8 : UInt<2> connect _ram_5_WIRE_8, _ram_5_T_41 connect _ram_5_WIRE_4.fmt, _ram_5_WIRE_8 node _ram_5_T_42 = mux(write_mask[5][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_5_T_43 = mux(write_mask[5][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_5_T_44 = mux(write_mask[5][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_5_T_45 = mux(write_mask[5][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_5_T_46 = or(_ram_5_T_42, _ram_5_T_43) node _ram_5_T_47 = or(_ram_5_T_46, _ram_5_T_44) node _ram_5_T_48 = or(_ram_5_T_47, _ram_5_T_45) wire _ram_5_WIRE_9 : UInt<2> connect _ram_5_WIRE_9, _ram_5_T_48 connect _ram_5_WIRE_4.typ, _ram_5_WIRE_9 node _ram_5_T_49 = mux(write_mask[5][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_5_T_50 = mux(write_mask[5][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_5_T_51 = mux(write_mask[5][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_5_T_52 = mux(write_mask[5][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_5_T_53 = or(_ram_5_T_49, _ram_5_T_50) node _ram_5_T_54 = or(_ram_5_T_53, _ram_5_T_51) node _ram_5_T_55 = or(_ram_5_T_54, _ram_5_T_52) wire _ram_5_WIRE_10 : UInt<2> connect _ram_5_WIRE_10, _ram_5_T_55 connect _ram_5_WIRE_4.fmaCmd, _ram_5_WIRE_10 node _ram_5_T_56 = mux(write_mask[5][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_5_T_57 = mux(write_mask[5][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_5_T_58 = mux(write_mask[5][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_5_T_59 = mux(write_mask[5][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_5_T_60 = or(_ram_5_T_56, _ram_5_T_57) node _ram_5_T_61 = or(_ram_5_T_60, _ram_5_T_58) node _ram_5_T_62 = or(_ram_5_T_61, _ram_5_T_59) wire _ram_5_WIRE_11 : UInt<3> connect _ram_5_WIRE_11, _ram_5_T_62 connect _ram_5_WIRE_4.rm, _ram_5_WIRE_11 node _ram_5_T_63 = mux(write_mask[5][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_5_T_64 = mux(write_mask[5][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_5_T_65 = mux(write_mask[5][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_5_T_66 = mux(write_mask[5][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_5_T_67 = or(_ram_5_T_63, _ram_5_T_64) node _ram_5_T_68 = or(_ram_5_T_67, _ram_5_T_65) node _ram_5_T_69 = or(_ram_5_T_68, _ram_5_T_66) wire _ram_5_WIRE_12 : UInt<1> connect _ram_5_WIRE_12, _ram_5_T_69 connect _ram_5_WIRE_4.vec, _ram_5_WIRE_12 node _ram_5_T_70 = mux(write_mask[5][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_5_T_71 = mux(write_mask[5][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_5_T_72 = mux(write_mask[5][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_5_T_73 = mux(write_mask[5][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_5_T_74 = or(_ram_5_T_70, _ram_5_T_71) node _ram_5_T_75 = or(_ram_5_T_74, _ram_5_T_72) node _ram_5_T_76 = or(_ram_5_T_75, _ram_5_T_73) wire _ram_5_WIRE_13 : UInt<1> connect _ram_5_WIRE_13, _ram_5_T_76 connect _ram_5_WIRE_4.wflags, _ram_5_WIRE_13 node _ram_5_T_77 = mux(write_mask[5][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_5_T_78 = mux(write_mask[5][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_5_T_79 = mux(write_mask[5][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_5_T_80 = mux(write_mask[5][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_5_T_81 = or(_ram_5_T_77, _ram_5_T_78) node _ram_5_T_82 = or(_ram_5_T_81, _ram_5_T_79) node _ram_5_T_83 = or(_ram_5_T_82, _ram_5_T_80) wire _ram_5_WIRE_14 : UInt<1> connect _ram_5_WIRE_14, _ram_5_T_83 connect _ram_5_WIRE_4.sqrt, _ram_5_WIRE_14 node _ram_5_T_84 = mux(write_mask[5][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_5_T_85 = mux(write_mask[5][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_5_T_86 = mux(write_mask[5][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_5_T_87 = mux(write_mask[5][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_5_T_88 = or(_ram_5_T_84, _ram_5_T_85) node _ram_5_T_89 = or(_ram_5_T_88, _ram_5_T_86) node _ram_5_T_90 = or(_ram_5_T_89, _ram_5_T_87) wire _ram_5_WIRE_15 : UInt<1> connect _ram_5_WIRE_15, _ram_5_T_90 connect _ram_5_WIRE_4.div, _ram_5_WIRE_15 node _ram_5_T_91 = mux(write_mask[5][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_5_T_92 = mux(write_mask[5][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_5_T_93 = mux(write_mask[5][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_5_T_94 = mux(write_mask[5][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_5_T_95 = or(_ram_5_T_91, _ram_5_T_92) node _ram_5_T_96 = or(_ram_5_T_95, _ram_5_T_93) node _ram_5_T_97 = or(_ram_5_T_96, _ram_5_T_94) wire _ram_5_WIRE_16 : UInt<1> connect _ram_5_WIRE_16, _ram_5_T_97 connect _ram_5_WIRE_4.fma, _ram_5_WIRE_16 node _ram_5_T_98 = mux(write_mask[5][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_5_T_99 = mux(write_mask[5][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_5_T_100 = mux(write_mask[5][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_5_T_101 = mux(write_mask[5][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_5_T_102 = or(_ram_5_T_98, _ram_5_T_99) node _ram_5_T_103 = or(_ram_5_T_102, _ram_5_T_100) node _ram_5_T_104 = or(_ram_5_T_103, _ram_5_T_101) wire _ram_5_WIRE_17 : UInt<1> connect _ram_5_WIRE_17, _ram_5_T_104 connect _ram_5_WIRE_4.fastpipe, _ram_5_WIRE_17 node _ram_5_T_105 = mux(write_mask[5][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_5_T_106 = mux(write_mask[5][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_5_T_107 = mux(write_mask[5][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_5_T_108 = mux(write_mask[5][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_5_T_109 = or(_ram_5_T_105, _ram_5_T_106) node _ram_5_T_110 = or(_ram_5_T_109, _ram_5_T_107) node _ram_5_T_111 = or(_ram_5_T_110, _ram_5_T_108) wire _ram_5_WIRE_18 : UInt<1> connect _ram_5_WIRE_18, _ram_5_T_111 connect _ram_5_WIRE_4.toint, _ram_5_WIRE_18 node _ram_5_T_112 = mux(write_mask[5][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_5_T_113 = mux(write_mask[5][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_5_T_114 = mux(write_mask[5][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_5_T_115 = mux(write_mask[5][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_5_T_116 = or(_ram_5_T_112, _ram_5_T_113) node _ram_5_T_117 = or(_ram_5_T_116, _ram_5_T_114) node _ram_5_T_118 = or(_ram_5_T_117, _ram_5_T_115) wire _ram_5_WIRE_19 : UInt<1> connect _ram_5_WIRE_19, _ram_5_T_118 connect _ram_5_WIRE_4.fromint, _ram_5_WIRE_19 node _ram_5_T_119 = mux(write_mask[5][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_5_T_120 = mux(write_mask[5][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_5_T_121 = mux(write_mask[5][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_5_T_122 = mux(write_mask[5][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_5_T_123 = or(_ram_5_T_119, _ram_5_T_120) node _ram_5_T_124 = or(_ram_5_T_123, _ram_5_T_121) node _ram_5_T_125 = or(_ram_5_T_124, _ram_5_T_122) wire _ram_5_WIRE_20 : UInt<2> connect _ram_5_WIRE_20, _ram_5_T_125 connect _ram_5_WIRE_4.typeTagOut, _ram_5_WIRE_20 node _ram_5_T_126 = mux(write_mask[5][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_5_T_127 = mux(write_mask[5][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_5_T_128 = mux(write_mask[5][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_5_T_129 = mux(write_mask[5][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_5_T_130 = or(_ram_5_T_126, _ram_5_T_127) node _ram_5_T_131 = or(_ram_5_T_130, _ram_5_T_128) node _ram_5_T_132 = or(_ram_5_T_131, _ram_5_T_129) wire _ram_5_WIRE_21 : UInt<2> connect _ram_5_WIRE_21, _ram_5_T_132 connect _ram_5_WIRE_4.typeTagIn, _ram_5_WIRE_21 node _ram_5_T_133 = mux(write_mask[5][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_5_T_134 = mux(write_mask[5][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_5_T_135 = mux(write_mask[5][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_5_T_136 = mux(write_mask[5][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_5_T_137 = or(_ram_5_T_133, _ram_5_T_134) node _ram_5_T_138 = or(_ram_5_T_137, _ram_5_T_135) node _ram_5_T_139 = or(_ram_5_T_138, _ram_5_T_136) wire _ram_5_WIRE_22 : UInt<1> connect _ram_5_WIRE_22, _ram_5_T_139 connect _ram_5_WIRE_4.swap23, _ram_5_WIRE_22 node _ram_5_T_140 = mux(write_mask[5][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_5_T_141 = mux(write_mask[5][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_5_T_142 = mux(write_mask[5][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_5_T_143 = mux(write_mask[5][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_5_T_144 = or(_ram_5_T_140, _ram_5_T_141) node _ram_5_T_145 = or(_ram_5_T_144, _ram_5_T_142) node _ram_5_T_146 = or(_ram_5_T_145, _ram_5_T_143) wire _ram_5_WIRE_23 : UInt<1> connect _ram_5_WIRE_23, _ram_5_T_146 connect _ram_5_WIRE_4.swap12, _ram_5_WIRE_23 node _ram_5_T_147 = mux(write_mask[5][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_5_T_148 = mux(write_mask[5][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_5_T_149 = mux(write_mask[5][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_5_T_150 = mux(write_mask[5][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_5_T_151 = or(_ram_5_T_147, _ram_5_T_148) node _ram_5_T_152 = or(_ram_5_T_151, _ram_5_T_149) node _ram_5_T_153 = or(_ram_5_T_152, _ram_5_T_150) wire _ram_5_WIRE_24 : UInt<1> connect _ram_5_WIRE_24, _ram_5_T_153 connect _ram_5_WIRE_4.ren3, _ram_5_WIRE_24 node _ram_5_T_154 = mux(write_mask[5][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_5_T_155 = mux(write_mask[5][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_5_T_156 = mux(write_mask[5][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_5_T_157 = mux(write_mask[5][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_5_T_158 = or(_ram_5_T_154, _ram_5_T_155) node _ram_5_T_159 = or(_ram_5_T_158, _ram_5_T_156) node _ram_5_T_160 = or(_ram_5_T_159, _ram_5_T_157) wire _ram_5_WIRE_25 : UInt<1> connect _ram_5_WIRE_25, _ram_5_T_160 connect _ram_5_WIRE_4.ren2, _ram_5_WIRE_25 node _ram_5_T_161 = mux(write_mask[5][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_5_T_162 = mux(write_mask[5][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_5_T_163 = mux(write_mask[5][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_5_T_164 = mux(write_mask[5][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_5_T_165 = or(_ram_5_T_161, _ram_5_T_162) node _ram_5_T_166 = or(_ram_5_T_165, _ram_5_T_163) node _ram_5_T_167 = or(_ram_5_T_166, _ram_5_T_164) wire _ram_5_WIRE_26 : UInt<1> connect _ram_5_WIRE_26, _ram_5_T_167 connect _ram_5_WIRE_4.ren1, _ram_5_WIRE_26 node _ram_5_T_168 = mux(write_mask[5][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_5_T_169 = mux(write_mask[5][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_5_T_170 = mux(write_mask[5][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_5_T_171 = mux(write_mask[5][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_5_T_172 = or(_ram_5_T_168, _ram_5_T_169) node _ram_5_T_173 = or(_ram_5_T_172, _ram_5_T_170) node _ram_5_T_174 = or(_ram_5_T_173, _ram_5_T_171) wire _ram_5_WIRE_27 : UInt<1> connect _ram_5_WIRE_27, _ram_5_T_174 connect _ram_5_WIRE_4.wen, _ram_5_WIRE_27 node _ram_5_T_175 = mux(write_mask[5][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_5_T_176 = mux(write_mask[5][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_5_T_177 = mux(write_mask[5][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_5_T_178 = mux(write_mask[5][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_5_T_179 = or(_ram_5_T_175, _ram_5_T_176) node _ram_5_T_180 = or(_ram_5_T_179, _ram_5_T_177) node _ram_5_T_181 = or(_ram_5_T_180, _ram_5_T_178) wire _ram_5_WIRE_28 : UInt<1> connect _ram_5_WIRE_28, _ram_5_T_181 connect _ram_5_WIRE_4.ldst, _ram_5_WIRE_28 connect _ram_5_WIRE_1.fdivin, _ram_5_WIRE_4 node _ram_5_T_182 = mux(write_mask[5][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_5_T_183 = mux(write_mask[5][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_5_T_184 = mux(write_mask[5][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_5_T_185 = mux(write_mask[5][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_5_T_186 = or(_ram_5_T_182, _ram_5_T_183) node _ram_5_T_187 = or(_ram_5_T_186, _ram_5_T_184) node _ram_5_T_188 = or(_ram_5_T_187, _ram_5_T_185) wire _ram_5_WIRE_29 : UInt<5> connect _ram_5_WIRE_29, _ram_5_T_188 connect _ram_5_WIRE_1.fexc, _ram_5_WIRE_29 node _ram_5_T_189 = mux(write_mask[5][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_5_T_190 = mux(write_mask[5][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_5_T_191 = mux(write_mask[5][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_5_T_192 = mux(write_mask[5][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_5_T_193 = or(_ram_5_T_189, _ram_5_T_190) node _ram_5_T_194 = or(_ram_5_T_193, _ram_5_T_191) node _ram_5_T_195 = or(_ram_5_T_194, _ram_5_T_192) wire _ram_5_WIRE_30 : UInt<5> connect _ram_5_WIRE_30, _ram_5_T_195 connect _ram_5_WIRE_1.fra3, _ram_5_WIRE_30 node _ram_5_T_196 = mux(write_mask[5][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_5_T_197 = mux(write_mask[5][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_5_T_198 = mux(write_mask[5][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_5_T_199 = mux(write_mask[5][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_5_T_200 = or(_ram_5_T_196, _ram_5_T_197) node _ram_5_T_201 = or(_ram_5_T_200, _ram_5_T_198) node _ram_5_T_202 = or(_ram_5_T_201, _ram_5_T_199) wire _ram_5_WIRE_31 : UInt<5> connect _ram_5_WIRE_31, _ram_5_T_202 connect _ram_5_WIRE_1.fra2, _ram_5_WIRE_31 node _ram_5_T_203 = mux(write_mask[5][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_5_T_204 = mux(write_mask[5][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_5_T_205 = mux(write_mask[5][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_5_T_206 = mux(write_mask[5][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_5_T_207 = or(_ram_5_T_203, _ram_5_T_204) node _ram_5_T_208 = or(_ram_5_T_207, _ram_5_T_205) node _ram_5_T_209 = or(_ram_5_T_208, _ram_5_T_206) wire _ram_5_WIRE_32 : UInt<5> connect _ram_5_WIRE_32, _ram_5_T_209 connect _ram_5_WIRE_1.fra1, _ram_5_WIRE_32 wire _ram_5_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_5_T_210 = mux(write_mask[5][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_5_T_211 = mux(write_mask[5][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_5_T_212 = mux(write_mask[5][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_5_T_213 = mux(write_mask[5][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_5_T_214 = or(_ram_5_T_210, _ram_5_T_211) node _ram_5_T_215 = or(_ram_5_T_214, _ram_5_T_212) node _ram_5_T_216 = or(_ram_5_T_215, _ram_5_T_213) wire _ram_5_WIRE_34 : UInt<64> connect _ram_5_WIRE_34, _ram_5_T_216 connect _ram_5_WIRE_33.bits, _ram_5_WIRE_34 node _ram_5_T_217 = mux(write_mask[5][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_5_T_218 = mux(write_mask[5][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_5_T_219 = mux(write_mask[5][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_5_T_220 = mux(write_mask[5][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_5_T_221 = or(_ram_5_T_217, _ram_5_T_218) node _ram_5_T_222 = or(_ram_5_T_221, _ram_5_T_219) node _ram_5_T_223 = or(_ram_5_T_222, _ram_5_T_220) wire _ram_5_WIRE_35 : UInt<1> connect _ram_5_WIRE_35, _ram_5_T_223 connect _ram_5_WIRE_33.valid, _ram_5_WIRE_35 connect _ram_5_WIRE_1.wdata, _ram_5_WIRE_33 node _ram_5_T_224 = mux(write_mask[5][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_5_T_225 = mux(write_mask[5][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_5_T_226 = mux(write_mask[5][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_5_T_227 = mux(write_mask[5][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_5_T_228 = or(_ram_5_T_224, _ram_5_T_225) node _ram_5_T_229 = or(_ram_5_T_228, _ram_5_T_226) node _ram_5_T_230 = or(_ram_5_T_229, _ram_5_T_227) wire _ram_5_WIRE_36 : UInt<1> connect _ram_5_WIRE_36, _ram_5_T_230 connect _ram_5_WIRE_1.uses_latealu, _ram_5_WIRE_36 node _ram_5_T_231 = mux(write_mask[5][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_5_T_232 = mux(write_mask[5][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_5_T_233 = mux(write_mask[5][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_5_T_234 = mux(write_mask[5][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_5_T_235 = or(_ram_5_T_231, _ram_5_T_232) node _ram_5_T_236 = or(_ram_5_T_235, _ram_5_T_233) node _ram_5_T_237 = or(_ram_5_T_236, _ram_5_T_234) wire _ram_5_WIRE_37 : UInt<1> connect _ram_5_WIRE_37, _ram_5_T_237 connect _ram_5_WIRE_1.uses_memalu, _ram_5_WIRE_37 node _ram_5_T_238 = mux(write_mask[5][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_5_T_239 = mux(write_mask[5][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_5_T_240 = mux(write_mask[5][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_5_T_241 = mux(write_mask[5][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_5_T_242 = or(_ram_5_T_238, _ram_5_T_239) node _ram_5_T_243 = or(_ram_5_T_242, _ram_5_T_240) node _ram_5_T_244 = or(_ram_5_T_243, _ram_5_T_241) wire _ram_5_WIRE_38 : UInt<64> connect _ram_5_WIRE_38, _ram_5_T_244 connect _ram_5_WIRE_1.rs3_data, _ram_5_WIRE_38 node _ram_5_T_245 = mux(write_mask[5][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_5_T_246 = mux(write_mask[5][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_5_T_247 = mux(write_mask[5][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_5_T_248 = mux(write_mask[5][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_5_T_249 = or(_ram_5_T_245, _ram_5_T_246) node _ram_5_T_250 = or(_ram_5_T_249, _ram_5_T_247) node _ram_5_T_251 = or(_ram_5_T_250, _ram_5_T_248) wire _ram_5_WIRE_39 : UInt<64> connect _ram_5_WIRE_39, _ram_5_T_251 connect _ram_5_WIRE_1.rs2_data, _ram_5_WIRE_39 node _ram_5_T_252 = mux(write_mask[5][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_5_T_253 = mux(write_mask[5][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_5_T_254 = mux(write_mask[5][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_5_T_255 = mux(write_mask[5][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_5_T_256 = or(_ram_5_T_252, _ram_5_T_253) node _ram_5_T_257 = or(_ram_5_T_256, _ram_5_T_254) node _ram_5_T_258 = or(_ram_5_T_257, _ram_5_T_255) wire _ram_5_WIRE_40 : UInt<64> connect _ram_5_WIRE_40, _ram_5_T_258 connect _ram_5_WIRE_1.rs1_data, _ram_5_WIRE_40 node _ram_5_T_259 = mux(write_mask[5][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_5_T_260 = mux(write_mask[5][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_5_T_261 = mux(write_mask[5][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_5_T_262 = mux(write_mask[5][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_5_T_263 = or(_ram_5_T_259, _ram_5_T_260) node _ram_5_T_264 = or(_ram_5_T_263, _ram_5_T_261) node _ram_5_T_265 = or(_ram_5_T_264, _ram_5_T_262) wire _ram_5_WIRE_41 : UInt<1> connect _ram_5_WIRE_41, _ram_5_T_265 connect _ram_5_WIRE_1.needs_replay, _ram_5_WIRE_41 node _ram_5_T_266 = mux(write_mask[5][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_5_T_267 = mux(write_mask[5][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_5_T_268 = mux(write_mask[5][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_5_T_269 = mux(write_mask[5][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_5_T_270 = or(_ram_5_T_266, _ram_5_T_267) node _ram_5_T_271 = or(_ram_5_T_270, _ram_5_T_268) node _ram_5_T_272 = or(_ram_5_T_271, _ram_5_T_269) wire _ram_5_WIRE_42 : UInt<64> connect _ram_5_WIRE_42, _ram_5_T_272 connect _ram_5_WIRE_1.xcpt_cause, _ram_5_WIRE_42 node _ram_5_T_273 = mux(write_mask[5][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_5_T_274 = mux(write_mask[5][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_5_T_275 = mux(write_mask[5][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_5_T_276 = mux(write_mask[5][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_5_T_277 = or(_ram_5_T_273, _ram_5_T_274) node _ram_5_T_278 = or(_ram_5_T_277, _ram_5_T_275) node _ram_5_T_279 = or(_ram_5_T_278, _ram_5_T_276) wire _ram_5_WIRE_43 : UInt<1> connect _ram_5_WIRE_43, _ram_5_T_279 connect _ram_5_WIRE_1.xcpt, _ram_5_WIRE_43 node _ram_5_T_280 = mux(write_mask[5][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_5_T_281 = mux(write_mask[5][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_5_T_282 = mux(write_mask[5][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_5_T_283 = mux(write_mask[5][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_5_T_284 = or(_ram_5_T_280, _ram_5_T_281) node _ram_5_T_285 = or(_ram_5_T_284, _ram_5_T_282) node _ram_5_T_286 = or(_ram_5_T_285, _ram_5_T_283) wire _ram_5_WIRE_44 : UInt<1> connect _ram_5_WIRE_44, _ram_5_T_286 connect _ram_5_WIRE_1.taken, _ram_5_WIRE_44 node _ram_5_T_287 = mux(write_mask[5][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_5_T_288 = mux(write_mask[5][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_5_T_289 = mux(write_mask[5][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_5_T_290 = mux(write_mask[5][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_5_T_291 = or(_ram_5_T_287, _ram_5_T_288) node _ram_5_T_292 = or(_ram_5_T_291, _ram_5_T_289) node _ram_5_T_293 = or(_ram_5_T_292, _ram_5_T_290) wire _ram_5_WIRE_45 : UInt<3> connect _ram_5_WIRE_45, _ram_5_T_293 connect _ram_5_WIRE_1.ras_head, _ram_5_WIRE_45 wire _ram_5_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_5_T_294 = mux(write_mask[5][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_5_T_295 = mux(write_mask[5][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_5_T_296 = mux(write_mask[5][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_5_T_297 = mux(write_mask[5][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_5_T_298 = or(_ram_5_T_294, _ram_5_T_295) node _ram_5_T_299 = or(_ram_5_T_298, _ram_5_T_296) node _ram_5_T_300 = or(_ram_5_T_299, _ram_5_T_297) wire _ram_5_WIRE_47 : UInt<40> connect _ram_5_WIRE_47, _ram_5_T_300 connect _ram_5_WIRE_46.bits, _ram_5_WIRE_47 node _ram_5_T_301 = mux(write_mask[5][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_5_T_302 = mux(write_mask[5][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_5_T_303 = mux(write_mask[5][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_5_T_304 = mux(write_mask[5][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_5_T_305 = or(_ram_5_T_301, _ram_5_T_302) node _ram_5_T_306 = or(_ram_5_T_305, _ram_5_T_303) node _ram_5_T_307 = or(_ram_5_T_306, _ram_5_T_304) wire _ram_5_WIRE_48 : UInt<1> connect _ram_5_WIRE_48, _ram_5_T_307 connect _ram_5_WIRE_46.valid, _ram_5_WIRE_48 connect _ram_5_WIRE_1.next_pc, _ram_5_WIRE_46 node _ram_5_T_308 = mux(write_mask[5][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_5_T_309 = mux(write_mask[5][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_5_T_310 = mux(write_mask[5][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_5_T_311 = mux(write_mask[5][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_5_T_312 = or(_ram_5_T_308, _ram_5_T_309) node _ram_5_T_313 = or(_ram_5_T_312, _ram_5_T_310) node _ram_5_T_314 = or(_ram_5_T_313, _ram_5_T_311) wire _ram_5_WIRE_49 : UInt<1> connect _ram_5_WIRE_49, _ram_5_T_314 connect _ram_5_WIRE_1.sfb_shadow, _ram_5_WIRE_49 node _ram_5_T_315 = mux(write_mask[5][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_5_T_316 = mux(write_mask[5][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_5_T_317 = mux(write_mask[5][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_5_T_318 = mux(write_mask[5][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_5_T_319 = or(_ram_5_T_315, _ram_5_T_316) node _ram_5_T_320 = or(_ram_5_T_319, _ram_5_T_317) node _ram_5_T_321 = or(_ram_5_T_320, _ram_5_T_318) wire _ram_5_WIRE_50 : UInt<1> connect _ram_5_WIRE_50, _ram_5_T_321 connect _ram_5_WIRE_1.sfb_br, _ram_5_WIRE_50 wire _ram_5_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_5_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_5_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_5_T_322 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_5_T_323 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_5_T_324 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_5_T_325 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_5_T_326 = or(_ram_5_T_322, _ram_5_T_323) node _ram_5_T_327 = or(_ram_5_T_326, _ram_5_T_324) node _ram_5_T_328 = or(_ram_5_T_327, _ram_5_T_325) wire _ram_5_WIRE_54 : UInt<2> connect _ram_5_WIRE_54, _ram_5_T_328 connect _ram_5_WIRE_53.value, _ram_5_WIRE_54 node _ram_5_T_329 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_5_T_330 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_5_T_331 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_5_T_332 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_5_T_333 = or(_ram_5_T_329, _ram_5_T_330) node _ram_5_T_334 = or(_ram_5_T_333, _ram_5_T_331) node _ram_5_T_335 = or(_ram_5_T_334, _ram_5_T_332) wire _ram_5_WIRE_55 : UInt<8> connect _ram_5_WIRE_55, _ram_5_T_335 connect _ram_5_WIRE_53.history, _ram_5_WIRE_55 connect _ram_5_WIRE_52.bht, _ram_5_WIRE_53 node _ram_5_T_336 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_5_T_337 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_5_T_338 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_5_T_339 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_5_T_340 = or(_ram_5_T_336, _ram_5_T_337) node _ram_5_T_341 = or(_ram_5_T_340, _ram_5_T_338) node _ram_5_T_342 = or(_ram_5_T_341, _ram_5_T_339) wire _ram_5_WIRE_56 : UInt<6> connect _ram_5_WIRE_56, _ram_5_T_342 connect _ram_5_WIRE_52.entry, _ram_5_WIRE_56 node _ram_5_T_343 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_5_T_344 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_5_T_345 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_5_T_346 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_5_T_347 = or(_ram_5_T_343, _ram_5_T_344) node _ram_5_T_348 = or(_ram_5_T_347, _ram_5_T_345) node _ram_5_T_349 = or(_ram_5_T_348, _ram_5_T_346) wire _ram_5_WIRE_57 : UInt<39> connect _ram_5_WIRE_57, _ram_5_T_349 connect _ram_5_WIRE_52.target, _ram_5_WIRE_57 node _ram_5_T_350 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_5_T_351 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_5_T_352 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_5_T_353 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_5_T_354 = or(_ram_5_T_350, _ram_5_T_351) node _ram_5_T_355 = or(_ram_5_T_354, _ram_5_T_352) node _ram_5_T_356 = or(_ram_5_T_355, _ram_5_T_353) wire _ram_5_WIRE_58 : UInt<2> connect _ram_5_WIRE_58, _ram_5_T_356 connect _ram_5_WIRE_52.bridx, _ram_5_WIRE_58 node _ram_5_T_357 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_5_T_358 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_5_T_359 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_5_T_360 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_5_T_361 = or(_ram_5_T_357, _ram_5_T_358) node _ram_5_T_362 = or(_ram_5_T_361, _ram_5_T_359) node _ram_5_T_363 = or(_ram_5_T_362, _ram_5_T_360) wire _ram_5_WIRE_59 : UInt<4> connect _ram_5_WIRE_59, _ram_5_T_363 connect _ram_5_WIRE_52.mask, _ram_5_WIRE_59 node _ram_5_T_364 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_5_T_365 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_5_T_366 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_5_T_367 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_5_T_368 = or(_ram_5_T_364, _ram_5_T_365) node _ram_5_T_369 = or(_ram_5_T_368, _ram_5_T_366) node _ram_5_T_370 = or(_ram_5_T_369, _ram_5_T_367) wire _ram_5_WIRE_60 : UInt<1> connect _ram_5_WIRE_60, _ram_5_T_370 connect _ram_5_WIRE_52.taken, _ram_5_WIRE_60 node _ram_5_T_371 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_5_T_372 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_5_T_373 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_5_T_374 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_5_T_375 = or(_ram_5_T_371, _ram_5_T_372) node _ram_5_T_376 = or(_ram_5_T_375, _ram_5_T_373) node _ram_5_T_377 = or(_ram_5_T_376, _ram_5_T_374) wire _ram_5_WIRE_61 : UInt<2> connect _ram_5_WIRE_61, _ram_5_T_377 connect _ram_5_WIRE_52.cfiType, _ram_5_WIRE_61 connect _ram_5_WIRE_51.bits, _ram_5_WIRE_52 node _ram_5_T_378 = mux(write_mask[5][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_5_T_379 = mux(write_mask[5][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_5_T_380 = mux(write_mask[5][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_5_T_381 = mux(write_mask[5][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_5_T_382 = or(_ram_5_T_378, _ram_5_T_379) node _ram_5_T_383 = or(_ram_5_T_382, _ram_5_T_380) node _ram_5_T_384 = or(_ram_5_T_383, _ram_5_T_381) wire _ram_5_WIRE_62 : UInt<1> connect _ram_5_WIRE_62, _ram_5_T_384 connect _ram_5_WIRE_51.valid, _ram_5_WIRE_62 connect _ram_5_WIRE_1.btb_resp, _ram_5_WIRE_51 node _ram_5_T_385 = mux(write_mask[5][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_5_T_386 = mux(write_mask[5][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_5_T_387 = mux(write_mask[5][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_5_T_388 = mux(write_mask[5][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_5_T_389 = or(_ram_5_T_385, _ram_5_T_386) node _ram_5_T_390 = or(_ram_5_T_389, _ram_5_T_387) node _ram_5_T_391 = or(_ram_5_T_390, _ram_5_T_388) wire _ram_5_WIRE_63 : UInt<1> connect _ram_5_WIRE_63, _ram_5_T_391 connect _ram_5_WIRE_1.sets_vcfg, _ram_5_WIRE_63 node _ram_5_T_392 = mux(write_mask[5][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_5_T_393 = mux(write_mask[5][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_5_T_394 = mux(write_mask[5][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_5_T_395 = mux(write_mask[5][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_5_T_396 = or(_ram_5_T_392, _ram_5_T_393) node _ram_5_T_397 = or(_ram_5_T_396, _ram_5_T_394) node _ram_5_T_398 = or(_ram_5_T_397, _ram_5_T_395) wire _ram_5_WIRE_64 : UInt<1> connect _ram_5_WIRE_64, _ram_5_T_398 connect _ram_5_WIRE_1.rvc, _ram_5_WIRE_64 wire _ram_5_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_5_T_399 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_5_T_400 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_5_T_401 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_5_T_402 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_5_T_403 = or(_ram_5_T_399, _ram_5_T_400) node _ram_5_T_404 = or(_ram_5_T_403, _ram_5_T_401) node _ram_5_T_405 = or(_ram_5_T_404, _ram_5_T_402) wire _ram_5_WIRE_66 : UInt<1> connect _ram_5_WIRE_66, _ram_5_T_405 connect _ram_5_WIRE_65.vec, _ram_5_WIRE_66 node _ram_5_T_406 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_5_T_407 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_5_T_408 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_5_T_409 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_5_T_410 = or(_ram_5_T_406, _ram_5_T_407) node _ram_5_T_411 = or(_ram_5_T_410, _ram_5_T_408) node _ram_5_T_412 = or(_ram_5_T_411, _ram_5_T_409) wire _ram_5_WIRE_67 : UInt<1> connect _ram_5_WIRE_67, _ram_5_T_412 connect _ram_5_WIRE_65.wflags, _ram_5_WIRE_67 node _ram_5_T_413 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_5_T_414 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_5_T_415 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_5_T_416 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_5_T_417 = or(_ram_5_T_413, _ram_5_T_414) node _ram_5_T_418 = or(_ram_5_T_417, _ram_5_T_415) node _ram_5_T_419 = or(_ram_5_T_418, _ram_5_T_416) wire _ram_5_WIRE_68 : UInt<1> connect _ram_5_WIRE_68, _ram_5_T_419 connect _ram_5_WIRE_65.sqrt, _ram_5_WIRE_68 node _ram_5_T_420 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_5_T_421 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_5_T_422 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_5_T_423 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_5_T_424 = or(_ram_5_T_420, _ram_5_T_421) node _ram_5_T_425 = or(_ram_5_T_424, _ram_5_T_422) node _ram_5_T_426 = or(_ram_5_T_425, _ram_5_T_423) wire _ram_5_WIRE_69 : UInt<1> connect _ram_5_WIRE_69, _ram_5_T_426 connect _ram_5_WIRE_65.div, _ram_5_WIRE_69 node _ram_5_T_427 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_5_T_428 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_5_T_429 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_5_T_430 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_5_T_431 = or(_ram_5_T_427, _ram_5_T_428) node _ram_5_T_432 = or(_ram_5_T_431, _ram_5_T_429) node _ram_5_T_433 = or(_ram_5_T_432, _ram_5_T_430) wire _ram_5_WIRE_70 : UInt<1> connect _ram_5_WIRE_70, _ram_5_T_433 connect _ram_5_WIRE_65.fma, _ram_5_WIRE_70 node _ram_5_T_434 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_5_T_435 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_5_T_436 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_5_T_437 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_5_T_438 = or(_ram_5_T_434, _ram_5_T_435) node _ram_5_T_439 = or(_ram_5_T_438, _ram_5_T_436) node _ram_5_T_440 = or(_ram_5_T_439, _ram_5_T_437) wire _ram_5_WIRE_71 : UInt<1> connect _ram_5_WIRE_71, _ram_5_T_440 connect _ram_5_WIRE_65.fastpipe, _ram_5_WIRE_71 node _ram_5_T_441 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_5_T_442 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_5_T_443 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_5_T_444 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_5_T_445 = or(_ram_5_T_441, _ram_5_T_442) node _ram_5_T_446 = or(_ram_5_T_445, _ram_5_T_443) node _ram_5_T_447 = or(_ram_5_T_446, _ram_5_T_444) wire _ram_5_WIRE_72 : UInt<1> connect _ram_5_WIRE_72, _ram_5_T_447 connect _ram_5_WIRE_65.toint, _ram_5_WIRE_72 node _ram_5_T_448 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_5_T_449 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_5_T_450 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_5_T_451 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_5_T_452 = or(_ram_5_T_448, _ram_5_T_449) node _ram_5_T_453 = or(_ram_5_T_452, _ram_5_T_450) node _ram_5_T_454 = or(_ram_5_T_453, _ram_5_T_451) wire _ram_5_WIRE_73 : UInt<1> connect _ram_5_WIRE_73, _ram_5_T_454 connect _ram_5_WIRE_65.fromint, _ram_5_WIRE_73 node _ram_5_T_455 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_5_T_456 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_5_T_457 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_5_T_458 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_5_T_459 = or(_ram_5_T_455, _ram_5_T_456) node _ram_5_T_460 = or(_ram_5_T_459, _ram_5_T_457) node _ram_5_T_461 = or(_ram_5_T_460, _ram_5_T_458) wire _ram_5_WIRE_74 : UInt<2> connect _ram_5_WIRE_74, _ram_5_T_461 connect _ram_5_WIRE_65.typeTagOut, _ram_5_WIRE_74 node _ram_5_T_462 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_5_T_463 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_5_T_464 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_5_T_465 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_5_T_466 = or(_ram_5_T_462, _ram_5_T_463) node _ram_5_T_467 = or(_ram_5_T_466, _ram_5_T_464) node _ram_5_T_468 = or(_ram_5_T_467, _ram_5_T_465) wire _ram_5_WIRE_75 : UInt<2> connect _ram_5_WIRE_75, _ram_5_T_468 connect _ram_5_WIRE_65.typeTagIn, _ram_5_WIRE_75 node _ram_5_T_469 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_5_T_470 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_5_T_471 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_5_T_472 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_5_T_473 = or(_ram_5_T_469, _ram_5_T_470) node _ram_5_T_474 = or(_ram_5_T_473, _ram_5_T_471) node _ram_5_T_475 = or(_ram_5_T_474, _ram_5_T_472) wire _ram_5_WIRE_76 : UInt<1> connect _ram_5_WIRE_76, _ram_5_T_475 connect _ram_5_WIRE_65.swap23, _ram_5_WIRE_76 node _ram_5_T_476 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_5_T_477 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_5_T_478 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_5_T_479 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_5_T_480 = or(_ram_5_T_476, _ram_5_T_477) node _ram_5_T_481 = or(_ram_5_T_480, _ram_5_T_478) node _ram_5_T_482 = or(_ram_5_T_481, _ram_5_T_479) wire _ram_5_WIRE_77 : UInt<1> connect _ram_5_WIRE_77, _ram_5_T_482 connect _ram_5_WIRE_65.swap12, _ram_5_WIRE_77 node _ram_5_T_483 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_5_T_484 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_5_T_485 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_5_T_486 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_5_T_487 = or(_ram_5_T_483, _ram_5_T_484) node _ram_5_T_488 = or(_ram_5_T_487, _ram_5_T_485) node _ram_5_T_489 = or(_ram_5_T_488, _ram_5_T_486) wire _ram_5_WIRE_78 : UInt<1> connect _ram_5_WIRE_78, _ram_5_T_489 connect _ram_5_WIRE_65.ren3, _ram_5_WIRE_78 node _ram_5_T_490 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_5_T_491 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_5_T_492 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_5_T_493 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_5_T_494 = or(_ram_5_T_490, _ram_5_T_491) node _ram_5_T_495 = or(_ram_5_T_494, _ram_5_T_492) node _ram_5_T_496 = or(_ram_5_T_495, _ram_5_T_493) wire _ram_5_WIRE_79 : UInt<1> connect _ram_5_WIRE_79, _ram_5_T_496 connect _ram_5_WIRE_65.ren2, _ram_5_WIRE_79 node _ram_5_T_497 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_5_T_498 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_5_T_499 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_5_T_500 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_5_T_501 = or(_ram_5_T_497, _ram_5_T_498) node _ram_5_T_502 = or(_ram_5_T_501, _ram_5_T_499) node _ram_5_T_503 = or(_ram_5_T_502, _ram_5_T_500) wire _ram_5_WIRE_80 : UInt<1> connect _ram_5_WIRE_80, _ram_5_T_503 connect _ram_5_WIRE_65.ren1, _ram_5_WIRE_80 node _ram_5_T_504 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_5_T_505 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_5_T_506 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_5_T_507 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_5_T_508 = or(_ram_5_T_504, _ram_5_T_505) node _ram_5_T_509 = or(_ram_5_T_508, _ram_5_T_506) node _ram_5_T_510 = or(_ram_5_T_509, _ram_5_T_507) wire _ram_5_WIRE_81 : UInt<1> connect _ram_5_WIRE_81, _ram_5_T_510 connect _ram_5_WIRE_65.wen, _ram_5_WIRE_81 node _ram_5_T_511 = mux(write_mask[5][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_5_T_512 = mux(write_mask[5][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_5_T_513 = mux(write_mask[5][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_5_T_514 = mux(write_mask[5][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_5_T_515 = or(_ram_5_T_511, _ram_5_T_512) node _ram_5_T_516 = or(_ram_5_T_515, _ram_5_T_513) node _ram_5_T_517 = or(_ram_5_T_516, _ram_5_T_514) wire _ram_5_WIRE_82 : UInt<1> connect _ram_5_WIRE_82, _ram_5_T_517 connect _ram_5_WIRE_65.ldst, _ram_5_WIRE_82 connect _ram_5_WIRE_1.fp_ctrl, _ram_5_WIRE_65 wire _ram_5_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_5_T_518 = mux(write_mask[5][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_5_T_519 = mux(write_mask[5][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_5_T_520 = mux(write_mask[5][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_5_T_521 = mux(write_mask[5][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_5_T_522 = or(_ram_5_T_518, _ram_5_T_519) node _ram_5_T_523 = or(_ram_5_T_522, _ram_5_T_520) node _ram_5_T_524 = or(_ram_5_T_523, _ram_5_T_521) wire _ram_5_WIRE_84 : UInt<1> connect _ram_5_WIRE_84, _ram_5_T_524 connect _ram_5_WIRE_83.vec, _ram_5_WIRE_84 node _ram_5_T_525 = mux(write_mask[5][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_5_T_526 = mux(write_mask[5][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_5_T_527 = mux(write_mask[5][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_5_T_528 = mux(write_mask[5][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_5_T_529 = or(_ram_5_T_525, _ram_5_T_526) node _ram_5_T_530 = or(_ram_5_T_529, _ram_5_T_527) node _ram_5_T_531 = or(_ram_5_T_530, _ram_5_T_528) wire _ram_5_WIRE_85 : UInt<1> connect _ram_5_WIRE_85, _ram_5_T_531 connect _ram_5_WIRE_83.dp, _ram_5_WIRE_85 node _ram_5_T_532 = mux(write_mask[5][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_5_T_533 = mux(write_mask[5][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_5_T_534 = mux(write_mask[5][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_5_T_535 = mux(write_mask[5][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_5_T_536 = or(_ram_5_T_532, _ram_5_T_533) node _ram_5_T_537 = or(_ram_5_T_536, _ram_5_T_534) node _ram_5_T_538 = or(_ram_5_T_537, _ram_5_T_535) wire _ram_5_WIRE_86 : UInt<1> connect _ram_5_WIRE_86, _ram_5_T_538 connect _ram_5_WIRE_83.amo, _ram_5_WIRE_86 node _ram_5_T_539 = mux(write_mask[5][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_5_T_540 = mux(write_mask[5][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_5_T_541 = mux(write_mask[5][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_5_T_542 = mux(write_mask[5][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_5_T_543 = or(_ram_5_T_539, _ram_5_T_540) node _ram_5_T_544 = or(_ram_5_T_543, _ram_5_T_541) node _ram_5_T_545 = or(_ram_5_T_544, _ram_5_T_542) wire _ram_5_WIRE_87 : UInt<1> connect _ram_5_WIRE_87, _ram_5_T_545 connect _ram_5_WIRE_83.fence, _ram_5_WIRE_87 node _ram_5_T_546 = mux(write_mask[5][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_5_T_547 = mux(write_mask[5][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_5_T_548 = mux(write_mask[5][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_5_T_549 = mux(write_mask[5][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_5_T_550 = or(_ram_5_T_546, _ram_5_T_547) node _ram_5_T_551 = or(_ram_5_T_550, _ram_5_T_548) node _ram_5_T_552 = or(_ram_5_T_551, _ram_5_T_549) wire _ram_5_WIRE_88 : UInt<1> connect _ram_5_WIRE_88, _ram_5_T_552 connect _ram_5_WIRE_83.fence_i, _ram_5_WIRE_88 node _ram_5_T_553 = mux(write_mask[5][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_5_T_554 = mux(write_mask[5][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_5_T_555 = mux(write_mask[5][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_5_T_556 = mux(write_mask[5][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_5_T_557 = or(_ram_5_T_553, _ram_5_T_554) node _ram_5_T_558 = or(_ram_5_T_557, _ram_5_T_555) node _ram_5_T_559 = or(_ram_5_T_558, _ram_5_T_556) wire _ram_5_WIRE_89 : UInt<3> connect _ram_5_WIRE_89, _ram_5_T_559 connect _ram_5_WIRE_83.csr, _ram_5_WIRE_89 node _ram_5_T_560 = mux(write_mask[5][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_5_T_561 = mux(write_mask[5][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_5_T_562 = mux(write_mask[5][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_5_T_563 = mux(write_mask[5][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_5_T_564 = or(_ram_5_T_560, _ram_5_T_561) node _ram_5_T_565 = or(_ram_5_T_564, _ram_5_T_562) node _ram_5_T_566 = or(_ram_5_T_565, _ram_5_T_563) wire _ram_5_WIRE_90 : UInt<1> connect _ram_5_WIRE_90, _ram_5_T_566 connect _ram_5_WIRE_83.wxd, _ram_5_WIRE_90 node _ram_5_T_567 = mux(write_mask[5][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_5_T_568 = mux(write_mask[5][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_5_T_569 = mux(write_mask[5][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_5_T_570 = mux(write_mask[5][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_5_T_571 = or(_ram_5_T_567, _ram_5_T_568) node _ram_5_T_572 = or(_ram_5_T_571, _ram_5_T_569) node _ram_5_T_573 = or(_ram_5_T_572, _ram_5_T_570) wire _ram_5_WIRE_91 : UInt<1> connect _ram_5_WIRE_91, _ram_5_T_573 connect _ram_5_WIRE_83.div, _ram_5_WIRE_91 node _ram_5_T_574 = mux(write_mask[5][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_5_T_575 = mux(write_mask[5][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_5_T_576 = mux(write_mask[5][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_5_T_577 = mux(write_mask[5][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_5_T_578 = or(_ram_5_T_574, _ram_5_T_575) node _ram_5_T_579 = or(_ram_5_T_578, _ram_5_T_576) node _ram_5_T_580 = or(_ram_5_T_579, _ram_5_T_577) wire _ram_5_WIRE_92 : UInt<1> connect _ram_5_WIRE_92, _ram_5_T_580 connect _ram_5_WIRE_83.mul, _ram_5_WIRE_92 node _ram_5_T_581 = mux(write_mask[5][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_5_T_582 = mux(write_mask[5][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_5_T_583 = mux(write_mask[5][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_5_T_584 = mux(write_mask[5][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_5_T_585 = or(_ram_5_T_581, _ram_5_T_582) node _ram_5_T_586 = or(_ram_5_T_585, _ram_5_T_583) node _ram_5_T_587 = or(_ram_5_T_586, _ram_5_T_584) wire _ram_5_WIRE_93 : UInt<1> connect _ram_5_WIRE_93, _ram_5_T_587 connect _ram_5_WIRE_83.wfd, _ram_5_WIRE_93 node _ram_5_T_588 = mux(write_mask[5][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_5_T_589 = mux(write_mask[5][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_5_T_590 = mux(write_mask[5][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_5_T_591 = mux(write_mask[5][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_5_T_592 = or(_ram_5_T_588, _ram_5_T_589) node _ram_5_T_593 = or(_ram_5_T_592, _ram_5_T_590) node _ram_5_T_594 = or(_ram_5_T_593, _ram_5_T_591) wire _ram_5_WIRE_94 : UInt<1> connect _ram_5_WIRE_94, _ram_5_T_594 connect _ram_5_WIRE_83.rfs3, _ram_5_WIRE_94 node _ram_5_T_595 = mux(write_mask[5][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_5_T_596 = mux(write_mask[5][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_5_T_597 = mux(write_mask[5][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_5_T_598 = mux(write_mask[5][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_5_T_599 = or(_ram_5_T_595, _ram_5_T_596) node _ram_5_T_600 = or(_ram_5_T_599, _ram_5_T_597) node _ram_5_T_601 = or(_ram_5_T_600, _ram_5_T_598) wire _ram_5_WIRE_95 : UInt<1> connect _ram_5_WIRE_95, _ram_5_T_601 connect _ram_5_WIRE_83.rfs2, _ram_5_WIRE_95 node _ram_5_T_602 = mux(write_mask[5][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_5_T_603 = mux(write_mask[5][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_5_T_604 = mux(write_mask[5][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_5_T_605 = mux(write_mask[5][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_5_T_606 = or(_ram_5_T_602, _ram_5_T_603) node _ram_5_T_607 = or(_ram_5_T_606, _ram_5_T_604) node _ram_5_T_608 = or(_ram_5_T_607, _ram_5_T_605) wire _ram_5_WIRE_96 : UInt<1> connect _ram_5_WIRE_96, _ram_5_T_608 connect _ram_5_WIRE_83.rfs1, _ram_5_WIRE_96 node _ram_5_T_609 = mux(write_mask[5][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_5_T_610 = mux(write_mask[5][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_5_T_611 = mux(write_mask[5][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_5_T_612 = mux(write_mask[5][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_5_T_613 = or(_ram_5_T_609, _ram_5_T_610) node _ram_5_T_614 = or(_ram_5_T_613, _ram_5_T_611) node _ram_5_T_615 = or(_ram_5_T_614, _ram_5_T_612) wire _ram_5_WIRE_97 : UInt<5> connect _ram_5_WIRE_97, _ram_5_T_615 connect _ram_5_WIRE_83.mem_cmd, _ram_5_WIRE_97 node _ram_5_T_616 = mux(write_mask[5][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_5_T_617 = mux(write_mask[5][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_5_T_618 = mux(write_mask[5][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_5_T_619 = mux(write_mask[5][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_5_T_620 = or(_ram_5_T_616, _ram_5_T_617) node _ram_5_T_621 = or(_ram_5_T_620, _ram_5_T_618) node _ram_5_T_622 = or(_ram_5_T_621, _ram_5_T_619) wire _ram_5_WIRE_98 : UInt<1> connect _ram_5_WIRE_98, _ram_5_T_622 connect _ram_5_WIRE_83.mem, _ram_5_WIRE_98 node _ram_5_T_623 = mux(write_mask[5][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_5_T_624 = mux(write_mask[5][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_5_T_625 = mux(write_mask[5][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_5_T_626 = mux(write_mask[5][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_5_T_627 = or(_ram_5_T_623, _ram_5_T_624) node _ram_5_T_628 = or(_ram_5_T_627, _ram_5_T_625) node _ram_5_T_629 = or(_ram_5_T_628, _ram_5_T_626) wire _ram_5_WIRE_99 : UInt<5> connect _ram_5_WIRE_99, _ram_5_T_629 connect _ram_5_WIRE_83.alu_fn, _ram_5_WIRE_99 node _ram_5_T_630 = mux(write_mask[5][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_5_T_631 = mux(write_mask[5][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_5_T_632 = mux(write_mask[5][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_5_T_633 = mux(write_mask[5][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_5_T_634 = or(_ram_5_T_630, _ram_5_T_631) node _ram_5_T_635 = or(_ram_5_T_634, _ram_5_T_632) node _ram_5_T_636 = or(_ram_5_T_635, _ram_5_T_633) wire _ram_5_WIRE_100 : UInt<1> connect _ram_5_WIRE_100, _ram_5_T_636 connect _ram_5_WIRE_83.alu_dw, _ram_5_WIRE_100 node _ram_5_T_637 = mux(write_mask[5][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_5_T_638 = mux(write_mask[5][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_5_T_639 = mux(write_mask[5][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_5_T_640 = mux(write_mask[5][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_5_T_641 = or(_ram_5_T_637, _ram_5_T_638) node _ram_5_T_642 = or(_ram_5_T_641, _ram_5_T_639) node _ram_5_T_643 = or(_ram_5_T_642, _ram_5_T_640) wire _ram_5_WIRE_101 : UInt<3> connect _ram_5_WIRE_101, _ram_5_T_643 connect _ram_5_WIRE_83.sel_imm, _ram_5_WIRE_101 node _ram_5_T_644 = mux(write_mask[5][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_5_T_645 = mux(write_mask[5][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_5_T_646 = mux(write_mask[5][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_5_T_647 = mux(write_mask[5][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_5_T_648 = or(_ram_5_T_644, _ram_5_T_645) node _ram_5_T_649 = or(_ram_5_T_648, _ram_5_T_646) node _ram_5_T_650 = or(_ram_5_T_649, _ram_5_T_647) wire _ram_5_WIRE_102 : UInt<2> connect _ram_5_WIRE_102, _ram_5_T_650 connect _ram_5_WIRE_83.sel_alu1, _ram_5_WIRE_102 node _ram_5_T_651 = mux(write_mask[5][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_5_T_652 = mux(write_mask[5][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_5_T_653 = mux(write_mask[5][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_5_T_654 = mux(write_mask[5][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_5_T_655 = or(_ram_5_T_651, _ram_5_T_652) node _ram_5_T_656 = or(_ram_5_T_655, _ram_5_T_653) node _ram_5_T_657 = or(_ram_5_T_656, _ram_5_T_654) wire _ram_5_WIRE_103 : UInt<3> connect _ram_5_WIRE_103, _ram_5_T_657 connect _ram_5_WIRE_83.sel_alu2, _ram_5_WIRE_103 node _ram_5_T_658 = mux(write_mask[5][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_5_T_659 = mux(write_mask[5][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_5_T_660 = mux(write_mask[5][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_5_T_661 = mux(write_mask[5][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_5_T_662 = or(_ram_5_T_658, _ram_5_T_659) node _ram_5_T_663 = or(_ram_5_T_662, _ram_5_T_660) node _ram_5_T_664 = or(_ram_5_T_663, _ram_5_T_661) wire _ram_5_WIRE_104 : UInt<1> connect _ram_5_WIRE_104, _ram_5_T_664 connect _ram_5_WIRE_83.rxs1, _ram_5_WIRE_104 node _ram_5_T_665 = mux(write_mask[5][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_5_T_666 = mux(write_mask[5][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_5_T_667 = mux(write_mask[5][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_5_T_668 = mux(write_mask[5][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_5_T_669 = or(_ram_5_T_665, _ram_5_T_666) node _ram_5_T_670 = or(_ram_5_T_669, _ram_5_T_667) node _ram_5_T_671 = or(_ram_5_T_670, _ram_5_T_668) wire _ram_5_WIRE_105 : UInt<1> connect _ram_5_WIRE_105, _ram_5_T_671 connect _ram_5_WIRE_83.rxs2, _ram_5_WIRE_105 node _ram_5_T_672 = mux(write_mask[5][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_5_T_673 = mux(write_mask[5][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_5_T_674 = mux(write_mask[5][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_5_T_675 = mux(write_mask[5][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_5_T_676 = or(_ram_5_T_672, _ram_5_T_673) node _ram_5_T_677 = or(_ram_5_T_676, _ram_5_T_674) node _ram_5_T_678 = or(_ram_5_T_677, _ram_5_T_675) wire _ram_5_WIRE_106 : UInt<1> connect _ram_5_WIRE_106, _ram_5_T_678 connect _ram_5_WIRE_83.jalr, _ram_5_WIRE_106 node _ram_5_T_679 = mux(write_mask[5][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_5_T_680 = mux(write_mask[5][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_5_T_681 = mux(write_mask[5][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_5_T_682 = mux(write_mask[5][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_5_T_683 = or(_ram_5_T_679, _ram_5_T_680) node _ram_5_T_684 = or(_ram_5_T_683, _ram_5_T_681) node _ram_5_T_685 = or(_ram_5_T_684, _ram_5_T_682) wire _ram_5_WIRE_107 : UInt<1> connect _ram_5_WIRE_107, _ram_5_T_685 connect _ram_5_WIRE_83.jal, _ram_5_WIRE_107 node _ram_5_T_686 = mux(write_mask[5][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_5_T_687 = mux(write_mask[5][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_5_T_688 = mux(write_mask[5][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_5_T_689 = mux(write_mask[5][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_5_T_690 = or(_ram_5_T_686, _ram_5_T_687) node _ram_5_T_691 = or(_ram_5_T_690, _ram_5_T_688) node _ram_5_T_692 = or(_ram_5_T_691, _ram_5_T_689) wire _ram_5_WIRE_108 : UInt<1> connect _ram_5_WIRE_108, _ram_5_T_692 connect _ram_5_WIRE_83.branch, _ram_5_WIRE_108 node _ram_5_T_693 = mux(write_mask[5][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_5_T_694 = mux(write_mask[5][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_5_T_695 = mux(write_mask[5][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_5_T_696 = mux(write_mask[5][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_5_T_697 = or(_ram_5_T_693, _ram_5_T_694) node _ram_5_T_698 = or(_ram_5_T_697, _ram_5_T_695) node _ram_5_T_699 = or(_ram_5_T_698, _ram_5_T_696) wire _ram_5_WIRE_109 : UInt<1> connect _ram_5_WIRE_109, _ram_5_T_699 connect _ram_5_WIRE_83.rocc, _ram_5_WIRE_109 node _ram_5_T_700 = mux(write_mask[5][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_5_T_701 = mux(write_mask[5][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_5_T_702 = mux(write_mask[5][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_5_T_703 = mux(write_mask[5][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_5_T_704 = or(_ram_5_T_700, _ram_5_T_701) node _ram_5_T_705 = or(_ram_5_T_704, _ram_5_T_702) node _ram_5_T_706 = or(_ram_5_T_705, _ram_5_T_703) wire _ram_5_WIRE_110 : UInt<1> connect _ram_5_WIRE_110, _ram_5_T_706 connect _ram_5_WIRE_83.fp, _ram_5_WIRE_110 node _ram_5_T_707 = mux(write_mask[5][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_5_T_708 = mux(write_mask[5][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_5_T_709 = mux(write_mask[5][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_5_T_710 = mux(write_mask[5][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_5_T_711 = or(_ram_5_T_707, _ram_5_T_708) node _ram_5_T_712 = or(_ram_5_T_711, _ram_5_T_709) node _ram_5_T_713 = or(_ram_5_T_712, _ram_5_T_710) wire _ram_5_WIRE_111 : UInt<1> connect _ram_5_WIRE_111, _ram_5_T_713 connect _ram_5_WIRE_83.legal, _ram_5_WIRE_111 connect _ram_5_WIRE_1.ctrl, _ram_5_WIRE_83 node _ram_5_T_714 = mux(write_mask[5][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_5_T_715 = mux(write_mask[5][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_5_T_716 = mux(write_mask[5][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_5_T_717 = mux(write_mask[5][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_5_T_718 = or(_ram_5_T_714, _ram_5_T_715) node _ram_5_T_719 = or(_ram_5_T_718, _ram_5_T_716) node _ram_5_T_720 = or(_ram_5_T_719, _ram_5_T_717) wire _ram_5_WIRE_112 : UInt<1> connect _ram_5_WIRE_112, _ram_5_T_720 connect _ram_5_WIRE_1.edge_inst, _ram_5_WIRE_112 node _ram_5_T_721 = mux(write_mask[5][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_5_T_722 = mux(write_mask[5][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_5_T_723 = mux(write_mask[5][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_5_T_724 = mux(write_mask[5][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_5_T_725 = or(_ram_5_T_721, _ram_5_T_722) node _ram_5_T_726 = or(_ram_5_T_725, _ram_5_T_723) node _ram_5_T_727 = or(_ram_5_T_726, _ram_5_T_724) wire _ram_5_WIRE_113 : UInt<40> connect _ram_5_WIRE_113, _ram_5_T_727 connect _ram_5_WIRE_1.pc, _ram_5_WIRE_113 node _ram_5_T_728 = mux(write_mask[5][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_5_T_729 = mux(write_mask[5][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_5_T_730 = mux(write_mask[5][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_5_T_731 = mux(write_mask[5][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_5_T_732 = or(_ram_5_T_728, _ram_5_T_729) node _ram_5_T_733 = or(_ram_5_T_732, _ram_5_T_730) node _ram_5_T_734 = or(_ram_5_T_733, _ram_5_T_731) wire _ram_5_WIRE_114 : UInt<32> connect _ram_5_WIRE_114, _ram_5_T_734 connect _ram_5_WIRE_1.raw_inst, _ram_5_WIRE_114 node _ram_5_T_735 = mux(write_mask[5][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_5_T_736 = mux(write_mask[5][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_5_T_737 = mux(write_mask[5][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_5_T_738 = mux(write_mask[5][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_5_T_739 = or(_ram_5_T_735, _ram_5_T_736) node _ram_5_T_740 = or(_ram_5_T_739, _ram_5_T_737) node _ram_5_T_741 = or(_ram_5_T_740, _ram_5_T_738) wire _ram_5_WIRE_115 : UInt<32> connect _ram_5_WIRE_115, _ram_5_T_741 connect _ram_5_WIRE_1.inst, _ram_5_WIRE_115 connect _ram_5_WIRE.bits, _ram_5_WIRE_1 node _ram_5_T_742 = mux(write_mask[5][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_5_T_743 = mux(write_mask[5][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_5_T_744 = mux(write_mask[5][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_5_T_745 = mux(write_mask[5][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_5_T_746 = or(_ram_5_T_742, _ram_5_T_743) node _ram_5_T_747 = or(_ram_5_T_746, _ram_5_T_744) node _ram_5_T_748 = or(_ram_5_T_747, _ram_5_T_745) wire _ram_5_WIRE_116 : UInt<1> connect _ram_5_WIRE_116, _ram_5_T_748 connect _ram_5_WIRE.valid, _ram_5_WIRE_116 connect ram[5], _ram_5_WIRE node _T_27 = eq(ram[6].valid, UInt<1>(0h0)) when _T_27 : wire _ram_6_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ram_6_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ram_6_T = mux(write_mask[6][0], in_uops[0].bits.flush_pipe, UInt<1>(0h0)) node _ram_6_T_1 = mux(write_mask[6][1], in_uops[1].bits.flush_pipe, UInt<1>(0h0)) node _ram_6_T_2 = mux(write_mask[6][2], in_uops[2].bits.flush_pipe, UInt<1>(0h0)) node _ram_6_T_3 = mux(write_mask[6][3], in_uops[3].bits.flush_pipe, UInt<1>(0h0)) node _ram_6_T_4 = or(_ram_6_T, _ram_6_T_1) node _ram_6_T_5 = or(_ram_6_T_4, _ram_6_T_2) node _ram_6_T_6 = or(_ram_6_T_5, _ram_6_T_3) wire _ram_6_WIRE_2 : UInt<1> connect _ram_6_WIRE_2, _ram_6_T_6 connect _ram_6_WIRE_1.flush_pipe, _ram_6_WIRE_2 node _ram_6_T_7 = mux(write_mask[6][0], in_uops[0].bits.mem_size, UInt<1>(0h0)) node _ram_6_T_8 = mux(write_mask[6][1], in_uops[1].bits.mem_size, UInt<1>(0h0)) node _ram_6_T_9 = mux(write_mask[6][2], in_uops[2].bits.mem_size, UInt<1>(0h0)) node _ram_6_T_10 = mux(write_mask[6][3], in_uops[3].bits.mem_size, UInt<1>(0h0)) node _ram_6_T_11 = or(_ram_6_T_7, _ram_6_T_8) node _ram_6_T_12 = or(_ram_6_T_11, _ram_6_T_9) node _ram_6_T_13 = or(_ram_6_T_12, _ram_6_T_10) wire _ram_6_WIRE_3 : UInt<2> connect _ram_6_WIRE_3, _ram_6_T_13 connect _ram_6_WIRE_1.mem_size, _ram_6_WIRE_3 wire _ram_6_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ram_6_T_14 = mux(write_mask[6][0], in_uops[0].bits.fdivin.in3, UInt<1>(0h0)) node _ram_6_T_15 = mux(write_mask[6][1], in_uops[1].bits.fdivin.in3, UInt<1>(0h0)) node _ram_6_T_16 = mux(write_mask[6][2], in_uops[2].bits.fdivin.in3, UInt<1>(0h0)) node _ram_6_T_17 = mux(write_mask[6][3], in_uops[3].bits.fdivin.in3, UInt<1>(0h0)) node _ram_6_T_18 = or(_ram_6_T_14, _ram_6_T_15) node _ram_6_T_19 = or(_ram_6_T_18, _ram_6_T_16) node _ram_6_T_20 = or(_ram_6_T_19, _ram_6_T_17) wire _ram_6_WIRE_5 : UInt<65> connect _ram_6_WIRE_5, _ram_6_T_20 connect _ram_6_WIRE_4.in3, _ram_6_WIRE_5 node _ram_6_T_21 = mux(write_mask[6][0], in_uops[0].bits.fdivin.in2, UInt<1>(0h0)) node _ram_6_T_22 = mux(write_mask[6][1], in_uops[1].bits.fdivin.in2, UInt<1>(0h0)) node _ram_6_T_23 = mux(write_mask[6][2], in_uops[2].bits.fdivin.in2, UInt<1>(0h0)) node _ram_6_T_24 = mux(write_mask[6][3], in_uops[3].bits.fdivin.in2, UInt<1>(0h0)) node _ram_6_T_25 = or(_ram_6_T_21, _ram_6_T_22) node _ram_6_T_26 = or(_ram_6_T_25, _ram_6_T_23) node _ram_6_T_27 = or(_ram_6_T_26, _ram_6_T_24) wire _ram_6_WIRE_6 : UInt<65> connect _ram_6_WIRE_6, _ram_6_T_27 connect _ram_6_WIRE_4.in2, _ram_6_WIRE_6 node _ram_6_T_28 = mux(write_mask[6][0], in_uops[0].bits.fdivin.in1, UInt<1>(0h0)) node _ram_6_T_29 = mux(write_mask[6][1], in_uops[1].bits.fdivin.in1, UInt<1>(0h0)) node _ram_6_T_30 = mux(write_mask[6][2], in_uops[2].bits.fdivin.in1, UInt<1>(0h0)) node _ram_6_T_31 = mux(write_mask[6][3], in_uops[3].bits.fdivin.in1, UInt<1>(0h0)) node _ram_6_T_32 = or(_ram_6_T_28, _ram_6_T_29) node _ram_6_T_33 = or(_ram_6_T_32, _ram_6_T_30) node _ram_6_T_34 = or(_ram_6_T_33, _ram_6_T_31) wire _ram_6_WIRE_7 : UInt<65> connect _ram_6_WIRE_7, _ram_6_T_34 connect _ram_6_WIRE_4.in1, _ram_6_WIRE_7 node _ram_6_T_35 = mux(write_mask[6][0], in_uops[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_6_T_36 = mux(write_mask[6][1], in_uops[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_6_T_37 = mux(write_mask[6][2], in_uops[2].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_6_T_38 = mux(write_mask[6][3], in_uops[3].bits.fdivin.fmt, UInt<1>(0h0)) node _ram_6_T_39 = or(_ram_6_T_35, _ram_6_T_36) node _ram_6_T_40 = or(_ram_6_T_39, _ram_6_T_37) node _ram_6_T_41 = or(_ram_6_T_40, _ram_6_T_38) wire _ram_6_WIRE_8 : UInt<2> connect _ram_6_WIRE_8, _ram_6_T_41 connect _ram_6_WIRE_4.fmt, _ram_6_WIRE_8 node _ram_6_T_42 = mux(write_mask[6][0], in_uops[0].bits.fdivin.typ, UInt<1>(0h0)) node _ram_6_T_43 = mux(write_mask[6][1], in_uops[1].bits.fdivin.typ, UInt<1>(0h0)) node _ram_6_T_44 = mux(write_mask[6][2], in_uops[2].bits.fdivin.typ, UInt<1>(0h0)) node _ram_6_T_45 = mux(write_mask[6][3], in_uops[3].bits.fdivin.typ, UInt<1>(0h0)) node _ram_6_T_46 = or(_ram_6_T_42, _ram_6_T_43) node _ram_6_T_47 = or(_ram_6_T_46, _ram_6_T_44) node _ram_6_T_48 = or(_ram_6_T_47, _ram_6_T_45) wire _ram_6_WIRE_9 : UInt<2> connect _ram_6_WIRE_9, _ram_6_T_48 connect _ram_6_WIRE_4.typ, _ram_6_WIRE_9 node _ram_6_T_49 = mux(write_mask[6][0], in_uops[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_6_T_50 = mux(write_mask[6][1], in_uops[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_6_T_51 = mux(write_mask[6][2], in_uops[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_6_T_52 = mux(write_mask[6][3], in_uops[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ram_6_T_53 = or(_ram_6_T_49, _ram_6_T_50) node _ram_6_T_54 = or(_ram_6_T_53, _ram_6_T_51) node _ram_6_T_55 = or(_ram_6_T_54, _ram_6_T_52) wire _ram_6_WIRE_10 : UInt<2> connect _ram_6_WIRE_10, _ram_6_T_55 connect _ram_6_WIRE_4.fmaCmd, _ram_6_WIRE_10 node _ram_6_T_56 = mux(write_mask[6][0], in_uops[0].bits.fdivin.rm, UInt<1>(0h0)) node _ram_6_T_57 = mux(write_mask[6][1], in_uops[1].bits.fdivin.rm, UInt<1>(0h0)) node _ram_6_T_58 = mux(write_mask[6][2], in_uops[2].bits.fdivin.rm, UInt<1>(0h0)) node _ram_6_T_59 = mux(write_mask[6][3], in_uops[3].bits.fdivin.rm, UInt<1>(0h0)) node _ram_6_T_60 = or(_ram_6_T_56, _ram_6_T_57) node _ram_6_T_61 = or(_ram_6_T_60, _ram_6_T_58) node _ram_6_T_62 = or(_ram_6_T_61, _ram_6_T_59) wire _ram_6_WIRE_11 : UInt<3> connect _ram_6_WIRE_11, _ram_6_T_62 connect _ram_6_WIRE_4.rm, _ram_6_WIRE_11 node _ram_6_T_63 = mux(write_mask[6][0], in_uops[0].bits.fdivin.vec, UInt<1>(0h0)) node _ram_6_T_64 = mux(write_mask[6][1], in_uops[1].bits.fdivin.vec, UInt<1>(0h0)) node _ram_6_T_65 = mux(write_mask[6][2], in_uops[2].bits.fdivin.vec, UInt<1>(0h0)) node _ram_6_T_66 = mux(write_mask[6][3], in_uops[3].bits.fdivin.vec, UInt<1>(0h0)) node _ram_6_T_67 = or(_ram_6_T_63, _ram_6_T_64) node _ram_6_T_68 = or(_ram_6_T_67, _ram_6_T_65) node _ram_6_T_69 = or(_ram_6_T_68, _ram_6_T_66) wire _ram_6_WIRE_12 : UInt<1> connect _ram_6_WIRE_12, _ram_6_T_69 connect _ram_6_WIRE_4.vec, _ram_6_WIRE_12 node _ram_6_T_70 = mux(write_mask[6][0], in_uops[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_6_T_71 = mux(write_mask[6][1], in_uops[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_6_T_72 = mux(write_mask[6][2], in_uops[2].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_6_T_73 = mux(write_mask[6][3], in_uops[3].bits.fdivin.wflags, UInt<1>(0h0)) node _ram_6_T_74 = or(_ram_6_T_70, _ram_6_T_71) node _ram_6_T_75 = or(_ram_6_T_74, _ram_6_T_72) node _ram_6_T_76 = or(_ram_6_T_75, _ram_6_T_73) wire _ram_6_WIRE_13 : UInt<1> connect _ram_6_WIRE_13, _ram_6_T_76 connect _ram_6_WIRE_4.wflags, _ram_6_WIRE_13 node _ram_6_T_77 = mux(write_mask[6][0], in_uops[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_6_T_78 = mux(write_mask[6][1], in_uops[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_6_T_79 = mux(write_mask[6][2], in_uops[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_6_T_80 = mux(write_mask[6][3], in_uops[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _ram_6_T_81 = or(_ram_6_T_77, _ram_6_T_78) node _ram_6_T_82 = or(_ram_6_T_81, _ram_6_T_79) node _ram_6_T_83 = or(_ram_6_T_82, _ram_6_T_80) wire _ram_6_WIRE_14 : UInt<1> connect _ram_6_WIRE_14, _ram_6_T_83 connect _ram_6_WIRE_4.sqrt, _ram_6_WIRE_14 node _ram_6_T_84 = mux(write_mask[6][0], in_uops[0].bits.fdivin.div, UInt<1>(0h0)) node _ram_6_T_85 = mux(write_mask[6][1], in_uops[1].bits.fdivin.div, UInt<1>(0h0)) node _ram_6_T_86 = mux(write_mask[6][2], in_uops[2].bits.fdivin.div, UInt<1>(0h0)) node _ram_6_T_87 = mux(write_mask[6][3], in_uops[3].bits.fdivin.div, UInt<1>(0h0)) node _ram_6_T_88 = or(_ram_6_T_84, _ram_6_T_85) node _ram_6_T_89 = or(_ram_6_T_88, _ram_6_T_86) node _ram_6_T_90 = or(_ram_6_T_89, _ram_6_T_87) wire _ram_6_WIRE_15 : UInt<1> connect _ram_6_WIRE_15, _ram_6_T_90 connect _ram_6_WIRE_4.div, _ram_6_WIRE_15 node _ram_6_T_91 = mux(write_mask[6][0], in_uops[0].bits.fdivin.fma, UInt<1>(0h0)) node _ram_6_T_92 = mux(write_mask[6][1], in_uops[1].bits.fdivin.fma, UInt<1>(0h0)) node _ram_6_T_93 = mux(write_mask[6][2], in_uops[2].bits.fdivin.fma, UInt<1>(0h0)) node _ram_6_T_94 = mux(write_mask[6][3], in_uops[3].bits.fdivin.fma, UInt<1>(0h0)) node _ram_6_T_95 = or(_ram_6_T_91, _ram_6_T_92) node _ram_6_T_96 = or(_ram_6_T_95, _ram_6_T_93) node _ram_6_T_97 = or(_ram_6_T_96, _ram_6_T_94) wire _ram_6_WIRE_16 : UInt<1> connect _ram_6_WIRE_16, _ram_6_T_97 connect _ram_6_WIRE_4.fma, _ram_6_WIRE_16 node _ram_6_T_98 = mux(write_mask[6][0], in_uops[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_6_T_99 = mux(write_mask[6][1], in_uops[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_6_T_100 = mux(write_mask[6][2], in_uops[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_6_T_101 = mux(write_mask[6][3], in_uops[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ram_6_T_102 = or(_ram_6_T_98, _ram_6_T_99) node _ram_6_T_103 = or(_ram_6_T_102, _ram_6_T_100) node _ram_6_T_104 = or(_ram_6_T_103, _ram_6_T_101) wire _ram_6_WIRE_17 : UInt<1> connect _ram_6_WIRE_17, _ram_6_T_104 connect _ram_6_WIRE_4.fastpipe, _ram_6_WIRE_17 node _ram_6_T_105 = mux(write_mask[6][0], in_uops[0].bits.fdivin.toint, UInt<1>(0h0)) node _ram_6_T_106 = mux(write_mask[6][1], in_uops[1].bits.fdivin.toint, UInt<1>(0h0)) node _ram_6_T_107 = mux(write_mask[6][2], in_uops[2].bits.fdivin.toint, UInt<1>(0h0)) node _ram_6_T_108 = mux(write_mask[6][3], in_uops[3].bits.fdivin.toint, UInt<1>(0h0)) node _ram_6_T_109 = or(_ram_6_T_105, _ram_6_T_106) node _ram_6_T_110 = or(_ram_6_T_109, _ram_6_T_107) node _ram_6_T_111 = or(_ram_6_T_110, _ram_6_T_108) wire _ram_6_WIRE_18 : UInt<1> connect _ram_6_WIRE_18, _ram_6_T_111 connect _ram_6_WIRE_4.toint, _ram_6_WIRE_18 node _ram_6_T_112 = mux(write_mask[6][0], in_uops[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_6_T_113 = mux(write_mask[6][1], in_uops[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_6_T_114 = mux(write_mask[6][2], in_uops[2].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_6_T_115 = mux(write_mask[6][3], in_uops[3].bits.fdivin.fromint, UInt<1>(0h0)) node _ram_6_T_116 = or(_ram_6_T_112, _ram_6_T_113) node _ram_6_T_117 = or(_ram_6_T_116, _ram_6_T_114) node _ram_6_T_118 = or(_ram_6_T_117, _ram_6_T_115) wire _ram_6_WIRE_19 : UInt<1> connect _ram_6_WIRE_19, _ram_6_T_118 connect _ram_6_WIRE_4.fromint, _ram_6_WIRE_19 node _ram_6_T_119 = mux(write_mask[6][0], in_uops[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_6_T_120 = mux(write_mask[6][1], in_uops[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_6_T_121 = mux(write_mask[6][2], in_uops[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_6_T_122 = mux(write_mask[6][3], in_uops[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ram_6_T_123 = or(_ram_6_T_119, _ram_6_T_120) node _ram_6_T_124 = or(_ram_6_T_123, _ram_6_T_121) node _ram_6_T_125 = or(_ram_6_T_124, _ram_6_T_122) wire _ram_6_WIRE_20 : UInt<2> connect _ram_6_WIRE_20, _ram_6_T_125 connect _ram_6_WIRE_4.typeTagOut, _ram_6_WIRE_20 node _ram_6_T_126 = mux(write_mask[6][0], in_uops[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_6_T_127 = mux(write_mask[6][1], in_uops[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_6_T_128 = mux(write_mask[6][2], in_uops[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_6_T_129 = mux(write_mask[6][3], in_uops[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ram_6_T_130 = or(_ram_6_T_126, _ram_6_T_127) node _ram_6_T_131 = or(_ram_6_T_130, _ram_6_T_128) node _ram_6_T_132 = or(_ram_6_T_131, _ram_6_T_129) wire _ram_6_WIRE_21 : UInt<2> connect _ram_6_WIRE_21, _ram_6_T_132 connect _ram_6_WIRE_4.typeTagIn, _ram_6_WIRE_21 node _ram_6_T_133 = mux(write_mask[6][0], in_uops[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_6_T_134 = mux(write_mask[6][1], in_uops[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_6_T_135 = mux(write_mask[6][2], in_uops[2].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_6_T_136 = mux(write_mask[6][3], in_uops[3].bits.fdivin.swap23, UInt<1>(0h0)) node _ram_6_T_137 = or(_ram_6_T_133, _ram_6_T_134) node _ram_6_T_138 = or(_ram_6_T_137, _ram_6_T_135) node _ram_6_T_139 = or(_ram_6_T_138, _ram_6_T_136) wire _ram_6_WIRE_22 : UInt<1> connect _ram_6_WIRE_22, _ram_6_T_139 connect _ram_6_WIRE_4.swap23, _ram_6_WIRE_22 node _ram_6_T_140 = mux(write_mask[6][0], in_uops[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_6_T_141 = mux(write_mask[6][1], in_uops[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_6_T_142 = mux(write_mask[6][2], in_uops[2].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_6_T_143 = mux(write_mask[6][3], in_uops[3].bits.fdivin.swap12, UInt<1>(0h0)) node _ram_6_T_144 = or(_ram_6_T_140, _ram_6_T_141) node _ram_6_T_145 = or(_ram_6_T_144, _ram_6_T_142) node _ram_6_T_146 = or(_ram_6_T_145, _ram_6_T_143) wire _ram_6_WIRE_23 : UInt<1> connect _ram_6_WIRE_23, _ram_6_T_146 connect _ram_6_WIRE_4.swap12, _ram_6_WIRE_23 node _ram_6_T_147 = mux(write_mask[6][0], in_uops[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_6_T_148 = mux(write_mask[6][1], in_uops[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_6_T_149 = mux(write_mask[6][2], in_uops[2].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_6_T_150 = mux(write_mask[6][3], in_uops[3].bits.fdivin.ren3, UInt<1>(0h0)) node _ram_6_T_151 = or(_ram_6_T_147, _ram_6_T_148) node _ram_6_T_152 = or(_ram_6_T_151, _ram_6_T_149) node _ram_6_T_153 = or(_ram_6_T_152, _ram_6_T_150) wire _ram_6_WIRE_24 : UInt<1> connect _ram_6_WIRE_24, _ram_6_T_153 connect _ram_6_WIRE_4.ren3, _ram_6_WIRE_24 node _ram_6_T_154 = mux(write_mask[6][0], in_uops[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_6_T_155 = mux(write_mask[6][1], in_uops[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_6_T_156 = mux(write_mask[6][2], in_uops[2].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_6_T_157 = mux(write_mask[6][3], in_uops[3].bits.fdivin.ren2, UInt<1>(0h0)) node _ram_6_T_158 = or(_ram_6_T_154, _ram_6_T_155) node _ram_6_T_159 = or(_ram_6_T_158, _ram_6_T_156) node _ram_6_T_160 = or(_ram_6_T_159, _ram_6_T_157) wire _ram_6_WIRE_25 : UInt<1> connect _ram_6_WIRE_25, _ram_6_T_160 connect _ram_6_WIRE_4.ren2, _ram_6_WIRE_25 node _ram_6_T_161 = mux(write_mask[6][0], in_uops[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_6_T_162 = mux(write_mask[6][1], in_uops[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_6_T_163 = mux(write_mask[6][2], in_uops[2].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_6_T_164 = mux(write_mask[6][3], in_uops[3].bits.fdivin.ren1, UInt<1>(0h0)) node _ram_6_T_165 = or(_ram_6_T_161, _ram_6_T_162) node _ram_6_T_166 = or(_ram_6_T_165, _ram_6_T_163) node _ram_6_T_167 = or(_ram_6_T_166, _ram_6_T_164) wire _ram_6_WIRE_26 : UInt<1> connect _ram_6_WIRE_26, _ram_6_T_167 connect _ram_6_WIRE_4.ren1, _ram_6_WIRE_26 node _ram_6_T_168 = mux(write_mask[6][0], in_uops[0].bits.fdivin.wen, UInt<1>(0h0)) node _ram_6_T_169 = mux(write_mask[6][1], in_uops[1].bits.fdivin.wen, UInt<1>(0h0)) node _ram_6_T_170 = mux(write_mask[6][2], in_uops[2].bits.fdivin.wen, UInt<1>(0h0)) node _ram_6_T_171 = mux(write_mask[6][3], in_uops[3].bits.fdivin.wen, UInt<1>(0h0)) node _ram_6_T_172 = or(_ram_6_T_168, _ram_6_T_169) node _ram_6_T_173 = or(_ram_6_T_172, _ram_6_T_170) node _ram_6_T_174 = or(_ram_6_T_173, _ram_6_T_171) wire _ram_6_WIRE_27 : UInt<1> connect _ram_6_WIRE_27, _ram_6_T_174 connect _ram_6_WIRE_4.wen, _ram_6_WIRE_27 node _ram_6_T_175 = mux(write_mask[6][0], in_uops[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_6_T_176 = mux(write_mask[6][1], in_uops[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_6_T_177 = mux(write_mask[6][2], in_uops[2].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_6_T_178 = mux(write_mask[6][3], in_uops[3].bits.fdivin.ldst, UInt<1>(0h0)) node _ram_6_T_179 = or(_ram_6_T_175, _ram_6_T_176) node _ram_6_T_180 = or(_ram_6_T_179, _ram_6_T_177) node _ram_6_T_181 = or(_ram_6_T_180, _ram_6_T_178) wire _ram_6_WIRE_28 : UInt<1> connect _ram_6_WIRE_28, _ram_6_T_181 connect _ram_6_WIRE_4.ldst, _ram_6_WIRE_28 connect _ram_6_WIRE_1.fdivin, _ram_6_WIRE_4 node _ram_6_T_182 = mux(write_mask[6][0], in_uops[0].bits.fexc, UInt<1>(0h0)) node _ram_6_T_183 = mux(write_mask[6][1], in_uops[1].bits.fexc, UInt<1>(0h0)) node _ram_6_T_184 = mux(write_mask[6][2], in_uops[2].bits.fexc, UInt<1>(0h0)) node _ram_6_T_185 = mux(write_mask[6][3], in_uops[3].bits.fexc, UInt<1>(0h0)) node _ram_6_T_186 = or(_ram_6_T_182, _ram_6_T_183) node _ram_6_T_187 = or(_ram_6_T_186, _ram_6_T_184) node _ram_6_T_188 = or(_ram_6_T_187, _ram_6_T_185) wire _ram_6_WIRE_29 : UInt<5> connect _ram_6_WIRE_29, _ram_6_T_188 connect _ram_6_WIRE_1.fexc, _ram_6_WIRE_29 node _ram_6_T_189 = mux(write_mask[6][0], in_uops[0].bits.fra3, UInt<1>(0h0)) node _ram_6_T_190 = mux(write_mask[6][1], in_uops[1].bits.fra3, UInt<1>(0h0)) node _ram_6_T_191 = mux(write_mask[6][2], in_uops[2].bits.fra3, UInt<1>(0h0)) node _ram_6_T_192 = mux(write_mask[6][3], in_uops[3].bits.fra3, UInt<1>(0h0)) node _ram_6_T_193 = or(_ram_6_T_189, _ram_6_T_190) node _ram_6_T_194 = or(_ram_6_T_193, _ram_6_T_191) node _ram_6_T_195 = or(_ram_6_T_194, _ram_6_T_192) wire _ram_6_WIRE_30 : UInt<5> connect _ram_6_WIRE_30, _ram_6_T_195 connect _ram_6_WIRE_1.fra3, _ram_6_WIRE_30 node _ram_6_T_196 = mux(write_mask[6][0], in_uops[0].bits.fra2, UInt<1>(0h0)) node _ram_6_T_197 = mux(write_mask[6][1], in_uops[1].bits.fra2, UInt<1>(0h0)) node _ram_6_T_198 = mux(write_mask[6][2], in_uops[2].bits.fra2, UInt<1>(0h0)) node _ram_6_T_199 = mux(write_mask[6][3], in_uops[3].bits.fra2, UInt<1>(0h0)) node _ram_6_T_200 = or(_ram_6_T_196, _ram_6_T_197) node _ram_6_T_201 = or(_ram_6_T_200, _ram_6_T_198) node _ram_6_T_202 = or(_ram_6_T_201, _ram_6_T_199) wire _ram_6_WIRE_31 : UInt<5> connect _ram_6_WIRE_31, _ram_6_T_202 connect _ram_6_WIRE_1.fra2, _ram_6_WIRE_31 node _ram_6_T_203 = mux(write_mask[6][0], in_uops[0].bits.fra1, UInt<1>(0h0)) node _ram_6_T_204 = mux(write_mask[6][1], in_uops[1].bits.fra1, UInt<1>(0h0)) node _ram_6_T_205 = mux(write_mask[6][2], in_uops[2].bits.fra1, UInt<1>(0h0)) node _ram_6_T_206 = mux(write_mask[6][3], in_uops[3].bits.fra1, UInt<1>(0h0)) node _ram_6_T_207 = or(_ram_6_T_203, _ram_6_T_204) node _ram_6_T_208 = or(_ram_6_T_207, _ram_6_T_205) node _ram_6_T_209 = or(_ram_6_T_208, _ram_6_T_206) wire _ram_6_WIRE_32 : UInt<5> connect _ram_6_WIRE_32, _ram_6_T_209 connect _ram_6_WIRE_1.fra1, _ram_6_WIRE_32 wire _ram_6_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ram_6_T_210 = mux(write_mask[6][0], in_uops[0].bits.wdata.bits, UInt<1>(0h0)) node _ram_6_T_211 = mux(write_mask[6][1], in_uops[1].bits.wdata.bits, UInt<1>(0h0)) node _ram_6_T_212 = mux(write_mask[6][2], in_uops[2].bits.wdata.bits, UInt<1>(0h0)) node _ram_6_T_213 = mux(write_mask[6][3], in_uops[3].bits.wdata.bits, UInt<1>(0h0)) node _ram_6_T_214 = or(_ram_6_T_210, _ram_6_T_211) node _ram_6_T_215 = or(_ram_6_T_214, _ram_6_T_212) node _ram_6_T_216 = or(_ram_6_T_215, _ram_6_T_213) wire _ram_6_WIRE_34 : UInt<64> connect _ram_6_WIRE_34, _ram_6_T_216 connect _ram_6_WIRE_33.bits, _ram_6_WIRE_34 node _ram_6_T_217 = mux(write_mask[6][0], in_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _ram_6_T_218 = mux(write_mask[6][1], in_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _ram_6_T_219 = mux(write_mask[6][2], in_uops[2].bits.wdata.valid, UInt<1>(0h0)) node _ram_6_T_220 = mux(write_mask[6][3], in_uops[3].bits.wdata.valid, UInt<1>(0h0)) node _ram_6_T_221 = or(_ram_6_T_217, _ram_6_T_218) node _ram_6_T_222 = or(_ram_6_T_221, _ram_6_T_219) node _ram_6_T_223 = or(_ram_6_T_222, _ram_6_T_220) wire _ram_6_WIRE_35 : UInt<1> connect _ram_6_WIRE_35, _ram_6_T_223 connect _ram_6_WIRE_33.valid, _ram_6_WIRE_35 connect _ram_6_WIRE_1.wdata, _ram_6_WIRE_33 node _ram_6_T_224 = mux(write_mask[6][0], in_uops[0].bits.uses_latealu, UInt<1>(0h0)) node _ram_6_T_225 = mux(write_mask[6][1], in_uops[1].bits.uses_latealu, UInt<1>(0h0)) node _ram_6_T_226 = mux(write_mask[6][2], in_uops[2].bits.uses_latealu, UInt<1>(0h0)) node _ram_6_T_227 = mux(write_mask[6][3], in_uops[3].bits.uses_latealu, UInt<1>(0h0)) node _ram_6_T_228 = or(_ram_6_T_224, _ram_6_T_225) node _ram_6_T_229 = or(_ram_6_T_228, _ram_6_T_226) node _ram_6_T_230 = or(_ram_6_T_229, _ram_6_T_227) wire _ram_6_WIRE_36 : UInt<1> connect _ram_6_WIRE_36, _ram_6_T_230 connect _ram_6_WIRE_1.uses_latealu, _ram_6_WIRE_36 node _ram_6_T_231 = mux(write_mask[6][0], in_uops[0].bits.uses_memalu, UInt<1>(0h0)) node _ram_6_T_232 = mux(write_mask[6][1], in_uops[1].bits.uses_memalu, UInt<1>(0h0)) node _ram_6_T_233 = mux(write_mask[6][2], in_uops[2].bits.uses_memalu, UInt<1>(0h0)) node _ram_6_T_234 = mux(write_mask[6][3], in_uops[3].bits.uses_memalu, UInt<1>(0h0)) node _ram_6_T_235 = or(_ram_6_T_231, _ram_6_T_232) node _ram_6_T_236 = or(_ram_6_T_235, _ram_6_T_233) node _ram_6_T_237 = or(_ram_6_T_236, _ram_6_T_234) wire _ram_6_WIRE_37 : UInt<1> connect _ram_6_WIRE_37, _ram_6_T_237 connect _ram_6_WIRE_1.uses_memalu, _ram_6_WIRE_37 node _ram_6_T_238 = mux(write_mask[6][0], in_uops[0].bits.rs3_data, UInt<1>(0h0)) node _ram_6_T_239 = mux(write_mask[6][1], in_uops[1].bits.rs3_data, UInt<1>(0h0)) node _ram_6_T_240 = mux(write_mask[6][2], in_uops[2].bits.rs3_data, UInt<1>(0h0)) node _ram_6_T_241 = mux(write_mask[6][3], in_uops[3].bits.rs3_data, UInt<1>(0h0)) node _ram_6_T_242 = or(_ram_6_T_238, _ram_6_T_239) node _ram_6_T_243 = or(_ram_6_T_242, _ram_6_T_240) node _ram_6_T_244 = or(_ram_6_T_243, _ram_6_T_241) wire _ram_6_WIRE_38 : UInt<64> connect _ram_6_WIRE_38, _ram_6_T_244 connect _ram_6_WIRE_1.rs3_data, _ram_6_WIRE_38 node _ram_6_T_245 = mux(write_mask[6][0], in_uops[0].bits.rs2_data, UInt<1>(0h0)) node _ram_6_T_246 = mux(write_mask[6][1], in_uops[1].bits.rs2_data, UInt<1>(0h0)) node _ram_6_T_247 = mux(write_mask[6][2], in_uops[2].bits.rs2_data, UInt<1>(0h0)) node _ram_6_T_248 = mux(write_mask[6][3], in_uops[3].bits.rs2_data, UInt<1>(0h0)) node _ram_6_T_249 = or(_ram_6_T_245, _ram_6_T_246) node _ram_6_T_250 = or(_ram_6_T_249, _ram_6_T_247) node _ram_6_T_251 = or(_ram_6_T_250, _ram_6_T_248) wire _ram_6_WIRE_39 : UInt<64> connect _ram_6_WIRE_39, _ram_6_T_251 connect _ram_6_WIRE_1.rs2_data, _ram_6_WIRE_39 node _ram_6_T_252 = mux(write_mask[6][0], in_uops[0].bits.rs1_data, UInt<1>(0h0)) node _ram_6_T_253 = mux(write_mask[6][1], in_uops[1].bits.rs1_data, UInt<1>(0h0)) node _ram_6_T_254 = mux(write_mask[6][2], in_uops[2].bits.rs1_data, UInt<1>(0h0)) node _ram_6_T_255 = mux(write_mask[6][3], in_uops[3].bits.rs1_data, UInt<1>(0h0)) node _ram_6_T_256 = or(_ram_6_T_252, _ram_6_T_253) node _ram_6_T_257 = or(_ram_6_T_256, _ram_6_T_254) node _ram_6_T_258 = or(_ram_6_T_257, _ram_6_T_255) wire _ram_6_WIRE_40 : UInt<64> connect _ram_6_WIRE_40, _ram_6_T_258 connect _ram_6_WIRE_1.rs1_data, _ram_6_WIRE_40 node _ram_6_T_259 = mux(write_mask[6][0], in_uops[0].bits.needs_replay, UInt<1>(0h0)) node _ram_6_T_260 = mux(write_mask[6][1], in_uops[1].bits.needs_replay, UInt<1>(0h0)) node _ram_6_T_261 = mux(write_mask[6][2], in_uops[2].bits.needs_replay, UInt<1>(0h0)) node _ram_6_T_262 = mux(write_mask[6][3], in_uops[3].bits.needs_replay, UInt<1>(0h0)) node _ram_6_T_263 = or(_ram_6_T_259, _ram_6_T_260) node _ram_6_T_264 = or(_ram_6_T_263, _ram_6_T_261) node _ram_6_T_265 = or(_ram_6_T_264, _ram_6_T_262) wire _ram_6_WIRE_41 : UInt<1> connect _ram_6_WIRE_41, _ram_6_T_265 connect _ram_6_WIRE_1.needs_replay, _ram_6_WIRE_41 node _ram_6_T_266 = mux(write_mask[6][0], in_uops[0].bits.xcpt_cause, UInt<1>(0h0)) node _ram_6_T_267 = mux(write_mask[6][1], in_uops[1].bits.xcpt_cause, UInt<1>(0h0)) node _ram_6_T_268 = mux(write_mask[6][2], in_uops[2].bits.xcpt_cause, UInt<1>(0h0)) node _ram_6_T_269 = mux(write_mask[6][3], in_uops[3].bits.xcpt_cause, UInt<1>(0h0)) node _ram_6_T_270 = or(_ram_6_T_266, _ram_6_T_267) node _ram_6_T_271 = or(_ram_6_T_270, _ram_6_T_268) node _ram_6_T_272 = or(_ram_6_T_271, _ram_6_T_269) wire _ram_6_WIRE_42 : UInt<64> connect _ram_6_WIRE_42, _ram_6_T_272 connect _ram_6_WIRE_1.xcpt_cause, _ram_6_WIRE_42 node _ram_6_T_273 = mux(write_mask[6][0], in_uops[0].bits.xcpt, UInt<1>(0h0)) node _ram_6_T_274 = mux(write_mask[6][1], in_uops[1].bits.xcpt, UInt<1>(0h0)) node _ram_6_T_275 = mux(write_mask[6][2], in_uops[2].bits.xcpt, UInt<1>(0h0)) node _ram_6_T_276 = mux(write_mask[6][3], in_uops[3].bits.xcpt, UInt<1>(0h0)) node _ram_6_T_277 = or(_ram_6_T_273, _ram_6_T_274) node _ram_6_T_278 = or(_ram_6_T_277, _ram_6_T_275) node _ram_6_T_279 = or(_ram_6_T_278, _ram_6_T_276) wire _ram_6_WIRE_43 : UInt<1> connect _ram_6_WIRE_43, _ram_6_T_279 connect _ram_6_WIRE_1.xcpt, _ram_6_WIRE_43 node _ram_6_T_280 = mux(write_mask[6][0], in_uops[0].bits.taken, UInt<1>(0h0)) node _ram_6_T_281 = mux(write_mask[6][1], in_uops[1].bits.taken, UInt<1>(0h0)) node _ram_6_T_282 = mux(write_mask[6][2], in_uops[2].bits.taken, UInt<1>(0h0)) node _ram_6_T_283 = mux(write_mask[6][3], in_uops[3].bits.taken, UInt<1>(0h0)) node _ram_6_T_284 = or(_ram_6_T_280, _ram_6_T_281) node _ram_6_T_285 = or(_ram_6_T_284, _ram_6_T_282) node _ram_6_T_286 = or(_ram_6_T_285, _ram_6_T_283) wire _ram_6_WIRE_44 : UInt<1> connect _ram_6_WIRE_44, _ram_6_T_286 connect _ram_6_WIRE_1.taken, _ram_6_WIRE_44 node _ram_6_T_287 = mux(write_mask[6][0], in_uops[0].bits.ras_head, UInt<1>(0h0)) node _ram_6_T_288 = mux(write_mask[6][1], in_uops[1].bits.ras_head, UInt<1>(0h0)) node _ram_6_T_289 = mux(write_mask[6][2], in_uops[2].bits.ras_head, UInt<1>(0h0)) node _ram_6_T_290 = mux(write_mask[6][3], in_uops[3].bits.ras_head, UInt<1>(0h0)) node _ram_6_T_291 = or(_ram_6_T_287, _ram_6_T_288) node _ram_6_T_292 = or(_ram_6_T_291, _ram_6_T_289) node _ram_6_T_293 = or(_ram_6_T_292, _ram_6_T_290) wire _ram_6_WIRE_45 : UInt<3> connect _ram_6_WIRE_45, _ram_6_T_293 connect _ram_6_WIRE_1.ras_head, _ram_6_WIRE_45 wire _ram_6_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ram_6_T_294 = mux(write_mask[6][0], in_uops[0].bits.next_pc.bits, UInt<1>(0h0)) node _ram_6_T_295 = mux(write_mask[6][1], in_uops[1].bits.next_pc.bits, UInt<1>(0h0)) node _ram_6_T_296 = mux(write_mask[6][2], in_uops[2].bits.next_pc.bits, UInt<1>(0h0)) node _ram_6_T_297 = mux(write_mask[6][3], in_uops[3].bits.next_pc.bits, UInt<1>(0h0)) node _ram_6_T_298 = or(_ram_6_T_294, _ram_6_T_295) node _ram_6_T_299 = or(_ram_6_T_298, _ram_6_T_296) node _ram_6_T_300 = or(_ram_6_T_299, _ram_6_T_297) wire _ram_6_WIRE_47 : UInt<40> connect _ram_6_WIRE_47, _ram_6_T_300 connect _ram_6_WIRE_46.bits, _ram_6_WIRE_47 node _ram_6_T_301 = mux(write_mask[6][0], in_uops[0].bits.next_pc.valid, UInt<1>(0h0)) node _ram_6_T_302 = mux(write_mask[6][1], in_uops[1].bits.next_pc.valid, UInt<1>(0h0)) node _ram_6_T_303 = mux(write_mask[6][2], in_uops[2].bits.next_pc.valid, UInt<1>(0h0)) node _ram_6_T_304 = mux(write_mask[6][3], in_uops[3].bits.next_pc.valid, UInt<1>(0h0)) node _ram_6_T_305 = or(_ram_6_T_301, _ram_6_T_302) node _ram_6_T_306 = or(_ram_6_T_305, _ram_6_T_303) node _ram_6_T_307 = or(_ram_6_T_306, _ram_6_T_304) wire _ram_6_WIRE_48 : UInt<1> connect _ram_6_WIRE_48, _ram_6_T_307 connect _ram_6_WIRE_46.valid, _ram_6_WIRE_48 connect _ram_6_WIRE_1.next_pc, _ram_6_WIRE_46 node _ram_6_T_308 = mux(write_mask[6][0], in_uops[0].bits.sfb_shadow, UInt<1>(0h0)) node _ram_6_T_309 = mux(write_mask[6][1], in_uops[1].bits.sfb_shadow, UInt<1>(0h0)) node _ram_6_T_310 = mux(write_mask[6][2], in_uops[2].bits.sfb_shadow, UInt<1>(0h0)) node _ram_6_T_311 = mux(write_mask[6][3], in_uops[3].bits.sfb_shadow, UInt<1>(0h0)) node _ram_6_T_312 = or(_ram_6_T_308, _ram_6_T_309) node _ram_6_T_313 = or(_ram_6_T_312, _ram_6_T_310) node _ram_6_T_314 = or(_ram_6_T_313, _ram_6_T_311) wire _ram_6_WIRE_49 : UInt<1> connect _ram_6_WIRE_49, _ram_6_T_314 connect _ram_6_WIRE_1.sfb_shadow, _ram_6_WIRE_49 node _ram_6_T_315 = mux(write_mask[6][0], in_uops[0].bits.sfb_br, UInt<1>(0h0)) node _ram_6_T_316 = mux(write_mask[6][1], in_uops[1].bits.sfb_br, UInt<1>(0h0)) node _ram_6_T_317 = mux(write_mask[6][2], in_uops[2].bits.sfb_br, UInt<1>(0h0)) node _ram_6_T_318 = mux(write_mask[6][3], in_uops[3].bits.sfb_br, UInt<1>(0h0)) node _ram_6_T_319 = or(_ram_6_T_315, _ram_6_T_316) node _ram_6_T_320 = or(_ram_6_T_319, _ram_6_T_317) node _ram_6_T_321 = or(_ram_6_T_320, _ram_6_T_318) wire _ram_6_WIRE_50 : UInt<1> connect _ram_6_WIRE_50, _ram_6_T_321 connect _ram_6_WIRE_1.sfb_br, _ram_6_WIRE_50 wire _ram_6_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ram_6_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ram_6_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ram_6_T_322 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_6_T_323 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_6_T_324 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_6_T_325 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ram_6_T_326 = or(_ram_6_T_322, _ram_6_T_323) node _ram_6_T_327 = or(_ram_6_T_326, _ram_6_T_324) node _ram_6_T_328 = or(_ram_6_T_327, _ram_6_T_325) wire _ram_6_WIRE_54 : UInt<2> connect _ram_6_WIRE_54, _ram_6_T_328 connect _ram_6_WIRE_53.value, _ram_6_WIRE_54 node _ram_6_T_329 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_6_T_330 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_6_T_331 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_6_T_332 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ram_6_T_333 = or(_ram_6_T_329, _ram_6_T_330) node _ram_6_T_334 = or(_ram_6_T_333, _ram_6_T_331) node _ram_6_T_335 = or(_ram_6_T_334, _ram_6_T_332) wire _ram_6_WIRE_55 : UInt<8> connect _ram_6_WIRE_55, _ram_6_T_335 connect _ram_6_WIRE_53.history, _ram_6_WIRE_55 connect _ram_6_WIRE_52.bht, _ram_6_WIRE_53 node _ram_6_T_336 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_6_T_337 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_6_T_338 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_6_T_339 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ram_6_T_340 = or(_ram_6_T_336, _ram_6_T_337) node _ram_6_T_341 = or(_ram_6_T_340, _ram_6_T_338) node _ram_6_T_342 = or(_ram_6_T_341, _ram_6_T_339) wire _ram_6_WIRE_56 : UInt<6> connect _ram_6_WIRE_56, _ram_6_T_342 connect _ram_6_WIRE_52.entry, _ram_6_WIRE_56 node _ram_6_T_343 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_6_T_344 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_6_T_345 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_6_T_346 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ram_6_T_347 = or(_ram_6_T_343, _ram_6_T_344) node _ram_6_T_348 = or(_ram_6_T_347, _ram_6_T_345) node _ram_6_T_349 = or(_ram_6_T_348, _ram_6_T_346) wire _ram_6_WIRE_57 : UInt<39> connect _ram_6_WIRE_57, _ram_6_T_349 connect _ram_6_WIRE_52.target, _ram_6_WIRE_57 node _ram_6_T_350 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_6_T_351 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_6_T_352 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_6_T_353 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ram_6_T_354 = or(_ram_6_T_350, _ram_6_T_351) node _ram_6_T_355 = or(_ram_6_T_354, _ram_6_T_352) node _ram_6_T_356 = or(_ram_6_T_355, _ram_6_T_353) wire _ram_6_WIRE_58 : UInt<2> connect _ram_6_WIRE_58, _ram_6_T_356 connect _ram_6_WIRE_52.bridx, _ram_6_WIRE_58 node _ram_6_T_357 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_6_T_358 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_6_T_359 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_6_T_360 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ram_6_T_361 = or(_ram_6_T_357, _ram_6_T_358) node _ram_6_T_362 = or(_ram_6_T_361, _ram_6_T_359) node _ram_6_T_363 = or(_ram_6_T_362, _ram_6_T_360) wire _ram_6_WIRE_59 : UInt<4> connect _ram_6_WIRE_59, _ram_6_T_363 connect _ram_6_WIRE_52.mask, _ram_6_WIRE_59 node _ram_6_T_364 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_6_T_365 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_6_T_366 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_6_T_367 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ram_6_T_368 = or(_ram_6_T_364, _ram_6_T_365) node _ram_6_T_369 = or(_ram_6_T_368, _ram_6_T_366) node _ram_6_T_370 = or(_ram_6_T_369, _ram_6_T_367) wire _ram_6_WIRE_60 : UInt<1> connect _ram_6_WIRE_60, _ram_6_T_370 connect _ram_6_WIRE_52.taken, _ram_6_WIRE_60 node _ram_6_T_371 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_6_T_372 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_6_T_373 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_6_T_374 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ram_6_T_375 = or(_ram_6_T_371, _ram_6_T_372) node _ram_6_T_376 = or(_ram_6_T_375, _ram_6_T_373) node _ram_6_T_377 = or(_ram_6_T_376, _ram_6_T_374) wire _ram_6_WIRE_61 : UInt<2> connect _ram_6_WIRE_61, _ram_6_T_377 connect _ram_6_WIRE_52.cfiType, _ram_6_WIRE_61 connect _ram_6_WIRE_51.bits, _ram_6_WIRE_52 node _ram_6_T_378 = mux(write_mask[6][0], in_uops[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_6_T_379 = mux(write_mask[6][1], in_uops[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_6_T_380 = mux(write_mask[6][2], in_uops[2].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_6_T_381 = mux(write_mask[6][3], in_uops[3].bits.btb_resp.valid, UInt<1>(0h0)) node _ram_6_T_382 = or(_ram_6_T_378, _ram_6_T_379) node _ram_6_T_383 = or(_ram_6_T_382, _ram_6_T_380) node _ram_6_T_384 = or(_ram_6_T_383, _ram_6_T_381) wire _ram_6_WIRE_62 : UInt<1> connect _ram_6_WIRE_62, _ram_6_T_384 connect _ram_6_WIRE_51.valid, _ram_6_WIRE_62 connect _ram_6_WIRE_1.btb_resp, _ram_6_WIRE_51 node _ram_6_T_385 = mux(write_mask[6][0], in_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _ram_6_T_386 = mux(write_mask[6][1], in_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _ram_6_T_387 = mux(write_mask[6][2], in_uops[2].bits.sets_vcfg, UInt<1>(0h0)) node _ram_6_T_388 = mux(write_mask[6][3], in_uops[3].bits.sets_vcfg, UInt<1>(0h0)) node _ram_6_T_389 = or(_ram_6_T_385, _ram_6_T_386) node _ram_6_T_390 = or(_ram_6_T_389, _ram_6_T_387) node _ram_6_T_391 = or(_ram_6_T_390, _ram_6_T_388) wire _ram_6_WIRE_63 : UInt<1> connect _ram_6_WIRE_63, _ram_6_T_391 connect _ram_6_WIRE_1.sets_vcfg, _ram_6_WIRE_63 node _ram_6_T_392 = mux(write_mask[6][0], in_uops[0].bits.rvc, UInt<1>(0h0)) node _ram_6_T_393 = mux(write_mask[6][1], in_uops[1].bits.rvc, UInt<1>(0h0)) node _ram_6_T_394 = mux(write_mask[6][2], in_uops[2].bits.rvc, UInt<1>(0h0)) node _ram_6_T_395 = mux(write_mask[6][3], in_uops[3].bits.rvc, UInt<1>(0h0)) node _ram_6_T_396 = or(_ram_6_T_392, _ram_6_T_393) node _ram_6_T_397 = or(_ram_6_T_396, _ram_6_T_394) node _ram_6_T_398 = or(_ram_6_T_397, _ram_6_T_395) wire _ram_6_WIRE_64 : UInt<1> connect _ram_6_WIRE_64, _ram_6_T_398 connect _ram_6_WIRE_1.rvc, _ram_6_WIRE_64 wire _ram_6_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ram_6_T_399 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_6_T_400 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_6_T_401 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_6_T_402 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ram_6_T_403 = or(_ram_6_T_399, _ram_6_T_400) node _ram_6_T_404 = or(_ram_6_T_403, _ram_6_T_401) node _ram_6_T_405 = or(_ram_6_T_404, _ram_6_T_402) wire _ram_6_WIRE_66 : UInt<1> connect _ram_6_WIRE_66, _ram_6_T_405 connect _ram_6_WIRE_65.vec, _ram_6_WIRE_66 node _ram_6_T_406 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_6_T_407 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_6_T_408 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_6_T_409 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ram_6_T_410 = or(_ram_6_T_406, _ram_6_T_407) node _ram_6_T_411 = or(_ram_6_T_410, _ram_6_T_408) node _ram_6_T_412 = or(_ram_6_T_411, _ram_6_T_409) wire _ram_6_WIRE_67 : UInt<1> connect _ram_6_WIRE_67, _ram_6_T_412 connect _ram_6_WIRE_65.wflags, _ram_6_WIRE_67 node _ram_6_T_413 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_6_T_414 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_6_T_415 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_6_T_416 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ram_6_T_417 = or(_ram_6_T_413, _ram_6_T_414) node _ram_6_T_418 = or(_ram_6_T_417, _ram_6_T_415) node _ram_6_T_419 = or(_ram_6_T_418, _ram_6_T_416) wire _ram_6_WIRE_68 : UInt<1> connect _ram_6_WIRE_68, _ram_6_T_419 connect _ram_6_WIRE_65.sqrt, _ram_6_WIRE_68 node _ram_6_T_420 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_6_T_421 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_6_T_422 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_6_T_423 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _ram_6_T_424 = or(_ram_6_T_420, _ram_6_T_421) node _ram_6_T_425 = or(_ram_6_T_424, _ram_6_T_422) node _ram_6_T_426 = or(_ram_6_T_425, _ram_6_T_423) wire _ram_6_WIRE_69 : UInt<1> connect _ram_6_WIRE_69, _ram_6_T_426 connect _ram_6_WIRE_65.div, _ram_6_WIRE_69 node _ram_6_T_427 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_6_T_428 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_6_T_429 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_6_T_430 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ram_6_T_431 = or(_ram_6_T_427, _ram_6_T_428) node _ram_6_T_432 = or(_ram_6_T_431, _ram_6_T_429) node _ram_6_T_433 = or(_ram_6_T_432, _ram_6_T_430) wire _ram_6_WIRE_70 : UInt<1> connect _ram_6_WIRE_70, _ram_6_T_433 connect _ram_6_WIRE_65.fma, _ram_6_WIRE_70 node _ram_6_T_434 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_6_T_435 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_6_T_436 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_6_T_437 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ram_6_T_438 = or(_ram_6_T_434, _ram_6_T_435) node _ram_6_T_439 = or(_ram_6_T_438, _ram_6_T_436) node _ram_6_T_440 = or(_ram_6_T_439, _ram_6_T_437) wire _ram_6_WIRE_71 : UInt<1> connect _ram_6_WIRE_71, _ram_6_T_440 connect _ram_6_WIRE_65.fastpipe, _ram_6_WIRE_71 node _ram_6_T_441 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_6_T_442 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_6_T_443 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_6_T_444 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ram_6_T_445 = or(_ram_6_T_441, _ram_6_T_442) node _ram_6_T_446 = or(_ram_6_T_445, _ram_6_T_443) node _ram_6_T_447 = or(_ram_6_T_446, _ram_6_T_444) wire _ram_6_WIRE_72 : UInt<1> connect _ram_6_WIRE_72, _ram_6_T_447 connect _ram_6_WIRE_65.toint, _ram_6_WIRE_72 node _ram_6_T_448 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_6_T_449 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_6_T_450 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_6_T_451 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ram_6_T_452 = or(_ram_6_T_448, _ram_6_T_449) node _ram_6_T_453 = or(_ram_6_T_452, _ram_6_T_450) node _ram_6_T_454 = or(_ram_6_T_453, _ram_6_T_451) wire _ram_6_WIRE_73 : UInt<1> connect _ram_6_WIRE_73, _ram_6_T_454 connect _ram_6_WIRE_65.fromint, _ram_6_WIRE_73 node _ram_6_T_455 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_6_T_456 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_6_T_457 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_6_T_458 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ram_6_T_459 = or(_ram_6_T_455, _ram_6_T_456) node _ram_6_T_460 = or(_ram_6_T_459, _ram_6_T_457) node _ram_6_T_461 = or(_ram_6_T_460, _ram_6_T_458) wire _ram_6_WIRE_74 : UInt<2> connect _ram_6_WIRE_74, _ram_6_T_461 connect _ram_6_WIRE_65.typeTagOut, _ram_6_WIRE_74 node _ram_6_T_462 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_6_T_463 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_6_T_464 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_6_T_465 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ram_6_T_466 = or(_ram_6_T_462, _ram_6_T_463) node _ram_6_T_467 = or(_ram_6_T_466, _ram_6_T_464) node _ram_6_T_468 = or(_ram_6_T_467, _ram_6_T_465) wire _ram_6_WIRE_75 : UInt<2> connect _ram_6_WIRE_75, _ram_6_T_468 connect _ram_6_WIRE_65.typeTagIn, _ram_6_WIRE_75 node _ram_6_T_469 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_6_T_470 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_6_T_471 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_6_T_472 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ram_6_T_473 = or(_ram_6_T_469, _ram_6_T_470) node _ram_6_T_474 = or(_ram_6_T_473, _ram_6_T_471) node _ram_6_T_475 = or(_ram_6_T_474, _ram_6_T_472) wire _ram_6_WIRE_76 : UInt<1> connect _ram_6_WIRE_76, _ram_6_T_475 connect _ram_6_WIRE_65.swap23, _ram_6_WIRE_76 node _ram_6_T_476 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_6_T_477 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_6_T_478 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_6_T_479 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ram_6_T_480 = or(_ram_6_T_476, _ram_6_T_477) node _ram_6_T_481 = or(_ram_6_T_480, _ram_6_T_478) node _ram_6_T_482 = or(_ram_6_T_481, _ram_6_T_479) wire _ram_6_WIRE_77 : UInt<1> connect _ram_6_WIRE_77, _ram_6_T_482 connect _ram_6_WIRE_65.swap12, _ram_6_WIRE_77 node _ram_6_T_483 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_6_T_484 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_6_T_485 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_6_T_486 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ram_6_T_487 = or(_ram_6_T_483, _ram_6_T_484) node _ram_6_T_488 = or(_ram_6_T_487, _ram_6_T_485) node _ram_6_T_489 = or(_ram_6_T_488, _ram_6_T_486) wire _ram_6_WIRE_78 : UInt<1> connect _ram_6_WIRE_78, _ram_6_T_489 connect _ram_6_WIRE_65.ren3, _ram_6_WIRE_78 node _ram_6_T_490 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_6_T_491 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_6_T_492 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_6_T_493 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ram_6_T_494 = or(_ram_6_T_490, _ram_6_T_491) node _ram_6_T_495 = or(_ram_6_T_494, _ram_6_T_492) node _ram_6_T_496 = or(_ram_6_T_495, _ram_6_T_493) wire _ram_6_WIRE_79 : UInt<1> connect _ram_6_WIRE_79, _ram_6_T_496 connect _ram_6_WIRE_65.ren2, _ram_6_WIRE_79 node _ram_6_T_497 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_6_T_498 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_6_T_499 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_6_T_500 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ram_6_T_501 = or(_ram_6_T_497, _ram_6_T_498) node _ram_6_T_502 = or(_ram_6_T_501, _ram_6_T_499) node _ram_6_T_503 = or(_ram_6_T_502, _ram_6_T_500) wire _ram_6_WIRE_80 : UInt<1> connect _ram_6_WIRE_80, _ram_6_T_503 connect _ram_6_WIRE_65.ren1, _ram_6_WIRE_80 node _ram_6_T_504 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_6_T_505 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_6_T_506 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_6_T_507 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ram_6_T_508 = or(_ram_6_T_504, _ram_6_T_505) node _ram_6_T_509 = or(_ram_6_T_508, _ram_6_T_506) node _ram_6_T_510 = or(_ram_6_T_509, _ram_6_T_507) wire _ram_6_WIRE_81 : UInt<1> connect _ram_6_WIRE_81, _ram_6_T_510 connect _ram_6_WIRE_65.wen, _ram_6_WIRE_81 node _ram_6_T_511 = mux(write_mask[6][0], in_uops[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_6_T_512 = mux(write_mask[6][1], in_uops[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_6_T_513 = mux(write_mask[6][2], in_uops[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_6_T_514 = mux(write_mask[6][3], in_uops[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ram_6_T_515 = or(_ram_6_T_511, _ram_6_T_512) node _ram_6_T_516 = or(_ram_6_T_515, _ram_6_T_513) node _ram_6_T_517 = or(_ram_6_T_516, _ram_6_T_514) wire _ram_6_WIRE_82 : UInt<1> connect _ram_6_WIRE_82, _ram_6_T_517 connect _ram_6_WIRE_65.ldst, _ram_6_WIRE_82 connect _ram_6_WIRE_1.fp_ctrl, _ram_6_WIRE_65 wire _ram_6_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ram_6_T_518 = mux(write_mask[6][0], in_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _ram_6_T_519 = mux(write_mask[6][1], in_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _ram_6_T_520 = mux(write_mask[6][2], in_uops[2].bits.ctrl.vec, UInt<1>(0h0)) node _ram_6_T_521 = mux(write_mask[6][3], in_uops[3].bits.ctrl.vec, UInt<1>(0h0)) node _ram_6_T_522 = or(_ram_6_T_518, _ram_6_T_519) node _ram_6_T_523 = or(_ram_6_T_522, _ram_6_T_520) node _ram_6_T_524 = or(_ram_6_T_523, _ram_6_T_521) wire _ram_6_WIRE_84 : UInt<1> connect _ram_6_WIRE_84, _ram_6_T_524 connect _ram_6_WIRE_83.vec, _ram_6_WIRE_84 node _ram_6_T_525 = mux(write_mask[6][0], in_uops[0].bits.ctrl.dp, UInt<1>(0h0)) node _ram_6_T_526 = mux(write_mask[6][1], in_uops[1].bits.ctrl.dp, UInt<1>(0h0)) node _ram_6_T_527 = mux(write_mask[6][2], in_uops[2].bits.ctrl.dp, UInt<1>(0h0)) node _ram_6_T_528 = mux(write_mask[6][3], in_uops[3].bits.ctrl.dp, UInt<1>(0h0)) node _ram_6_T_529 = or(_ram_6_T_525, _ram_6_T_526) node _ram_6_T_530 = or(_ram_6_T_529, _ram_6_T_527) node _ram_6_T_531 = or(_ram_6_T_530, _ram_6_T_528) wire _ram_6_WIRE_85 : UInt<1> connect _ram_6_WIRE_85, _ram_6_T_531 connect _ram_6_WIRE_83.dp, _ram_6_WIRE_85 node _ram_6_T_532 = mux(write_mask[6][0], in_uops[0].bits.ctrl.amo, UInt<1>(0h0)) node _ram_6_T_533 = mux(write_mask[6][1], in_uops[1].bits.ctrl.amo, UInt<1>(0h0)) node _ram_6_T_534 = mux(write_mask[6][2], in_uops[2].bits.ctrl.amo, UInt<1>(0h0)) node _ram_6_T_535 = mux(write_mask[6][3], in_uops[3].bits.ctrl.amo, UInt<1>(0h0)) node _ram_6_T_536 = or(_ram_6_T_532, _ram_6_T_533) node _ram_6_T_537 = or(_ram_6_T_536, _ram_6_T_534) node _ram_6_T_538 = or(_ram_6_T_537, _ram_6_T_535) wire _ram_6_WIRE_86 : UInt<1> connect _ram_6_WIRE_86, _ram_6_T_538 connect _ram_6_WIRE_83.amo, _ram_6_WIRE_86 node _ram_6_T_539 = mux(write_mask[6][0], in_uops[0].bits.ctrl.fence, UInt<1>(0h0)) node _ram_6_T_540 = mux(write_mask[6][1], in_uops[1].bits.ctrl.fence, UInt<1>(0h0)) node _ram_6_T_541 = mux(write_mask[6][2], in_uops[2].bits.ctrl.fence, UInt<1>(0h0)) node _ram_6_T_542 = mux(write_mask[6][3], in_uops[3].bits.ctrl.fence, UInt<1>(0h0)) node _ram_6_T_543 = or(_ram_6_T_539, _ram_6_T_540) node _ram_6_T_544 = or(_ram_6_T_543, _ram_6_T_541) node _ram_6_T_545 = or(_ram_6_T_544, _ram_6_T_542) wire _ram_6_WIRE_87 : UInt<1> connect _ram_6_WIRE_87, _ram_6_T_545 connect _ram_6_WIRE_83.fence, _ram_6_WIRE_87 node _ram_6_T_546 = mux(write_mask[6][0], in_uops[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_6_T_547 = mux(write_mask[6][1], in_uops[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_6_T_548 = mux(write_mask[6][2], in_uops[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_6_T_549 = mux(write_mask[6][3], in_uops[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _ram_6_T_550 = or(_ram_6_T_546, _ram_6_T_547) node _ram_6_T_551 = or(_ram_6_T_550, _ram_6_T_548) node _ram_6_T_552 = or(_ram_6_T_551, _ram_6_T_549) wire _ram_6_WIRE_88 : UInt<1> connect _ram_6_WIRE_88, _ram_6_T_552 connect _ram_6_WIRE_83.fence_i, _ram_6_WIRE_88 node _ram_6_T_553 = mux(write_mask[6][0], in_uops[0].bits.ctrl.csr, UInt<1>(0h0)) node _ram_6_T_554 = mux(write_mask[6][1], in_uops[1].bits.ctrl.csr, UInt<1>(0h0)) node _ram_6_T_555 = mux(write_mask[6][2], in_uops[2].bits.ctrl.csr, UInt<1>(0h0)) node _ram_6_T_556 = mux(write_mask[6][3], in_uops[3].bits.ctrl.csr, UInt<1>(0h0)) node _ram_6_T_557 = or(_ram_6_T_553, _ram_6_T_554) node _ram_6_T_558 = or(_ram_6_T_557, _ram_6_T_555) node _ram_6_T_559 = or(_ram_6_T_558, _ram_6_T_556) wire _ram_6_WIRE_89 : UInt<3> connect _ram_6_WIRE_89, _ram_6_T_559 connect _ram_6_WIRE_83.csr, _ram_6_WIRE_89 node _ram_6_T_560 = mux(write_mask[6][0], in_uops[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_6_T_561 = mux(write_mask[6][1], in_uops[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_6_T_562 = mux(write_mask[6][2], in_uops[2].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_6_T_563 = mux(write_mask[6][3], in_uops[3].bits.ctrl.wxd, UInt<1>(0h0)) node _ram_6_T_564 = or(_ram_6_T_560, _ram_6_T_561) node _ram_6_T_565 = or(_ram_6_T_564, _ram_6_T_562) node _ram_6_T_566 = or(_ram_6_T_565, _ram_6_T_563) wire _ram_6_WIRE_90 : UInt<1> connect _ram_6_WIRE_90, _ram_6_T_566 connect _ram_6_WIRE_83.wxd, _ram_6_WIRE_90 node _ram_6_T_567 = mux(write_mask[6][0], in_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _ram_6_T_568 = mux(write_mask[6][1], in_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _ram_6_T_569 = mux(write_mask[6][2], in_uops[2].bits.ctrl.div, UInt<1>(0h0)) node _ram_6_T_570 = mux(write_mask[6][3], in_uops[3].bits.ctrl.div, UInt<1>(0h0)) node _ram_6_T_571 = or(_ram_6_T_567, _ram_6_T_568) node _ram_6_T_572 = or(_ram_6_T_571, _ram_6_T_569) node _ram_6_T_573 = or(_ram_6_T_572, _ram_6_T_570) wire _ram_6_WIRE_91 : UInt<1> connect _ram_6_WIRE_91, _ram_6_T_573 connect _ram_6_WIRE_83.div, _ram_6_WIRE_91 node _ram_6_T_574 = mux(write_mask[6][0], in_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _ram_6_T_575 = mux(write_mask[6][1], in_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _ram_6_T_576 = mux(write_mask[6][2], in_uops[2].bits.ctrl.mul, UInt<1>(0h0)) node _ram_6_T_577 = mux(write_mask[6][3], in_uops[3].bits.ctrl.mul, UInt<1>(0h0)) node _ram_6_T_578 = or(_ram_6_T_574, _ram_6_T_575) node _ram_6_T_579 = or(_ram_6_T_578, _ram_6_T_576) node _ram_6_T_580 = or(_ram_6_T_579, _ram_6_T_577) wire _ram_6_WIRE_92 : UInt<1> connect _ram_6_WIRE_92, _ram_6_T_580 connect _ram_6_WIRE_83.mul, _ram_6_WIRE_92 node _ram_6_T_581 = mux(write_mask[6][0], in_uops[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_6_T_582 = mux(write_mask[6][1], in_uops[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_6_T_583 = mux(write_mask[6][2], in_uops[2].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_6_T_584 = mux(write_mask[6][3], in_uops[3].bits.ctrl.wfd, UInt<1>(0h0)) node _ram_6_T_585 = or(_ram_6_T_581, _ram_6_T_582) node _ram_6_T_586 = or(_ram_6_T_585, _ram_6_T_583) node _ram_6_T_587 = or(_ram_6_T_586, _ram_6_T_584) wire _ram_6_WIRE_93 : UInt<1> connect _ram_6_WIRE_93, _ram_6_T_587 connect _ram_6_WIRE_83.wfd, _ram_6_WIRE_93 node _ram_6_T_588 = mux(write_mask[6][0], in_uops[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_6_T_589 = mux(write_mask[6][1], in_uops[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_6_T_590 = mux(write_mask[6][2], in_uops[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_6_T_591 = mux(write_mask[6][3], in_uops[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _ram_6_T_592 = or(_ram_6_T_588, _ram_6_T_589) node _ram_6_T_593 = or(_ram_6_T_592, _ram_6_T_590) node _ram_6_T_594 = or(_ram_6_T_593, _ram_6_T_591) wire _ram_6_WIRE_94 : UInt<1> connect _ram_6_WIRE_94, _ram_6_T_594 connect _ram_6_WIRE_83.rfs3, _ram_6_WIRE_94 node _ram_6_T_595 = mux(write_mask[6][0], in_uops[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_6_T_596 = mux(write_mask[6][1], in_uops[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_6_T_597 = mux(write_mask[6][2], in_uops[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_6_T_598 = mux(write_mask[6][3], in_uops[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _ram_6_T_599 = or(_ram_6_T_595, _ram_6_T_596) node _ram_6_T_600 = or(_ram_6_T_599, _ram_6_T_597) node _ram_6_T_601 = or(_ram_6_T_600, _ram_6_T_598) wire _ram_6_WIRE_95 : UInt<1> connect _ram_6_WIRE_95, _ram_6_T_601 connect _ram_6_WIRE_83.rfs2, _ram_6_WIRE_95 node _ram_6_T_602 = mux(write_mask[6][0], in_uops[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_6_T_603 = mux(write_mask[6][1], in_uops[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_6_T_604 = mux(write_mask[6][2], in_uops[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_6_T_605 = mux(write_mask[6][3], in_uops[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _ram_6_T_606 = or(_ram_6_T_602, _ram_6_T_603) node _ram_6_T_607 = or(_ram_6_T_606, _ram_6_T_604) node _ram_6_T_608 = or(_ram_6_T_607, _ram_6_T_605) wire _ram_6_WIRE_96 : UInt<1> connect _ram_6_WIRE_96, _ram_6_T_608 connect _ram_6_WIRE_83.rfs1, _ram_6_WIRE_96 node _ram_6_T_609 = mux(write_mask[6][0], in_uops[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_6_T_610 = mux(write_mask[6][1], in_uops[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_6_T_611 = mux(write_mask[6][2], in_uops[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_6_T_612 = mux(write_mask[6][3], in_uops[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ram_6_T_613 = or(_ram_6_T_609, _ram_6_T_610) node _ram_6_T_614 = or(_ram_6_T_613, _ram_6_T_611) node _ram_6_T_615 = or(_ram_6_T_614, _ram_6_T_612) wire _ram_6_WIRE_97 : UInt<5> connect _ram_6_WIRE_97, _ram_6_T_615 connect _ram_6_WIRE_83.mem_cmd, _ram_6_WIRE_97 node _ram_6_T_616 = mux(write_mask[6][0], in_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _ram_6_T_617 = mux(write_mask[6][1], in_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _ram_6_T_618 = mux(write_mask[6][2], in_uops[2].bits.ctrl.mem, UInt<1>(0h0)) node _ram_6_T_619 = mux(write_mask[6][3], in_uops[3].bits.ctrl.mem, UInt<1>(0h0)) node _ram_6_T_620 = or(_ram_6_T_616, _ram_6_T_617) node _ram_6_T_621 = or(_ram_6_T_620, _ram_6_T_618) node _ram_6_T_622 = or(_ram_6_T_621, _ram_6_T_619) wire _ram_6_WIRE_98 : UInt<1> connect _ram_6_WIRE_98, _ram_6_T_622 connect _ram_6_WIRE_83.mem, _ram_6_WIRE_98 node _ram_6_T_623 = mux(write_mask[6][0], in_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_6_T_624 = mux(write_mask[6][1], in_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_6_T_625 = mux(write_mask[6][2], in_uops[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_6_T_626 = mux(write_mask[6][3], in_uops[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ram_6_T_627 = or(_ram_6_T_623, _ram_6_T_624) node _ram_6_T_628 = or(_ram_6_T_627, _ram_6_T_625) node _ram_6_T_629 = or(_ram_6_T_628, _ram_6_T_626) wire _ram_6_WIRE_99 : UInt<5> connect _ram_6_WIRE_99, _ram_6_T_629 connect _ram_6_WIRE_83.alu_fn, _ram_6_WIRE_99 node _ram_6_T_630 = mux(write_mask[6][0], in_uops[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_6_T_631 = mux(write_mask[6][1], in_uops[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_6_T_632 = mux(write_mask[6][2], in_uops[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_6_T_633 = mux(write_mask[6][3], in_uops[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ram_6_T_634 = or(_ram_6_T_630, _ram_6_T_631) node _ram_6_T_635 = or(_ram_6_T_634, _ram_6_T_632) node _ram_6_T_636 = or(_ram_6_T_635, _ram_6_T_633) wire _ram_6_WIRE_100 : UInt<1> connect _ram_6_WIRE_100, _ram_6_T_636 connect _ram_6_WIRE_83.alu_dw, _ram_6_WIRE_100 node _ram_6_T_637 = mux(write_mask[6][0], in_uops[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_6_T_638 = mux(write_mask[6][1], in_uops[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_6_T_639 = mux(write_mask[6][2], in_uops[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_6_T_640 = mux(write_mask[6][3], in_uops[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ram_6_T_641 = or(_ram_6_T_637, _ram_6_T_638) node _ram_6_T_642 = or(_ram_6_T_641, _ram_6_T_639) node _ram_6_T_643 = or(_ram_6_T_642, _ram_6_T_640) wire _ram_6_WIRE_101 : UInt<3> connect _ram_6_WIRE_101, _ram_6_T_643 connect _ram_6_WIRE_83.sel_imm, _ram_6_WIRE_101 node _ram_6_T_644 = mux(write_mask[6][0], in_uops[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_6_T_645 = mux(write_mask[6][1], in_uops[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_6_T_646 = mux(write_mask[6][2], in_uops[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_6_T_647 = mux(write_mask[6][3], in_uops[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ram_6_T_648 = or(_ram_6_T_644, _ram_6_T_645) node _ram_6_T_649 = or(_ram_6_T_648, _ram_6_T_646) node _ram_6_T_650 = or(_ram_6_T_649, _ram_6_T_647) wire _ram_6_WIRE_102 : UInt<2> connect _ram_6_WIRE_102, _ram_6_T_650 connect _ram_6_WIRE_83.sel_alu1, _ram_6_WIRE_102 node _ram_6_T_651 = mux(write_mask[6][0], in_uops[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_6_T_652 = mux(write_mask[6][1], in_uops[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_6_T_653 = mux(write_mask[6][2], in_uops[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_6_T_654 = mux(write_mask[6][3], in_uops[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ram_6_T_655 = or(_ram_6_T_651, _ram_6_T_652) node _ram_6_T_656 = or(_ram_6_T_655, _ram_6_T_653) node _ram_6_T_657 = or(_ram_6_T_656, _ram_6_T_654) wire _ram_6_WIRE_103 : UInt<3> connect _ram_6_WIRE_103, _ram_6_T_657 connect _ram_6_WIRE_83.sel_alu2, _ram_6_WIRE_103 node _ram_6_T_658 = mux(write_mask[6][0], in_uops[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_6_T_659 = mux(write_mask[6][1], in_uops[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_6_T_660 = mux(write_mask[6][2], in_uops[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_6_T_661 = mux(write_mask[6][3], in_uops[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _ram_6_T_662 = or(_ram_6_T_658, _ram_6_T_659) node _ram_6_T_663 = or(_ram_6_T_662, _ram_6_T_660) node _ram_6_T_664 = or(_ram_6_T_663, _ram_6_T_661) wire _ram_6_WIRE_104 : UInt<1> connect _ram_6_WIRE_104, _ram_6_T_664 connect _ram_6_WIRE_83.rxs1, _ram_6_WIRE_104 node _ram_6_T_665 = mux(write_mask[6][0], in_uops[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_6_T_666 = mux(write_mask[6][1], in_uops[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_6_T_667 = mux(write_mask[6][2], in_uops[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_6_T_668 = mux(write_mask[6][3], in_uops[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _ram_6_T_669 = or(_ram_6_T_665, _ram_6_T_666) node _ram_6_T_670 = or(_ram_6_T_669, _ram_6_T_667) node _ram_6_T_671 = or(_ram_6_T_670, _ram_6_T_668) wire _ram_6_WIRE_105 : UInt<1> connect _ram_6_WIRE_105, _ram_6_T_671 connect _ram_6_WIRE_83.rxs2, _ram_6_WIRE_105 node _ram_6_T_672 = mux(write_mask[6][0], in_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_6_T_673 = mux(write_mask[6][1], in_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_6_T_674 = mux(write_mask[6][2], in_uops[2].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_6_T_675 = mux(write_mask[6][3], in_uops[3].bits.ctrl.jalr, UInt<1>(0h0)) node _ram_6_T_676 = or(_ram_6_T_672, _ram_6_T_673) node _ram_6_T_677 = or(_ram_6_T_676, _ram_6_T_674) node _ram_6_T_678 = or(_ram_6_T_677, _ram_6_T_675) wire _ram_6_WIRE_106 : UInt<1> connect _ram_6_WIRE_106, _ram_6_T_678 connect _ram_6_WIRE_83.jalr, _ram_6_WIRE_106 node _ram_6_T_679 = mux(write_mask[6][0], in_uops[0].bits.ctrl.jal, UInt<1>(0h0)) node _ram_6_T_680 = mux(write_mask[6][1], in_uops[1].bits.ctrl.jal, UInt<1>(0h0)) node _ram_6_T_681 = mux(write_mask[6][2], in_uops[2].bits.ctrl.jal, UInt<1>(0h0)) node _ram_6_T_682 = mux(write_mask[6][3], in_uops[3].bits.ctrl.jal, UInt<1>(0h0)) node _ram_6_T_683 = or(_ram_6_T_679, _ram_6_T_680) node _ram_6_T_684 = or(_ram_6_T_683, _ram_6_T_681) node _ram_6_T_685 = or(_ram_6_T_684, _ram_6_T_682) wire _ram_6_WIRE_107 : UInt<1> connect _ram_6_WIRE_107, _ram_6_T_685 connect _ram_6_WIRE_83.jal, _ram_6_WIRE_107 node _ram_6_T_686 = mux(write_mask[6][0], in_uops[0].bits.ctrl.branch, UInt<1>(0h0)) node _ram_6_T_687 = mux(write_mask[6][1], in_uops[1].bits.ctrl.branch, UInt<1>(0h0)) node _ram_6_T_688 = mux(write_mask[6][2], in_uops[2].bits.ctrl.branch, UInt<1>(0h0)) node _ram_6_T_689 = mux(write_mask[6][3], in_uops[3].bits.ctrl.branch, UInt<1>(0h0)) node _ram_6_T_690 = or(_ram_6_T_686, _ram_6_T_687) node _ram_6_T_691 = or(_ram_6_T_690, _ram_6_T_688) node _ram_6_T_692 = or(_ram_6_T_691, _ram_6_T_689) wire _ram_6_WIRE_108 : UInt<1> connect _ram_6_WIRE_108, _ram_6_T_692 connect _ram_6_WIRE_83.branch, _ram_6_WIRE_108 node _ram_6_T_693 = mux(write_mask[6][0], in_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_6_T_694 = mux(write_mask[6][1], in_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_6_T_695 = mux(write_mask[6][2], in_uops[2].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_6_T_696 = mux(write_mask[6][3], in_uops[3].bits.ctrl.rocc, UInt<1>(0h0)) node _ram_6_T_697 = or(_ram_6_T_693, _ram_6_T_694) node _ram_6_T_698 = or(_ram_6_T_697, _ram_6_T_695) node _ram_6_T_699 = or(_ram_6_T_698, _ram_6_T_696) wire _ram_6_WIRE_109 : UInt<1> connect _ram_6_WIRE_109, _ram_6_T_699 connect _ram_6_WIRE_83.rocc, _ram_6_WIRE_109 node _ram_6_T_700 = mux(write_mask[6][0], in_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _ram_6_T_701 = mux(write_mask[6][1], in_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _ram_6_T_702 = mux(write_mask[6][2], in_uops[2].bits.ctrl.fp, UInt<1>(0h0)) node _ram_6_T_703 = mux(write_mask[6][3], in_uops[3].bits.ctrl.fp, UInt<1>(0h0)) node _ram_6_T_704 = or(_ram_6_T_700, _ram_6_T_701) node _ram_6_T_705 = or(_ram_6_T_704, _ram_6_T_702) node _ram_6_T_706 = or(_ram_6_T_705, _ram_6_T_703) wire _ram_6_WIRE_110 : UInt<1> connect _ram_6_WIRE_110, _ram_6_T_706 connect _ram_6_WIRE_83.fp, _ram_6_WIRE_110 node _ram_6_T_707 = mux(write_mask[6][0], in_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _ram_6_T_708 = mux(write_mask[6][1], in_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _ram_6_T_709 = mux(write_mask[6][2], in_uops[2].bits.ctrl.legal, UInt<1>(0h0)) node _ram_6_T_710 = mux(write_mask[6][3], in_uops[3].bits.ctrl.legal, UInt<1>(0h0)) node _ram_6_T_711 = or(_ram_6_T_707, _ram_6_T_708) node _ram_6_T_712 = or(_ram_6_T_711, _ram_6_T_709) node _ram_6_T_713 = or(_ram_6_T_712, _ram_6_T_710) wire _ram_6_WIRE_111 : UInt<1> connect _ram_6_WIRE_111, _ram_6_T_713 connect _ram_6_WIRE_83.legal, _ram_6_WIRE_111 connect _ram_6_WIRE_1.ctrl, _ram_6_WIRE_83 node _ram_6_T_714 = mux(write_mask[6][0], in_uops[0].bits.edge_inst, UInt<1>(0h0)) node _ram_6_T_715 = mux(write_mask[6][1], in_uops[1].bits.edge_inst, UInt<1>(0h0)) node _ram_6_T_716 = mux(write_mask[6][2], in_uops[2].bits.edge_inst, UInt<1>(0h0)) node _ram_6_T_717 = mux(write_mask[6][3], in_uops[3].bits.edge_inst, UInt<1>(0h0)) node _ram_6_T_718 = or(_ram_6_T_714, _ram_6_T_715) node _ram_6_T_719 = or(_ram_6_T_718, _ram_6_T_716) node _ram_6_T_720 = or(_ram_6_T_719, _ram_6_T_717) wire _ram_6_WIRE_112 : UInt<1> connect _ram_6_WIRE_112, _ram_6_T_720 connect _ram_6_WIRE_1.edge_inst, _ram_6_WIRE_112 node _ram_6_T_721 = mux(write_mask[6][0], in_uops[0].bits.pc, UInt<1>(0h0)) node _ram_6_T_722 = mux(write_mask[6][1], in_uops[1].bits.pc, UInt<1>(0h0)) node _ram_6_T_723 = mux(write_mask[6][2], in_uops[2].bits.pc, UInt<1>(0h0)) node _ram_6_T_724 = mux(write_mask[6][3], in_uops[3].bits.pc, UInt<1>(0h0)) node _ram_6_T_725 = or(_ram_6_T_721, _ram_6_T_722) node _ram_6_T_726 = or(_ram_6_T_725, _ram_6_T_723) node _ram_6_T_727 = or(_ram_6_T_726, _ram_6_T_724) wire _ram_6_WIRE_113 : UInt<40> connect _ram_6_WIRE_113, _ram_6_T_727 connect _ram_6_WIRE_1.pc, _ram_6_WIRE_113 node _ram_6_T_728 = mux(write_mask[6][0], in_uops[0].bits.raw_inst, UInt<1>(0h0)) node _ram_6_T_729 = mux(write_mask[6][1], in_uops[1].bits.raw_inst, UInt<1>(0h0)) node _ram_6_T_730 = mux(write_mask[6][2], in_uops[2].bits.raw_inst, UInt<1>(0h0)) node _ram_6_T_731 = mux(write_mask[6][3], in_uops[3].bits.raw_inst, UInt<1>(0h0)) node _ram_6_T_732 = or(_ram_6_T_728, _ram_6_T_729) node _ram_6_T_733 = or(_ram_6_T_732, _ram_6_T_730) node _ram_6_T_734 = or(_ram_6_T_733, _ram_6_T_731) wire _ram_6_WIRE_114 : UInt<32> connect _ram_6_WIRE_114, _ram_6_T_734 connect _ram_6_WIRE_1.raw_inst, _ram_6_WIRE_114 node _ram_6_T_735 = mux(write_mask[6][0], in_uops[0].bits.inst, UInt<1>(0h0)) node _ram_6_T_736 = mux(write_mask[6][1], in_uops[1].bits.inst, UInt<1>(0h0)) node _ram_6_T_737 = mux(write_mask[6][2], in_uops[2].bits.inst, UInt<1>(0h0)) node _ram_6_T_738 = mux(write_mask[6][3], in_uops[3].bits.inst, UInt<1>(0h0)) node _ram_6_T_739 = or(_ram_6_T_735, _ram_6_T_736) node _ram_6_T_740 = or(_ram_6_T_739, _ram_6_T_737) node _ram_6_T_741 = or(_ram_6_T_740, _ram_6_T_738) wire _ram_6_WIRE_115 : UInt<32> connect _ram_6_WIRE_115, _ram_6_T_741 connect _ram_6_WIRE_1.inst, _ram_6_WIRE_115 connect _ram_6_WIRE.bits, _ram_6_WIRE_1 node _ram_6_T_742 = mux(write_mask[6][0], in_uops[0].valid, UInt<1>(0h0)) node _ram_6_T_743 = mux(write_mask[6][1], in_uops[1].valid, UInt<1>(0h0)) node _ram_6_T_744 = mux(write_mask[6][2], in_uops[2].valid, UInt<1>(0h0)) node _ram_6_T_745 = mux(write_mask[6][3], in_uops[3].valid, UInt<1>(0h0)) node _ram_6_T_746 = or(_ram_6_T_742, _ram_6_T_743) node _ram_6_T_747 = or(_ram_6_T_746, _ram_6_T_744) node _ram_6_T_748 = or(_ram_6_T_747, _ram_6_T_745) wire _ram_6_WIRE_116 : UInt<1> connect _ram_6_WIRE_116, _ram_6_T_748 connect _ram_6_WIRE.valid, _ram_6_WIRE_116 connect ram[6], _ram_6_WIRE node _out_uop_T = bits(deq_ptr, 0, 0) node _out_uop_T_1 = bits(deq_ptr, 1, 1) node _out_uop_T_2 = bits(deq_ptr, 2, 2) node _out_uop_T_3 = bits(deq_ptr, 3, 3) node _out_uop_T_4 = bits(deq_ptr, 4, 4) node _out_uop_T_5 = bits(deq_ptr, 5, 5) node _out_uop_T_6 = bits(deq_ptr, 6, 6) wire out_uop : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _out_uop_WIRE : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _out_uop_T_7 = mux(_out_uop_T, ram[0].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_8 = mux(_out_uop_T_1, ram[1].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_9 = mux(_out_uop_T_2, ram[2].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_10 = mux(_out_uop_T_3, ram[3].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_11 = mux(_out_uop_T_4, ram[4].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_12 = mux(_out_uop_T_5, ram[5].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_13 = mux(_out_uop_T_6, ram[6].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_14 = or(_out_uop_T_7, _out_uop_T_8) node _out_uop_T_15 = or(_out_uop_T_14, _out_uop_T_9) node _out_uop_T_16 = or(_out_uop_T_15, _out_uop_T_10) node _out_uop_T_17 = or(_out_uop_T_16, _out_uop_T_11) node _out_uop_T_18 = or(_out_uop_T_17, _out_uop_T_12) node _out_uop_T_19 = or(_out_uop_T_18, _out_uop_T_13) wire _out_uop_WIRE_1 : UInt<1> connect _out_uop_WIRE_1, _out_uop_T_19 connect _out_uop_WIRE.flush_pipe, _out_uop_WIRE_1 node _out_uop_T_20 = mux(_out_uop_T, ram[0].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_21 = mux(_out_uop_T_1, ram[1].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_22 = mux(_out_uop_T_2, ram[2].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_23 = mux(_out_uop_T_3, ram[3].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_24 = mux(_out_uop_T_4, ram[4].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_25 = mux(_out_uop_T_5, ram[5].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_26 = mux(_out_uop_T_6, ram[6].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_27 = or(_out_uop_T_20, _out_uop_T_21) node _out_uop_T_28 = or(_out_uop_T_27, _out_uop_T_22) node _out_uop_T_29 = or(_out_uop_T_28, _out_uop_T_23) node _out_uop_T_30 = or(_out_uop_T_29, _out_uop_T_24) node _out_uop_T_31 = or(_out_uop_T_30, _out_uop_T_25) node _out_uop_T_32 = or(_out_uop_T_31, _out_uop_T_26) wire _out_uop_WIRE_2 : UInt<2> connect _out_uop_WIRE_2, _out_uop_T_32 connect _out_uop_WIRE.mem_size, _out_uop_WIRE_2 wire _out_uop_WIRE_3 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _out_uop_T_33 = mux(_out_uop_T, ram[0].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_34 = mux(_out_uop_T_1, ram[1].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_35 = mux(_out_uop_T_2, ram[2].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_36 = mux(_out_uop_T_3, ram[3].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_37 = mux(_out_uop_T_4, ram[4].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_38 = mux(_out_uop_T_5, ram[5].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_39 = mux(_out_uop_T_6, ram[6].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_40 = or(_out_uop_T_33, _out_uop_T_34) node _out_uop_T_41 = or(_out_uop_T_40, _out_uop_T_35) node _out_uop_T_42 = or(_out_uop_T_41, _out_uop_T_36) node _out_uop_T_43 = or(_out_uop_T_42, _out_uop_T_37) node _out_uop_T_44 = or(_out_uop_T_43, _out_uop_T_38) node _out_uop_T_45 = or(_out_uop_T_44, _out_uop_T_39) wire _out_uop_WIRE_4 : UInt<65> connect _out_uop_WIRE_4, _out_uop_T_45 connect _out_uop_WIRE_3.in3, _out_uop_WIRE_4 node _out_uop_T_46 = mux(_out_uop_T, ram[0].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_47 = mux(_out_uop_T_1, ram[1].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_48 = mux(_out_uop_T_2, ram[2].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_49 = mux(_out_uop_T_3, ram[3].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_50 = mux(_out_uop_T_4, ram[4].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_51 = mux(_out_uop_T_5, ram[5].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_52 = mux(_out_uop_T_6, ram[6].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_53 = or(_out_uop_T_46, _out_uop_T_47) node _out_uop_T_54 = or(_out_uop_T_53, _out_uop_T_48) node _out_uop_T_55 = or(_out_uop_T_54, _out_uop_T_49) node _out_uop_T_56 = or(_out_uop_T_55, _out_uop_T_50) node _out_uop_T_57 = or(_out_uop_T_56, _out_uop_T_51) node _out_uop_T_58 = or(_out_uop_T_57, _out_uop_T_52) wire _out_uop_WIRE_5 : UInt<65> connect _out_uop_WIRE_5, _out_uop_T_58 connect _out_uop_WIRE_3.in2, _out_uop_WIRE_5 node _out_uop_T_59 = mux(_out_uop_T, ram[0].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_60 = mux(_out_uop_T_1, ram[1].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_61 = mux(_out_uop_T_2, ram[2].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_62 = mux(_out_uop_T_3, ram[3].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_63 = mux(_out_uop_T_4, ram[4].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_64 = mux(_out_uop_T_5, ram[5].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_65 = mux(_out_uop_T_6, ram[6].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_66 = or(_out_uop_T_59, _out_uop_T_60) node _out_uop_T_67 = or(_out_uop_T_66, _out_uop_T_61) node _out_uop_T_68 = or(_out_uop_T_67, _out_uop_T_62) node _out_uop_T_69 = or(_out_uop_T_68, _out_uop_T_63) node _out_uop_T_70 = or(_out_uop_T_69, _out_uop_T_64) node _out_uop_T_71 = or(_out_uop_T_70, _out_uop_T_65) wire _out_uop_WIRE_6 : UInt<65> connect _out_uop_WIRE_6, _out_uop_T_71 connect _out_uop_WIRE_3.in1, _out_uop_WIRE_6 node _out_uop_T_72 = mux(_out_uop_T, ram[0].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_73 = mux(_out_uop_T_1, ram[1].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_74 = mux(_out_uop_T_2, ram[2].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_75 = mux(_out_uop_T_3, ram[3].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_76 = mux(_out_uop_T_4, ram[4].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_77 = mux(_out_uop_T_5, ram[5].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_78 = mux(_out_uop_T_6, ram[6].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_79 = or(_out_uop_T_72, _out_uop_T_73) node _out_uop_T_80 = or(_out_uop_T_79, _out_uop_T_74) node _out_uop_T_81 = or(_out_uop_T_80, _out_uop_T_75) node _out_uop_T_82 = or(_out_uop_T_81, _out_uop_T_76) node _out_uop_T_83 = or(_out_uop_T_82, _out_uop_T_77) node _out_uop_T_84 = or(_out_uop_T_83, _out_uop_T_78) wire _out_uop_WIRE_7 : UInt<2> connect _out_uop_WIRE_7, _out_uop_T_84 connect _out_uop_WIRE_3.fmt, _out_uop_WIRE_7 node _out_uop_T_85 = mux(_out_uop_T, ram[0].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_86 = mux(_out_uop_T_1, ram[1].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_87 = mux(_out_uop_T_2, ram[2].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_88 = mux(_out_uop_T_3, ram[3].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_89 = mux(_out_uop_T_4, ram[4].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_90 = mux(_out_uop_T_5, ram[5].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_91 = mux(_out_uop_T_6, ram[6].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_92 = or(_out_uop_T_85, _out_uop_T_86) node _out_uop_T_93 = or(_out_uop_T_92, _out_uop_T_87) node _out_uop_T_94 = or(_out_uop_T_93, _out_uop_T_88) node _out_uop_T_95 = or(_out_uop_T_94, _out_uop_T_89) node _out_uop_T_96 = or(_out_uop_T_95, _out_uop_T_90) node _out_uop_T_97 = or(_out_uop_T_96, _out_uop_T_91) wire _out_uop_WIRE_8 : UInt<2> connect _out_uop_WIRE_8, _out_uop_T_97 connect _out_uop_WIRE_3.typ, _out_uop_WIRE_8 node _out_uop_T_98 = mux(_out_uop_T, ram[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_99 = mux(_out_uop_T_1, ram[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_100 = mux(_out_uop_T_2, ram[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_101 = mux(_out_uop_T_3, ram[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_102 = mux(_out_uop_T_4, ram[4].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_103 = mux(_out_uop_T_5, ram[5].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_104 = mux(_out_uop_T_6, ram[6].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_105 = or(_out_uop_T_98, _out_uop_T_99) node _out_uop_T_106 = or(_out_uop_T_105, _out_uop_T_100) node _out_uop_T_107 = or(_out_uop_T_106, _out_uop_T_101) node _out_uop_T_108 = or(_out_uop_T_107, _out_uop_T_102) node _out_uop_T_109 = or(_out_uop_T_108, _out_uop_T_103) node _out_uop_T_110 = or(_out_uop_T_109, _out_uop_T_104) wire _out_uop_WIRE_9 : UInt<2> connect _out_uop_WIRE_9, _out_uop_T_110 connect _out_uop_WIRE_3.fmaCmd, _out_uop_WIRE_9 node _out_uop_T_111 = mux(_out_uop_T, ram[0].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_112 = mux(_out_uop_T_1, ram[1].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_113 = mux(_out_uop_T_2, ram[2].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_114 = mux(_out_uop_T_3, ram[3].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_115 = mux(_out_uop_T_4, ram[4].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_116 = mux(_out_uop_T_5, ram[5].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_117 = mux(_out_uop_T_6, ram[6].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_118 = or(_out_uop_T_111, _out_uop_T_112) node _out_uop_T_119 = or(_out_uop_T_118, _out_uop_T_113) node _out_uop_T_120 = or(_out_uop_T_119, _out_uop_T_114) node _out_uop_T_121 = or(_out_uop_T_120, _out_uop_T_115) node _out_uop_T_122 = or(_out_uop_T_121, _out_uop_T_116) node _out_uop_T_123 = or(_out_uop_T_122, _out_uop_T_117) wire _out_uop_WIRE_10 : UInt<3> connect _out_uop_WIRE_10, _out_uop_T_123 connect _out_uop_WIRE_3.rm, _out_uop_WIRE_10 node _out_uop_T_124 = mux(_out_uop_T, ram[0].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_125 = mux(_out_uop_T_1, ram[1].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_126 = mux(_out_uop_T_2, ram[2].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_127 = mux(_out_uop_T_3, ram[3].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_128 = mux(_out_uop_T_4, ram[4].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_129 = mux(_out_uop_T_5, ram[5].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_130 = mux(_out_uop_T_6, ram[6].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_131 = or(_out_uop_T_124, _out_uop_T_125) node _out_uop_T_132 = or(_out_uop_T_131, _out_uop_T_126) node _out_uop_T_133 = or(_out_uop_T_132, _out_uop_T_127) node _out_uop_T_134 = or(_out_uop_T_133, _out_uop_T_128) node _out_uop_T_135 = or(_out_uop_T_134, _out_uop_T_129) node _out_uop_T_136 = or(_out_uop_T_135, _out_uop_T_130) wire _out_uop_WIRE_11 : UInt<1> connect _out_uop_WIRE_11, _out_uop_T_136 connect _out_uop_WIRE_3.vec, _out_uop_WIRE_11 node _out_uop_T_137 = mux(_out_uop_T, ram[0].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_138 = mux(_out_uop_T_1, ram[1].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_139 = mux(_out_uop_T_2, ram[2].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_140 = mux(_out_uop_T_3, ram[3].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_141 = mux(_out_uop_T_4, ram[4].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_142 = mux(_out_uop_T_5, ram[5].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_143 = mux(_out_uop_T_6, ram[6].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_144 = or(_out_uop_T_137, _out_uop_T_138) node _out_uop_T_145 = or(_out_uop_T_144, _out_uop_T_139) node _out_uop_T_146 = or(_out_uop_T_145, _out_uop_T_140) node _out_uop_T_147 = or(_out_uop_T_146, _out_uop_T_141) node _out_uop_T_148 = or(_out_uop_T_147, _out_uop_T_142) node _out_uop_T_149 = or(_out_uop_T_148, _out_uop_T_143) wire _out_uop_WIRE_12 : UInt<1> connect _out_uop_WIRE_12, _out_uop_T_149 connect _out_uop_WIRE_3.wflags, _out_uop_WIRE_12 node _out_uop_T_150 = mux(_out_uop_T, ram[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_151 = mux(_out_uop_T_1, ram[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_152 = mux(_out_uop_T_2, ram[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_153 = mux(_out_uop_T_3, ram[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_154 = mux(_out_uop_T_4, ram[4].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_155 = mux(_out_uop_T_5, ram[5].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_156 = mux(_out_uop_T_6, ram[6].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_157 = or(_out_uop_T_150, _out_uop_T_151) node _out_uop_T_158 = or(_out_uop_T_157, _out_uop_T_152) node _out_uop_T_159 = or(_out_uop_T_158, _out_uop_T_153) node _out_uop_T_160 = or(_out_uop_T_159, _out_uop_T_154) node _out_uop_T_161 = or(_out_uop_T_160, _out_uop_T_155) node _out_uop_T_162 = or(_out_uop_T_161, _out_uop_T_156) wire _out_uop_WIRE_13 : UInt<1> connect _out_uop_WIRE_13, _out_uop_T_162 connect _out_uop_WIRE_3.sqrt, _out_uop_WIRE_13 node _out_uop_T_163 = mux(_out_uop_T, ram[0].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_164 = mux(_out_uop_T_1, ram[1].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_165 = mux(_out_uop_T_2, ram[2].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_166 = mux(_out_uop_T_3, ram[3].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_167 = mux(_out_uop_T_4, ram[4].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_168 = mux(_out_uop_T_5, ram[5].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_169 = mux(_out_uop_T_6, ram[6].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_170 = or(_out_uop_T_163, _out_uop_T_164) node _out_uop_T_171 = or(_out_uop_T_170, _out_uop_T_165) node _out_uop_T_172 = or(_out_uop_T_171, _out_uop_T_166) node _out_uop_T_173 = or(_out_uop_T_172, _out_uop_T_167) node _out_uop_T_174 = or(_out_uop_T_173, _out_uop_T_168) node _out_uop_T_175 = or(_out_uop_T_174, _out_uop_T_169) wire _out_uop_WIRE_14 : UInt<1> connect _out_uop_WIRE_14, _out_uop_T_175 connect _out_uop_WIRE_3.div, _out_uop_WIRE_14 node _out_uop_T_176 = mux(_out_uop_T, ram[0].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_177 = mux(_out_uop_T_1, ram[1].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_178 = mux(_out_uop_T_2, ram[2].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_179 = mux(_out_uop_T_3, ram[3].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_180 = mux(_out_uop_T_4, ram[4].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_181 = mux(_out_uop_T_5, ram[5].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_182 = mux(_out_uop_T_6, ram[6].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_183 = or(_out_uop_T_176, _out_uop_T_177) node _out_uop_T_184 = or(_out_uop_T_183, _out_uop_T_178) node _out_uop_T_185 = or(_out_uop_T_184, _out_uop_T_179) node _out_uop_T_186 = or(_out_uop_T_185, _out_uop_T_180) node _out_uop_T_187 = or(_out_uop_T_186, _out_uop_T_181) node _out_uop_T_188 = or(_out_uop_T_187, _out_uop_T_182) wire _out_uop_WIRE_15 : UInt<1> connect _out_uop_WIRE_15, _out_uop_T_188 connect _out_uop_WIRE_3.fma, _out_uop_WIRE_15 node _out_uop_T_189 = mux(_out_uop_T, ram[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_190 = mux(_out_uop_T_1, ram[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_191 = mux(_out_uop_T_2, ram[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_192 = mux(_out_uop_T_3, ram[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_193 = mux(_out_uop_T_4, ram[4].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_194 = mux(_out_uop_T_5, ram[5].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_195 = mux(_out_uop_T_6, ram[6].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_196 = or(_out_uop_T_189, _out_uop_T_190) node _out_uop_T_197 = or(_out_uop_T_196, _out_uop_T_191) node _out_uop_T_198 = or(_out_uop_T_197, _out_uop_T_192) node _out_uop_T_199 = or(_out_uop_T_198, _out_uop_T_193) node _out_uop_T_200 = or(_out_uop_T_199, _out_uop_T_194) node _out_uop_T_201 = or(_out_uop_T_200, _out_uop_T_195) wire _out_uop_WIRE_16 : UInt<1> connect _out_uop_WIRE_16, _out_uop_T_201 connect _out_uop_WIRE_3.fastpipe, _out_uop_WIRE_16 node _out_uop_T_202 = mux(_out_uop_T, ram[0].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_203 = mux(_out_uop_T_1, ram[1].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_204 = mux(_out_uop_T_2, ram[2].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_205 = mux(_out_uop_T_3, ram[3].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_206 = mux(_out_uop_T_4, ram[4].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_207 = mux(_out_uop_T_5, ram[5].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_208 = mux(_out_uop_T_6, ram[6].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_209 = or(_out_uop_T_202, _out_uop_T_203) node _out_uop_T_210 = or(_out_uop_T_209, _out_uop_T_204) node _out_uop_T_211 = or(_out_uop_T_210, _out_uop_T_205) node _out_uop_T_212 = or(_out_uop_T_211, _out_uop_T_206) node _out_uop_T_213 = or(_out_uop_T_212, _out_uop_T_207) node _out_uop_T_214 = or(_out_uop_T_213, _out_uop_T_208) wire _out_uop_WIRE_17 : UInt<1> connect _out_uop_WIRE_17, _out_uop_T_214 connect _out_uop_WIRE_3.toint, _out_uop_WIRE_17 node _out_uop_T_215 = mux(_out_uop_T, ram[0].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_216 = mux(_out_uop_T_1, ram[1].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_217 = mux(_out_uop_T_2, ram[2].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_218 = mux(_out_uop_T_3, ram[3].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_219 = mux(_out_uop_T_4, ram[4].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_220 = mux(_out_uop_T_5, ram[5].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_221 = mux(_out_uop_T_6, ram[6].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_222 = or(_out_uop_T_215, _out_uop_T_216) node _out_uop_T_223 = or(_out_uop_T_222, _out_uop_T_217) node _out_uop_T_224 = or(_out_uop_T_223, _out_uop_T_218) node _out_uop_T_225 = or(_out_uop_T_224, _out_uop_T_219) node _out_uop_T_226 = or(_out_uop_T_225, _out_uop_T_220) node _out_uop_T_227 = or(_out_uop_T_226, _out_uop_T_221) wire _out_uop_WIRE_18 : UInt<1> connect _out_uop_WIRE_18, _out_uop_T_227 connect _out_uop_WIRE_3.fromint, _out_uop_WIRE_18 node _out_uop_T_228 = mux(_out_uop_T, ram[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_229 = mux(_out_uop_T_1, ram[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_230 = mux(_out_uop_T_2, ram[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_231 = mux(_out_uop_T_3, ram[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_232 = mux(_out_uop_T_4, ram[4].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_233 = mux(_out_uop_T_5, ram[5].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_234 = mux(_out_uop_T_6, ram[6].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_235 = or(_out_uop_T_228, _out_uop_T_229) node _out_uop_T_236 = or(_out_uop_T_235, _out_uop_T_230) node _out_uop_T_237 = or(_out_uop_T_236, _out_uop_T_231) node _out_uop_T_238 = or(_out_uop_T_237, _out_uop_T_232) node _out_uop_T_239 = or(_out_uop_T_238, _out_uop_T_233) node _out_uop_T_240 = or(_out_uop_T_239, _out_uop_T_234) wire _out_uop_WIRE_19 : UInt<2> connect _out_uop_WIRE_19, _out_uop_T_240 connect _out_uop_WIRE_3.typeTagOut, _out_uop_WIRE_19 node _out_uop_T_241 = mux(_out_uop_T, ram[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_242 = mux(_out_uop_T_1, ram[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_243 = mux(_out_uop_T_2, ram[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_244 = mux(_out_uop_T_3, ram[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_245 = mux(_out_uop_T_4, ram[4].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_246 = mux(_out_uop_T_5, ram[5].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_247 = mux(_out_uop_T_6, ram[6].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_248 = or(_out_uop_T_241, _out_uop_T_242) node _out_uop_T_249 = or(_out_uop_T_248, _out_uop_T_243) node _out_uop_T_250 = or(_out_uop_T_249, _out_uop_T_244) node _out_uop_T_251 = or(_out_uop_T_250, _out_uop_T_245) node _out_uop_T_252 = or(_out_uop_T_251, _out_uop_T_246) node _out_uop_T_253 = or(_out_uop_T_252, _out_uop_T_247) wire _out_uop_WIRE_20 : UInt<2> connect _out_uop_WIRE_20, _out_uop_T_253 connect _out_uop_WIRE_3.typeTagIn, _out_uop_WIRE_20 node _out_uop_T_254 = mux(_out_uop_T, ram[0].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_255 = mux(_out_uop_T_1, ram[1].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_256 = mux(_out_uop_T_2, ram[2].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_257 = mux(_out_uop_T_3, ram[3].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_258 = mux(_out_uop_T_4, ram[4].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_259 = mux(_out_uop_T_5, ram[5].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_260 = mux(_out_uop_T_6, ram[6].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_261 = or(_out_uop_T_254, _out_uop_T_255) node _out_uop_T_262 = or(_out_uop_T_261, _out_uop_T_256) node _out_uop_T_263 = or(_out_uop_T_262, _out_uop_T_257) node _out_uop_T_264 = or(_out_uop_T_263, _out_uop_T_258) node _out_uop_T_265 = or(_out_uop_T_264, _out_uop_T_259) node _out_uop_T_266 = or(_out_uop_T_265, _out_uop_T_260) wire _out_uop_WIRE_21 : UInt<1> connect _out_uop_WIRE_21, _out_uop_T_266 connect _out_uop_WIRE_3.swap23, _out_uop_WIRE_21 node _out_uop_T_267 = mux(_out_uop_T, ram[0].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_268 = mux(_out_uop_T_1, ram[1].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_269 = mux(_out_uop_T_2, ram[2].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_270 = mux(_out_uop_T_3, ram[3].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_271 = mux(_out_uop_T_4, ram[4].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_272 = mux(_out_uop_T_5, ram[5].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_273 = mux(_out_uop_T_6, ram[6].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_274 = or(_out_uop_T_267, _out_uop_T_268) node _out_uop_T_275 = or(_out_uop_T_274, _out_uop_T_269) node _out_uop_T_276 = or(_out_uop_T_275, _out_uop_T_270) node _out_uop_T_277 = or(_out_uop_T_276, _out_uop_T_271) node _out_uop_T_278 = or(_out_uop_T_277, _out_uop_T_272) node _out_uop_T_279 = or(_out_uop_T_278, _out_uop_T_273) wire _out_uop_WIRE_22 : UInt<1> connect _out_uop_WIRE_22, _out_uop_T_279 connect _out_uop_WIRE_3.swap12, _out_uop_WIRE_22 node _out_uop_T_280 = mux(_out_uop_T, ram[0].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_281 = mux(_out_uop_T_1, ram[1].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_282 = mux(_out_uop_T_2, ram[2].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_283 = mux(_out_uop_T_3, ram[3].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_284 = mux(_out_uop_T_4, ram[4].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_285 = mux(_out_uop_T_5, ram[5].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_286 = mux(_out_uop_T_6, ram[6].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_287 = or(_out_uop_T_280, _out_uop_T_281) node _out_uop_T_288 = or(_out_uop_T_287, _out_uop_T_282) node _out_uop_T_289 = or(_out_uop_T_288, _out_uop_T_283) node _out_uop_T_290 = or(_out_uop_T_289, _out_uop_T_284) node _out_uop_T_291 = or(_out_uop_T_290, _out_uop_T_285) node _out_uop_T_292 = or(_out_uop_T_291, _out_uop_T_286) wire _out_uop_WIRE_23 : UInt<1> connect _out_uop_WIRE_23, _out_uop_T_292 connect _out_uop_WIRE_3.ren3, _out_uop_WIRE_23 node _out_uop_T_293 = mux(_out_uop_T, ram[0].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_294 = mux(_out_uop_T_1, ram[1].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_295 = mux(_out_uop_T_2, ram[2].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_296 = mux(_out_uop_T_3, ram[3].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_297 = mux(_out_uop_T_4, ram[4].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_298 = mux(_out_uop_T_5, ram[5].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_299 = mux(_out_uop_T_6, ram[6].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_300 = or(_out_uop_T_293, _out_uop_T_294) node _out_uop_T_301 = or(_out_uop_T_300, _out_uop_T_295) node _out_uop_T_302 = or(_out_uop_T_301, _out_uop_T_296) node _out_uop_T_303 = or(_out_uop_T_302, _out_uop_T_297) node _out_uop_T_304 = or(_out_uop_T_303, _out_uop_T_298) node _out_uop_T_305 = or(_out_uop_T_304, _out_uop_T_299) wire _out_uop_WIRE_24 : UInt<1> connect _out_uop_WIRE_24, _out_uop_T_305 connect _out_uop_WIRE_3.ren2, _out_uop_WIRE_24 node _out_uop_T_306 = mux(_out_uop_T, ram[0].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_307 = mux(_out_uop_T_1, ram[1].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_308 = mux(_out_uop_T_2, ram[2].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_309 = mux(_out_uop_T_3, ram[3].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_310 = mux(_out_uop_T_4, ram[4].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_311 = mux(_out_uop_T_5, ram[5].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_312 = mux(_out_uop_T_6, ram[6].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_313 = or(_out_uop_T_306, _out_uop_T_307) node _out_uop_T_314 = or(_out_uop_T_313, _out_uop_T_308) node _out_uop_T_315 = or(_out_uop_T_314, _out_uop_T_309) node _out_uop_T_316 = or(_out_uop_T_315, _out_uop_T_310) node _out_uop_T_317 = or(_out_uop_T_316, _out_uop_T_311) node _out_uop_T_318 = or(_out_uop_T_317, _out_uop_T_312) wire _out_uop_WIRE_25 : UInt<1> connect _out_uop_WIRE_25, _out_uop_T_318 connect _out_uop_WIRE_3.ren1, _out_uop_WIRE_25 node _out_uop_T_319 = mux(_out_uop_T, ram[0].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_320 = mux(_out_uop_T_1, ram[1].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_321 = mux(_out_uop_T_2, ram[2].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_322 = mux(_out_uop_T_3, ram[3].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_323 = mux(_out_uop_T_4, ram[4].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_324 = mux(_out_uop_T_5, ram[5].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_325 = mux(_out_uop_T_6, ram[6].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_326 = or(_out_uop_T_319, _out_uop_T_320) node _out_uop_T_327 = or(_out_uop_T_326, _out_uop_T_321) node _out_uop_T_328 = or(_out_uop_T_327, _out_uop_T_322) node _out_uop_T_329 = or(_out_uop_T_328, _out_uop_T_323) node _out_uop_T_330 = or(_out_uop_T_329, _out_uop_T_324) node _out_uop_T_331 = or(_out_uop_T_330, _out_uop_T_325) wire _out_uop_WIRE_26 : UInt<1> connect _out_uop_WIRE_26, _out_uop_T_331 connect _out_uop_WIRE_3.wen, _out_uop_WIRE_26 node _out_uop_T_332 = mux(_out_uop_T, ram[0].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_333 = mux(_out_uop_T_1, ram[1].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_334 = mux(_out_uop_T_2, ram[2].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_335 = mux(_out_uop_T_3, ram[3].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_336 = mux(_out_uop_T_4, ram[4].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_337 = mux(_out_uop_T_5, ram[5].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_338 = mux(_out_uop_T_6, ram[6].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_339 = or(_out_uop_T_332, _out_uop_T_333) node _out_uop_T_340 = or(_out_uop_T_339, _out_uop_T_334) node _out_uop_T_341 = or(_out_uop_T_340, _out_uop_T_335) node _out_uop_T_342 = or(_out_uop_T_341, _out_uop_T_336) node _out_uop_T_343 = or(_out_uop_T_342, _out_uop_T_337) node _out_uop_T_344 = or(_out_uop_T_343, _out_uop_T_338) wire _out_uop_WIRE_27 : UInt<1> connect _out_uop_WIRE_27, _out_uop_T_344 connect _out_uop_WIRE_3.ldst, _out_uop_WIRE_27 connect _out_uop_WIRE.fdivin, _out_uop_WIRE_3 node _out_uop_T_345 = mux(_out_uop_T, ram[0].bits.fexc, UInt<1>(0h0)) node _out_uop_T_346 = mux(_out_uop_T_1, ram[1].bits.fexc, UInt<1>(0h0)) node _out_uop_T_347 = mux(_out_uop_T_2, ram[2].bits.fexc, UInt<1>(0h0)) node _out_uop_T_348 = mux(_out_uop_T_3, ram[3].bits.fexc, UInt<1>(0h0)) node _out_uop_T_349 = mux(_out_uop_T_4, ram[4].bits.fexc, UInt<1>(0h0)) node _out_uop_T_350 = mux(_out_uop_T_5, ram[5].bits.fexc, UInt<1>(0h0)) node _out_uop_T_351 = mux(_out_uop_T_6, ram[6].bits.fexc, UInt<1>(0h0)) node _out_uop_T_352 = or(_out_uop_T_345, _out_uop_T_346) node _out_uop_T_353 = or(_out_uop_T_352, _out_uop_T_347) node _out_uop_T_354 = or(_out_uop_T_353, _out_uop_T_348) node _out_uop_T_355 = or(_out_uop_T_354, _out_uop_T_349) node _out_uop_T_356 = or(_out_uop_T_355, _out_uop_T_350) node _out_uop_T_357 = or(_out_uop_T_356, _out_uop_T_351) wire _out_uop_WIRE_28 : UInt<5> connect _out_uop_WIRE_28, _out_uop_T_357 connect _out_uop_WIRE.fexc, _out_uop_WIRE_28 node _out_uop_T_358 = mux(_out_uop_T, ram[0].bits.fra3, UInt<1>(0h0)) node _out_uop_T_359 = mux(_out_uop_T_1, ram[1].bits.fra3, UInt<1>(0h0)) node _out_uop_T_360 = mux(_out_uop_T_2, ram[2].bits.fra3, UInt<1>(0h0)) node _out_uop_T_361 = mux(_out_uop_T_3, ram[3].bits.fra3, UInt<1>(0h0)) node _out_uop_T_362 = mux(_out_uop_T_4, ram[4].bits.fra3, UInt<1>(0h0)) node _out_uop_T_363 = mux(_out_uop_T_5, ram[5].bits.fra3, UInt<1>(0h0)) node _out_uop_T_364 = mux(_out_uop_T_6, ram[6].bits.fra3, UInt<1>(0h0)) node _out_uop_T_365 = or(_out_uop_T_358, _out_uop_T_359) node _out_uop_T_366 = or(_out_uop_T_365, _out_uop_T_360) node _out_uop_T_367 = or(_out_uop_T_366, _out_uop_T_361) node _out_uop_T_368 = or(_out_uop_T_367, _out_uop_T_362) node _out_uop_T_369 = or(_out_uop_T_368, _out_uop_T_363) node _out_uop_T_370 = or(_out_uop_T_369, _out_uop_T_364) wire _out_uop_WIRE_29 : UInt<5> connect _out_uop_WIRE_29, _out_uop_T_370 connect _out_uop_WIRE.fra3, _out_uop_WIRE_29 node _out_uop_T_371 = mux(_out_uop_T, ram[0].bits.fra2, UInt<1>(0h0)) node _out_uop_T_372 = mux(_out_uop_T_1, ram[1].bits.fra2, UInt<1>(0h0)) node _out_uop_T_373 = mux(_out_uop_T_2, ram[2].bits.fra2, UInt<1>(0h0)) node _out_uop_T_374 = mux(_out_uop_T_3, ram[3].bits.fra2, UInt<1>(0h0)) node _out_uop_T_375 = mux(_out_uop_T_4, ram[4].bits.fra2, UInt<1>(0h0)) node _out_uop_T_376 = mux(_out_uop_T_5, ram[5].bits.fra2, UInt<1>(0h0)) node _out_uop_T_377 = mux(_out_uop_T_6, ram[6].bits.fra2, UInt<1>(0h0)) node _out_uop_T_378 = or(_out_uop_T_371, _out_uop_T_372) node _out_uop_T_379 = or(_out_uop_T_378, _out_uop_T_373) node _out_uop_T_380 = or(_out_uop_T_379, _out_uop_T_374) node _out_uop_T_381 = or(_out_uop_T_380, _out_uop_T_375) node _out_uop_T_382 = or(_out_uop_T_381, _out_uop_T_376) node _out_uop_T_383 = or(_out_uop_T_382, _out_uop_T_377) wire _out_uop_WIRE_30 : UInt<5> connect _out_uop_WIRE_30, _out_uop_T_383 connect _out_uop_WIRE.fra2, _out_uop_WIRE_30 node _out_uop_T_384 = mux(_out_uop_T, ram[0].bits.fra1, UInt<1>(0h0)) node _out_uop_T_385 = mux(_out_uop_T_1, ram[1].bits.fra1, UInt<1>(0h0)) node _out_uop_T_386 = mux(_out_uop_T_2, ram[2].bits.fra1, UInt<1>(0h0)) node _out_uop_T_387 = mux(_out_uop_T_3, ram[3].bits.fra1, UInt<1>(0h0)) node _out_uop_T_388 = mux(_out_uop_T_4, ram[4].bits.fra1, UInt<1>(0h0)) node _out_uop_T_389 = mux(_out_uop_T_5, ram[5].bits.fra1, UInt<1>(0h0)) node _out_uop_T_390 = mux(_out_uop_T_6, ram[6].bits.fra1, UInt<1>(0h0)) node _out_uop_T_391 = or(_out_uop_T_384, _out_uop_T_385) node _out_uop_T_392 = or(_out_uop_T_391, _out_uop_T_386) node _out_uop_T_393 = or(_out_uop_T_392, _out_uop_T_387) node _out_uop_T_394 = or(_out_uop_T_393, _out_uop_T_388) node _out_uop_T_395 = or(_out_uop_T_394, _out_uop_T_389) node _out_uop_T_396 = or(_out_uop_T_395, _out_uop_T_390) wire _out_uop_WIRE_31 : UInt<5> connect _out_uop_WIRE_31, _out_uop_T_396 connect _out_uop_WIRE.fra1, _out_uop_WIRE_31 wire _out_uop_WIRE_32 : { valid : UInt<1>, bits : UInt<64>} node _out_uop_T_397 = mux(_out_uop_T, ram[0].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_398 = mux(_out_uop_T_1, ram[1].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_399 = mux(_out_uop_T_2, ram[2].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_400 = mux(_out_uop_T_3, ram[3].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_401 = mux(_out_uop_T_4, ram[4].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_402 = mux(_out_uop_T_5, ram[5].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_403 = mux(_out_uop_T_6, ram[6].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_404 = or(_out_uop_T_397, _out_uop_T_398) node _out_uop_T_405 = or(_out_uop_T_404, _out_uop_T_399) node _out_uop_T_406 = or(_out_uop_T_405, _out_uop_T_400) node _out_uop_T_407 = or(_out_uop_T_406, _out_uop_T_401) node _out_uop_T_408 = or(_out_uop_T_407, _out_uop_T_402) node _out_uop_T_409 = or(_out_uop_T_408, _out_uop_T_403) wire _out_uop_WIRE_33 : UInt<64> connect _out_uop_WIRE_33, _out_uop_T_409 connect _out_uop_WIRE_32.bits, _out_uop_WIRE_33 node _out_uop_T_410 = mux(_out_uop_T, ram[0].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_411 = mux(_out_uop_T_1, ram[1].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_412 = mux(_out_uop_T_2, ram[2].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_413 = mux(_out_uop_T_3, ram[3].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_414 = mux(_out_uop_T_4, ram[4].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_415 = mux(_out_uop_T_5, ram[5].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_416 = mux(_out_uop_T_6, ram[6].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_417 = or(_out_uop_T_410, _out_uop_T_411) node _out_uop_T_418 = or(_out_uop_T_417, _out_uop_T_412) node _out_uop_T_419 = or(_out_uop_T_418, _out_uop_T_413) node _out_uop_T_420 = or(_out_uop_T_419, _out_uop_T_414) node _out_uop_T_421 = or(_out_uop_T_420, _out_uop_T_415) node _out_uop_T_422 = or(_out_uop_T_421, _out_uop_T_416) wire _out_uop_WIRE_34 : UInt<1> connect _out_uop_WIRE_34, _out_uop_T_422 connect _out_uop_WIRE_32.valid, _out_uop_WIRE_34 connect _out_uop_WIRE.wdata, _out_uop_WIRE_32 node _out_uop_T_423 = mux(_out_uop_T, ram[0].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_424 = mux(_out_uop_T_1, ram[1].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_425 = mux(_out_uop_T_2, ram[2].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_426 = mux(_out_uop_T_3, ram[3].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_427 = mux(_out_uop_T_4, ram[4].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_428 = mux(_out_uop_T_5, ram[5].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_429 = mux(_out_uop_T_6, ram[6].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_430 = or(_out_uop_T_423, _out_uop_T_424) node _out_uop_T_431 = or(_out_uop_T_430, _out_uop_T_425) node _out_uop_T_432 = or(_out_uop_T_431, _out_uop_T_426) node _out_uop_T_433 = or(_out_uop_T_432, _out_uop_T_427) node _out_uop_T_434 = or(_out_uop_T_433, _out_uop_T_428) node _out_uop_T_435 = or(_out_uop_T_434, _out_uop_T_429) wire _out_uop_WIRE_35 : UInt<1> connect _out_uop_WIRE_35, _out_uop_T_435 connect _out_uop_WIRE.uses_latealu, _out_uop_WIRE_35 node _out_uop_T_436 = mux(_out_uop_T, ram[0].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_437 = mux(_out_uop_T_1, ram[1].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_438 = mux(_out_uop_T_2, ram[2].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_439 = mux(_out_uop_T_3, ram[3].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_440 = mux(_out_uop_T_4, ram[4].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_441 = mux(_out_uop_T_5, ram[5].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_442 = mux(_out_uop_T_6, ram[6].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_443 = or(_out_uop_T_436, _out_uop_T_437) node _out_uop_T_444 = or(_out_uop_T_443, _out_uop_T_438) node _out_uop_T_445 = or(_out_uop_T_444, _out_uop_T_439) node _out_uop_T_446 = or(_out_uop_T_445, _out_uop_T_440) node _out_uop_T_447 = or(_out_uop_T_446, _out_uop_T_441) node _out_uop_T_448 = or(_out_uop_T_447, _out_uop_T_442) wire _out_uop_WIRE_36 : UInt<1> connect _out_uop_WIRE_36, _out_uop_T_448 connect _out_uop_WIRE.uses_memalu, _out_uop_WIRE_36 node _out_uop_T_449 = mux(_out_uop_T, ram[0].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_450 = mux(_out_uop_T_1, ram[1].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_451 = mux(_out_uop_T_2, ram[2].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_452 = mux(_out_uop_T_3, ram[3].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_453 = mux(_out_uop_T_4, ram[4].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_454 = mux(_out_uop_T_5, ram[5].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_455 = mux(_out_uop_T_6, ram[6].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_456 = or(_out_uop_T_449, _out_uop_T_450) node _out_uop_T_457 = or(_out_uop_T_456, _out_uop_T_451) node _out_uop_T_458 = or(_out_uop_T_457, _out_uop_T_452) node _out_uop_T_459 = or(_out_uop_T_458, _out_uop_T_453) node _out_uop_T_460 = or(_out_uop_T_459, _out_uop_T_454) node _out_uop_T_461 = or(_out_uop_T_460, _out_uop_T_455) wire _out_uop_WIRE_37 : UInt<64> connect _out_uop_WIRE_37, _out_uop_T_461 connect _out_uop_WIRE.rs3_data, _out_uop_WIRE_37 node _out_uop_T_462 = mux(_out_uop_T, ram[0].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_463 = mux(_out_uop_T_1, ram[1].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_464 = mux(_out_uop_T_2, ram[2].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_465 = mux(_out_uop_T_3, ram[3].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_466 = mux(_out_uop_T_4, ram[4].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_467 = mux(_out_uop_T_5, ram[5].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_468 = mux(_out_uop_T_6, ram[6].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_469 = or(_out_uop_T_462, _out_uop_T_463) node _out_uop_T_470 = or(_out_uop_T_469, _out_uop_T_464) node _out_uop_T_471 = or(_out_uop_T_470, _out_uop_T_465) node _out_uop_T_472 = or(_out_uop_T_471, _out_uop_T_466) node _out_uop_T_473 = or(_out_uop_T_472, _out_uop_T_467) node _out_uop_T_474 = or(_out_uop_T_473, _out_uop_T_468) wire _out_uop_WIRE_38 : UInt<64> connect _out_uop_WIRE_38, _out_uop_T_474 connect _out_uop_WIRE.rs2_data, _out_uop_WIRE_38 node _out_uop_T_475 = mux(_out_uop_T, ram[0].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_476 = mux(_out_uop_T_1, ram[1].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_477 = mux(_out_uop_T_2, ram[2].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_478 = mux(_out_uop_T_3, ram[3].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_479 = mux(_out_uop_T_4, ram[4].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_480 = mux(_out_uop_T_5, ram[5].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_481 = mux(_out_uop_T_6, ram[6].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_482 = or(_out_uop_T_475, _out_uop_T_476) node _out_uop_T_483 = or(_out_uop_T_482, _out_uop_T_477) node _out_uop_T_484 = or(_out_uop_T_483, _out_uop_T_478) node _out_uop_T_485 = or(_out_uop_T_484, _out_uop_T_479) node _out_uop_T_486 = or(_out_uop_T_485, _out_uop_T_480) node _out_uop_T_487 = or(_out_uop_T_486, _out_uop_T_481) wire _out_uop_WIRE_39 : UInt<64> connect _out_uop_WIRE_39, _out_uop_T_487 connect _out_uop_WIRE.rs1_data, _out_uop_WIRE_39 node _out_uop_T_488 = mux(_out_uop_T, ram[0].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_489 = mux(_out_uop_T_1, ram[1].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_490 = mux(_out_uop_T_2, ram[2].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_491 = mux(_out_uop_T_3, ram[3].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_492 = mux(_out_uop_T_4, ram[4].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_493 = mux(_out_uop_T_5, ram[5].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_494 = mux(_out_uop_T_6, ram[6].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_495 = or(_out_uop_T_488, _out_uop_T_489) node _out_uop_T_496 = or(_out_uop_T_495, _out_uop_T_490) node _out_uop_T_497 = or(_out_uop_T_496, _out_uop_T_491) node _out_uop_T_498 = or(_out_uop_T_497, _out_uop_T_492) node _out_uop_T_499 = or(_out_uop_T_498, _out_uop_T_493) node _out_uop_T_500 = or(_out_uop_T_499, _out_uop_T_494) wire _out_uop_WIRE_40 : UInt<1> connect _out_uop_WIRE_40, _out_uop_T_500 connect _out_uop_WIRE.needs_replay, _out_uop_WIRE_40 node _out_uop_T_501 = mux(_out_uop_T, ram[0].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_502 = mux(_out_uop_T_1, ram[1].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_503 = mux(_out_uop_T_2, ram[2].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_504 = mux(_out_uop_T_3, ram[3].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_505 = mux(_out_uop_T_4, ram[4].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_506 = mux(_out_uop_T_5, ram[5].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_507 = mux(_out_uop_T_6, ram[6].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_508 = or(_out_uop_T_501, _out_uop_T_502) node _out_uop_T_509 = or(_out_uop_T_508, _out_uop_T_503) node _out_uop_T_510 = or(_out_uop_T_509, _out_uop_T_504) node _out_uop_T_511 = or(_out_uop_T_510, _out_uop_T_505) node _out_uop_T_512 = or(_out_uop_T_511, _out_uop_T_506) node _out_uop_T_513 = or(_out_uop_T_512, _out_uop_T_507) wire _out_uop_WIRE_41 : UInt<64> connect _out_uop_WIRE_41, _out_uop_T_513 connect _out_uop_WIRE.xcpt_cause, _out_uop_WIRE_41 node _out_uop_T_514 = mux(_out_uop_T, ram[0].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_515 = mux(_out_uop_T_1, ram[1].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_516 = mux(_out_uop_T_2, ram[2].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_517 = mux(_out_uop_T_3, ram[3].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_518 = mux(_out_uop_T_4, ram[4].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_519 = mux(_out_uop_T_5, ram[5].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_520 = mux(_out_uop_T_6, ram[6].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_521 = or(_out_uop_T_514, _out_uop_T_515) node _out_uop_T_522 = or(_out_uop_T_521, _out_uop_T_516) node _out_uop_T_523 = or(_out_uop_T_522, _out_uop_T_517) node _out_uop_T_524 = or(_out_uop_T_523, _out_uop_T_518) node _out_uop_T_525 = or(_out_uop_T_524, _out_uop_T_519) node _out_uop_T_526 = or(_out_uop_T_525, _out_uop_T_520) wire _out_uop_WIRE_42 : UInt<1> connect _out_uop_WIRE_42, _out_uop_T_526 connect _out_uop_WIRE.xcpt, _out_uop_WIRE_42 node _out_uop_T_527 = mux(_out_uop_T, ram[0].bits.taken, UInt<1>(0h0)) node _out_uop_T_528 = mux(_out_uop_T_1, ram[1].bits.taken, UInt<1>(0h0)) node _out_uop_T_529 = mux(_out_uop_T_2, ram[2].bits.taken, UInt<1>(0h0)) node _out_uop_T_530 = mux(_out_uop_T_3, ram[3].bits.taken, UInt<1>(0h0)) node _out_uop_T_531 = mux(_out_uop_T_4, ram[4].bits.taken, UInt<1>(0h0)) node _out_uop_T_532 = mux(_out_uop_T_5, ram[5].bits.taken, UInt<1>(0h0)) node _out_uop_T_533 = mux(_out_uop_T_6, ram[6].bits.taken, UInt<1>(0h0)) node _out_uop_T_534 = or(_out_uop_T_527, _out_uop_T_528) node _out_uop_T_535 = or(_out_uop_T_534, _out_uop_T_529) node _out_uop_T_536 = or(_out_uop_T_535, _out_uop_T_530) node _out_uop_T_537 = or(_out_uop_T_536, _out_uop_T_531) node _out_uop_T_538 = or(_out_uop_T_537, _out_uop_T_532) node _out_uop_T_539 = or(_out_uop_T_538, _out_uop_T_533) wire _out_uop_WIRE_43 : UInt<1> connect _out_uop_WIRE_43, _out_uop_T_539 connect _out_uop_WIRE.taken, _out_uop_WIRE_43 node _out_uop_T_540 = mux(_out_uop_T, ram[0].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_541 = mux(_out_uop_T_1, ram[1].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_542 = mux(_out_uop_T_2, ram[2].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_543 = mux(_out_uop_T_3, ram[3].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_544 = mux(_out_uop_T_4, ram[4].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_545 = mux(_out_uop_T_5, ram[5].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_546 = mux(_out_uop_T_6, ram[6].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_547 = or(_out_uop_T_540, _out_uop_T_541) node _out_uop_T_548 = or(_out_uop_T_547, _out_uop_T_542) node _out_uop_T_549 = or(_out_uop_T_548, _out_uop_T_543) node _out_uop_T_550 = or(_out_uop_T_549, _out_uop_T_544) node _out_uop_T_551 = or(_out_uop_T_550, _out_uop_T_545) node _out_uop_T_552 = or(_out_uop_T_551, _out_uop_T_546) wire _out_uop_WIRE_44 : UInt<3> connect _out_uop_WIRE_44, _out_uop_T_552 connect _out_uop_WIRE.ras_head, _out_uop_WIRE_44 wire _out_uop_WIRE_45 : { valid : UInt<1>, bits : UInt<40>} node _out_uop_T_553 = mux(_out_uop_T, ram[0].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_554 = mux(_out_uop_T_1, ram[1].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_555 = mux(_out_uop_T_2, ram[2].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_556 = mux(_out_uop_T_3, ram[3].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_557 = mux(_out_uop_T_4, ram[4].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_558 = mux(_out_uop_T_5, ram[5].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_559 = mux(_out_uop_T_6, ram[6].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_560 = or(_out_uop_T_553, _out_uop_T_554) node _out_uop_T_561 = or(_out_uop_T_560, _out_uop_T_555) node _out_uop_T_562 = or(_out_uop_T_561, _out_uop_T_556) node _out_uop_T_563 = or(_out_uop_T_562, _out_uop_T_557) node _out_uop_T_564 = or(_out_uop_T_563, _out_uop_T_558) node _out_uop_T_565 = or(_out_uop_T_564, _out_uop_T_559) wire _out_uop_WIRE_46 : UInt<40> connect _out_uop_WIRE_46, _out_uop_T_565 connect _out_uop_WIRE_45.bits, _out_uop_WIRE_46 node _out_uop_T_566 = mux(_out_uop_T, ram[0].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_567 = mux(_out_uop_T_1, ram[1].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_568 = mux(_out_uop_T_2, ram[2].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_569 = mux(_out_uop_T_3, ram[3].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_570 = mux(_out_uop_T_4, ram[4].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_571 = mux(_out_uop_T_5, ram[5].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_572 = mux(_out_uop_T_6, ram[6].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_573 = or(_out_uop_T_566, _out_uop_T_567) node _out_uop_T_574 = or(_out_uop_T_573, _out_uop_T_568) node _out_uop_T_575 = or(_out_uop_T_574, _out_uop_T_569) node _out_uop_T_576 = or(_out_uop_T_575, _out_uop_T_570) node _out_uop_T_577 = or(_out_uop_T_576, _out_uop_T_571) node _out_uop_T_578 = or(_out_uop_T_577, _out_uop_T_572) wire _out_uop_WIRE_47 : UInt<1> connect _out_uop_WIRE_47, _out_uop_T_578 connect _out_uop_WIRE_45.valid, _out_uop_WIRE_47 connect _out_uop_WIRE.next_pc, _out_uop_WIRE_45 node _out_uop_T_579 = mux(_out_uop_T, ram[0].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_580 = mux(_out_uop_T_1, ram[1].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_581 = mux(_out_uop_T_2, ram[2].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_582 = mux(_out_uop_T_3, ram[3].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_583 = mux(_out_uop_T_4, ram[4].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_584 = mux(_out_uop_T_5, ram[5].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_585 = mux(_out_uop_T_6, ram[6].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_586 = or(_out_uop_T_579, _out_uop_T_580) node _out_uop_T_587 = or(_out_uop_T_586, _out_uop_T_581) node _out_uop_T_588 = or(_out_uop_T_587, _out_uop_T_582) node _out_uop_T_589 = or(_out_uop_T_588, _out_uop_T_583) node _out_uop_T_590 = or(_out_uop_T_589, _out_uop_T_584) node _out_uop_T_591 = or(_out_uop_T_590, _out_uop_T_585) wire _out_uop_WIRE_48 : UInt<1> connect _out_uop_WIRE_48, _out_uop_T_591 connect _out_uop_WIRE.sfb_shadow, _out_uop_WIRE_48 node _out_uop_T_592 = mux(_out_uop_T, ram[0].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_593 = mux(_out_uop_T_1, ram[1].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_594 = mux(_out_uop_T_2, ram[2].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_595 = mux(_out_uop_T_3, ram[3].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_596 = mux(_out_uop_T_4, ram[4].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_597 = mux(_out_uop_T_5, ram[5].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_598 = mux(_out_uop_T_6, ram[6].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_599 = or(_out_uop_T_592, _out_uop_T_593) node _out_uop_T_600 = or(_out_uop_T_599, _out_uop_T_594) node _out_uop_T_601 = or(_out_uop_T_600, _out_uop_T_595) node _out_uop_T_602 = or(_out_uop_T_601, _out_uop_T_596) node _out_uop_T_603 = or(_out_uop_T_602, _out_uop_T_597) node _out_uop_T_604 = or(_out_uop_T_603, _out_uop_T_598) wire _out_uop_WIRE_49 : UInt<1> connect _out_uop_WIRE_49, _out_uop_T_604 connect _out_uop_WIRE.sfb_br, _out_uop_WIRE_49 wire _out_uop_WIRE_50 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _out_uop_WIRE_51 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _out_uop_WIRE_52 : { history : UInt<8>, value : UInt<2>} node _out_uop_T_605 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_606 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_607 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_608 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_609 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_610 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_611 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_612 = or(_out_uop_T_605, _out_uop_T_606) node _out_uop_T_613 = or(_out_uop_T_612, _out_uop_T_607) node _out_uop_T_614 = or(_out_uop_T_613, _out_uop_T_608) node _out_uop_T_615 = or(_out_uop_T_614, _out_uop_T_609) node _out_uop_T_616 = or(_out_uop_T_615, _out_uop_T_610) node _out_uop_T_617 = or(_out_uop_T_616, _out_uop_T_611) wire _out_uop_WIRE_53 : UInt<2> connect _out_uop_WIRE_53, _out_uop_T_617 connect _out_uop_WIRE_52.value, _out_uop_WIRE_53 node _out_uop_T_618 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_619 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_620 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_621 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_622 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_623 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_624 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_625 = or(_out_uop_T_618, _out_uop_T_619) node _out_uop_T_626 = or(_out_uop_T_625, _out_uop_T_620) node _out_uop_T_627 = or(_out_uop_T_626, _out_uop_T_621) node _out_uop_T_628 = or(_out_uop_T_627, _out_uop_T_622) node _out_uop_T_629 = or(_out_uop_T_628, _out_uop_T_623) node _out_uop_T_630 = or(_out_uop_T_629, _out_uop_T_624) wire _out_uop_WIRE_54 : UInt<8> connect _out_uop_WIRE_54, _out_uop_T_630 connect _out_uop_WIRE_52.history, _out_uop_WIRE_54 connect _out_uop_WIRE_51.bht, _out_uop_WIRE_52 node _out_uop_T_631 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_632 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_633 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_634 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_635 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_636 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_637 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_638 = or(_out_uop_T_631, _out_uop_T_632) node _out_uop_T_639 = or(_out_uop_T_638, _out_uop_T_633) node _out_uop_T_640 = or(_out_uop_T_639, _out_uop_T_634) node _out_uop_T_641 = or(_out_uop_T_640, _out_uop_T_635) node _out_uop_T_642 = or(_out_uop_T_641, _out_uop_T_636) node _out_uop_T_643 = or(_out_uop_T_642, _out_uop_T_637) wire _out_uop_WIRE_55 : UInt<6> connect _out_uop_WIRE_55, _out_uop_T_643 connect _out_uop_WIRE_51.entry, _out_uop_WIRE_55 node _out_uop_T_644 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_645 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_646 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_647 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_648 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_649 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_650 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_651 = or(_out_uop_T_644, _out_uop_T_645) node _out_uop_T_652 = or(_out_uop_T_651, _out_uop_T_646) node _out_uop_T_653 = or(_out_uop_T_652, _out_uop_T_647) node _out_uop_T_654 = or(_out_uop_T_653, _out_uop_T_648) node _out_uop_T_655 = or(_out_uop_T_654, _out_uop_T_649) node _out_uop_T_656 = or(_out_uop_T_655, _out_uop_T_650) wire _out_uop_WIRE_56 : UInt<39> connect _out_uop_WIRE_56, _out_uop_T_656 connect _out_uop_WIRE_51.target, _out_uop_WIRE_56 node _out_uop_T_657 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_658 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_659 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_660 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_661 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_662 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_663 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_664 = or(_out_uop_T_657, _out_uop_T_658) node _out_uop_T_665 = or(_out_uop_T_664, _out_uop_T_659) node _out_uop_T_666 = or(_out_uop_T_665, _out_uop_T_660) node _out_uop_T_667 = or(_out_uop_T_666, _out_uop_T_661) node _out_uop_T_668 = or(_out_uop_T_667, _out_uop_T_662) node _out_uop_T_669 = or(_out_uop_T_668, _out_uop_T_663) wire _out_uop_WIRE_57 : UInt<2> connect _out_uop_WIRE_57, _out_uop_T_669 connect _out_uop_WIRE_51.bridx, _out_uop_WIRE_57 node _out_uop_T_670 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_671 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_672 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_673 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_674 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_675 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_676 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_677 = or(_out_uop_T_670, _out_uop_T_671) node _out_uop_T_678 = or(_out_uop_T_677, _out_uop_T_672) node _out_uop_T_679 = or(_out_uop_T_678, _out_uop_T_673) node _out_uop_T_680 = or(_out_uop_T_679, _out_uop_T_674) node _out_uop_T_681 = or(_out_uop_T_680, _out_uop_T_675) node _out_uop_T_682 = or(_out_uop_T_681, _out_uop_T_676) wire _out_uop_WIRE_58 : UInt<4> connect _out_uop_WIRE_58, _out_uop_T_682 connect _out_uop_WIRE_51.mask, _out_uop_WIRE_58 node _out_uop_T_683 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_684 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_685 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_686 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_687 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_688 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_689 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_690 = or(_out_uop_T_683, _out_uop_T_684) node _out_uop_T_691 = or(_out_uop_T_690, _out_uop_T_685) node _out_uop_T_692 = or(_out_uop_T_691, _out_uop_T_686) node _out_uop_T_693 = or(_out_uop_T_692, _out_uop_T_687) node _out_uop_T_694 = or(_out_uop_T_693, _out_uop_T_688) node _out_uop_T_695 = or(_out_uop_T_694, _out_uop_T_689) wire _out_uop_WIRE_59 : UInt<1> connect _out_uop_WIRE_59, _out_uop_T_695 connect _out_uop_WIRE_51.taken, _out_uop_WIRE_59 node _out_uop_T_696 = mux(_out_uop_T, ram[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_697 = mux(_out_uop_T_1, ram[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_698 = mux(_out_uop_T_2, ram[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_699 = mux(_out_uop_T_3, ram[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_700 = mux(_out_uop_T_4, ram[4].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_701 = mux(_out_uop_T_5, ram[5].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_702 = mux(_out_uop_T_6, ram[6].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_703 = or(_out_uop_T_696, _out_uop_T_697) node _out_uop_T_704 = or(_out_uop_T_703, _out_uop_T_698) node _out_uop_T_705 = or(_out_uop_T_704, _out_uop_T_699) node _out_uop_T_706 = or(_out_uop_T_705, _out_uop_T_700) node _out_uop_T_707 = or(_out_uop_T_706, _out_uop_T_701) node _out_uop_T_708 = or(_out_uop_T_707, _out_uop_T_702) wire _out_uop_WIRE_60 : UInt<2> connect _out_uop_WIRE_60, _out_uop_T_708 connect _out_uop_WIRE_51.cfiType, _out_uop_WIRE_60 connect _out_uop_WIRE_50.bits, _out_uop_WIRE_51 node _out_uop_T_709 = mux(_out_uop_T, ram[0].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_710 = mux(_out_uop_T_1, ram[1].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_711 = mux(_out_uop_T_2, ram[2].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_712 = mux(_out_uop_T_3, ram[3].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_713 = mux(_out_uop_T_4, ram[4].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_714 = mux(_out_uop_T_5, ram[5].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_715 = mux(_out_uop_T_6, ram[6].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_716 = or(_out_uop_T_709, _out_uop_T_710) node _out_uop_T_717 = or(_out_uop_T_716, _out_uop_T_711) node _out_uop_T_718 = or(_out_uop_T_717, _out_uop_T_712) node _out_uop_T_719 = or(_out_uop_T_718, _out_uop_T_713) node _out_uop_T_720 = or(_out_uop_T_719, _out_uop_T_714) node _out_uop_T_721 = or(_out_uop_T_720, _out_uop_T_715) wire _out_uop_WIRE_61 : UInt<1> connect _out_uop_WIRE_61, _out_uop_T_721 connect _out_uop_WIRE_50.valid, _out_uop_WIRE_61 connect _out_uop_WIRE.btb_resp, _out_uop_WIRE_50 node _out_uop_T_722 = mux(_out_uop_T, ram[0].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_723 = mux(_out_uop_T_1, ram[1].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_724 = mux(_out_uop_T_2, ram[2].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_725 = mux(_out_uop_T_3, ram[3].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_726 = mux(_out_uop_T_4, ram[4].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_727 = mux(_out_uop_T_5, ram[5].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_728 = mux(_out_uop_T_6, ram[6].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_729 = or(_out_uop_T_722, _out_uop_T_723) node _out_uop_T_730 = or(_out_uop_T_729, _out_uop_T_724) node _out_uop_T_731 = or(_out_uop_T_730, _out_uop_T_725) node _out_uop_T_732 = or(_out_uop_T_731, _out_uop_T_726) node _out_uop_T_733 = or(_out_uop_T_732, _out_uop_T_727) node _out_uop_T_734 = or(_out_uop_T_733, _out_uop_T_728) wire _out_uop_WIRE_62 : UInt<1> connect _out_uop_WIRE_62, _out_uop_T_734 connect _out_uop_WIRE.sets_vcfg, _out_uop_WIRE_62 node _out_uop_T_735 = mux(_out_uop_T, ram[0].bits.rvc, UInt<1>(0h0)) node _out_uop_T_736 = mux(_out_uop_T_1, ram[1].bits.rvc, UInt<1>(0h0)) node _out_uop_T_737 = mux(_out_uop_T_2, ram[2].bits.rvc, UInt<1>(0h0)) node _out_uop_T_738 = mux(_out_uop_T_3, ram[3].bits.rvc, UInt<1>(0h0)) node _out_uop_T_739 = mux(_out_uop_T_4, ram[4].bits.rvc, UInt<1>(0h0)) node _out_uop_T_740 = mux(_out_uop_T_5, ram[5].bits.rvc, UInt<1>(0h0)) node _out_uop_T_741 = mux(_out_uop_T_6, ram[6].bits.rvc, UInt<1>(0h0)) node _out_uop_T_742 = or(_out_uop_T_735, _out_uop_T_736) node _out_uop_T_743 = or(_out_uop_T_742, _out_uop_T_737) node _out_uop_T_744 = or(_out_uop_T_743, _out_uop_T_738) node _out_uop_T_745 = or(_out_uop_T_744, _out_uop_T_739) node _out_uop_T_746 = or(_out_uop_T_745, _out_uop_T_740) node _out_uop_T_747 = or(_out_uop_T_746, _out_uop_T_741) wire _out_uop_WIRE_63 : UInt<1> connect _out_uop_WIRE_63, _out_uop_T_747 connect _out_uop_WIRE.rvc, _out_uop_WIRE_63 wire _out_uop_WIRE_64 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _out_uop_T_748 = mux(_out_uop_T, ram[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_749 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_750 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_751 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_752 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_753 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_754 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_755 = or(_out_uop_T_748, _out_uop_T_749) node _out_uop_T_756 = or(_out_uop_T_755, _out_uop_T_750) node _out_uop_T_757 = or(_out_uop_T_756, _out_uop_T_751) node _out_uop_T_758 = or(_out_uop_T_757, _out_uop_T_752) node _out_uop_T_759 = or(_out_uop_T_758, _out_uop_T_753) node _out_uop_T_760 = or(_out_uop_T_759, _out_uop_T_754) wire _out_uop_WIRE_65 : UInt<1> connect _out_uop_WIRE_65, _out_uop_T_760 connect _out_uop_WIRE_64.vec, _out_uop_WIRE_65 node _out_uop_T_761 = mux(_out_uop_T, ram[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_762 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_763 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_764 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_765 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_766 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_767 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_768 = or(_out_uop_T_761, _out_uop_T_762) node _out_uop_T_769 = or(_out_uop_T_768, _out_uop_T_763) node _out_uop_T_770 = or(_out_uop_T_769, _out_uop_T_764) node _out_uop_T_771 = or(_out_uop_T_770, _out_uop_T_765) node _out_uop_T_772 = or(_out_uop_T_771, _out_uop_T_766) node _out_uop_T_773 = or(_out_uop_T_772, _out_uop_T_767) wire _out_uop_WIRE_66 : UInt<1> connect _out_uop_WIRE_66, _out_uop_T_773 connect _out_uop_WIRE_64.wflags, _out_uop_WIRE_66 node _out_uop_T_774 = mux(_out_uop_T, ram[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_775 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_776 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_777 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_778 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_779 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_780 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_781 = or(_out_uop_T_774, _out_uop_T_775) node _out_uop_T_782 = or(_out_uop_T_781, _out_uop_T_776) node _out_uop_T_783 = or(_out_uop_T_782, _out_uop_T_777) node _out_uop_T_784 = or(_out_uop_T_783, _out_uop_T_778) node _out_uop_T_785 = or(_out_uop_T_784, _out_uop_T_779) node _out_uop_T_786 = or(_out_uop_T_785, _out_uop_T_780) wire _out_uop_WIRE_67 : UInt<1> connect _out_uop_WIRE_67, _out_uop_T_786 connect _out_uop_WIRE_64.sqrt, _out_uop_WIRE_67 node _out_uop_T_787 = mux(_out_uop_T, ram[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_788 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_789 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_790 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_791 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_792 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_793 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_794 = or(_out_uop_T_787, _out_uop_T_788) node _out_uop_T_795 = or(_out_uop_T_794, _out_uop_T_789) node _out_uop_T_796 = or(_out_uop_T_795, _out_uop_T_790) node _out_uop_T_797 = or(_out_uop_T_796, _out_uop_T_791) node _out_uop_T_798 = or(_out_uop_T_797, _out_uop_T_792) node _out_uop_T_799 = or(_out_uop_T_798, _out_uop_T_793) wire _out_uop_WIRE_68 : UInt<1> connect _out_uop_WIRE_68, _out_uop_T_799 connect _out_uop_WIRE_64.div, _out_uop_WIRE_68 node _out_uop_T_800 = mux(_out_uop_T, ram[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_801 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_802 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_803 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_804 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_805 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_806 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_807 = or(_out_uop_T_800, _out_uop_T_801) node _out_uop_T_808 = or(_out_uop_T_807, _out_uop_T_802) node _out_uop_T_809 = or(_out_uop_T_808, _out_uop_T_803) node _out_uop_T_810 = or(_out_uop_T_809, _out_uop_T_804) node _out_uop_T_811 = or(_out_uop_T_810, _out_uop_T_805) node _out_uop_T_812 = or(_out_uop_T_811, _out_uop_T_806) wire _out_uop_WIRE_69 : UInt<1> connect _out_uop_WIRE_69, _out_uop_T_812 connect _out_uop_WIRE_64.fma, _out_uop_WIRE_69 node _out_uop_T_813 = mux(_out_uop_T, ram[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_814 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_815 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_816 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_817 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_818 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_819 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_820 = or(_out_uop_T_813, _out_uop_T_814) node _out_uop_T_821 = or(_out_uop_T_820, _out_uop_T_815) node _out_uop_T_822 = or(_out_uop_T_821, _out_uop_T_816) node _out_uop_T_823 = or(_out_uop_T_822, _out_uop_T_817) node _out_uop_T_824 = or(_out_uop_T_823, _out_uop_T_818) node _out_uop_T_825 = or(_out_uop_T_824, _out_uop_T_819) wire _out_uop_WIRE_70 : UInt<1> connect _out_uop_WIRE_70, _out_uop_T_825 connect _out_uop_WIRE_64.fastpipe, _out_uop_WIRE_70 node _out_uop_T_826 = mux(_out_uop_T, ram[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_827 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_828 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_829 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_830 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_831 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_832 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_833 = or(_out_uop_T_826, _out_uop_T_827) node _out_uop_T_834 = or(_out_uop_T_833, _out_uop_T_828) node _out_uop_T_835 = or(_out_uop_T_834, _out_uop_T_829) node _out_uop_T_836 = or(_out_uop_T_835, _out_uop_T_830) node _out_uop_T_837 = or(_out_uop_T_836, _out_uop_T_831) node _out_uop_T_838 = or(_out_uop_T_837, _out_uop_T_832) wire _out_uop_WIRE_71 : UInt<1> connect _out_uop_WIRE_71, _out_uop_T_838 connect _out_uop_WIRE_64.toint, _out_uop_WIRE_71 node _out_uop_T_839 = mux(_out_uop_T, ram[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_840 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_841 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_842 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_843 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_844 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_845 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_846 = or(_out_uop_T_839, _out_uop_T_840) node _out_uop_T_847 = or(_out_uop_T_846, _out_uop_T_841) node _out_uop_T_848 = or(_out_uop_T_847, _out_uop_T_842) node _out_uop_T_849 = or(_out_uop_T_848, _out_uop_T_843) node _out_uop_T_850 = or(_out_uop_T_849, _out_uop_T_844) node _out_uop_T_851 = or(_out_uop_T_850, _out_uop_T_845) wire _out_uop_WIRE_72 : UInt<1> connect _out_uop_WIRE_72, _out_uop_T_851 connect _out_uop_WIRE_64.fromint, _out_uop_WIRE_72 node _out_uop_T_852 = mux(_out_uop_T, ram[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_853 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_854 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_855 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_856 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_857 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_858 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_859 = or(_out_uop_T_852, _out_uop_T_853) node _out_uop_T_860 = or(_out_uop_T_859, _out_uop_T_854) node _out_uop_T_861 = or(_out_uop_T_860, _out_uop_T_855) node _out_uop_T_862 = or(_out_uop_T_861, _out_uop_T_856) node _out_uop_T_863 = or(_out_uop_T_862, _out_uop_T_857) node _out_uop_T_864 = or(_out_uop_T_863, _out_uop_T_858) wire _out_uop_WIRE_73 : UInt<2> connect _out_uop_WIRE_73, _out_uop_T_864 connect _out_uop_WIRE_64.typeTagOut, _out_uop_WIRE_73 node _out_uop_T_865 = mux(_out_uop_T, ram[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_866 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_867 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_868 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_869 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_870 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_871 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_872 = or(_out_uop_T_865, _out_uop_T_866) node _out_uop_T_873 = or(_out_uop_T_872, _out_uop_T_867) node _out_uop_T_874 = or(_out_uop_T_873, _out_uop_T_868) node _out_uop_T_875 = or(_out_uop_T_874, _out_uop_T_869) node _out_uop_T_876 = or(_out_uop_T_875, _out_uop_T_870) node _out_uop_T_877 = or(_out_uop_T_876, _out_uop_T_871) wire _out_uop_WIRE_74 : UInt<2> connect _out_uop_WIRE_74, _out_uop_T_877 connect _out_uop_WIRE_64.typeTagIn, _out_uop_WIRE_74 node _out_uop_T_878 = mux(_out_uop_T, ram[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_879 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_880 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_881 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_882 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_883 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_884 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_885 = or(_out_uop_T_878, _out_uop_T_879) node _out_uop_T_886 = or(_out_uop_T_885, _out_uop_T_880) node _out_uop_T_887 = or(_out_uop_T_886, _out_uop_T_881) node _out_uop_T_888 = or(_out_uop_T_887, _out_uop_T_882) node _out_uop_T_889 = or(_out_uop_T_888, _out_uop_T_883) node _out_uop_T_890 = or(_out_uop_T_889, _out_uop_T_884) wire _out_uop_WIRE_75 : UInt<1> connect _out_uop_WIRE_75, _out_uop_T_890 connect _out_uop_WIRE_64.swap23, _out_uop_WIRE_75 node _out_uop_T_891 = mux(_out_uop_T, ram[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_892 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_893 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_894 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_895 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_896 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_897 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_898 = or(_out_uop_T_891, _out_uop_T_892) node _out_uop_T_899 = or(_out_uop_T_898, _out_uop_T_893) node _out_uop_T_900 = or(_out_uop_T_899, _out_uop_T_894) node _out_uop_T_901 = or(_out_uop_T_900, _out_uop_T_895) node _out_uop_T_902 = or(_out_uop_T_901, _out_uop_T_896) node _out_uop_T_903 = or(_out_uop_T_902, _out_uop_T_897) wire _out_uop_WIRE_76 : UInt<1> connect _out_uop_WIRE_76, _out_uop_T_903 connect _out_uop_WIRE_64.swap12, _out_uop_WIRE_76 node _out_uop_T_904 = mux(_out_uop_T, ram[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_905 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_906 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_907 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_908 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_909 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_910 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_911 = or(_out_uop_T_904, _out_uop_T_905) node _out_uop_T_912 = or(_out_uop_T_911, _out_uop_T_906) node _out_uop_T_913 = or(_out_uop_T_912, _out_uop_T_907) node _out_uop_T_914 = or(_out_uop_T_913, _out_uop_T_908) node _out_uop_T_915 = or(_out_uop_T_914, _out_uop_T_909) node _out_uop_T_916 = or(_out_uop_T_915, _out_uop_T_910) wire _out_uop_WIRE_77 : UInt<1> connect _out_uop_WIRE_77, _out_uop_T_916 connect _out_uop_WIRE_64.ren3, _out_uop_WIRE_77 node _out_uop_T_917 = mux(_out_uop_T, ram[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_918 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_919 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_920 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_921 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_922 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_923 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_924 = or(_out_uop_T_917, _out_uop_T_918) node _out_uop_T_925 = or(_out_uop_T_924, _out_uop_T_919) node _out_uop_T_926 = or(_out_uop_T_925, _out_uop_T_920) node _out_uop_T_927 = or(_out_uop_T_926, _out_uop_T_921) node _out_uop_T_928 = or(_out_uop_T_927, _out_uop_T_922) node _out_uop_T_929 = or(_out_uop_T_928, _out_uop_T_923) wire _out_uop_WIRE_78 : UInt<1> connect _out_uop_WIRE_78, _out_uop_T_929 connect _out_uop_WIRE_64.ren2, _out_uop_WIRE_78 node _out_uop_T_930 = mux(_out_uop_T, ram[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_931 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_932 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_933 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_934 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_935 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_936 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_937 = or(_out_uop_T_930, _out_uop_T_931) node _out_uop_T_938 = or(_out_uop_T_937, _out_uop_T_932) node _out_uop_T_939 = or(_out_uop_T_938, _out_uop_T_933) node _out_uop_T_940 = or(_out_uop_T_939, _out_uop_T_934) node _out_uop_T_941 = or(_out_uop_T_940, _out_uop_T_935) node _out_uop_T_942 = or(_out_uop_T_941, _out_uop_T_936) wire _out_uop_WIRE_79 : UInt<1> connect _out_uop_WIRE_79, _out_uop_T_942 connect _out_uop_WIRE_64.ren1, _out_uop_WIRE_79 node _out_uop_T_943 = mux(_out_uop_T, ram[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_944 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_945 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_946 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_947 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_948 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_949 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_950 = or(_out_uop_T_943, _out_uop_T_944) node _out_uop_T_951 = or(_out_uop_T_950, _out_uop_T_945) node _out_uop_T_952 = or(_out_uop_T_951, _out_uop_T_946) node _out_uop_T_953 = or(_out_uop_T_952, _out_uop_T_947) node _out_uop_T_954 = or(_out_uop_T_953, _out_uop_T_948) node _out_uop_T_955 = or(_out_uop_T_954, _out_uop_T_949) wire _out_uop_WIRE_80 : UInt<1> connect _out_uop_WIRE_80, _out_uop_T_955 connect _out_uop_WIRE_64.wen, _out_uop_WIRE_80 node _out_uop_T_956 = mux(_out_uop_T, ram[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_957 = mux(_out_uop_T_1, ram[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_958 = mux(_out_uop_T_2, ram[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_959 = mux(_out_uop_T_3, ram[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_960 = mux(_out_uop_T_4, ram[4].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_961 = mux(_out_uop_T_5, ram[5].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_962 = mux(_out_uop_T_6, ram[6].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_963 = or(_out_uop_T_956, _out_uop_T_957) node _out_uop_T_964 = or(_out_uop_T_963, _out_uop_T_958) node _out_uop_T_965 = or(_out_uop_T_964, _out_uop_T_959) node _out_uop_T_966 = or(_out_uop_T_965, _out_uop_T_960) node _out_uop_T_967 = or(_out_uop_T_966, _out_uop_T_961) node _out_uop_T_968 = or(_out_uop_T_967, _out_uop_T_962) wire _out_uop_WIRE_81 : UInt<1> connect _out_uop_WIRE_81, _out_uop_T_968 connect _out_uop_WIRE_64.ldst, _out_uop_WIRE_81 connect _out_uop_WIRE.fp_ctrl, _out_uop_WIRE_64 wire _out_uop_WIRE_82 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _out_uop_T_969 = mux(_out_uop_T, ram[0].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_970 = mux(_out_uop_T_1, ram[1].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_971 = mux(_out_uop_T_2, ram[2].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_972 = mux(_out_uop_T_3, ram[3].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_973 = mux(_out_uop_T_4, ram[4].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_974 = mux(_out_uop_T_5, ram[5].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_975 = mux(_out_uop_T_6, ram[6].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_976 = or(_out_uop_T_969, _out_uop_T_970) node _out_uop_T_977 = or(_out_uop_T_976, _out_uop_T_971) node _out_uop_T_978 = or(_out_uop_T_977, _out_uop_T_972) node _out_uop_T_979 = or(_out_uop_T_978, _out_uop_T_973) node _out_uop_T_980 = or(_out_uop_T_979, _out_uop_T_974) node _out_uop_T_981 = or(_out_uop_T_980, _out_uop_T_975) wire _out_uop_WIRE_83 : UInt<1> connect _out_uop_WIRE_83, _out_uop_T_981 connect _out_uop_WIRE_82.vec, _out_uop_WIRE_83 node _out_uop_T_982 = mux(_out_uop_T, ram[0].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_983 = mux(_out_uop_T_1, ram[1].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_984 = mux(_out_uop_T_2, ram[2].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_985 = mux(_out_uop_T_3, ram[3].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_986 = mux(_out_uop_T_4, ram[4].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_987 = mux(_out_uop_T_5, ram[5].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_988 = mux(_out_uop_T_6, ram[6].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_989 = or(_out_uop_T_982, _out_uop_T_983) node _out_uop_T_990 = or(_out_uop_T_989, _out_uop_T_984) node _out_uop_T_991 = or(_out_uop_T_990, _out_uop_T_985) node _out_uop_T_992 = or(_out_uop_T_991, _out_uop_T_986) node _out_uop_T_993 = or(_out_uop_T_992, _out_uop_T_987) node _out_uop_T_994 = or(_out_uop_T_993, _out_uop_T_988) wire _out_uop_WIRE_84 : UInt<1> connect _out_uop_WIRE_84, _out_uop_T_994 connect _out_uop_WIRE_82.dp, _out_uop_WIRE_84 node _out_uop_T_995 = mux(_out_uop_T, ram[0].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_996 = mux(_out_uop_T_1, ram[1].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_997 = mux(_out_uop_T_2, ram[2].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_998 = mux(_out_uop_T_3, ram[3].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_999 = mux(_out_uop_T_4, ram[4].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_1000 = mux(_out_uop_T_5, ram[5].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_1001 = mux(_out_uop_T_6, ram[6].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_1002 = or(_out_uop_T_995, _out_uop_T_996) node _out_uop_T_1003 = or(_out_uop_T_1002, _out_uop_T_997) node _out_uop_T_1004 = or(_out_uop_T_1003, _out_uop_T_998) node _out_uop_T_1005 = or(_out_uop_T_1004, _out_uop_T_999) node _out_uop_T_1006 = or(_out_uop_T_1005, _out_uop_T_1000) node _out_uop_T_1007 = or(_out_uop_T_1006, _out_uop_T_1001) wire _out_uop_WIRE_85 : UInt<1> connect _out_uop_WIRE_85, _out_uop_T_1007 connect _out_uop_WIRE_82.amo, _out_uop_WIRE_85 node _out_uop_T_1008 = mux(_out_uop_T, ram[0].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1009 = mux(_out_uop_T_1, ram[1].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1010 = mux(_out_uop_T_2, ram[2].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1011 = mux(_out_uop_T_3, ram[3].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1012 = mux(_out_uop_T_4, ram[4].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1013 = mux(_out_uop_T_5, ram[5].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1014 = mux(_out_uop_T_6, ram[6].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_1015 = or(_out_uop_T_1008, _out_uop_T_1009) node _out_uop_T_1016 = or(_out_uop_T_1015, _out_uop_T_1010) node _out_uop_T_1017 = or(_out_uop_T_1016, _out_uop_T_1011) node _out_uop_T_1018 = or(_out_uop_T_1017, _out_uop_T_1012) node _out_uop_T_1019 = or(_out_uop_T_1018, _out_uop_T_1013) node _out_uop_T_1020 = or(_out_uop_T_1019, _out_uop_T_1014) wire _out_uop_WIRE_86 : UInt<1> connect _out_uop_WIRE_86, _out_uop_T_1020 connect _out_uop_WIRE_82.fence, _out_uop_WIRE_86 node _out_uop_T_1021 = mux(_out_uop_T, ram[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1022 = mux(_out_uop_T_1, ram[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1023 = mux(_out_uop_T_2, ram[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1024 = mux(_out_uop_T_3, ram[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1025 = mux(_out_uop_T_4, ram[4].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1026 = mux(_out_uop_T_5, ram[5].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1027 = mux(_out_uop_T_6, ram[6].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_1028 = or(_out_uop_T_1021, _out_uop_T_1022) node _out_uop_T_1029 = or(_out_uop_T_1028, _out_uop_T_1023) node _out_uop_T_1030 = or(_out_uop_T_1029, _out_uop_T_1024) node _out_uop_T_1031 = or(_out_uop_T_1030, _out_uop_T_1025) node _out_uop_T_1032 = or(_out_uop_T_1031, _out_uop_T_1026) node _out_uop_T_1033 = or(_out_uop_T_1032, _out_uop_T_1027) wire _out_uop_WIRE_87 : UInt<1> connect _out_uop_WIRE_87, _out_uop_T_1033 connect _out_uop_WIRE_82.fence_i, _out_uop_WIRE_87 node _out_uop_T_1034 = mux(_out_uop_T, ram[0].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1035 = mux(_out_uop_T_1, ram[1].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1036 = mux(_out_uop_T_2, ram[2].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1037 = mux(_out_uop_T_3, ram[3].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1038 = mux(_out_uop_T_4, ram[4].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1039 = mux(_out_uop_T_5, ram[5].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1040 = mux(_out_uop_T_6, ram[6].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_1041 = or(_out_uop_T_1034, _out_uop_T_1035) node _out_uop_T_1042 = or(_out_uop_T_1041, _out_uop_T_1036) node _out_uop_T_1043 = or(_out_uop_T_1042, _out_uop_T_1037) node _out_uop_T_1044 = or(_out_uop_T_1043, _out_uop_T_1038) node _out_uop_T_1045 = or(_out_uop_T_1044, _out_uop_T_1039) node _out_uop_T_1046 = or(_out_uop_T_1045, _out_uop_T_1040) wire _out_uop_WIRE_88 : UInt<3> connect _out_uop_WIRE_88, _out_uop_T_1046 connect _out_uop_WIRE_82.csr, _out_uop_WIRE_88 node _out_uop_T_1047 = mux(_out_uop_T, ram[0].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1048 = mux(_out_uop_T_1, ram[1].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1049 = mux(_out_uop_T_2, ram[2].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1050 = mux(_out_uop_T_3, ram[3].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1051 = mux(_out_uop_T_4, ram[4].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1052 = mux(_out_uop_T_5, ram[5].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1053 = mux(_out_uop_T_6, ram[6].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_1054 = or(_out_uop_T_1047, _out_uop_T_1048) node _out_uop_T_1055 = or(_out_uop_T_1054, _out_uop_T_1049) node _out_uop_T_1056 = or(_out_uop_T_1055, _out_uop_T_1050) node _out_uop_T_1057 = or(_out_uop_T_1056, _out_uop_T_1051) node _out_uop_T_1058 = or(_out_uop_T_1057, _out_uop_T_1052) node _out_uop_T_1059 = or(_out_uop_T_1058, _out_uop_T_1053) wire _out_uop_WIRE_89 : UInt<1> connect _out_uop_WIRE_89, _out_uop_T_1059 connect _out_uop_WIRE_82.wxd, _out_uop_WIRE_89 node _out_uop_T_1060 = mux(_out_uop_T, ram[0].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1061 = mux(_out_uop_T_1, ram[1].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1062 = mux(_out_uop_T_2, ram[2].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1063 = mux(_out_uop_T_3, ram[3].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1064 = mux(_out_uop_T_4, ram[4].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1065 = mux(_out_uop_T_5, ram[5].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1066 = mux(_out_uop_T_6, ram[6].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_1067 = or(_out_uop_T_1060, _out_uop_T_1061) node _out_uop_T_1068 = or(_out_uop_T_1067, _out_uop_T_1062) node _out_uop_T_1069 = or(_out_uop_T_1068, _out_uop_T_1063) node _out_uop_T_1070 = or(_out_uop_T_1069, _out_uop_T_1064) node _out_uop_T_1071 = or(_out_uop_T_1070, _out_uop_T_1065) node _out_uop_T_1072 = or(_out_uop_T_1071, _out_uop_T_1066) wire _out_uop_WIRE_90 : UInt<1> connect _out_uop_WIRE_90, _out_uop_T_1072 connect _out_uop_WIRE_82.div, _out_uop_WIRE_90 node _out_uop_T_1073 = mux(_out_uop_T, ram[0].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1074 = mux(_out_uop_T_1, ram[1].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1075 = mux(_out_uop_T_2, ram[2].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1076 = mux(_out_uop_T_3, ram[3].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1077 = mux(_out_uop_T_4, ram[4].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1078 = mux(_out_uop_T_5, ram[5].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1079 = mux(_out_uop_T_6, ram[6].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_1080 = or(_out_uop_T_1073, _out_uop_T_1074) node _out_uop_T_1081 = or(_out_uop_T_1080, _out_uop_T_1075) node _out_uop_T_1082 = or(_out_uop_T_1081, _out_uop_T_1076) node _out_uop_T_1083 = or(_out_uop_T_1082, _out_uop_T_1077) node _out_uop_T_1084 = or(_out_uop_T_1083, _out_uop_T_1078) node _out_uop_T_1085 = or(_out_uop_T_1084, _out_uop_T_1079) wire _out_uop_WIRE_91 : UInt<1> connect _out_uop_WIRE_91, _out_uop_T_1085 connect _out_uop_WIRE_82.mul, _out_uop_WIRE_91 node _out_uop_T_1086 = mux(_out_uop_T, ram[0].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1087 = mux(_out_uop_T_1, ram[1].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1088 = mux(_out_uop_T_2, ram[2].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1089 = mux(_out_uop_T_3, ram[3].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1090 = mux(_out_uop_T_4, ram[4].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1091 = mux(_out_uop_T_5, ram[5].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1092 = mux(_out_uop_T_6, ram[6].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_1093 = or(_out_uop_T_1086, _out_uop_T_1087) node _out_uop_T_1094 = or(_out_uop_T_1093, _out_uop_T_1088) node _out_uop_T_1095 = or(_out_uop_T_1094, _out_uop_T_1089) node _out_uop_T_1096 = or(_out_uop_T_1095, _out_uop_T_1090) node _out_uop_T_1097 = or(_out_uop_T_1096, _out_uop_T_1091) node _out_uop_T_1098 = or(_out_uop_T_1097, _out_uop_T_1092) wire _out_uop_WIRE_92 : UInt<1> connect _out_uop_WIRE_92, _out_uop_T_1098 connect _out_uop_WIRE_82.wfd, _out_uop_WIRE_92 node _out_uop_T_1099 = mux(_out_uop_T, ram[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1100 = mux(_out_uop_T_1, ram[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1101 = mux(_out_uop_T_2, ram[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1102 = mux(_out_uop_T_3, ram[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1103 = mux(_out_uop_T_4, ram[4].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1104 = mux(_out_uop_T_5, ram[5].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1105 = mux(_out_uop_T_6, ram[6].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_1106 = or(_out_uop_T_1099, _out_uop_T_1100) node _out_uop_T_1107 = or(_out_uop_T_1106, _out_uop_T_1101) node _out_uop_T_1108 = or(_out_uop_T_1107, _out_uop_T_1102) node _out_uop_T_1109 = or(_out_uop_T_1108, _out_uop_T_1103) node _out_uop_T_1110 = or(_out_uop_T_1109, _out_uop_T_1104) node _out_uop_T_1111 = or(_out_uop_T_1110, _out_uop_T_1105) wire _out_uop_WIRE_93 : UInt<1> connect _out_uop_WIRE_93, _out_uop_T_1111 connect _out_uop_WIRE_82.rfs3, _out_uop_WIRE_93 node _out_uop_T_1112 = mux(_out_uop_T, ram[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1113 = mux(_out_uop_T_1, ram[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1114 = mux(_out_uop_T_2, ram[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1115 = mux(_out_uop_T_3, ram[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1116 = mux(_out_uop_T_4, ram[4].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1117 = mux(_out_uop_T_5, ram[5].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1118 = mux(_out_uop_T_6, ram[6].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_1119 = or(_out_uop_T_1112, _out_uop_T_1113) node _out_uop_T_1120 = or(_out_uop_T_1119, _out_uop_T_1114) node _out_uop_T_1121 = or(_out_uop_T_1120, _out_uop_T_1115) node _out_uop_T_1122 = or(_out_uop_T_1121, _out_uop_T_1116) node _out_uop_T_1123 = or(_out_uop_T_1122, _out_uop_T_1117) node _out_uop_T_1124 = or(_out_uop_T_1123, _out_uop_T_1118) wire _out_uop_WIRE_94 : UInt<1> connect _out_uop_WIRE_94, _out_uop_T_1124 connect _out_uop_WIRE_82.rfs2, _out_uop_WIRE_94 node _out_uop_T_1125 = mux(_out_uop_T, ram[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1126 = mux(_out_uop_T_1, ram[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1127 = mux(_out_uop_T_2, ram[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1128 = mux(_out_uop_T_3, ram[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1129 = mux(_out_uop_T_4, ram[4].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1130 = mux(_out_uop_T_5, ram[5].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1131 = mux(_out_uop_T_6, ram[6].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_1132 = or(_out_uop_T_1125, _out_uop_T_1126) node _out_uop_T_1133 = or(_out_uop_T_1132, _out_uop_T_1127) node _out_uop_T_1134 = or(_out_uop_T_1133, _out_uop_T_1128) node _out_uop_T_1135 = or(_out_uop_T_1134, _out_uop_T_1129) node _out_uop_T_1136 = or(_out_uop_T_1135, _out_uop_T_1130) node _out_uop_T_1137 = or(_out_uop_T_1136, _out_uop_T_1131) wire _out_uop_WIRE_95 : UInt<1> connect _out_uop_WIRE_95, _out_uop_T_1137 connect _out_uop_WIRE_82.rfs1, _out_uop_WIRE_95 node _out_uop_T_1138 = mux(_out_uop_T, ram[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1139 = mux(_out_uop_T_1, ram[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1140 = mux(_out_uop_T_2, ram[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1141 = mux(_out_uop_T_3, ram[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1142 = mux(_out_uop_T_4, ram[4].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1143 = mux(_out_uop_T_5, ram[5].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1144 = mux(_out_uop_T_6, ram[6].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_1145 = or(_out_uop_T_1138, _out_uop_T_1139) node _out_uop_T_1146 = or(_out_uop_T_1145, _out_uop_T_1140) node _out_uop_T_1147 = or(_out_uop_T_1146, _out_uop_T_1141) node _out_uop_T_1148 = or(_out_uop_T_1147, _out_uop_T_1142) node _out_uop_T_1149 = or(_out_uop_T_1148, _out_uop_T_1143) node _out_uop_T_1150 = or(_out_uop_T_1149, _out_uop_T_1144) wire _out_uop_WIRE_96 : UInt<5> connect _out_uop_WIRE_96, _out_uop_T_1150 connect _out_uop_WIRE_82.mem_cmd, _out_uop_WIRE_96 node _out_uop_T_1151 = mux(_out_uop_T, ram[0].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1152 = mux(_out_uop_T_1, ram[1].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1153 = mux(_out_uop_T_2, ram[2].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1154 = mux(_out_uop_T_3, ram[3].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1155 = mux(_out_uop_T_4, ram[4].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1156 = mux(_out_uop_T_5, ram[5].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1157 = mux(_out_uop_T_6, ram[6].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_1158 = or(_out_uop_T_1151, _out_uop_T_1152) node _out_uop_T_1159 = or(_out_uop_T_1158, _out_uop_T_1153) node _out_uop_T_1160 = or(_out_uop_T_1159, _out_uop_T_1154) node _out_uop_T_1161 = or(_out_uop_T_1160, _out_uop_T_1155) node _out_uop_T_1162 = or(_out_uop_T_1161, _out_uop_T_1156) node _out_uop_T_1163 = or(_out_uop_T_1162, _out_uop_T_1157) wire _out_uop_WIRE_97 : UInt<1> connect _out_uop_WIRE_97, _out_uop_T_1163 connect _out_uop_WIRE_82.mem, _out_uop_WIRE_97 node _out_uop_T_1164 = mux(_out_uop_T, ram[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1165 = mux(_out_uop_T_1, ram[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1166 = mux(_out_uop_T_2, ram[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1167 = mux(_out_uop_T_3, ram[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1168 = mux(_out_uop_T_4, ram[4].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1169 = mux(_out_uop_T_5, ram[5].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1170 = mux(_out_uop_T_6, ram[6].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_1171 = or(_out_uop_T_1164, _out_uop_T_1165) node _out_uop_T_1172 = or(_out_uop_T_1171, _out_uop_T_1166) node _out_uop_T_1173 = or(_out_uop_T_1172, _out_uop_T_1167) node _out_uop_T_1174 = or(_out_uop_T_1173, _out_uop_T_1168) node _out_uop_T_1175 = or(_out_uop_T_1174, _out_uop_T_1169) node _out_uop_T_1176 = or(_out_uop_T_1175, _out_uop_T_1170) wire _out_uop_WIRE_98 : UInt<5> connect _out_uop_WIRE_98, _out_uop_T_1176 connect _out_uop_WIRE_82.alu_fn, _out_uop_WIRE_98 node _out_uop_T_1177 = mux(_out_uop_T, ram[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1178 = mux(_out_uop_T_1, ram[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1179 = mux(_out_uop_T_2, ram[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1180 = mux(_out_uop_T_3, ram[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1181 = mux(_out_uop_T_4, ram[4].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1182 = mux(_out_uop_T_5, ram[5].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1183 = mux(_out_uop_T_6, ram[6].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_1184 = or(_out_uop_T_1177, _out_uop_T_1178) node _out_uop_T_1185 = or(_out_uop_T_1184, _out_uop_T_1179) node _out_uop_T_1186 = or(_out_uop_T_1185, _out_uop_T_1180) node _out_uop_T_1187 = or(_out_uop_T_1186, _out_uop_T_1181) node _out_uop_T_1188 = or(_out_uop_T_1187, _out_uop_T_1182) node _out_uop_T_1189 = or(_out_uop_T_1188, _out_uop_T_1183) wire _out_uop_WIRE_99 : UInt<1> connect _out_uop_WIRE_99, _out_uop_T_1189 connect _out_uop_WIRE_82.alu_dw, _out_uop_WIRE_99 node _out_uop_T_1190 = mux(_out_uop_T, ram[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1191 = mux(_out_uop_T_1, ram[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1192 = mux(_out_uop_T_2, ram[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1193 = mux(_out_uop_T_3, ram[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1194 = mux(_out_uop_T_4, ram[4].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1195 = mux(_out_uop_T_5, ram[5].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1196 = mux(_out_uop_T_6, ram[6].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_1197 = or(_out_uop_T_1190, _out_uop_T_1191) node _out_uop_T_1198 = or(_out_uop_T_1197, _out_uop_T_1192) node _out_uop_T_1199 = or(_out_uop_T_1198, _out_uop_T_1193) node _out_uop_T_1200 = or(_out_uop_T_1199, _out_uop_T_1194) node _out_uop_T_1201 = or(_out_uop_T_1200, _out_uop_T_1195) node _out_uop_T_1202 = or(_out_uop_T_1201, _out_uop_T_1196) wire _out_uop_WIRE_100 : UInt<3> connect _out_uop_WIRE_100, _out_uop_T_1202 connect _out_uop_WIRE_82.sel_imm, _out_uop_WIRE_100 node _out_uop_T_1203 = mux(_out_uop_T, ram[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1204 = mux(_out_uop_T_1, ram[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1205 = mux(_out_uop_T_2, ram[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1206 = mux(_out_uop_T_3, ram[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1207 = mux(_out_uop_T_4, ram[4].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1208 = mux(_out_uop_T_5, ram[5].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1209 = mux(_out_uop_T_6, ram[6].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_1210 = or(_out_uop_T_1203, _out_uop_T_1204) node _out_uop_T_1211 = or(_out_uop_T_1210, _out_uop_T_1205) node _out_uop_T_1212 = or(_out_uop_T_1211, _out_uop_T_1206) node _out_uop_T_1213 = or(_out_uop_T_1212, _out_uop_T_1207) node _out_uop_T_1214 = or(_out_uop_T_1213, _out_uop_T_1208) node _out_uop_T_1215 = or(_out_uop_T_1214, _out_uop_T_1209) wire _out_uop_WIRE_101 : UInt<2> connect _out_uop_WIRE_101, _out_uop_T_1215 connect _out_uop_WIRE_82.sel_alu1, _out_uop_WIRE_101 node _out_uop_T_1216 = mux(_out_uop_T, ram[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1217 = mux(_out_uop_T_1, ram[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1218 = mux(_out_uop_T_2, ram[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1219 = mux(_out_uop_T_3, ram[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1220 = mux(_out_uop_T_4, ram[4].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1221 = mux(_out_uop_T_5, ram[5].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1222 = mux(_out_uop_T_6, ram[6].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_1223 = or(_out_uop_T_1216, _out_uop_T_1217) node _out_uop_T_1224 = or(_out_uop_T_1223, _out_uop_T_1218) node _out_uop_T_1225 = or(_out_uop_T_1224, _out_uop_T_1219) node _out_uop_T_1226 = or(_out_uop_T_1225, _out_uop_T_1220) node _out_uop_T_1227 = or(_out_uop_T_1226, _out_uop_T_1221) node _out_uop_T_1228 = or(_out_uop_T_1227, _out_uop_T_1222) wire _out_uop_WIRE_102 : UInt<3> connect _out_uop_WIRE_102, _out_uop_T_1228 connect _out_uop_WIRE_82.sel_alu2, _out_uop_WIRE_102 node _out_uop_T_1229 = mux(_out_uop_T, ram[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1230 = mux(_out_uop_T_1, ram[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1231 = mux(_out_uop_T_2, ram[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1232 = mux(_out_uop_T_3, ram[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1233 = mux(_out_uop_T_4, ram[4].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1234 = mux(_out_uop_T_5, ram[5].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1235 = mux(_out_uop_T_6, ram[6].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_1236 = or(_out_uop_T_1229, _out_uop_T_1230) node _out_uop_T_1237 = or(_out_uop_T_1236, _out_uop_T_1231) node _out_uop_T_1238 = or(_out_uop_T_1237, _out_uop_T_1232) node _out_uop_T_1239 = or(_out_uop_T_1238, _out_uop_T_1233) node _out_uop_T_1240 = or(_out_uop_T_1239, _out_uop_T_1234) node _out_uop_T_1241 = or(_out_uop_T_1240, _out_uop_T_1235) wire _out_uop_WIRE_103 : UInt<1> connect _out_uop_WIRE_103, _out_uop_T_1241 connect _out_uop_WIRE_82.rxs1, _out_uop_WIRE_103 node _out_uop_T_1242 = mux(_out_uop_T, ram[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1243 = mux(_out_uop_T_1, ram[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1244 = mux(_out_uop_T_2, ram[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1245 = mux(_out_uop_T_3, ram[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1246 = mux(_out_uop_T_4, ram[4].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1247 = mux(_out_uop_T_5, ram[5].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1248 = mux(_out_uop_T_6, ram[6].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_1249 = or(_out_uop_T_1242, _out_uop_T_1243) node _out_uop_T_1250 = or(_out_uop_T_1249, _out_uop_T_1244) node _out_uop_T_1251 = or(_out_uop_T_1250, _out_uop_T_1245) node _out_uop_T_1252 = or(_out_uop_T_1251, _out_uop_T_1246) node _out_uop_T_1253 = or(_out_uop_T_1252, _out_uop_T_1247) node _out_uop_T_1254 = or(_out_uop_T_1253, _out_uop_T_1248) wire _out_uop_WIRE_104 : UInt<1> connect _out_uop_WIRE_104, _out_uop_T_1254 connect _out_uop_WIRE_82.rxs2, _out_uop_WIRE_104 node _out_uop_T_1255 = mux(_out_uop_T, ram[0].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1256 = mux(_out_uop_T_1, ram[1].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1257 = mux(_out_uop_T_2, ram[2].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1258 = mux(_out_uop_T_3, ram[3].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1259 = mux(_out_uop_T_4, ram[4].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1260 = mux(_out_uop_T_5, ram[5].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1261 = mux(_out_uop_T_6, ram[6].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_1262 = or(_out_uop_T_1255, _out_uop_T_1256) node _out_uop_T_1263 = or(_out_uop_T_1262, _out_uop_T_1257) node _out_uop_T_1264 = or(_out_uop_T_1263, _out_uop_T_1258) node _out_uop_T_1265 = or(_out_uop_T_1264, _out_uop_T_1259) node _out_uop_T_1266 = or(_out_uop_T_1265, _out_uop_T_1260) node _out_uop_T_1267 = or(_out_uop_T_1266, _out_uop_T_1261) wire _out_uop_WIRE_105 : UInt<1> connect _out_uop_WIRE_105, _out_uop_T_1267 connect _out_uop_WIRE_82.jalr, _out_uop_WIRE_105 node _out_uop_T_1268 = mux(_out_uop_T, ram[0].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1269 = mux(_out_uop_T_1, ram[1].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1270 = mux(_out_uop_T_2, ram[2].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1271 = mux(_out_uop_T_3, ram[3].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1272 = mux(_out_uop_T_4, ram[4].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1273 = mux(_out_uop_T_5, ram[5].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1274 = mux(_out_uop_T_6, ram[6].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_1275 = or(_out_uop_T_1268, _out_uop_T_1269) node _out_uop_T_1276 = or(_out_uop_T_1275, _out_uop_T_1270) node _out_uop_T_1277 = or(_out_uop_T_1276, _out_uop_T_1271) node _out_uop_T_1278 = or(_out_uop_T_1277, _out_uop_T_1272) node _out_uop_T_1279 = or(_out_uop_T_1278, _out_uop_T_1273) node _out_uop_T_1280 = or(_out_uop_T_1279, _out_uop_T_1274) wire _out_uop_WIRE_106 : UInt<1> connect _out_uop_WIRE_106, _out_uop_T_1280 connect _out_uop_WIRE_82.jal, _out_uop_WIRE_106 node _out_uop_T_1281 = mux(_out_uop_T, ram[0].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1282 = mux(_out_uop_T_1, ram[1].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1283 = mux(_out_uop_T_2, ram[2].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1284 = mux(_out_uop_T_3, ram[3].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1285 = mux(_out_uop_T_4, ram[4].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1286 = mux(_out_uop_T_5, ram[5].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1287 = mux(_out_uop_T_6, ram[6].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_1288 = or(_out_uop_T_1281, _out_uop_T_1282) node _out_uop_T_1289 = or(_out_uop_T_1288, _out_uop_T_1283) node _out_uop_T_1290 = or(_out_uop_T_1289, _out_uop_T_1284) node _out_uop_T_1291 = or(_out_uop_T_1290, _out_uop_T_1285) node _out_uop_T_1292 = or(_out_uop_T_1291, _out_uop_T_1286) node _out_uop_T_1293 = or(_out_uop_T_1292, _out_uop_T_1287) wire _out_uop_WIRE_107 : UInt<1> connect _out_uop_WIRE_107, _out_uop_T_1293 connect _out_uop_WIRE_82.branch, _out_uop_WIRE_107 node _out_uop_T_1294 = mux(_out_uop_T, ram[0].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1295 = mux(_out_uop_T_1, ram[1].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1296 = mux(_out_uop_T_2, ram[2].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1297 = mux(_out_uop_T_3, ram[3].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1298 = mux(_out_uop_T_4, ram[4].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1299 = mux(_out_uop_T_5, ram[5].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1300 = mux(_out_uop_T_6, ram[6].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_1301 = or(_out_uop_T_1294, _out_uop_T_1295) node _out_uop_T_1302 = or(_out_uop_T_1301, _out_uop_T_1296) node _out_uop_T_1303 = or(_out_uop_T_1302, _out_uop_T_1297) node _out_uop_T_1304 = or(_out_uop_T_1303, _out_uop_T_1298) node _out_uop_T_1305 = or(_out_uop_T_1304, _out_uop_T_1299) node _out_uop_T_1306 = or(_out_uop_T_1305, _out_uop_T_1300) wire _out_uop_WIRE_108 : UInt<1> connect _out_uop_WIRE_108, _out_uop_T_1306 connect _out_uop_WIRE_82.rocc, _out_uop_WIRE_108 node _out_uop_T_1307 = mux(_out_uop_T, ram[0].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1308 = mux(_out_uop_T_1, ram[1].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1309 = mux(_out_uop_T_2, ram[2].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1310 = mux(_out_uop_T_3, ram[3].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1311 = mux(_out_uop_T_4, ram[4].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1312 = mux(_out_uop_T_5, ram[5].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1313 = mux(_out_uop_T_6, ram[6].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_1314 = or(_out_uop_T_1307, _out_uop_T_1308) node _out_uop_T_1315 = or(_out_uop_T_1314, _out_uop_T_1309) node _out_uop_T_1316 = or(_out_uop_T_1315, _out_uop_T_1310) node _out_uop_T_1317 = or(_out_uop_T_1316, _out_uop_T_1311) node _out_uop_T_1318 = or(_out_uop_T_1317, _out_uop_T_1312) node _out_uop_T_1319 = or(_out_uop_T_1318, _out_uop_T_1313) wire _out_uop_WIRE_109 : UInt<1> connect _out_uop_WIRE_109, _out_uop_T_1319 connect _out_uop_WIRE_82.fp, _out_uop_WIRE_109 node _out_uop_T_1320 = mux(_out_uop_T, ram[0].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1321 = mux(_out_uop_T_1, ram[1].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1322 = mux(_out_uop_T_2, ram[2].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1323 = mux(_out_uop_T_3, ram[3].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1324 = mux(_out_uop_T_4, ram[4].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1325 = mux(_out_uop_T_5, ram[5].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1326 = mux(_out_uop_T_6, ram[6].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_1327 = or(_out_uop_T_1320, _out_uop_T_1321) node _out_uop_T_1328 = or(_out_uop_T_1327, _out_uop_T_1322) node _out_uop_T_1329 = or(_out_uop_T_1328, _out_uop_T_1323) node _out_uop_T_1330 = or(_out_uop_T_1329, _out_uop_T_1324) node _out_uop_T_1331 = or(_out_uop_T_1330, _out_uop_T_1325) node _out_uop_T_1332 = or(_out_uop_T_1331, _out_uop_T_1326) wire _out_uop_WIRE_110 : UInt<1> connect _out_uop_WIRE_110, _out_uop_T_1332 connect _out_uop_WIRE_82.legal, _out_uop_WIRE_110 connect _out_uop_WIRE.ctrl, _out_uop_WIRE_82 node _out_uop_T_1333 = mux(_out_uop_T, ram[0].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1334 = mux(_out_uop_T_1, ram[1].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1335 = mux(_out_uop_T_2, ram[2].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1336 = mux(_out_uop_T_3, ram[3].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1337 = mux(_out_uop_T_4, ram[4].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1338 = mux(_out_uop_T_5, ram[5].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1339 = mux(_out_uop_T_6, ram[6].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_1340 = or(_out_uop_T_1333, _out_uop_T_1334) node _out_uop_T_1341 = or(_out_uop_T_1340, _out_uop_T_1335) node _out_uop_T_1342 = or(_out_uop_T_1341, _out_uop_T_1336) node _out_uop_T_1343 = or(_out_uop_T_1342, _out_uop_T_1337) node _out_uop_T_1344 = or(_out_uop_T_1343, _out_uop_T_1338) node _out_uop_T_1345 = or(_out_uop_T_1344, _out_uop_T_1339) wire _out_uop_WIRE_111 : UInt<1> connect _out_uop_WIRE_111, _out_uop_T_1345 connect _out_uop_WIRE.edge_inst, _out_uop_WIRE_111 node _out_uop_T_1346 = mux(_out_uop_T, ram[0].bits.pc, UInt<1>(0h0)) node _out_uop_T_1347 = mux(_out_uop_T_1, ram[1].bits.pc, UInt<1>(0h0)) node _out_uop_T_1348 = mux(_out_uop_T_2, ram[2].bits.pc, UInt<1>(0h0)) node _out_uop_T_1349 = mux(_out_uop_T_3, ram[3].bits.pc, UInt<1>(0h0)) node _out_uop_T_1350 = mux(_out_uop_T_4, ram[4].bits.pc, UInt<1>(0h0)) node _out_uop_T_1351 = mux(_out_uop_T_5, ram[5].bits.pc, UInt<1>(0h0)) node _out_uop_T_1352 = mux(_out_uop_T_6, ram[6].bits.pc, UInt<1>(0h0)) node _out_uop_T_1353 = or(_out_uop_T_1346, _out_uop_T_1347) node _out_uop_T_1354 = or(_out_uop_T_1353, _out_uop_T_1348) node _out_uop_T_1355 = or(_out_uop_T_1354, _out_uop_T_1349) node _out_uop_T_1356 = or(_out_uop_T_1355, _out_uop_T_1350) node _out_uop_T_1357 = or(_out_uop_T_1356, _out_uop_T_1351) node _out_uop_T_1358 = or(_out_uop_T_1357, _out_uop_T_1352) wire _out_uop_WIRE_112 : UInt<40> connect _out_uop_WIRE_112, _out_uop_T_1358 connect _out_uop_WIRE.pc, _out_uop_WIRE_112 node _out_uop_T_1359 = mux(_out_uop_T, ram[0].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1360 = mux(_out_uop_T_1, ram[1].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1361 = mux(_out_uop_T_2, ram[2].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1362 = mux(_out_uop_T_3, ram[3].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1363 = mux(_out_uop_T_4, ram[4].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1364 = mux(_out_uop_T_5, ram[5].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1365 = mux(_out_uop_T_6, ram[6].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_1366 = or(_out_uop_T_1359, _out_uop_T_1360) node _out_uop_T_1367 = or(_out_uop_T_1366, _out_uop_T_1361) node _out_uop_T_1368 = or(_out_uop_T_1367, _out_uop_T_1362) node _out_uop_T_1369 = or(_out_uop_T_1368, _out_uop_T_1363) node _out_uop_T_1370 = or(_out_uop_T_1369, _out_uop_T_1364) node _out_uop_T_1371 = or(_out_uop_T_1370, _out_uop_T_1365) wire _out_uop_WIRE_113 : UInt<32> connect _out_uop_WIRE_113, _out_uop_T_1371 connect _out_uop_WIRE.raw_inst, _out_uop_WIRE_113 node _out_uop_T_1372 = mux(_out_uop_T, ram[0].bits.inst, UInt<1>(0h0)) node _out_uop_T_1373 = mux(_out_uop_T_1, ram[1].bits.inst, UInt<1>(0h0)) node _out_uop_T_1374 = mux(_out_uop_T_2, ram[2].bits.inst, UInt<1>(0h0)) node _out_uop_T_1375 = mux(_out_uop_T_3, ram[3].bits.inst, UInt<1>(0h0)) node _out_uop_T_1376 = mux(_out_uop_T_4, ram[4].bits.inst, UInt<1>(0h0)) node _out_uop_T_1377 = mux(_out_uop_T_5, ram[5].bits.inst, UInt<1>(0h0)) node _out_uop_T_1378 = mux(_out_uop_T_6, ram[6].bits.inst, UInt<1>(0h0)) node _out_uop_T_1379 = or(_out_uop_T_1372, _out_uop_T_1373) node _out_uop_T_1380 = or(_out_uop_T_1379, _out_uop_T_1374) node _out_uop_T_1381 = or(_out_uop_T_1380, _out_uop_T_1375) node _out_uop_T_1382 = or(_out_uop_T_1381, _out_uop_T_1376) node _out_uop_T_1383 = or(_out_uop_T_1382, _out_uop_T_1377) node _out_uop_T_1384 = or(_out_uop_T_1383, _out_uop_T_1378) wire _out_uop_WIRE_114 : UInt<32> connect _out_uop_WIRE_114, _out_uop_T_1384 connect _out_uop_WIRE.inst, _out_uop_WIRE_114 connect out_uop.bits, _out_uop_WIRE node _out_uop_T_1385 = mux(_out_uop_T, ram[0].valid, UInt<1>(0h0)) node _out_uop_T_1386 = mux(_out_uop_T_1, ram[1].valid, UInt<1>(0h0)) node _out_uop_T_1387 = mux(_out_uop_T_2, ram[2].valid, UInt<1>(0h0)) node _out_uop_T_1388 = mux(_out_uop_T_3, ram[3].valid, UInt<1>(0h0)) node _out_uop_T_1389 = mux(_out_uop_T_4, ram[4].valid, UInt<1>(0h0)) node _out_uop_T_1390 = mux(_out_uop_T_5, ram[5].valid, UInt<1>(0h0)) node _out_uop_T_1391 = mux(_out_uop_T_6, ram[6].valid, UInt<1>(0h0)) node _out_uop_T_1392 = or(_out_uop_T_1385, _out_uop_T_1386) node _out_uop_T_1393 = or(_out_uop_T_1392, _out_uop_T_1387) node _out_uop_T_1394 = or(_out_uop_T_1393, _out_uop_T_1388) node _out_uop_T_1395 = or(_out_uop_T_1394, _out_uop_T_1389) node _out_uop_T_1396 = or(_out_uop_T_1395, _out_uop_T_1390) node _out_uop_T_1397 = or(_out_uop_T_1396, _out_uop_T_1391) wire _out_uop_WIRE_115 : UInt<1> connect _out_uop_WIRE_115, _out_uop_T_1397 connect out_uop.valid, _out_uop_WIRE_115 connect io.deq[0].valid, out_uop.valid connect io.deq[0].bits, out_uop.bits node _T_28 = and(io.deq[0].ready, io.deq[0].valid) node _T_29 = or(UInt<7>(0h0), deq_ptr) node _T_30 = mux(_T_28, _T_29, UInt<7>(0h0)) node _T_31 = shl(deq_ptr, 1) node _T_32 = bits(deq_ptr, 6, 6) node _T_33 = or(_T_31, _T_32) node _T_34 = bits(_T_33, 6, 0) node _out_uop_T_1398 = bits(_T_34, 0, 0) node _out_uop_T_1399 = bits(_T_34, 1, 1) node _out_uop_T_1400 = bits(_T_34, 2, 2) node _out_uop_T_1401 = bits(_T_34, 3, 3) node _out_uop_T_1402 = bits(_T_34, 4, 4) node _out_uop_T_1403 = bits(_T_34, 5, 5) node _out_uop_T_1404 = bits(_T_34, 6, 6) wire out_uop_1 : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _out_uop_WIRE_116 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _out_uop_T_1405 = mux(_out_uop_T_1398, ram[0].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1406 = mux(_out_uop_T_1399, ram[1].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1407 = mux(_out_uop_T_1400, ram[2].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1408 = mux(_out_uop_T_1401, ram[3].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1409 = mux(_out_uop_T_1402, ram[4].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1410 = mux(_out_uop_T_1403, ram[5].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1411 = mux(_out_uop_T_1404, ram[6].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_1412 = or(_out_uop_T_1405, _out_uop_T_1406) node _out_uop_T_1413 = or(_out_uop_T_1412, _out_uop_T_1407) node _out_uop_T_1414 = or(_out_uop_T_1413, _out_uop_T_1408) node _out_uop_T_1415 = or(_out_uop_T_1414, _out_uop_T_1409) node _out_uop_T_1416 = or(_out_uop_T_1415, _out_uop_T_1410) node _out_uop_T_1417 = or(_out_uop_T_1416, _out_uop_T_1411) wire _out_uop_WIRE_117 : UInt<1> connect _out_uop_WIRE_117, _out_uop_T_1417 connect _out_uop_WIRE_116.flush_pipe, _out_uop_WIRE_117 node _out_uop_T_1418 = mux(_out_uop_T_1398, ram[0].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1419 = mux(_out_uop_T_1399, ram[1].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1420 = mux(_out_uop_T_1400, ram[2].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1421 = mux(_out_uop_T_1401, ram[3].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1422 = mux(_out_uop_T_1402, ram[4].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1423 = mux(_out_uop_T_1403, ram[5].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1424 = mux(_out_uop_T_1404, ram[6].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_1425 = or(_out_uop_T_1418, _out_uop_T_1419) node _out_uop_T_1426 = or(_out_uop_T_1425, _out_uop_T_1420) node _out_uop_T_1427 = or(_out_uop_T_1426, _out_uop_T_1421) node _out_uop_T_1428 = or(_out_uop_T_1427, _out_uop_T_1422) node _out_uop_T_1429 = or(_out_uop_T_1428, _out_uop_T_1423) node _out_uop_T_1430 = or(_out_uop_T_1429, _out_uop_T_1424) wire _out_uop_WIRE_118 : UInt<2> connect _out_uop_WIRE_118, _out_uop_T_1430 connect _out_uop_WIRE_116.mem_size, _out_uop_WIRE_118 wire _out_uop_WIRE_119 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _out_uop_T_1431 = mux(_out_uop_T_1398, ram[0].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1432 = mux(_out_uop_T_1399, ram[1].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1433 = mux(_out_uop_T_1400, ram[2].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1434 = mux(_out_uop_T_1401, ram[3].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1435 = mux(_out_uop_T_1402, ram[4].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1436 = mux(_out_uop_T_1403, ram[5].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1437 = mux(_out_uop_T_1404, ram[6].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_1438 = or(_out_uop_T_1431, _out_uop_T_1432) node _out_uop_T_1439 = or(_out_uop_T_1438, _out_uop_T_1433) node _out_uop_T_1440 = or(_out_uop_T_1439, _out_uop_T_1434) node _out_uop_T_1441 = or(_out_uop_T_1440, _out_uop_T_1435) node _out_uop_T_1442 = or(_out_uop_T_1441, _out_uop_T_1436) node _out_uop_T_1443 = or(_out_uop_T_1442, _out_uop_T_1437) wire _out_uop_WIRE_120 : UInt<65> connect _out_uop_WIRE_120, _out_uop_T_1443 connect _out_uop_WIRE_119.in3, _out_uop_WIRE_120 node _out_uop_T_1444 = mux(_out_uop_T_1398, ram[0].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1445 = mux(_out_uop_T_1399, ram[1].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1446 = mux(_out_uop_T_1400, ram[2].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1447 = mux(_out_uop_T_1401, ram[3].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1448 = mux(_out_uop_T_1402, ram[4].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1449 = mux(_out_uop_T_1403, ram[5].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1450 = mux(_out_uop_T_1404, ram[6].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_1451 = or(_out_uop_T_1444, _out_uop_T_1445) node _out_uop_T_1452 = or(_out_uop_T_1451, _out_uop_T_1446) node _out_uop_T_1453 = or(_out_uop_T_1452, _out_uop_T_1447) node _out_uop_T_1454 = or(_out_uop_T_1453, _out_uop_T_1448) node _out_uop_T_1455 = or(_out_uop_T_1454, _out_uop_T_1449) node _out_uop_T_1456 = or(_out_uop_T_1455, _out_uop_T_1450) wire _out_uop_WIRE_121 : UInt<65> connect _out_uop_WIRE_121, _out_uop_T_1456 connect _out_uop_WIRE_119.in2, _out_uop_WIRE_121 node _out_uop_T_1457 = mux(_out_uop_T_1398, ram[0].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1458 = mux(_out_uop_T_1399, ram[1].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1459 = mux(_out_uop_T_1400, ram[2].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1460 = mux(_out_uop_T_1401, ram[3].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1461 = mux(_out_uop_T_1402, ram[4].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1462 = mux(_out_uop_T_1403, ram[5].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1463 = mux(_out_uop_T_1404, ram[6].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_1464 = or(_out_uop_T_1457, _out_uop_T_1458) node _out_uop_T_1465 = or(_out_uop_T_1464, _out_uop_T_1459) node _out_uop_T_1466 = or(_out_uop_T_1465, _out_uop_T_1460) node _out_uop_T_1467 = or(_out_uop_T_1466, _out_uop_T_1461) node _out_uop_T_1468 = or(_out_uop_T_1467, _out_uop_T_1462) node _out_uop_T_1469 = or(_out_uop_T_1468, _out_uop_T_1463) wire _out_uop_WIRE_122 : UInt<65> connect _out_uop_WIRE_122, _out_uop_T_1469 connect _out_uop_WIRE_119.in1, _out_uop_WIRE_122 node _out_uop_T_1470 = mux(_out_uop_T_1398, ram[0].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1471 = mux(_out_uop_T_1399, ram[1].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1472 = mux(_out_uop_T_1400, ram[2].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1473 = mux(_out_uop_T_1401, ram[3].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1474 = mux(_out_uop_T_1402, ram[4].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1475 = mux(_out_uop_T_1403, ram[5].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1476 = mux(_out_uop_T_1404, ram[6].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_1477 = or(_out_uop_T_1470, _out_uop_T_1471) node _out_uop_T_1478 = or(_out_uop_T_1477, _out_uop_T_1472) node _out_uop_T_1479 = or(_out_uop_T_1478, _out_uop_T_1473) node _out_uop_T_1480 = or(_out_uop_T_1479, _out_uop_T_1474) node _out_uop_T_1481 = or(_out_uop_T_1480, _out_uop_T_1475) node _out_uop_T_1482 = or(_out_uop_T_1481, _out_uop_T_1476) wire _out_uop_WIRE_123 : UInt<2> connect _out_uop_WIRE_123, _out_uop_T_1482 connect _out_uop_WIRE_119.fmt, _out_uop_WIRE_123 node _out_uop_T_1483 = mux(_out_uop_T_1398, ram[0].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1484 = mux(_out_uop_T_1399, ram[1].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1485 = mux(_out_uop_T_1400, ram[2].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1486 = mux(_out_uop_T_1401, ram[3].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1487 = mux(_out_uop_T_1402, ram[4].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1488 = mux(_out_uop_T_1403, ram[5].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1489 = mux(_out_uop_T_1404, ram[6].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_1490 = or(_out_uop_T_1483, _out_uop_T_1484) node _out_uop_T_1491 = or(_out_uop_T_1490, _out_uop_T_1485) node _out_uop_T_1492 = or(_out_uop_T_1491, _out_uop_T_1486) node _out_uop_T_1493 = or(_out_uop_T_1492, _out_uop_T_1487) node _out_uop_T_1494 = or(_out_uop_T_1493, _out_uop_T_1488) node _out_uop_T_1495 = or(_out_uop_T_1494, _out_uop_T_1489) wire _out_uop_WIRE_124 : UInt<2> connect _out_uop_WIRE_124, _out_uop_T_1495 connect _out_uop_WIRE_119.typ, _out_uop_WIRE_124 node _out_uop_T_1496 = mux(_out_uop_T_1398, ram[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1497 = mux(_out_uop_T_1399, ram[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1498 = mux(_out_uop_T_1400, ram[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1499 = mux(_out_uop_T_1401, ram[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1500 = mux(_out_uop_T_1402, ram[4].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1501 = mux(_out_uop_T_1403, ram[5].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1502 = mux(_out_uop_T_1404, ram[6].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_1503 = or(_out_uop_T_1496, _out_uop_T_1497) node _out_uop_T_1504 = or(_out_uop_T_1503, _out_uop_T_1498) node _out_uop_T_1505 = or(_out_uop_T_1504, _out_uop_T_1499) node _out_uop_T_1506 = or(_out_uop_T_1505, _out_uop_T_1500) node _out_uop_T_1507 = or(_out_uop_T_1506, _out_uop_T_1501) node _out_uop_T_1508 = or(_out_uop_T_1507, _out_uop_T_1502) wire _out_uop_WIRE_125 : UInt<2> connect _out_uop_WIRE_125, _out_uop_T_1508 connect _out_uop_WIRE_119.fmaCmd, _out_uop_WIRE_125 node _out_uop_T_1509 = mux(_out_uop_T_1398, ram[0].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1510 = mux(_out_uop_T_1399, ram[1].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1511 = mux(_out_uop_T_1400, ram[2].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1512 = mux(_out_uop_T_1401, ram[3].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1513 = mux(_out_uop_T_1402, ram[4].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1514 = mux(_out_uop_T_1403, ram[5].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1515 = mux(_out_uop_T_1404, ram[6].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_1516 = or(_out_uop_T_1509, _out_uop_T_1510) node _out_uop_T_1517 = or(_out_uop_T_1516, _out_uop_T_1511) node _out_uop_T_1518 = or(_out_uop_T_1517, _out_uop_T_1512) node _out_uop_T_1519 = or(_out_uop_T_1518, _out_uop_T_1513) node _out_uop_T_1520 = or(_out_uop_T_1519, _out_uop_T_1514) node _out_uop_T_1521 = or(_out_uop_T_1520, _out_uop_T_1515) wire _out_uop_WIRE_126 : UInt<3> connect _out_uop_WIRE_126, _out_uop_T_1521 connect _out_uop_WIRE_119.rm, _out_uop_WIRE_126 node _out_uop_T_1522 = mux(_out_uop_T_1398, ram[0].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1523 = mux(_out_uop_T_1399, ram[1].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1524 = mux(_out_uop_T_1400, ram[2].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1525 = mux(_out_uop_T_1401, ram[3].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1526 = mux(_out_uop_T_1402, ram[4].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1527 = mux(_out_uop_T_1403, ram[5].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1528 = mux(_out_uop_T_1404, ram[6].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_1529 = or(_out_uop_T_1522, _out_uop_T_1523) node _out_uop_T_1530 = or(_out_uop_T_1529, _out_uop_T_1524) node _out_uop_T_1531 = or(_out_uop_T_1530, _out_uop_T_1525) node _out_uop_T_1532 = or(_out_uop_T_1531, _out_uop_T_1526) node _out_uop_T_1533 = or(_out_uop_T_1532, _out_uop_T_1527) node _out_uop_T_1534 = or(_out_uop_T_1533, _out_uop_T_1528) wire _out_uop_WIRE_127 : UInt<1> connect _out_uop_WIRE_127, _out_uop_T_1534 connect _out_uop_WIRE_119.vec, _out_uop_WIRE_127 node _out_uop_T_1535 = mux(_out_uop_T_1398, ram[0].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1536 = mux(_out_uop_T_1399, ram[1].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1537 = mux(_out_uop_T_1400, ram[2].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1538 = mux(_out_uop_T_1401, ram[3].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1539 = mux(_out_uop_T_1402, ram[4].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1540 = mux(_out_uop_T_1403, ram[5].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1541 = mux(_out_uop_T_1404, ram[6].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_1542 = or(_out_uop_T_1535, _out_uop_T_1536) node _out_uop_T_1543 = or(_out_uop_T_1542, _out_uop_T_1537) node _out_uop_T_1544 = or(_out_uop_T_1543, _out_uop_T_1538) node _out_uop_T_1545 = or(_out_uop_T_1544, _out_uop_T_1539) node _out_uop_T_1546 = or(_out_uop_T_1545, _out_uop_T_1540) node _out_uop_T_1547 = or(_out_uop_T_1546, _out_uop_T_1541) wire _out_uop_WIRE_128 : UInt<1> connect _out_uop_WIRE_128, _out_uop_T_1547 connect _out_uop_WIRE_119.wflags, _out_uop_WIRE_128 node _out_uop_T_1548 = mux(_out_uop_T_1398, ram[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1549 = mux(_out_uop_T_1399, ram[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1550 = mux(_out_uop_T_1400, ram[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1551 = mux(_out_uop_T_1401, ram[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1552 = mux(_out_uop_T_1402, ram[4].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1553 = mux(_out_uop_T_1403, ram[5].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1554 = mux(_out_uop_T_1404, ram[6].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_1555 = or(_out_uop_T_1548, _out_uop_T_1549) node _out_uop_T_1556 = or(_out_uop_T_1555, _out_uop_T_1550) node _out_uop_T_1557 = or(_out_uop_T_1556, _out_uop_T_1551) node _out_uop_T_1558 = or(_out_uop_T_1557, _out_uop_T_1552) node _out_uop_T_1559 = or(_out_uop_T_1558, _out_uop_T_1553) node _out_uop_T_1560 = or(_out_uop_T_1559, _out_uop_T_1554) wire _out_uop_WIRE_129 : UInt<1> connect _out_uop_WIRE_129, _out_uop_T_1560 connect _out_uop_WIRE_119.sqrt, _out_uop_WIRE_129 node _out_uop_T_1561 = mux(_out_uop_T_1398, ram[0].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1562 = mux(_out_uop_T_1399, ram[1].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1563 = mux(_out_uop_T_1400, ram[2].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1564 = mux(_out_uop_T_1401, ram[3].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1565 = mux(_out_uop_T_1402, ram[4].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1566 = mux(_out_uop_T_1403, ram[5].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1567 = mux(_out_uop_T_1404, ram[6].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_1568 = or(_out_uop_T_1561, _out_uop_T_1562) node _out_uop_T_1569 = or(_out_uop_T_1568, _out_uop_T_1563) node _out_uop_T_1570 = or(_out_uop_T_1569, _out_uop_T_1564) node _out_uop_T_1571 = or(_out_uop_T_1570, _out_uop_T_1565) node _out_uop_T_1572 = or(_out_uop_T_1571, _out_uop_T_1566) node _out_uop_T_1573 = or(_out_uop_T_1572, _out_uop_T_1567) wire _out_uop_WIRE_130 : UInt<1> connect _out_uop_WIRE_130, _out_uop_T_1573 connect _out_uop_WIRE_119.div, _out_uop_WIRE_130 node _out_uop_T_1574 = mux(_out_uop_T_1398, ram[0].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1575 = mux(_out_uop_T_1399, ram[1].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1576 = mux(_out_uop_T_1400, ram[2].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1577 = mux(_out_uop_T_1401, ram[3].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1578 = mux(_out_uop_T_1402, ram[4].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1579 = mux(_out_uop_T_1403, ram[5].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1580 = mux(_out_uop_T_1404, ram[6].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_1581 = or(_out_uop_T_1574, _out_uop_T_1575) node _out_uop_T_1582 = or(_out_uop_T_1581, _out_uop_T_1576) node _out_uop_T_1583 = or(_out_uop_T_1582, _out_uop_T_1577) node _out_uop_T_1584 = or(_out_uop_T_1583, _out_uop_T_1578) node _out_uop_T_1585 = or(_out_uop_T_1584, _out_uop_T_1579) node _out_uop_T_1586 = or(_out_uop_T_1585, _out_uop_T_1580) wire _out_uop_WIRE_131 : UInt<1> connect _out_uop_WIRE_131, _out_uop_T_1586 connect _out_uop_WIRE_119.fma, _out_uop_WIRE_131 node _out_uop_T_1587 = mux(_out_uop_T_1398, ram[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1588 = mux(_out_uop_T_1399, ram[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1589 = mux(_out_uop_T_1400, ram[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1590 = mux(_out_uop_T_1401, ram[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1591 = mux(_out_uop_T_1402, ram[4].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1592 = mux(_out_uop_T_1403, ram[5].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1593 = mux(_out_uop_T_1404, ram[6].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_1594 = or(_out_uop_T_1587, _out_uop_T_1588) node _out_uop_T_1595 = or(_out_uop_T_1594, _out_uop_T_1589) node _out_uop_T_1596 = or(_out_uop_T_1595, _out_uop_T_1590) node _out_uop_T_1597 = or(_out_uop_T_1596, _out_uop_T_1591) node _out_uop_T_1598 = or(_out_uop_T_1597, _out_uop_T_1592) node _out_uop_T_1599 = or(_out_uop_T_1598, _out_uop_T_1593) wire _out_uop_WIRE_132 : UInt<1> connect _out_uop_WIRE_132, _out_uop_T_1599 connect _out_uop_WIRE_119.fastpipe, _out_uop_WIRE_132 node _out_uop_T_1600 = mux(_out_uop_T_1398, ram[0].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1601 = mux(_out_uop_T_1399, ram[1].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1602 = mux(_out_uop_T_1400, ram[2].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1603 = mux(_out_uop_T_1401, ram[3].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1604 = mux(_out_uop_T_1402, ram[4].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1605 = mux(_out_uop_T_1403, ram[5].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1606 = mux(_out_uop_T_1404, ram[6].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_1607 = or(_out_uop_T_1600, _out_uop_T_1601) node _out_uop_T_1608 = or(_out_uop_T_1607, _out_uop_T_1602) node _out_uop_T_1609 = or(_out_uop_T_1608, _out_uop_T_1603) node _out_uop_T_1610 = or(_out_uop_T_1609, _out_uop_T_1604) node _out_uop_T_1611 = or(_out_uop_T_1610, _out_uop_T_1605) node _out_uop_T_1612 = or(_out_uop_T_1611, _out_uop_T_1606) wire _out_uop_WIRE_133 : UInt<1> connect _out_uop_WIRE_133, _out_uop_T_1612 connect _out_uop_WIRE_119.toint, _out_uop_WIRE_133 node _out_uop_T_1613 = mux(_out_uop_T_1398, ram[0].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1614 = mux(_out_uop_T_1399, ram[1].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1615 = mux(_out_uop_T_1400, ram[2].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1616 = mux(_out_uop_T_1401, ram[3].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1617 = mux(_out_uop_T_1402, ram[4].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1618 = mux(_out_uop_T_1403, ram[5].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1619 = mux(_out_uop_T_1404, ram[6].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_1620 = or(_out_uop_T_1613, _out_uop_T_1614) node _out_uop_T_1621 = or(_out_uop_T_1620, _out_uop_T_1615) node _out_uop_T_1622 = or(_out_uop_T_1621, _out_uop_T_1616) node _out_uop_T_1623 = or(_out_uop_T_1622, _out_uop_T_1617) node _out_uop_T_1624 = or(_out_uop_T_1623, _out_uop_T_1618) node _out_uop_T_1625 = or(_out_uop_T_1624, _out_uop_T_1619) wire _out_uop_WIRE_134 : UInt<1> connect _out_uop_WIRE_134, _out_uop_T_1625 connect _out_uop_WIRE_119.fromint, _out_uop_WIRE_134 node _out_uop_T_1626 = mux(_out_uop_T_1398, ram[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1627 = mux(_out_uop_T_1399, ram[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1628 = mux(_out_uop_T_1400, ram[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1629 = mux(_out_uop_T_1401, ram[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1630 = mux(_out_uop_T_1402, ram[4].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1631 = mux(_out_uop_T_1403, ram[5].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1632 = mux(_out_uop_T_1404, ram[6].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_1633 = or(_out_uop_T_1626, _out_uop_T_1627) node _out_uop_T_1634 = or(_out_uop_T_1633, _out_uop_T_1628) node _out_uop_T_1635 = or(_out_uop_T_1634, _out_uop_T_1629) node _out_uop_T_1636 = or(_out_uop_T_1635, _out_uop_T_1630) node _out_uop_T_1637 = or(_out_uop_T_1636, _out_uop_T_1631) node _out_uop_T_1638 = or(_out_uop_T_1637, _out_uop_T_1632) wire _out_uop_WIRE_135 : UInt<2> connect _out_uop_WIRE_135, _out_uop_T_1638 connect _out_uop_WIRE_119.typeTagOut, _out_uop_WIRE_135 node _out_uop_T_1639 = mux(_out_uop_T_1398, ram[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1640 = mux(_out_uop_T_1399, ram[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1641 = mux(_out_uop_T_1400, ram[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1642 = mux(_out_uop_T_1401, ram[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1643 = mux(_out_uop_T_1402, ram[4].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1644 = mux(_out_uop_T_1403, ram[5].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1645 = mux(_out_uop_T_1404, ram[6].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_1646 = or(_out_uop_T_1639, _out_uop_T_1640) node _out_uop_T_1647 = or(_out_uop_T_1646, _out_uop_T_1641) node _out_uop_T_1648 = or(_out_uop_T_1647, _out_uop_T_1642) node _out_uop_T_1649 = or(_out_uop_T_1648, _out_uop_T_1643) node _out_uop_T_1650 = or(_out_uop_T_1649, _out_uop_T_1644) node _out_uop_T_1651 = or(_out_uop_T_1650, _out_uop_T_1645) wire _out_uop_WIRE_136 : UInt<2> connect _out_uop_WIRE_136, _out_uop_T_1651 connect _out_uop_WIRE_119.typeTagIn, _out_uop_WIRE_136 node _out_uop_T_1652 = mux(_out_uop_T_1398, ram[0].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1653 = mux(_out_uop_T_1399, ram[1].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1654 = mux(_out_uop_T_1400, ram[2].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1655 = mux(_out_uop_T_1401, ram[3].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1656 = mux(_out_uop_T_1402, ram[4].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1657 = mux(_out_uop_T_1403, ram[5].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1658 = mux(_out_uop_T_1404, ram[6].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_1659 = or(_out_uop_T_1652, _out_uop_T_1653) node _out_uop_T_1660 = or(_out_uop_T_1659, _out_uop_T_1654) node _out_uop_T_1661 = or(_out_uop_T_1660, _out_uop_T_1655) node _out_uop_T_1662 = or(_out_uop_T_1661, _out_uop_T_1656) node _out_uop_T_1663 = or(_out_uop_T_1662, _out_uop_T_1657) node _out_uop_T_1664 = or(_out_uop_T_1663, _out_uop_T_1658) wire _out_uop_WIRE_137 : UInt<1> connect _out_uop_WIRE_137, _out_uop_T_1664 connect _out_uop_WIRE_119.swap23, _out_uop_WIRE_137 node _out_uop_T_1665 = mux(_out_uop_T_1398, ram[0].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1666 = mux(_out_uop_T_1399, ram[1].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1667 = mux(_out_uop_T_1400, ram[2].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1668 = mux(_out_uop_T_1401, ram[3].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1669 = mux(_out_uop_T_1402, ram[4].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1670 = mux(_out_uop_T_1403, ram[5].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1671 = mux(_out_uop_T_1404, ram[6].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_1672 = or(_out_uop_T_1665, _out_uop_T_1666) node _out_uop_T_1673 = or(_out_uop_T_1672, _out_uop_T_1667) node _out_uop_T_1674 = or(_out_uop_T_1673, _out_uop_T_1668) node _out_uop_T_1675 = or(_out_uop_T_1674, _out_uop_T_1669) node _out_uop_T_1676 = or(_out_uop_T_1675, _out_uop_T_1670) node _out_uop_T_1677 = or(_out_uop_T_1676, _out_uop_T_1671) wire _out_uop_WIRE_138 : UInt<1> connect _out_uop_WIRE_138, _out_uop_T_1677 connect _out_uop_WIRE_119.swap12, _out_uop_WIRE_138 node _out_uop_T_1678 = mux(_out_uop_T_1398, ram[0].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1679 = mux(_out_uop_T_1399, ram[1].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1680 = mux(_out_uop_T_1400, ram[2].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1681 = mux(_out_uop_T_1401, ram[3].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1682 = mux(_out_uop_T_1402, ram[4].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1683 = mux(_out_uop_T_1403, ram[5].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1684 = mux(_out_uop_T_1404, ram[6].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_1685 = or(_out_uop_T_1678, _out_uop_T_1679) node _out_uop_T_1686 = or(_out_uop_T_1685, _out_uop_T_1680) node _out_uop_T_1687 = or(_out_uop_T_1686, _out_uop_T_1681) node _out_uop_T_1688 = or(_out_uop_T_1687, _out_uop_T_1682) node _out_uop_T_1689 = or(_out_uop_T_1688, _out_uop_T_1683) node _out_uop_T_1690 = or(_out_uop_T_1689, _out_uop_T_1684) wire _out_uop_WIRE_139 : UInt<1> connect _out_uop_WIRE_139, _out_uop_T_1690 connect _out_uop_WIRE_119.ren3, _out_uop_WIRE_139 node _out_uop_T_1691 = mux(_out_uop_T_1398, ram[0].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1692 = mux(_out_uop_T_1399, ram[1].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1693 = mux(_out_uop_T_1400, ram[2].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1694 = mux(_out_uop_T_1401, ram[3].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1695 = mux(_out_uop_T_1402, ram[4].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1696 = mux(_out_uop_T_1403, ram[5].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1697 = mux(_out_uop_T_1404, ram[6].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_1698 = or(_out_uop_T_1691, _out_uop_T_1692) node _out_uop_T_1699 = or(_out_uop_T_1698, _out_uop_T_1693) node _out_uop_T_1700 = or(_out_uop_T_1699, _out_uop_T_1694) node _out_uop_T_1701 = or(_out_uop_T_1700, _out_uop_T_1695) node _out_uop_T_1702 = or(_out_uop_T_1701, _out_uop_T_1696) node _out_uop_T_1703 = or(_out_uop_T_1702, _out_uop_T_1697) wire _out_uop_WIRE_140 : UInt<1> connect _out_uop_WIRE_140, _out_uop_T_1703 connect _out_uop_WIRE_119.ren2, _out_uop_WIRE_140 node _out_uop_T_1704 = mux(_out_uop_T_1398, ram[0].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1705 = mux(_out_uop_T_1399, ram[1].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1706 = mux(_out_uop_T_1400, ram[2].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1707 = mux(_out_uop_T_1401, ram[3].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1708 = mux(_out_uop_T_1402, ram[4].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1709 = mux(_out_uop_T_1403, ram[5].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1710 = mux(_out_uop_T_1404, ram[6].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_1711 = or(_out_uop_T_1704, _out_uop_T_1705) node _out_uop_T_1712 = or(_out_uop_T_1711, _out_uop_T_1706) node _out_uop_T_1713 = or(_out_uop_T_1712, _out_uop_T_1707) node _out_uop_T_1714 = or(_out_uop_T_1713, _out_uop_T_1708) node _out_uop_T_1715 = or(_out_uop_T_1714, _out_uop_T_1709) node _out_uop_T_1716 = or(_out_uop_T_1715, _out_uop_T_1710) wire _out_uop_WIRE_141 : UInt<1> connect _out_uop_WIRE_141, _out_uop_T_1716 connect _out_uop_WIRE_119.ren1, _out_uop_WIRE_141 node _out_uop_T_1717 = mux(_out_uop_T_1398, ram[0].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1718 = mux(_out_uop_T_1399, ram[1].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1719 = mux(_out_uop_T_1400, ram[2].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1720 = mux(_out_uop_T_1401, ram[3].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1721 = mux(_out_uop_T_1402, ram[4].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1722 = mux(_out_uop_T_1403, ram[5].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1723 = mux(_out_uop_T_1404, ram[6].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_1724 = or(_out_uop_T_1717, _out_uop_T_1718) node _out_uop_T_1725 = or(_out_uop_T_1724, _out_uop_T_1719) node _out_uop_T_1726 = or(_out_uop_T_1725, _out_uop_T_1720) node _out_uop_T_1727 = or(_out_uop_T_1726, _out_uop_T_1721) node _out_uop_T_1728 = or(_out_uop_T_1727, _out_uop_T_1722) node _out_uop_T_1729 = or(_out_uop_T_1728, _out_uop_T_1723) wire _out_uop_WIRE_142 : UInt<1> connect _out_uop_WIRE_142, _out_uop_T_1729 connect _out_uop_WIRE_119.wen, _out_uop_WIRE_142 node _out_uop_T_1730 = mux(_out_uop_T_1398, ram[0].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1731 = mux(_out_uop_T_1399, ram[1].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1732 = mux(_out_uop_T_1400, ram[2].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1733 = mux(_out_uop_T_1401, ram[3].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1734 = mux(_out_uop_T_1402, ram[4].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1735 = mux(_out_uop_T_1403, ram[5].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1736 = mux(_out_uop_T_1404, ram[6].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_1737 = or(_out_uop_T_1730, _out_uop_T_1731) node _out_uop_T_1738 = or(_out_uop_T_1737, _out_uop_T_1732) node _out_uop_T_1739 = or(_out_uop_T_1738, _out_uop_T_1733) node _out_uop_T_1740 = or(_out_uop_T_1739, _out_uop_T_1734) node _out_uop_T_1741 = or(_out_uop_T_1740, _out_uop_T_1735) node _out_uop_T_1742 = or(_out_uop_T_1741, _out_uop_T_1736) wire _out_uop_WIRE_143 : UInt<1> connect _out_uop_WIRE_143, _out_uop_T_1742 connect _out_uop_WIRE_119.ldst, _out_uop_WIRE_143 connect _out_uop_WIRE_116.fdivin, _out_uop_WIRE_119 node _out_uop_T_1743 = mux(_out_uop_T_1398, ram[0].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1744 = mux(_out_uop_T_1399, ram[1].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1745 = mux(_out_uop_T_1400, ram[2].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1746 = mux(_out_uop_T_1401, ram[3].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1747 = mux(_out_uop_T_1402, ram[4].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1748 = mux(_out_uop_T_1403, ram[5].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1749 = mux(_out_uop_T_1404, ram[6].bits.fexc, UInt<1>(0h0)) node _out_uop_T_1750 = or(_out_uop_T_1743, _out_uop_T_1744) node _out_uop_T_1751 = or(_out_uop_T_1750, _out_uop_T_1745) node _out_uop_T_1752 = or(_out_uop_T_1751, _out_uop_T_1746) node _out_uop_T_1753 = or(_out_uop_T_1752, _out_uop_T_1747) node _out_uop_T_1754 = or(_out_uop_T_1753, _out_uop_T_1748) node _out_uop_T_1755 = or(_out_uop_T_1754, _out_uop_T_1749) wire _out_uop_WIRE_144 : UInt<5> connect _out_uop_WIRE_144, _out_uop_T_1755 connect _out_uop_WIRE_116.fexc, _out_uop_WIRE_144 node _out_uop_T_1756 = mux(_out_uop_T_1398, ram[0].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1757 = mux(_out_uop_T_1399, ram[1].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1758 = mux(_out_uop_T_1400, ram[2].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1759 = mux(_out_uop_T_1401, ram[3].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1760 = mux(_out_uop_T_1402, ram[4].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1761 = mux(_out_uop_T_1403, ram[5].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1762 = mux(_out_uop_T_1404, ram[6].bits.fra3, UInt<1>(0h0)) node _out_uop_T_1763 = or(_out_uop_T_1756, _out_uop_T_1757) node _out_uop_T_1764 = or(_out_uop_T_1763, _out_uop_T_1758) node _out_uop_T_1765 = or(_out_uop_T_1764, _out_uop_T_1759) node _out_uop_T_1766 = or(_out_uop_T_1765, _out_uop_T_1760) node _out_uop_T_1767 = or(_out_uop_T_1766, _out_uop_T_1761) node _out_uop_T_1768 = or(_out_uop_T_1767, _out_uop_T_1762) wire _out_uop_WIRE_145 : UInt<5> connect _out_uop_WIRE_145, _out_uop_T_1768 connect _out_uop_WIRE_116.fra3, _out_uop_WIRE_145 node _out_uop_T_1769 = mux(_out_uop_T_1398, ram[0].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1770 = mux(_out_uop_T_1399, ram[1].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1771 = mux(_out_uop_T_1400, ram[2].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1772 = mux(_out_uop_T_1401, ram[3].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1773 = mux(_out_uop_T_1402, ram[4].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1774 = mux(_out_uop_T_1403, ram[5].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1775 = mux(_out_uop_T_1404, ram[6].bits.fra2, UInt<1>(0h0)) node _out_uop_T_1776 = or(_out_uop_T_1769, _out_uop_T_1770) node _out_uop_T_1777 = or(_out_uop_T_1776, _out_uop_T_1771) node _out_uop_T_1778 = or(_out_uop_T_1777, _out_uop_T_1772) node _out_uop_T_1779 = or(_out_uop_T_1778, _out_uop_T_1773) node _out_uop_T_1780 = or(_out_uop_T_1779, _out_uop_T_1774) node _out_uop_T_1781 = or(_out_uop_T_1780, _out_uop_T_1775) wire _out_uop_WIRE_146 : UInt<5> connect _out_uop_WIRE_146, _out_uop_T_1781 connect _out_uop_WIRE_116.fra2, _out_uop_WIRE_146 node _out_uop_T_1782 = mux(_out_uop_T_1398, ram[0].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1783 = mux(_out_uop_T_1399, ram[1].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1784 = mux(_out_uop_T_1400, ram[2].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1785 = mux(_out_uop_T_1401, ram[3].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1786 = mux(_out_uop_T_1402, ram[4].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1787 = mux(_out_uop_T_1403, ram[5].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1788 = mux(_out_uop_T_1404, ram[6].bits.fra1, UInt<1>(0h0)) node _out_uop_T_1789 = or(_out_uop_T_1782, _out_uop_T_1783) node _out_uop_T_1790 = or(_out_uop_T_1789, _out_uop_T_1784) node _out_uop_T_1791 = or(_out_uop_T_1790, _out_uop_T_1785) node _out_uop_T_1792 = or(_out_uop_T_1791, _out_uop_T_1786) node _out_uop_T_1793 = or(_out_uop_T_1792, _out_uop_T_1787) node _out_uop_T_1794 = or(_out_uop_T_1793, _out_uop_T_1788) wire _out_uop_WIRE_147 : UInt<5> connect _out_uop_WIRE_147, _out_uop_T_1794 connect _out_uop_WIRE_116.fra1, _out_uop_WIRE_147 wire _out_uop_WIRE_148 : { valid : UInt<1>, bits : UInt<64>} node _out_uop_T_1795 = mux(_out_uop_T_1398, ram[0].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1796 = mux(_out_uop_T_1399, ram[1].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1797 = mux(_out_uop_T_1400, ram[2].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1798 = mux(_out_uop_T_1401, ram[3].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1799 = mux(_out_uop_T_1402, ram[4].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1800 = mux(_out_uop_T_1403, ram[5].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1801 = mux(_out_uop_T_1404, ram[6].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_1802 = or(_out_uop_T_1795, _out_uop_T_1796) node _out_uop_T_1803 = or(_out_uop_T_1802, _out_uop_T_1797) node _out_uop_T_1804 = or(_out_uop_T_1803, _out_uop_T_1798) node _out_uop_T_1805 = or(_out_uop_T_1804, _out_uop_T_1799) node _out_uop_T_1806 = or(_out_uop_T_1805, _out_uop_T_1800) node _out_uop_T_1807 = or(_out_uop_T_1806, _out_uop_T_1801) wire _out_uop_WIRE_149 : UInt<64> connect _out_uop_WIRE_149, _out_uop_T_1807 connect _out_uop_WIRE_148.bits, _out_uop_WIRE_149 node _out_uop_T_1808 = mux(_out_uop_T_1398, ram[0].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1809 = mux(_out_uop_T_1399, ram[1].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1810 = mux(_out_uop_T_1400, ram[2].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1811 = mux(_out_uop_T_1401, ram[3].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1812 = mux(_out_uop_T_1402, ram[4].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1813 = mux(_out_uop_T_1403, ram[5].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1814 = mux(_out_uop_T_1404, ram[6].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_1815 = or(_out_uop_T_1808, _out_uop_T_1809) node _out_uop_T_1816 = or(_out_uop_T_1815, _out_uop_T_1810) node _out_uop_T_1817 = or(_out_uop_T_1816, _out_uop_T_1811) node _out_uop_T_1818 = or(_out_uop_T_1817, _out_uop_T_1812) node _out_uop_T_1819 = or(_out_uop_T_1818, _out_uop_T_1813) node _out_uop_T_1820 = or(_out_uop_T_1819, _out_uop_T_1814) wire _out_uop_WIRE_150 : UInt<1> connect _out_uop_WIRE_150, _out_uop_T_1820 connect _out_uop_WIRE_148.valid, _out_uop_WIRE_150 connect _out_uop_WIRE_116.wdata, _out_uop_WIRE_148 node _out_uop_T_1821 = mux(_out_uop_T_1398, ram[0].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1822 = mux(_out_uop_T_1399, ram[1].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1823 = mux(_out_uop_T_1400, ram[2].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1824 = mux(_out_uop_T_1401, ram[3].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1825 = mux(_out_uop_T_1402, ram[4].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1826 = mux(_out_uop_T_1403, ram[5].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1827 = mux(_out_uop_T_1404, ram[6].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_1828 = or(_out_uop_T_1821, _out_uop_T_1822) node _out_uop_T_1829 = or(_out_uop_T_1828, _out_uop_T_1823) node _out_uop_T_1830 = or(_out_uop_T_1829, _out_uop_T_1824) node _out_uop_T_1831 = or(_out_uop_T_1830, _out_uop_T_1825) node _out_uop_T_1832 = or(_out_uop_T_1831, _out_uop_T_1826) node _out_uop_T_1833 = or(_out_uop_T_1832, _out_uop_T_1827) wire _out_uop_WIRE_151 : UInt<1> connect _out_uop_WIRE_151, _out_uop_T_1833 connect _out_uop_WIRE_116.uses_latealu, _out_uop_WIRE_151 node _out_uop_T_1834 = mux(_out_uop_T_1398, ram[0].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1835 = mux(_out_uop_T_1399, ram[1].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1836 = mux(_out_uop_T_1400, ram[2].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1837 = mux(_out_uop_T_1401, ram[3].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1838 = mux(_out_uop_T_1402, ram[4].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1839 = mux(_out_uop_T_1403, ram[5].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1840 = mux(_out_uop_T_1404, ram[6].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_1841 = or(_out_uop_T_1834, _out_uop_T_1835) node _out_uop_T_1842 = or(_out_uop_T_1841, _out_uop_T_1836) node _out_uop_T_1843 = or(_out_uop_T_1842, _out_uop_T_1837) node _out_uop_T_1844 = or(_out_uop_T_1843, _out_uop_T_1838) node _out_uop_T_1845 = or(_out_uop_T_1844, _out_uop_T_1839) node _out_uop_T_1846 = or(_out_uop_T_1845, _out_uop_T_1840) wire _out_uop_WIRE_152 : UInt<1> connect _out_uop_WIRE_152, _out_uop_T_1846 connect _out_uop_WIRE_116.uses_memalu, _out_uop_WIRE_152 node _out_uop_T_1847 = mux(_out_uop_T_1398, ram[0].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1848 = mux(_out_uop_T_1399, ram[1].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1849 = mux(_out_uop_T_1400, ram[2].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1850 = mux(_out_uop_T_1401, ram[3].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1851 = mux(_out_uop_T_1402, ram[4].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1852 = mux(_out_uop_T_1403, ram[5].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1853 = mux(_out_uop_T_1404, ram[6].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_1854 = or(_out_uop_T_1847, _out_uop_T_1848) node _out_uop_T_1855 = or(_out_uop_T_1854, _out_uop_T_1849) node _out_uop_T_1856 = or(_out_uop_T_1855, _out_uop_T_1850) node _out_uop_T_1857 = or(_out_uop_T_1856, _out_uop_T_1851) node _out_uop_T_1858 = or(_out_uop_T_1857, _out_uop_T_1852) node _out_uop_T_1859 = or(_out_uop_T_1858, _out_uop_T_1853) wire _out_uop_WIRE_153 : UInt<64> connect _out_uop_WIRE_153, _out_uop_T_1859 connect _out_uop_WIRE_116.rs3_data, _out_uop_WIRE_153 node _out_uop_T_1860 = mux(_out_uop_T_1398, ram[0].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1861 = mux(_out_uop_T_1399, ram[1].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1862 = mux(_out_uop_T_1400, ram[2].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1863 = mux(_out_uop_T_1401, ram[3].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1864 = mux(_out_uop_T_1402, ram[4].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1865 = mux(_out_uop_T_1403, ram[5].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1866 = mux(_out_uop_T_1404, ram[6].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_1867 = or(_out_uop_T_1860, _out_uop_T_1861) node _out_uop_T_1868 = or(_out_uop_T_1867, _out_uop_T_1862) node _out_uop_T_1869 = or(_out_uop_T_1868, _out_uop_T_1863) node _out_uop_T_1870 = or(_out_uop_T_1869, _out_uop_T_1864) node _out_uop_T_1871 = or(_out_uop_T_1870, _out_uop_T_1865) node _out_uop_T_1872 = or(_out_uop_T_1871, _out_uop_T_1866) wire _out_uop_WIRE_154 : UInt<64> connect _out_uop_WIRE_154, _out_uop_T_1872 connect _out_uop_WIRE_116.rs2_data, _out_uop_WIRE_154 node _out_uop_T_1873 = mux(_out_uop_T_1398, ram[0].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1874 = mux(_out_uop_T_1399, ram[1].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1875 = mux(_out_uop_T_1400, ram[2].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1876 = mux(_out_uop_T_1401, ram[3].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1877 = mux(_out_uop_T_1402, ram[4].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1878 = mux(_out_uop_T_1403, ram[5].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1879 = mux(_out_uop_T_1404, ram[6].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_1880 = or(_out_uop_T_1873, _out_uop_T_1874) node _out_uop_T_1881 = or(_out_uop_T_1880, _out_uop_T_1875) node _out_uop_T_1882 = or(_out_uop_T_1881, _out_uop_T_1876) node _out_uop_T_1883 = or(_out_uop_T_1882, _out_uop_T_1877) node _out_uop_T_1884 = or(_out_uop_T_1883, _out_uop_T_1878) node _out_uop_T_1885 = or(_out_uop_T_1884, _out_uop_T_1879) wire _out_uop_WIRE_155 : UInt<64> connect _out_uop_WIRE_155, _out_uop_T_1885 connect _out_uop_WIRE_116.rs1_data, _out_uop_WIRE_155 node _out_uop_T_1886 = mux(_out_uop_T_1398, ram[0].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1887 = mux(_out_uop_T_1399, ram[1].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1888 = mux(_out_uop_T_1400, ram[2].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1889 = mux(_out_uop_T_1401, ram[3].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1890 = mux(_out_uop_T_1402, ram[4].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1891 = mux(_out_uop_T_1403, ram[5].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1892 = mux(_out_uop_T_1404, ram[6].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_1893 = or(_out_uop_T_1886, _out_uop_T_1887) node _out_uop_T_1894 = or(_out_uop_T_1893, _out_uop_T_1888) node _out_uop_T_1895 = or(_out_uop_T_1894, _out_uop_T_1889) node _out_uop_T_1896 = or(_out_uop_T_1895, _out_uop_T_1890) node _out_uop_T_1897 = or(_out_uop_T_1896, _out_uop_T_1891) node _out_uop_T_1898 = or(_out_uop_T_1897, _out_uop_T_1892) wire _out_uop_WIRE_156 : UInt<1> connect _out_uop_WIRE_156, _out_uop_T_1898 connect _out_uop_WIRE_116.needs_replay, _out_uop_WIRE_156 node _out_uop_T_1899 = mux(_out_uop_T_1398, ram[0].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1900 = mux(_out_uop_T_1399, ram[1].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1901 = mux(_out_uop_T_1400, ram[2].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1902 = mux(_out_uop_T_1401, ram[3].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1903 = mux(_out_uop_T_1402, ram[4].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1904 = mux(_out_uop_T_1403, ram[5].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1905 = mux(_out_uop_T_1404, ram[6].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_1906 = or(_out_uop_T_1899, _out_uop_T_1900) node _out_uop_T_1907 = or(_out_uop_T_1906, _out_uop_T_1901) node _out_uop_T_1908 = or(_out_uop_T_1907, _out_uop_T_1902) node _out_uop_T_1909 = or(_out_uop_T_1908, _out_uop_T_1903) node _out_uop_T_1910 = or(_out_uop_T_1909, _out_uop_T_1904) node _out_uop_T_1911 = or(_out_uop_T_1910, _out_uop_T_1905) wire _out_uop_WIRE_157 : UInt<64> connect _out_uop_WIRE_157, _out_uop_T_1911 connect _out_uop_WIRE_116.xcpt_cause, _out_uop_WIRE_157 node _out_uop_T_1912 = mux(_out_uop_T_1398, ram[0].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1913 = mux(_out_uop_T_1399, ram[1].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1914 = mux(_out_uop_T_1400, ram[2].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1915 = mux(_out_uop_T_1401, ram[3].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1916 = mux(_out_uop_T_1402, ram[4].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1917 = mux(_out_uop_T_1403, ram[5].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1918 = mux(_out_uop_T_1404, ram[6].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_1919 = or(_out_uop_T_1912, _out_uop_T_1913) node _out_uop_T_1920 = or(_out_uop_T_1919, _out_uop_T_1914) node _out_uop_T_1921 = or(_out_uop_T_1920, _out_uop_T_1915) node _out_uop_T_1922 = or(_out_uop_T_1921, _out_uop_T_1916) node _out_uop_T_1923 = or(_out_uop_T_1922, _out_uop_T_1917) node _out_uop_T_1924 = or(_out_uop_T_1923, _out_uop_T_1918) wire _out_uop_WIRE_158 : UInt<1> connect _out_uop_WIRE_158, _out_uop_T_1924 connect _out_uop_WIRE_116.xcpt, _out_uop_WIRE_158 node _out_uop_T_1925 = mux(_out_uop_T_1398, ram[0].bits.taken, UInt<1>(0h0)) node _out_uop_T_1926 = mux(_out_uop_T_1399, ram[1].bits.taken, UInt<1>(0h0)) node _out_uop_T_1927 = mux(_out_uop_T_1400, ram[2].bits.taken, UInt<1>(0h0)) node _out_uop_T_1928 = mux(_out_uop_T_1401, ram[3].bits.taken, UInt<1>(0h0)) node _out_uop_T_1929 = mux(_out_uop_T_1402, ram[4].bits.taken, UInt<1>(0h0)) node _out_uop_T_1930 = mux(_out_uop_T_1403, ram[5].bits.taken, UInt<1>(0h0)) node _out_uop_T_1931 = mux(_out_uop_T_1404, ram[6].bits.taken, UInt<1>(0h0)) node _out_uop_T_1932 = or(_out_uop_T_1925, _out_uop_T_1926) node _out_uop_T_1933 = or(_out_uop_T_1932, _out_uop_T_1927) node _out_uop_T_1934 = or(_out_uop_T_1933, _out_uop_T_1928) node _out_uop_T_1935 = or(_out_uop_T_1934, _out_uop_T_1929) node _out_uop_T_1936 = or(_out_uop_T_1935, _out_uop_T_1930) node _out_uop_T_1937 = or(_out_uop_T_1936, _out_uop_T_1931) wire _out_uop_WIRE_159 : UInt<1> connect _out_uop_WIRE_159, _out_uop_T_1937 connect _out_uop_WIRE_116.taken, _out_uop_WIRE_159 node _out_uop_T_1938 = mux(_out_uop_T_1398, ram[0].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1939 = mux(_out_uop_T_1399, ram[1].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1940 = mux(_out_uop_T_1400, ram[2].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1941 = mux(_out_uop_T_1401, ram[3].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1942 = mux(_out_uop_T_1402, ram[4].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1943 = mux(_out_uop_T_1403, ram[5].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1944 = mux(_out_uop_T_1404, ram[6].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_1945 = or(_out_uop_T_1938, _out_uop_T_1939) node _out_uop_T_1946 = or(_out_uop_T_1945, _out_uop_T_1940) node _out_uop_T_1947 = or(_out_uop_T_1946, _out_uop_T_1941) node _out_uop_T_1948 = or(_out_uop_T_1947, _out_uop_T_1942) node _out_uop_T_1949 = or(_out_uop_T_1948, _out_uop_T_1943) node _out_uop_T_1950 = or(_out_uop_T_1949, _out_uop_T_1944) wire _out_uop_WIRE_160 : UInt<3> connect _out_uop_WIRE_160, _out_uop_T_1950 connect _out_uop_WIRE_116.ras_head, _out_uop_WIRE_160 wire _out_uop_WIRE_161 : { valid : UInt<1>, bits : UInt<40>} node _out_uop_T_1951 = mux(_out_uop_T_1398, ram[0].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1952 = mux(_out_uop_T_1399, ram[1].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1953 = mux(_out_uop_T_1400, ram[2].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1954 = mux(_out_uop_T_1401, ram[3].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1955 = mux(_out_uop_T_1402, ram[4].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1956 = mux(_out_uop_T_1403, ram[5].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1957 = mux(_out_uop_T_1404, ram[6].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_1958 = or(_out_uop_T_1951, _out_uop_T_1952) node _out_uop_T_1959 = or(_out_uop_T_1958, _out_uop_T_1953) node _out_uop_T_1960 = or(_out_uop_T_1959, _out_uop_T_1954) node _out_uop_T_1961 = or(_out_uop_T_1960, _out_uop_T_1955) node _out_uop_T_1962 = or(_out_uop_T_1961, _out_uop_T_1956) node _out_uop_T_1963 = or(_out_uop_T_1962, _out_uop_T_1957) wire _out_uop_WIRE_162 : UInt<40> connect _out_uop_WIRE_162, _out_uop_T_1963 connect _out_uop_WIRE_161.bits, _out_uop_WIRE_162 node _out_uop_T_1964 = mux(_out_uop_T_1398, ram[0].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1965 = mux(_out_uop_T_1399, ram[1].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1966 = mux(_out_uop_T_1400, ram[2].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1967 = mux(_out_uop_T_1401, ram[3].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1968 = mux(_out_uop_T_1402, ram[4].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1969 = mux(_out_uop_T_1403, ram[5].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1970 = mux(_out_uop_T_1404, ram[6].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_1971 = or(_out_uop_T_1964, _out_uop_T_1965) node _out_uop_T_1972 = or(_out_uop_T_1971, _out_uop_T_1966) node _out_uop_T_1973 = or(_out_uop_T_1972, _out_uop_T_1967) node _out_uop_T_1974 = or(_out_uop_T_1973, _out_uop_T_1968) node _out_uop_T_1975 = or(_out_uop_T_1974, _out_uop_T_1969) node _out_uop_T_1976 = or(_out_uop_T_1975, _out_uop_T_1970) wire _out_uop_WIRE_163 : UInt<1> connect _out_uop_WIRE_163, _out_uop_T_1976 connect _out_uop_WIRE_161.valid, _out_uop_WIRE_163 connect _out_uop_WIRE_116.next_pc, _out_uop_WIRE_161 node _out_uop_T_1977 = mux(_out_uop_T_1398, ram[0].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1978 = mux(_out_uop_T_1399, ram[1].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1979 = mux(_out_uop_T_1400, ram[2].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1980 = mux(_out_uop_T_1401, ram[3].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1981 = mux(_out_uop_T_1402, ram[4].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1982 = mux(_out_uop_T_1403, ram[5].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1983 = mux(_out_uop_T_1404, ram[6].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_1984 = or(_out_uop_T_1977, _out_uop_T_1978) node _out_uop_T_1985 = or(_out_uop_T_1984, _out_uop_T_1979) node _out_uop_T_1986 = or(_out_uop_T_1985, _out_uop_T_1980) node _out_uop_T_1987 = or(_out_uop_T_1986, _out_uop_T_1981) node _out_uop_T_1988 = or(_out_uop_T_1987, _out_uop_T_1982) node _out_uop_T_1989 = or(_out_uop_T_1988, _out_uop_T_1983) wire _out_uop_WIRE_164 : UInt<1> connect _out_uop_WIRE_164, _out_uop_T_1989 connect _out_uop_WIRE_116.sfb_shadow, _out_uop_WIRE_164 node _out_uop_T_1990 = mux(_out_uop_T_1398, ram[0].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1991 = mux(_out_uop_T_1399, ram[1].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1992 = mux(_out_uop_T_1400, ram[2].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1993 = mux(_out_uop_T_1401, ram[3].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1994 = mux(_out_uop_T_1402, ram[4].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1995 = mux(_out_uop_T_1403, ram[5].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1996 = mux(_out_uop_T_1404, ram[6].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_1997 = or(_out_uop_T_1990, _out_uop_T_1991) node _out_uop_T_1998 = or(_out_uop_T_1997, _out_uop_T_1992) node _out_uop_T_1999 = or(_out_uop_T_1998, _out_uop_T_1993) node _out_uop_T_2000 = or(_out_uop_T_1999, _out_uop_T_1994) node _out_uop_T_2001 = or(_out_uop_T_2000, _out_uop_T_1995) node _out_uop_T_2002 = or(_out_uop_T_2001, _out_uop_T_1996) wire _out_uop_WIRE_165 : UInt<1> connect _out_uop_WIRE_165, _out_uop_T_2002 connect _out_uop_WIRE_116.sfb_br, _out_uop_WIRE_165 wire _out_uop_WIRE_166 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _out_uop_WIRE_167 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _out_uop_WIRE_168 : { history : UInt<8>, value : UInt<2>} node _out_uop_T_2003 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2004 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2005 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2006 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2007 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2008 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2009 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_2010 = or(_out_uop_T_2003, _out_uop_T_2004) node _out_uop_T_2011 = or(_out_uop_T_2010, _out_uop_T_2005) node _out_uop_T_2012 = or(_out_uop_T_2011, _out_uop_T_2006) node _out_uop_T_2013 = or(_out_uop_T_2012, _out_uop_T_2007) node _out_uop_T_2014 = or(_out_uop_T_2013, _out_uop_T_2008) node _out_uop_T_2015 = or(_out_uop_T_2014, _out_uop_T_2009) wire _out_uop_WIRE_169 : UInt<2> connect _out_uop_WIRE_169, _out_uop_T_2015 connect _out_uop_WIRE_168.value, _out_uop_WIRE_169 node _out_uop_T_2016 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2017 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2018 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2019 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2020 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2021 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2022 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_2023 = or(_out_uop_T_2016, _out_uop_T_2017) node _out_uop_T_2024 = or(_out_uop_T_2023, _out_uop_T_2018) node _out_uop_T_2025 = or(_out_uop_T_2024, _out_uop_T_2019) node _out_uop_T_2026 = or(_out_uop_T_2025, _out_uop_T_2020) node _out_uop_T_2027 = or(_out_uop_T_2026, _out_uop_T_2021) node _out_uop_T_2028 = or(_out_uop_T_2027, _out_uop_T_2022) wire _out_uop_WIRE_170 : UInt<8> connect _out_uop_WIRE_170, _out_uop_T_2028 connect _out_uop_WIRE_168.history, _out_uop_WIRE_170 connect _out_uop_WIRE_167.bht, _out_uop_WIRE_168 node _out_uop_T_2029 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2030 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2031 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2032 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2033 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2034 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2035 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_2036 = or(_out_uop_T_2029, _out_uop_T_2030) node _out_uop_T_2037 = or(_out_uop_T_2036, _out_uop_T_2031) node _out_uop_T_2038 = or(_out_uop_T_2037, _out_uop_T_2032) node _out_uop_T_2039 = or(_out_uop_T_2038, _out_uop_T_2033) node _out_uop_T_2040 = or(_out_uop_T_2039, _out_uop_T_2034) node _out_uop_T_2041 = or(_out_uop_T_2040, _out_uop_T_2035) wire _out_uop_WIRE_171 : UInt<6> connect _out_uop_WIRE_171, _out_uop_T_2041 connect _out_uop_WIRE_167.entry, _out_uop_WIRE_171 node _out_uop_T_2042 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2043 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2044 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2045 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2046 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2047 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2048 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_2049 = or(_out_uop_T_2042, _out_uop_T_2043) node _out_uop_T_2050 = or(_out_uop_T_2049, _out_uop_T_2044) node _out_uop_T_2051 = or(_out_uop_T_2050, _out_uop_T_2045) node _out_uop_T_2052 = or(_out_uop_T_2051, _out_uop_T_2046) node _out_uop_T_2053 = or(_out_uop_T_2052, _out_uop_T_2047) node _out_uop_T_2054 = or(_out_uop_T_2053, _out_uop_T_2048) wire _out_uop_WIRE_172 : UInt<39> connect _out_uop_WIRE_172, _out_uop_T_2054 connect _out_uop_WIRE_167.target, _out_uop_WIRE_172 node _out_uop_T_2055 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2056 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2057 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2058 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2059 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2060 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2061 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_2062 = or(_out_uop_T_2055, _out_uop_T_2056) node _out_uop_T_2063 = or(_out_uop_T_2062, _out_uop_T_2057) node _out_uop_T_2064 = or(_out_uop_T_2063, _out_uop_T_2058) node _out_uop_T_2065 = or(_out_uop_T_2064, _out_uop_T_2059) node _out_uop_T_2066 = or(_out_uop_T_2065, _out_uop_T_2060) node _out_uop_T_2067 = or(_out_uop_T_2066, _out_uop_T_2061) wire _out_uop_WIRE_173 : UInt<2> connect _out_uop_WIRE_173, _out_uop_T_2067 connect _out_uop_WIRE_167.bridx, _out_uop_WIRE_173 node _out_uop_T_2068 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2069 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2070 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2071 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2072 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2073 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2074 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_2075 = or(_out_uop_T_2068, _out_uop_T_2069) node _out_uop_T_2076 = or(_out_uop_T_2075, _out_uop_T_2070) node _out_uop_T_2077 = or(_out_uop_T_2076, _out_uop_T_2071) node _out_uop_T_2078 = or(_out_uop_T_2077, _out_uop_T_2072) node _out_uop_T_2079 = or(_out_uop_T_2078, _out_uop_T_2073) node _out_uop_T_2080 = or(_out_uop_T_2079, _out_uop_T_2074) wire _out_uop_WIRE_174 : UInt<4> connect _out_uop_WIRE_174, _out_uop_T_2080 connect _out_uop_WIRE_167.mask, _out_uop_WIRE_174 node _out_uop_T_2081 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2082 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2083 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2084 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2085 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2086 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2087 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_2088 = or(_out_uop_T_2081, _out_uop_T_2082) node _out_uop_T_2089 = or(_out_uop_T_2088, _out_uop_T_2083) node _out_uop_T_2090 = or(_out_uop_T_2089, _out_uop_T_2084) node _out_uop_T_2091 = or(_out_uop_T_2090, _out_uop_T_2085) node _out_uop_T_2092 = or(_out_uop_T_2091, _out_uop_T_2086) node _out_uop_T_2093 = or(_out_uop_T_2092, _out_uop_T_2087) wire _out_uop_WIRE_175 : UInt<1> connect _out_uop_WIRE_175, _out_uop_T_2093 connect _out_uop_WIRE_167.taken, _out_uop_WIRE_175 node _out_uop_T_2094 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2095 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2096 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2097 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2098 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2099 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2100 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_2101 = or(_out_uop_T_2094, _out_uop_T_2095) node _out_uop_T_2102 = or(_out_uop_T_2101, _out_uop_T_2096) node _out_uop_T_2103 = or(_out_uop_T_2102, _out_uop_T_2097) node _out_uop_T_2104 = or(_out_uop_T_2103, _out_uop_T_2098) node _out_uop_T_2105 = or(_out_uop_T_2104, _out_uop_T_2099) node _out_uop_T_2106 = or(_out_uop_T_2105, _out_uop_T_2100) wire _out_uop_WIRE_176 : UInt<2> connect _out_uop_WIRE_176, _out_uop_T_2106 connect _out_uop_WIRE_167.cfiType, _out_uop_WIRE_176 connect _out_uop_WIRE_166.bits, _out_uop_WIRE_167 node _out_uop_T_2107 = mux(_out_uop_T_1398, ram[0].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2108 = mux(_out_uop_T_1399, ram[1].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2109 = mux(_out_uop_T_1400, ram[2].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2110 = mux(_out_uop_T_1401, ram[3].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2111 = mux(_out_uop_T_1402, ram[4].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2112 = mux(_out_uop_T_1403, ram[5].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2113 = mux(_out_uop_T_1404, ram[6].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_2114 = or(_out_uop_T_2107, _out_uop_T_2108) node _out_uop_T_2115 = or(_out_uop_T_2114, _out_uop_T_2109) node _out_uop_T_2116 = or(_out_uop_T_2115, _out_uop_T_2110) node _out_uop_T_2117 = or(_out_uop_T_2116, _out_uop_T_2111) node _out_uop_T_2118 = or(_out_uop_T_2117, _out_uop_T_2112) node _out_uop_T_2119 = or(_out_uop_T_2118, _out_uop_T_2113) wire _out_uop_WIRE_177 : UInt<1> connect _out_uop_WIRE_177, _out_uop_T_2119 connect _out_uop_WIRE_166.valid, _out_uop_WIRE_177 connect _out_uop_WIRE_116.btb_resp, _out_uop_WIRE_166 node _out_uop_T_2120 = mux(_out_uop_T_1398, ram[0].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2121 = mux(_out_uop_T_1399, ram[1].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2122 = mux(_out_uop_T_1400, ram[2].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2123 = mux(_out_uop_T_1401, ram[3].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2124 = mux(_out_uop_T_1402, ram[4].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2125 = mux(_out_uop_T_1403, ram[5].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2126 = mux(_out_uop_T_1404, ram[6].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_2127 = or(_out_uop_T_2120, _out_uop_T_2121) node _out_uop_T_2128 = or(_out_uop_T_2127, _out_uop_T_2122) node _out_uop_T_2129 = or(_out_uop_T_2128, _out_uop_T_2123) node _out_uop_T_2130 = or(_out_uop_T_2129, _out_uop_T_2124) node _out_uop_T_2131 = or(_out_uop_T_2130, _out_uop_T_2125) node _out_uop_T_2132 = or(_out_uop_T_2131, _out_uop_T_2126) wire _out_uop_WIRE_178 : UInt<1> connect _out_uop_WIRE_178, _out_uop_T_2132 connect _out_uop_WIRE_116.sets_vcfg, _out_uop_WIRE_178 node _out_uop_T_2133 = mux(_out_uop_T_1398, ram[0].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2134 = mux(_out_uop_T_1399, ram[1].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2135 = mux(_out_uop_T_1400, ram[2].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2136 = mux(_out_uop_T_1401, ram[3].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2137 = mux(_out_uop_T_1402, ram[4].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2138 = mux(_out_uop_T_1403, ram[5].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2139 = mux(_out_uop_T_1404, ram[6].bits.rvc, UInt<1>(0h0)) node _out_uop_T_2140 = or(_out_uop_T_2133, _out_uop_T_2134) node _out_uop_T_2141 = or(_out_uop_T_2140, _out_uop_T_2135) node _out_uop_T_2142 = or(_out_uop_T_2141, _out_uop_T_2136) node _out_uop_T_2143 = or(_out_uop_T_2142, _out_uop_T_2137) node _out_uop_T_2144 = or(_out_uop_T_2143, _out_uop_T_2138) node _out_uop_T_2145 = or(_out_uop_T_2144, _out_uop_T_2139) wire _out_uop_WIRE_179 : UInt<1> connect _out_uop_WIRE_179, _out_uop_T_2145 connect _out_uop_WIRE_116.rvc, _out_uop_WIRE_179 wire _out_uop_WIRE_180 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _out_uop_T_2146 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2147 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2148 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2149 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2150 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2151 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2152 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2153 = or(_out_uop_T_2146, _out_uop_T_2147) node _out_uop_T_2154 = or(_out_uop_T_2153, _out_uop_T_2148) node _out_uop_T_2155 = or(_out_uop_T_2154, _out_uop_T_2149) node _out_uop_T_2156 = or(_out_uop_T_2155, _out_uop_T_2150) node _out_uop_T_2157 = or(_out_uop_T_2156, _out_uop_T_2151) node _out_uop_T_2158 = or(_out_uop_T_2157, _out_uop_T_2152) wire _out_uop_WIRE_181 : UInt<1> connect _out_uop_WIRE_181, _out_uop_T_2158 connect _out_uop_WIRE_180.vec, _out_uop_WIRE_181 node _out_uop_T_2159 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2160 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2161 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2162 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2163 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2164 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2165 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_2166 = or(_out_uop_T_2159, _out_uop_T_2160) node _out_uop_T_2167 = or(_out_uop_T_2166, _out_uop_T_2161) node _out_uop_T_2168 = or(_out_uop_T_2167, _out_uop_T_2162) node _out_uop_T_2169 = or(_out_uop_T_2168, _out_uop_T_2163) node _out_uop_T_2170 = or(_out_uop_T_2169, _out_uop_T_2164) node _out_uop_T_2171 = or(_out_uop_T_2170, _out_uop_T_2165) wire _out_uop_WIRE_182 : UInt<1> connect _out_uop_WIRE_182, _out_uop_T_2171 connect _out_uop_WIRE_180.wflags, _out_uop_WIRE_182 node _out_uop_T_2172 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2173 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2174 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2175 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2176 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2177 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2178 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_2179 = or(_out_uop_T_2172, _out_uop_T_2173) node _out_uop_T_2180 = or(_out_uop_T_2179, _out_uop_T_2174) node _out_uop_T_2181 = or(_out_uop_T_2180, _out_uop_T_2175) node _out_uop_T_2182 = or(_out_uop_T_2181, _out_uop_T_2176) node _out_uop_T_2183 = or(_out_uop_T_2182, _out_uop_T_2177) node _out_uop_T_2184 = or(_out_uop_T_2183, _out_uop_T_2178) wire _out_uop_WIRE_183 : UInt<1> connect _out_uop_WIRE_183, _out_uop_T_2184 connect _out_uop_WIRE_180.sqrt, _out_uop_WIRE_183 node _out_uop_T_2185 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2186 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2187 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2188 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2189 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2190 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2191 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_2192 = or(_out_uop_T_2185, _out_uop_T_2186) node _out_uop_T_2193 = or(_out_uop_T_2192, _out_uop_T_2187) node _out_uop_T_2194 = or(_out_uop_T_2193, _out_uop_T_2188) node _out_uop_T_2195 = or(_out_uop_T_2194, _out_uop_T_2189) node _out_uop_T_2196 = or(_out_uop_T_2195, _out_uop_T_2190) node _out_uop_T_2197 = or(_out_uop_T_2196, _out_uop_T_2191) wire _out_uop_WIRE_184 : UInt<1> connect _out_uop_WIRE_184, _out_uop_T_2197 connect _out_uop_WIRE_180.div, _out_uop_WIRE_184 node _out_uop_T_2198 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2199 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2200 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2201 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2202 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2203 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2204 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_2205 = or(_out_uop_T_2198, _out_uop_T_2199) node _out_uop_T_2206 = or(_out_uop_T_2205, _out_uop_T_2200) node _out_uop_T_2207 = or(_out_uop_T_2206, _out_uop_T_2201) node _out_uop_T_2208 = or(_out_uop_T_2207, _out_uop_T_2202) node _out_uop_T_2209 = or(_out_uop_T_2208, _out_uop_T_2203) node _out_uop_T_2210 = or(_out_uop_T_2209, _out_uop_T_2204) wire _out_uop_WIRE_185 : UInt<1> connect _out_uop_WIRE_185, _out_uop_T_2210 connect _out_uop_WIRE_180.fma, _out_uop_WIRE_185 node _out_uop_T_2211 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2212 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2213 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2214 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2215 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2216 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2217 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_2218 = or(_out_uop_T_2211, _out_uop_T_2212) node _out_uop_T_2219 = or(_out_uop_T_2218, _out_uop_T_2213) node _out_uop_T_2220 = or(_out_uop_T_2219, _out_uop_T_2214) node _out_uop_T_2221 = or(_out_uop_T_2220, _out_uop_T_2215) node _out_uop_T_2222 = or(_out_uop_T_2221, _out_uop_T_2216) node _out_uop_T_2223 = or(_out_uop_T_2222, _out_uop_T_2217) wire _out_uop_WIRE_186 : UInt<1> connect _out_uop_WIRE_186, _out_uop_T_2223 connect _out_uop_WIRE_180.fastpipe, _out_uop_WIRE_186 node _out_uop_T_2224 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2225 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2226 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2227 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2228 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2229 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2230 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_2231 = or(_out_uop_T_2224, _out_uop_T_2225) node _out_uop_T_2232 = or(_out_uop_T_2231, _out_uop_T_2226) node _out_uop_T_2233 = or(_out_uop_T_2232, _out_uop_T_2227) node _out_uop_T_2234 = or(_out_uop_T_2233, _out_uop_T_2228) node _out_uop_T_2235 = or(_out_uop_T_2234, _out_uop_T_2229) node _out_uop_T_2236 = or(_out_uop_T_2235, _out_uop_T_2230) wire _out_uop_WIRE_187 : UInt<1> connect _out_uop_WIRE_187, _out_uop_T_2236 connect _out_uop_WIRE_180.toint, _out_uop_WIRE_187 node _out_uop_T_2237 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2238 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2239 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2240 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2241 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2242 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2243 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_2244 = or(_out_uop_T_2237, _out_uop_T_2238) node _out_uop_T_2245 = or(_out_uop_T_2244, _out_uop_T_2239) node _out_uop_T_2246 = or(_out_uop_T_2245, _out_uop_T_2240) node _out_uop_T_2247 = or(_out_uop_T_2246, _out_uop_T_2241) node _out_uop_T_2248 = or(_out_uop_T_2247, _out_uop_T_2242) node _out_uop_T_2249 = or(_out_uop_T_2248, _out_uop_T_2243) wire _out_uop_WIRE_188 : UInt<1> connect _out_uop_WIRE_188, _out_uop_T_2249 connect _out_uop_WIRE_180.fromint, _out_uop_WIRE_188 node _out_uop_T_2250 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2251 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2252 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2253 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2254 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2255 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2256 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_2257 = or(_out_uop_T_2250, _out_uop_T_2251) node _out_uop_T_2258 = or(_out_uop_T_2257, _out_uop_T_2252) node _out_uop_T_2259 = or(_out_uop_T_2258, _out_uop_T_2253) node _out_uop_T_2260 = or(_out_uop_T_2259, _out_uop_T_2254) node _out_uop_T_2261 = or(_out_uop_T_2260, _out_uop_T_2255) node _out_uop_T_2262 = or(_out_uop_T_2261, _out_uop_T_2256) wire _out_uop_WIRE_189 : UInt<2> connect _out_uop_WIRE_189, _out_uop_T_2262 connect _out_uop_WIRE_180.typeTagOut, _out_uop_WIRE_189 node _out_uop_T_2263 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2264 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2265 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2266 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2267 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2268 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2269 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_2270 = or(_out_uop_T_2263, _out_uop_T_2264) node _out_uop_T_2271 = or(_out_uop_T_2270, _out_uop_T_2265) node _out_uop_T_2272 = or(_out_uop_T_2271, _out_uop_T_2266) node _out_uop_T_2273 = or(_out_uop_T_2272, _out_uop_T_2267) node _out_uop_T_2274 = or(_out_uop_T_2273, _out_uop_T_2268) node _out_uop_T_2275 = or(_out_uop_T_2274, _out_uop_T_2269) wire _out_uop_WIRE_190 : UInt<2> connect _out_uop_WIRE_190, _out_uop_T_2275 connect _out_uop_WIRE_180.typeTagIn, _out_uop_WIRE_190 node _out_uop_T_2276 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2277 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2278 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2279 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2280 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2281 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2282 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_2283 = or(_out_uop_T_2276, _out_uop_T_2277) node _out_uop_T_2284 = or(_out_uop_T_2283, _out_uop_T_2278) node _out_uop_T_2285 = or(_out_uop_T_2284, _out_uop_T_2279) node _out_uop_T_2286 = or(_out_uop_T_2285, _out_uop_T_2280) node _out_uop_T_2287 = or(_out_uop_T_2286, _out_uop_T_2281) node _out_uop_T_2288 = or(_out_uop_T_2287, _out_uop_T_2282) wire _out_uop_WIRE_191 : UInt<1> connect _out_uop_WIRE_191, _out_uop_T_2288 connect _out_uop_WIRE_180.swap23, _out_uop_WIRE_191 node _out_uop_T_2289 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2290 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2291 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2292 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2293 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2294 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2295 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_2296 = or(_out_uop_T_2289, _out_uop_T_2290) node _out_uop_T_2297 = or(_out_uop_T_2296, _out_uop_T_2291) node _out_uop_T_2298 = or(_out_uop_T_2297, _out_uop_T_2292) node _out_uop_T_2299 = or(_out_uop_T_2298, _out_uop_T_2293) node _out_uop_T_2300 = or(_out_uop_T_2299, _out_uop_T_2294) node _out_uop_T_2301 = or(_out_uop_T_2300, _out_uop_T_2295) wire _out_uop_WIRE_192 : UInt<1> connect _out_uop_WIRE_192, _out_uop_T_2301 connect _out_uop_WIRE_180.swap12, _out_uop_WIRE_192 node _out_uop_T_2302 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2303 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2304 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2305 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2306 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2307 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2308 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_2309 = or(_out_uop_T_2302, _out_uop_T_2303) node _out_uop_T_2310 = or(_out_uop_T_2309, _out_uop_T_2304) node _out_uop_T_2311 = or(_out_uop_T_2310, _out_uop_T_2305) node _out_uop_T_2312 = or(_out_uop_T_2311, _out_uop_T_2306) node _out_uop_T_2313 = or(_out_uop_T_2312, _out_uop_T_2307) node _out_uop_T_2314 = or(_out_uop_T_2313, _out_uop_T_2308) wire _out_uop_WIRE_193 : UInt<1> connect _out_uop_WIRE_193, _out_uop_T_2314 connect _out_uop_WIRE_180.ren3, _out_uop_WIRE_193 node _out_uop_T_2315 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2316 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2317 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2318 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2319 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2320 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2321 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_2322 = or(_out_uop_T_2315, _out_uop_T_2316) node _out_uop_T_2323 = or(_out_uop_T_2322, _out_uop_T_2317) node _out_uop_T_2324 = or(_out_uop_T_2323, _out_uop_T_2318) node _out_uop_T_2325 = or(_out_uop_T_2324, _out_uop_T_2319) node _out_uop_T_2326 = or(_out_uop_T_2325, _out_uop_T_2320) node _out_uop_T_2327 = or(_out_uop_T_2326, _out_uop_T_2321) wire _out_uop_WIRE_194 : UInt<1> connect _out_uop_WIRE_194, _out_uop_T_2327 connect _out_uop_WIRE_180.ren2, _out_uop_WIRE_194 node _out_uop_T_2328 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2329 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2330 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2331 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2332 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2333 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2334 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_2335 = or(_out_uop_T_2328, _out_uop_T_2329) node _out_uop_T_2336 = or(_out_uop_T_2335, _out_uop_T_2330) node _out_uop_T_2337 = or(_out_uop_T_2336, _out_uop_T_2331) node _out_uop_T_2338 = or(_out_uop_T_2337, _out_uop_T_2332) node _out_uop_T_2339 = or(_out_uop_T_2338, _out_uop_T_2333) node _out_uop_T_2340 = or(_out_uop_T_2339, _out_uop_T_2334) wire _out_uop_WIRE_195 : UInt<1> connect _out_uop_WIRE_195, _out_uop_T_2340 connect _out_uop_WIRE_180.ren1, _out_uop_WIRE_195 node _out_uop_T_2341 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2342 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2343 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2344 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2345 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2346 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2347 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_2348 = or(_out_uop_T_2341, _out_uop_T_2342) node _out_uop_T_2349 = or(_out_uop_T_2348, _out_uop_T_2343) node _out_uop_T_2350 = or(_out_uop_T_2349, _out_uop_T_2344) node _out_uop_T_2351 = or(_out_uop_T_2350, _out_uop_T_2345) node _out_uop_T_2352 = or(_out_uop_T_2351, _out_uop_T_2346) node _out_uop_T_2353 = or(_out_uop_T_2352, _out_uop_T_2347) wire _out_uop_WIRE_196 : UInt<1> connect _out_uop_WIRE_196, _out_uop_T_2353 connect _out_uop_WIRE_180.wen, _out_uop_WIRE_196 node _out_uop_T_2354 = mux(_out_uop_T_1398, ram[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2355 = mux(_out_uop_T_1399, ram[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2356 = mux(_out_uop_T_1400, ram[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2357 = mux(_out_uop_T_1401, ram[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2358 = mux(_out_uop_T_1402, ram[4].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2359 = mux(_out_uop_T_1403, ram[5].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2360 = mux(_out_uop_T_1404, ram[6].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_2361 = or(_out_uop_T_2354, _out_uop_T_2355) node _out_uop_T_2362 = or(_out_uop_T_2361, _out_uop_T_2356) node _out_uop_T_2363 = or(_out_uop_T_2362, _out_uop_T_2357) node _out_uop_T_2364 = or(_out_uop_T_2363, _out_uop_T_2358) node _out_uop_T_2365 = or(_out_uop_T_2364, _out_uop_T_2359) node _out_uop_T_2366 = or(_out_uop_T_2365, _out_uop_T_2360) wire _out_uop_WIRE_197 : UInt<1> connect _out_uop_WIRE_197, _out_uop_T_2366 connect _out_uop_WIRE_180.ldst, _out_uop_WIRE_197 connect _out_uop_WIRE_116.fp_ctrl, _out_uop_WIRE_180 wire _out_uop_WIRE_198 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _out_uop_T_2367 = mux(_out_uop_T_1398, ram[0].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2368 = mux(_out_uop_T_1399, ram[1].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2369 = mux(_out_uop_T_1400, ram[2].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2370 = mux(_out_uop_T_1401, ram[3].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2371 = mux(_out_uop_T_1402, ram[4].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2372 = mux(_out_uop_T_1403, ram[5].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2373 = mux(_out_uop_T_1404, ram[6].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_2374 = or(_out_uop_T_2367, _out_uop_T_2368) node _out_uop_T_2375 = or(_out_uop_T_2374, _out_uop_T_2369) node _out_uop_T_2376 = or(_out_uop_T_2375, _out_uop_T_2370) node _out_uop_T_2377 = or(_out_uop_T_2376, _out_uop_T_2371) node _out_uop_T_2378 = or(_out_uop_T_2377, _out_uop_T_2372) node _out_uop_T_2379 = or(_out_uop_T_2378, _out_uop_T_2373) wire _out_uop_WIRE_199 : UInt<1> connect _out_uop_WIRE_199, _out_uop_T_2379 connect _out_uop_WIRE_198.vec, _out_uop_WIRE_199 node _out_uop_T_2380 = mux(_out_uop_T_1398, ram[0].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2381 = mux(_out_uop_T_1399, ram[1].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2382 = mux(_out_uop_T_1400, ram[2].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2383 = mux(_out_uop_T_1401, ram[3].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2384 = mux(_out_uop_T_1402, ram[4].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2385 = mux(_out_uop_T_1403, ram[5].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2386 = mux(_out_uop_T_1404, ram[6].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_2387 = or(_out_uop_T_2380, _out_uop_T_2381) node _out_uop_T_2388 = or(_out_uop_T_2387, _out_uop_T_2382) node _out_uop_T_2389 = or(_out_uop_T_2388, _out_uop_T_2383) node _out_uop_T_2390 = or(_out_uop_T_2389, _out_uop_T_2384) node _out_uop_T_2391 = or(_out_uop_T_2390, _out_uop_T_2385) node _out_uop_T_2392 = or(_out_uop_T_2391, _out_uop_T_2386) wire _out_uop_WIRE_200 : UInt<1> connect _out_uop_WIRE_200, _out_uop_T_2392 connect _out_uop_WIRE_198.dp, _out_uop_WIRE_200 node _out_uop_T_2393 = mux(_out_uop_T_1398, ram[0].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2394 = mux(_out_uop_T_1399, ram[1].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2395 = mux(_out_uop_T_1400, ram[2].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2396 = mux(_out_uop_T_1401, ram[3].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2397 = mux(_out_uop_T_1402, ram[4].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2398 = mux(_out_uop_T_1403, ram[5].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2399 = mux(_out_uop_T_1404, ram[6].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_2400 = or(_out_uop_T_2393, _out_uop_T_2394) node _out_uop_T_2401 = or(_out_uop_T_2400, _out_uop_T_2395) node _out_uop_T_2402 = or(_out_uop_T_2401, _out_uop_T_2396) node _out_uop_T_2403 = or(_out_uop_T_2402, _out_uop_T_2397) node _out_uop_T_2404 = or(_out_uop_T_2403, _out_uop_T_2398) node _out_uop_T_2405 = or(_out_uop_T_2404, _out_uop_T_2399) wire _out_uop_WIRE_201 : UInt<1> connect _out_uop_WIRE_201, _out_uop_T_2405 connect _out_uop_WIRE_198.amo, _out_uop_WIRE_201 node _out_uop_T_2406 = mux(_out_uop_T_1398, ram[0].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2407 = mux(_out_uop_T_1399, ram[1].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2408 = mux(_out_uop_T_1400, ram[2].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2409 = mux(_out_uop_T_1401, ram[3].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2410 = mux(_out_uop_T_1402, ram[4].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2411 = mux(_out_uop_T_1403, ram[5].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2412 = mux(_out_uop_T_1404, ram[6].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_2413 = or(_out_uop_T_2406, _out_uop_T_2407) node _out_uop_T_2414 = or(_out_uop_T_2413, _out_uop_T_2408) node _out_uop_T_2415 = or(_out_uop_T_2414, _out_uop_T_2409) node _out_uop_T_2416 = or(_out_uop_T_2415, _out_uop_T_2410) node _out_uop_T_2417 = or(_out_uop_T_2416, _out_uop_T_2411) node _out_uop_T_2418 = or(_out_uop_T_2417, _out_uop_T_2412) wire _out_uop_WIRE_202 : UInt<1> connect _out_uop_WIRE_202, _out_uop_T_2418 connect _out_uop_WIRE_198.fence, _out_uop_WIRE_202 node _out_uop_T_2419 = mux(_out_uop_T_1398, ram[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2420 = mux(_out_uop_T_1399, ram[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2421 = mux(_out_uop_T_1400, ram[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2422 = mux(_out_uop_T_1401, ram[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2423 = mux(_out_uop_T_1402, ram[4].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2424 = mux(_out_uop_T_1403, ram[5].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2425 = mux(_out_uop_T_1404, ram[6].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_2426 = or(_out_uop_T_2419, _out_uop_T_2420) node _out_uop_T_2427 = or(_out_uop_T_2426, _out_uop_T_2421) node _out_uop_T_2428 = or(_out_uop_T_2427, _out_uop_T_2422) node _out_uop_T_2429 = or(_out_uop_T_2428, _out_uop_T_2423) node _out_uop_T_2430 = or(_out_uop_T_2429, _out_uop_T_2424) node _out_uop_T_2431 = or(_out_uop_T_2430, _out_uop_T_2425) wire _out_uop_WIRE_203 : UInt<1> connect _out_uop_WIRE_203, _out_uop_T_2431 connect _out_uop_WIRE_198.fence_i, _out_uop_WIRE_203 node _out_uop_T_2432 = mux(_out_uop_T_1398, ram[0].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2433 = mux(_out_uop_T_1399, ram[1].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2434 = mux(_out_uop_T_1400, ram[2].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2435 = mux(_out_uop_T_1401, ram[3].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2436 = mux(_out_uop_T_1402, ram[4].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2437 = mux(_out_uop_T_1403, ram[5].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2438 = mux(_out_uop_T_1404, ram[6].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_2439 = or(_out_uop_T_2432, _out_uop_T_2433) node _out_uop_T_2440 = or(_out_uop_T_2439, _out_uop_T_2434) node _out_uop_T_2441 = or(_out_uop_T_2440, _out_uop_T_2435) node _out_uop_T_2442 = or(_out_uop_T_2441, _out_uop_T_2436) node _out_uop_T_2443 = or(_out_uop_T_2442, _out_uop_T_2437) node _out_uop_T_2444 = or(_out_uop_T_2443, _out_uop_T_2438) wire _out_uop_WIRE_204 : UInt<3> connect _out_uop_WIRE_204, _out_uop_T_2444 connect _out_uop_WIRE_198.csr, _out_uop_WIRE_204 node _out_uop_T_2445 = mux(_out_uop_T_1398, ram[0].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2446 = mux(_out_uop_T_1399, ram[1].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2447 = mux(_out_uop_T_1400, ram[2].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2448 = mux(_out_uop_T_1401, ram[3].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2449 = mux(_out_uop_T_1402, ram[4].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2450 = mux(_out_uop_T_1403, ram[5].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2451 = mux(_out_uop_T_1404, ram[6].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_2452 = or(_out_uop_T_2445, _out_uop_T_2446) node _out_uop_T_2453 = or(_out_uop_T_2452, _out_uop_T_2447) node _out_uop_T_2454 = or(_out_uop_T_2453, _out_uop_T_2448) node _out_uop_T_2455 = or(_out_uop_T_2454, _out_uop_T_2449) node _out_uop_T_2456 = or(_out_uop_T_2455, _out_uop_T_2450) node _out_uop_T_2457 = or(_out_uop_T_2456, _out_uop_T_2451) wire _out_uop_WIRE_205 : UInt<1> connect _out_uop_WIRE_205, _out_uop_T_2457 connect _out_uop_WIRE_198.wxd, _out_uop_WIRE_205 node _out_uop_T_2458 = mux(_out_uop_T_1398, ram[0].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2459 = mux(_out_uop_T_1399, ram[1].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2460 = mux(_out_uop_T_1400, ram[2].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2461 = mux(_out_uop_T_1401, ram[3].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2462 = mux(_out_uop_T_1402, ram[4].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2463 = mux(_out_uop_T_1403, ram[5].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2464 = mux(_out_uop_T_1404, ram[6].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_2465 = or(_out_uop_T_2458, _out_uop_T_2459) node _out_uop_T_2466 = or(_out_uop_T_2465, _out_uop_T_2460) node _out_uop_T_2467 = or(_out_uop_T_2466, _out_uop_T_2461) node _out_uop_T_2468 = or(_out_uop_T_2467, _out_uop_T_2462) node _out_uop_T_2469 = or(_out_uop_T_2468, _out_uop_T_2463) node _out_uop_T_2470 = or(_out_uop_T_2469, _out_uop_T_2464) wire _out_uop_WIRE_206 : UInt<1> connect _out_uop_WIRE_206, _out_uop_T_2470 connect _out_uop_WIRE_198.div, _out_uop_WIRE_206 node _out_uop_T_2471 = mux(_out_uop_T_1398, ram[0].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2472 = mux(_out_uop_T_1399, ram[1].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2473 = mux(_out_uop_T_1400, ram[2].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2474 = mux(_out_uop_T_1401, ram[3].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2475 = mux(_out_uop_T_1402, ram[4].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2476 = mux(_out_uop_T_1403, ram[5].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2477 = mux(_out_uop_T_1404, ram[6].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_2478 = or(_out_uop_T_2471, _out_uop_T_2472) node _out_uop_T_2479 = or(_out_uop_T_2478, _out_uop_T_2473) node _out_uop_T_2480 = or(_out_uop_T_2479, _out_uop_T_2474) node _out_uop_T_2481 = or(_out_uop_T_2480, _out_uop_T_2475) node _out_uop_T_2482 = or(_out_uop_T_2481, _out_uop_T_2476) node _out_uop_T_2483 = or(_out_uop_T_2482, _out_uop_T_2477) wire _out_uop_WIRE_207 : UInt<1> connect _out_uop_WIRE_207, _out_uop_T_2483 connect _out_uop_WIRE_198.mul, _out_uop_WIRE_207 node _out_uop_T_2484 = mux(_out_uop_T_1398, ram[0].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2485 = mux(_out_uop_T_1399, ram[1].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2486 = mux(_out_uop_T_1400, ram[2].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2487 = mux(_out_uop_T_1401, ram[3].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2488 = mux(_out_uop_T_1402, ram[4].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2489 = mux(_out_uop_T_1403, ram[5].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2490 = mux(_out_uop_T_1404, ram[6].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_2491 = or(_out_uop_T_2484, _out_uop_T_2485) node _out_uop_T_2492 = or(_out_uop_T_2491, _out_uop_T_2486) node _out_uop_T_2493 = or(_out_uop_T_2492, _out_uop_T_2487) node _out_uop_T_2494 = or(_out_uop_T_2493, _out_uop_T_2488) node _out_uop_T_2495 = or(_out_uop_T_2494, _out_uop_T_2489) node _out_uop_T_2496 = or(_out_uop_T_2495, _out_uop_T_2490) wire _out_uop_WIRE_208 : UInt<1> connect _out_uop_WIRE_208, _out_uop_T_2496 connect _out_uop_WIRE_198.wfd, _out_uop_WIRE_208 node _out_uop_T_2497 = mux(_out_uop_T_1398, ram[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2498 = mux(_out_uop_T_1399, ram[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2499 = mux(_out_uop_T_1400, ram[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2500 = mux(_out_uop_T_1401, ram[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2501 = mux(_out_uop_T_1402, ram[4].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2502 = mux(_out_uop_T_1403, ram[5].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2503 = mux(_out_uop_T_1404, ram[6].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_2504 = or(_out_uop_T_2497, _out_uop_T_2498) node _out_uop_T_2505 = or(_out_uop_T_2504, _out_uop_T_2499) node _out_uop_T_2506 = or(_out_uop_T_2505, _out_uop_T_2500) node _out_uop_T_2507 = or(_out_uop_T_2506, _out_uop_T_2501) node _out_uop_T_2508 = or(_out_uop_T_2507, _out_uop_T_2502) node _out_uop_T_2509 = or(_out_uop_T_2508, _out_uop_T_2503) wire _out_uop_WIRE_209 : UInt<1> connect _out_uop_WIRE_209, _out_uop_T_2509 connect _out_uop_WIRE_198.rfs3, _out_uop_WIRE_209 node _out_uop_T_2510 = mux(_out_uop_T_1398, ram[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2511 = mux(_out_uop_T_1399, ram[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2512 = mux(_out_uop_T_1400, ram[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2513 = mux(_out_uop_T_1401, ram[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2514 = mux(_out_uop_T_1402, ram[4].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2515 = mux(_out_uop_T_1403, ram[5].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2516 = mux(_out_uop_T_1404, ram[6].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_2517 = or(_out_uop_T_2510, _out_uop_T_2511) node _out_uop_T_2518 = or(_out_uop_T_2517, _out_uop_T_2512) node _out_uop_T_2519 = or(_out_uop_T_2518, _out_uop_T_2513) node _out_uop_T_2520 = or(_out_uop_T_2519, _out_uop_T_2514) node _out_uop_T_2521 = or(_out_uop_T_2520, _out_uop_T_2515) node _out_uop_T_2522 = or(_out_uop_T_2521, _out_uop_T_2516) wire _out_uop_WIRE_210 : UInt<1> connect _out_uop_WIRE_210, _out_uop_T_2522 connect _out_uop_WIRE_198.rfs2, _out_uop_WIRE_210 node _out_uop_T_2523 = mux(_out_uop_T_1398, ram[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2524 = mux(_out_uop_T_1399, ram[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2525 = mux(_out_uop_T_1400, ram[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2526 = mux(_out_uop_T_1401, ram[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2527 = mux(_out_uop_T_1402, ram[4].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2528 = mux(_out_uop_T_1403, ram[5].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2529 = mux(_out_uop_T_1404, ram[6].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_2530 = or(_out_uop_T_2523, _out_uop_T_2524) node _out_uop_T_2531 = or(_out_uop_T_2530, _out_uop_T_2525) node _out_uop_T_2532 = or(_out_uop_T_2531, _out_uop_T_2526) node _out_uop_T_2533 = or(_out_uop_T_2532, _out_uop_T_2527) node _out_uop_T_2534 = or(_out_uop_T_2533, _out_uop_T_2528) node _out_uop_T_2535 = or(_out_uop_T_2534, _out_uop_T_2529) wire _out_uop_WIRE_211 : UInt<1> connect _out_uop_WIRE_211, _out_uop_T_2535 connect _out_uop_WIRE_198.rfs1, _out_uop_WIRE_211 node _out_uop_T_2536 = mux(_out_uop_T_1398, ram[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2537 = mux(_out_uop_T_1399, ram[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2538 = mux(_out_uop_T_1400, ram[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2539 = mux(_out_uop_T_1401, ram[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2540 = mux(_out_uop_T_1402, ram[4].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2541 = mux(_out_uop_T_1403, ram[5].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2542 = mux(_out_uop_T_1404, ram[6].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_2543 = or(_out_uop_T_2536, _out_uop_T_2537) node _out_uop_T_2544 = or(_out_uop_T_2543, _out_uop_T_2538) node _out_uop_T_2545 = or(_out_uop_T_2544, _out_uop_T_2539) node _out_uop_T_2546 = or(_out_uop_T_2545, _out_uop_T_2540) node _out_uop_T_2547 = or(_out_uop_T_2546, _out_uop_T_2541) node _out_uop_T_2548 = or(_out_uop_T_2547, _out_uop_T_2542) wire _out_uop_WIRE_212 : UInt<5> connect _out_uop_WIRE_212, _out_uop_T_2548 connect _out_uop_WIRE_198.mem_cmd, _out_uop_WIRE_212 node _out_uop_T_2549 = mux(_out_uop_T_1398, ram[0].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2550 = mux(_out_uop_T_1399, ram[1].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2551 = mux(_out_uop_T_1400, ram[2].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2552 = mux(_out_uop_T_1401, ram[3].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2553 = mux(_out_uop_T_1402, ram[4].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2554 = mux(_out_uop_T_1403, ram[5].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2555 = mux(_out_uop_T_1404, ram[6].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_2556 = or(_out_uop_T_2549, _out_uop_T_2550) node _out_uop_T_2557 = or(_out_uop_T_2556, _out_uop_T_2551) node _out_uop_T_2558 = or(_out_uop_T_2557, _out_uop_T_2552) node _out_uop_T_2559 = or(_out_uop_T_2558, _out_uop_T_2553) node _out_uop_T_2560 = or(_out_uop_T_2559, _out_uop_T_2554) node _out_uop_T_2561 = or(_out_uop_T_2560, _out_uop_T_2555) wire _out_uop_WIRE_213 : UInt<1> connect _out_uop_WIRE_213, _out_uop_T_2561 connect _out_uop_WIRE_198.mem, _out_uop_WIRE_213 node _out_uop_T_2562 = mux(_out_uop_T_1398, ram[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2563 = mux(_out_uop_T_1399, ram[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2564 = mux(_out_uop_T_1400, ram[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2565 = mux(_out_uop_T_1401, ram[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2566 = mux(_out_uop_T_1402, ram[4].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2567 = mux(_out_uop_T_1403, ram[5].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2568 = mux(_out_uop_T_1404, ram[6].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_2569 = or(_out_uop_T_2562, _out_uop_T_2563) node _out_uop_T_2570 = or(_out_uop_T_2569, _out_uop_T_2564) node _out_uop_T_2571 = or(_out_uop_T_2570, _out_uop_T_2565) node _out_uop_T_2572 = or(_out_uop_T_2571, _out_uop_T_2566) node _out_uop_T_2573 = or(_out_uop_T_2572, _out_uop_T_2567) node _out_uop_T_2574 = or(_out_uop_T_2573, _out_uop_T_2568) wire _out_uop_WIRE_214 : UInt<5> connect _out_uop_WIRE_214, _out_uop_T_2574 connect _out_uop_WIRE_198.alu_fn, _out_uop_WIRE_214 node _out_uop_T_2575 = mux(_out_uop_T_1398, ram[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2576 = mux(_out_uop_T_1399, ram[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2577 = mux(_out_uop_T_1400, ram[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2578 = mux(_out_uop_T_1401, ram[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2579 = mux(_out_uop_T_1402, ram[4].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2580 = mux(_out_uop_T_1403, ram[5].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2581 = mux(_out_uop_T_1404, ram[6].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_2582 = or(_out_uop_T_2575, _out_uop_T_2576) node _out_uop_T_2583 = or(_out_uop_T_2582, _out_uop_T_2577) node _out_uop_T_2584 = or(_out_uop_T_2583, _out_uop_T_2578) node _out_uop_T_2585 = or(_out_uop_T_2584, _out_uop_T_2579) node _out_uop_T_2586 = or(_out_uop_T_2585, _out_uop_T_2580) node _out_uop_T_2587 = or(_out_uop_T_2586, _out_uop_T_2581) wire _out_uop_WIRE_215 : UInt<1> connect _out_uop_WIRE_215, _out_uop_T_2587 connect _out_uop_WIRE_198.alu_dw, _out_uop_WIRE_215 node _out_uop_T_2588 = mux(_out_uop_T_1398, ram[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2589 = mux(_out_uop_T_1399, ram[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2590 = mux(_out_uop_T_1400, ram[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2591 = mux(_out_uop_T_1401, ram[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2592 = mux(_out_uop_T_1402, ram[4].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2593 = mux(_out_uop_T_1403, ram[5].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2594 = mux(_out_uop_T_1404, ram[6].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_2595 = or(_out_uop_T_2588, _out_uop_T_2589) node _out_uop_T_2596 = or(_out_uop_T_2595, _out_uop_T_2590) node _out_uop_T_2597 = or(_out_uop_T_2596, _out_uop_T_2591) node _out_uop_T_2598 = or(_out_uop_T_2597, _out_uop_T_2592) node _out_uop_T_2599 = or(_out_uop_T_2598, _out_uop_T_2593) node _out_uop_T_2600 = or(_out_uop_T_2599, _out_uop_T_2594) wire _out_uop_WIRE_216 : UInt<3> connect _out_uop_WIRE_216, _out_uop_T_2600 connect _out_uop_WIRE_198.sel_imm, _out_uop_WIRE_216 node _out_uop_T_2601 = mux(_out_uop_T_1398, ram[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2602 = mux(_out_uop_T_1399, ram[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2603 = mux(_out_uop_T_1400, ram[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2604 = mux(_out_uop_T_1401, ram[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2605 = mux(_out_uop_T_1402, ram[4].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2606 = mux(_out_uop_T_1403, ram[5].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2607 = mux(_out_uop_T_1404, ram[6].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_2608 = or(_out_uop_T_2601, _out_uop_T_2602) node _out_uop_T_2609 = or(_out_uop_T_2608, _out_uop_T_2603) node _out_uop_T_2610 = or(_out_uop_T_2609, _out_uop_T_2604) node _out_uop_T_2611 = or(_out_uop_T_2610, _out_uop_T_2605) node _out_uop_T_2612 = or(_out_uop_T_2611, _out_uop_T_2606) node _out_uop_T_2613 = or(_out_uop_T_2612, _out_uop_T_2607) wire _out_uop_WIRE_217 : UInt<2> connect _out_uop_WIRE_217, _out_uop_T_2613 connect _out_uop_WIRE_198.sel_alu1, _out_uop_WIRE_217 node _out_uop_T_2614 = mux(_out_uop_T_1398, ram[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2615 = mux(_out_uop_T_1399, ram[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2616 = mux(_out_uop_T_1400, ram[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2617 = mux(_out_uop_T_1401, ram[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2618 = mux(_out_uop_T_1402, ram[4].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2619 = mux(_out_uop_T_1403, ram[5].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2620 = mux(_out_uop_T_1404, ram[6].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_2621 = or(_out_uop_T_2614, _out_uop_T_2615) node _out_uop_T_2622 = or(_out_uop_T_2621, _out_uop_T_2616) node _out_uop_T_2623 = or(_out_uop_T_2622, _out_uop_T_2617) node _out_uop_T_2624 = or(_out_uop_T_2623, _out_uop_T_2618) node _out_uop_T_2625 = or(_out_uop_T_2624, _out_uop_T_2619) node _out_uop_T_2626 = or(_out_uop_T_2625, _out_uop_T_2620) wire _out_uop_WIRE_218 : UInt<3> connect _out_uop_WIRE_218, _out_uop_T_2626 connect _out_uop_WIRE_198.sel_alu2, _out_uop_WIRE_218 node _out_uop_T_2627 = mux(_out_uop_T_1398, ram[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2628 = mux(_out_uop_T_1399, ram[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2629 = mux(_out_uop_T_1400, ram[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2630 = mux(_out_uop_T_1401, ram[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2631 = mux(_out_uop_T_1402, ram[4].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2632 = mux(_out_uop_T_1403, ram[5].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2633 = mux(_out_uop_T_1404, ram[6].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_2634 = or(_out_uop_T_2627, _out_uop_T_2628) node _out_uop_T_2635 = or(_out_uop_T_2634, _out_uop_T_2629) node _out_uop_T_2636 = or(_out_uop_T_2635, _out_uop_T_2630) node _out_uop_T_2637 = or(_out_uop_T_2636, _out_uop_T_2631) node _out_uop_T_2638 = or(_out_uop_T_2637, _out_uop_T_2632) node _out_uop_T_2639 = or(_out_uop_T_2638, _out_uop_T_2633) wire _out_uop_WIRE_219 : UInt<1> connect _out_uop_WIRE_219, _out_uop_T_2639 connect _out_uop_WIRE_198.rxs1, _out_uop_WIRE_219 node _out_uop_T_2640 = mux(_out_uop_T_1398, ram[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2641 = mux(_out_uop_T_1399, ram[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2642 = mux(_out_uop_T_1400, ram[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2643 = mux(_out_uop_T_1401, ram[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2644 = mux(_out_uop_T_1402, ram[4].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2645 = mux(_out_uop_T_1403, ram[5].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2646 = mux(_out_uop_T_1404, ram[6].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_2647 = or(_out_uop_T_2640, _out_uop_T_2641) node _out_uop_T_2648 = or(_out_uop_T_2647, _out_uop_T_2642) node _out_uop_T_2649 = or(_out_uop_T_2648, _out_uop_T_2643) node _out_uop_T_2650 = or(_out_uop_T_2649, _out_uop_T_2644) node _out_uop_T_2651 = or(_out_uop_T_2650, _out_uop_T_2645) node _out_uop_T_2652 = or(_out_uop_T_2651, _out_uop_T_2646) wire _out_uop_WIRE_220 : UInt<1> connect _out_uop_WIRE_220, _out_uop_T_2652 connect _out_uop_WIRE_198.rxs2, _out_uop_WIRE_220 node _out_uop_T_2653 = mux(_out_uop_T_1398, ram[0].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2654 = mux(_out_uop_T_1399, ram[1].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2655 = mux(_out_uop_T_1400, ram[2].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2656 = mux(_out_uop_T_1401, ram[3].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2657 = mux(_out_uop_T_1402, ram[4].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2658 = mux(_out_uop_T_1403, ram[5].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2659 = mux(_out_uop_T_1404, ram[6].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_2660 = or(_out_uop_T_2653, _out_uop_T_2654) node _out_uop_T_2661 = or(_out_uop_T_2660, _out_uop_T_2655) node _out_uop_T_2662 = or(_out_uop_T_2661, _out_uop_T_2656) node _out_uop_T_2663 = or(_out_uop_T_2662, _out_uop_T_2657) node _out_uop_T_2664 = or(_out_uop_T_2663, _out_uop_T_2658) node _out_uop_T_2665 = or(_out_uop_T_2664, _out_uop_T_2659) wire _out_uop_WIRE_221 : UInt<1> connect _out_uop_WIRE_221, _out_uop_T_2665 connect _out_uop_WIRE_198.jalr, _out_uop_WIRE_221 node _out_uop_T_2666 = mux(_out_uop_T_1398, ram[0].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2667 = mux(_out_uop_T_1399, ram[1].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2668 = mux(_out_uop_T_1400, ram[2].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2669 = mux(_out_uop_T_1401, ram[3].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2670 = mux(_out_uop_T_1402, ram[4].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2671 = mux(_out_uop_T_1403, ram[5].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2672 = mux(_out_uop_T_1404, ram[6].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_2673 = or(_out_uop_T_2666, _out_uop_T_2667) node _out_uop_T_2674 = or(_out_uop_T_2673, _out_uop_T_2668) node _out_uop_T_2675 = or(_out_uop_T_2674, _out_uop_T_2669) node _out_uop_T_2676 = or(_out_uop_T_2675, _out_uop_T_2670) node _out_uop_T_2677 = or(_out_uop_T_2676, _out_uop_T_2671) node _out_uop_T_2678 = or(_out_uop_T_2677, _out_uop_T_2672) wire _out_uop_WIRE_222 : UInt<1> connect _out_uop_WIRE_222, _out_uop_T_2678 connect _out_uop_WIRE_198.jal, _out_uop_WIRE_222 node _out_uop_T_2679 = mux(_out_uop_T_1398, ram[0].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2680 = mux(_out_uop_T_1399, ram[1].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2681 = mux(_out_uop_T_1400, ram[2].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2682 = mux(_out_uop_T_1401, ram[3].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2683 = mux(_out_uop_T_1402, ram[4].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2684 = mux(_out_uop_T_1403, ram[5].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2685 = mux(_out_uop_T_1404, ram[6].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_2686 = or(_out_uop_T_2679, _out_uop_T_2680) node _out_uop_T_2687 = or(_out_uop_T_2686, _out_uop_T_2681) node _out_uop_T_2688 = or(_out_uop_T_2687, _out_uop_T_2682) node _out_uop_T_2689 = or(_out_uop_T_2688, _out_uop_T_2683) node _out_uop_T_2690 = or(_out_uop_T_2689, _out_uop_T_2684) node _out_uop_T_2691 = or(_out_uop_T_2690, _out_uop_T_2685) wire _out_uop_WIRE_223 : UInt<1> connect _out_uop_WIRE_223, _out_uop_T_2691 connect _out_uop_WIRE_198.branch, _out_uop_WIRE_223 node _out_uop_T_2692 = mux(_out_uop_T_1398, ram[0].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2693 = mux(_out_uop_T_1399, ram[1].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2694 = mux(_out_uop_T_1400, ram[2].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2695 = mux(_out_uop_T_1401, ram[3].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2696 = mux(_out_uop_T_1402, ram[4].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2697 = mux(_out_uop_T_1403, ram[5].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2698 = mux(_out_uop_T_1404, ram[6].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_2699 = or(_out_uop_T_2692, _out_uop_T_2693) node _out_uop_T_2700 = or(_out_uop_T_2699, _out_uop_T_2694) node _out_uop_T_2701 = or(_out_uop_T_2700, _out_uop_T_2695) node _out_uop_T_2702 = or(_out_uop_T_2701, _out_uop_T_2696) node _out_uop_T_2703 = or(_out_uop_T_2702, _out_uop_T_2697) node _out_uop_T_2704 = or(_out_uop_T_2703, _out_uop_T_2698) wire _out_uop_WIRE_224 : UInt<1> connect _out_uop_WIRE_224, _out_uop_T_2704 connect _out_uop_WIRE_198.rocc, _out_uop_WIRE_224 node _out_uop_T_2705 = mux(_out_uop_T_1398, ram[0].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2706 = mux(_out_uop_T_1399, ram[1].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2707 = mux(_out_uop_T_1400, ram[2].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2708 = mux(_out_uop_T_1401, ram[3].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2709 = mux(_out_uop_T_1402, ram[4].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2710 = mux(_out_uop_T_1403, ram[5].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2711 = mux(_out_uop_T_1404, ram[6].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_2712 = or(_out_uop_T_2705, _out_uop_T_2706) node _out_uop_T_2713 = or(_out_uop_T_2712, _out_uop_T_2707) node _out_uop_T_2714 = or(_out_uop_T_2713, _out_uop_T_2708) node _out_uop_T_2715 = or(_out_uop_T_2714, _out_uop_T_2709) node _out_uop_T_2716 = or(_out_uop_T_2715, _out_uop_T_2710) node _out_uop_T_2717 = or(_out_uop_T_2716, _out_uop_T_2711) wire _out_uop_WIRE_225 : UInt<1> connect _out_uop_WIRE_225, _out_uop_T_2717 connect _out_uop_WIRE_198.fp, _out_uop_WIRE_225 node _out_uop_T_2718 = mux(_out_uop_T_1398, ram[0].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2719 = mux(_out_uop_T_1399, ram[1].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2720 = mux(_out_uop_T_1400, ram[2].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2721 = mux(_out_uop_T_1401, ram[3].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2722 = mux(_out_uop_T_1402, ram[4].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2723 = mux(_out_uop_T_1403, ram[5].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2724 = mux(_out_uop_T_1404, ram[6].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_2725 = or(_out_uop_T_2718, _out_uop_T_2719) node _out_uop_T_2726 = or(_out_uop_T_2725, _out_uop_T_2720) node _out_uop_T_2727 = or(_out_uop_T_2726, _out_uop_T_2721) node _out_uop_T_2728 = or(_out_uop_T_2727, _out_uop_T_2722) node _out_uop_T_2729 = or(_out_uop_T_2728, _out_uop_T_2723) node _out_uop_T_2730 = or(_out_uop_T_2729, _out_uop_T_2724) wire _out_uop_WIRE_226 : UInt<1> connect _out_uop_WIRE_226, _out_uop_T_2730 connect _out_uop_WIRE_198.legal, _out_uop_WIRE_226 connect _out_uop_WIRE_116.ctrl, _out_uop_WIRE_198 node _out_uop_T_2731 = mux(_out_uop_T_1398, ram[0].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2732 = mux(_out_uop_T_1399, ram[1].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2733 = mux(_out_uop_T_1400, ram[2].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2734 = mux(_out_uop_T_1401, ram[3].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2735 = mux(_out_uop_T_1402, ram[4].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2736 = mux(_out_uop_T_1403, ram[5].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2737 = mux(_out_uop_T_1404, ram[6].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_2738 = or(_out_uop_T_2731, _out_uop_T_2732) node _out_uop_T_2739 = or(_out_uop_T_2738, _out_uop_T_2733) node _out_uop_T_2740 = or(_out_uop_T_2739, _out_uop_T_2734) node _out_uop_T_2741 = or(_out_uop_T_2740, _out_uop_T_2735) node _out_uop_T_2742 = or(_out_uop_T_2741, _out_uop_T_2736) node _out_uop_T_2743 = or(_out_uop_T_2742, _out_uop_T_2737) wire _out_uop_WIRE_227 : UInt<1> connect _out_uop_WIRE_227, _out_uop_T_2743 connect _out_uop_WIRE_116.edge_inst, _out_uop_WIRE_227 node _out_uop_T_2744 = mux(_out_uop_T_1398, ram[0].bits.pc, UInt<1>(0h0)) node _out_uop_T_2745 = mux(_out_uop_T_1399, ram[1].bits.pc, UInt<1>(0h0)) node _out_uop_T_2746 = mux(_out_uop_T_1400, ram[2].bits.pc, UInt<1>(0h0)) node _out_uop_T_2747 = mux(_out_uop_T_1401, ram[3].bits.pc, UInt<1>(0h0)) node _out_uop_T_2748 = mux(_out_uop_T_1402, ram[4].bits.pc, UInt<1>(0h0)) node _out_uop_T_2749 = mux(_out_uop_T_1403, ram[5].bits.pc, UInt<1>(0h0)) node _out_uop_T_2750 = mux(_out_uop_T_1404, ram[6].bits.pc, UInt<1>(0h0)) node _out_uop_T_2751 = or(_out_uop_T_2744, _out_uop_T_2745) node _out_uop_T_2752 = or(_out_uop_T_2751, _out_uop_T_2746) node _out_uop_T_2753 = or(_out_uop_T_2752, _out_uop_T_2747) node _out_uop_T_2754 = or(_out_uop_T_2753, _out_uop_T_2748) node _out_uop_T_2755 = or(_out_uop_T_2754, _out_uop_T_2749) node _out_uop_T_2756 = or(_out_uop_T_2755, _out_uop_T_2750) wire _out_uop_WIRE_228 : UInt<40> connect _out_uop_WIRE_228, _out_uop_T_2756 connect _out_uop_WIRE_116.pc, _out_uop_WIRE_228 node _out_uop_T_2757 = mux(_out_uop_T_1398, ram[0].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2758 = mux(_out_uop_T_1399, ram[1].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2759 = mux(_out_uop_T_1400, ram[2].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2760 = mux(_out_uop_T_1401, ram[3].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2761 = mux(_out_uop_T_1402, ram[4].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2762 = mux(_out_uop_T_1403, ram[5].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2763 = mux(_out_uop_T_1404, ram[6].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_2764 = or(_out_uop_T_2757, _out_uop_T_2758) node _out_uop_T_2765 = or(_out_uop_T_2764, _out_uop_T_2759) node _out_uop_T_2766 = or(_out_uop_T_2765, _out_uop_T_2760) node _out_uop_T_2767 = or(_out_uop_T_2766, _out_uop_T_2761) node _out_uop_T_2768 = or(_out_uop_T_2767, _out_uop_T_2762) node _out_uop_T_2769 = or(_out_uop_T_2768, _out_uop_T_2763) wire _out_uop_WIRE_229 : UInt<32> connect _out_uop_WIRE_229, _out_uop_T_2769 connect _out_uop_WIRE_116.raw_inst, _out_uop_WIRE_229 node _out_uop_T_2770 = mux(_out_uop_T_1398, ram[0].bits.inst, UInt<1>(0h0)) node _out_uop_T_2771 = mux(_out_uop_T_1399, ram[1].bits.inst, UInt<1>(0h0)) node _out_uop_T_2772 = mux(_out_uop_T_1400, ram[2].bits.inst, UInt<1>(0h0)) node _out_uop_T_2773 = mux(_out_uop_T_1401, ram[3].bits.inst, UInt<1>(0h0)) node _out_uop_T_2774 = mux(_out_uop_T_1402, ram[4].bits.inst, UInt<1>(0h0)) node _out_uop_T_2775 = mux(_out_uop_T_1403, ram[5].bits.inst, UInt<1>(0h0)) node _out_uop_T_2776 = mux(_out_uop_T_1404, ram[6].bits.inst, UInt<1>(0h0)) node _out_uop_T_2777 = or(_out_uop_T_2770, _out_uop_T_2771) node _out_uop_T_2778 = or(_out_uop_T_2777, _out_uop_T_2772) node _out_uop_T_2779 = or(_out_uop_T_2778, _out_uop_T_2773) node _out_uop_T_2780 = or(_out_uop_T_2779, _out_uop_T_2774) node _out_uop_T_2781 = or(_out_uop_T_2780, _out_uop_T_2775) node _out_uop_T_2782 = or(_out_uop_T_2781, _out_uop_T_2776) wire _out_uop_WIRE_230 : UInt<32> connect _out_uop_WIRE_230, _out_uop_T_2782 connect _out_uop_WIRE_116.inst, _out_uop_WIRE_230 connect out_uop_1.bits, _out_uop_WIRE_116 node _out_uop_T_2783 = mux(_out_uop_T_1398, ram[0].valid, UInt<1>(0h0)) node _out_uop_T_2784 = mux(_out_uop_T_1399, ram[1].valid, UInt<1>(0h0)) node _out_uop_T_2785 = mux(_out_uop_T_1400, ram[2].valid, UInt<1>(0h0)) node _out_uop_T_2786 = mux(_out_uop_T_1401, ram[3].valid, UInt<1>(0h0)) node _out_uop_T_2787 = mux(_out_uop_T_1402, ram[4].valid, UInt<1>(0h0)) node _out_uop_T_2788 = mux(_out_uop_T_1403, ram[5].valid, UInt<1>(0h0)) node _out_uop_T_2789 = mux(_out_uop_T_1404, ram[6].valid, UInt<1>(0h0)) node _out_uop_T_2790 = or(_out_uop_T_2783, _out_uop_T_2784) node _out_uop_T_2791 = or(_out_uop_T_2790, _out_uop_T_2785) node _out_uop_T_2792 = or(_out_uop_T_2791, _out_uop_T_2786) node _out_uop_T_2793 = or(_out_uop_T_2792, _out_uop_T_2787) node _out_uop_T_2794 = or(_out_uop_T_2793, _out_uop_T_2788) node _out_uop_T_2795 = or(_out_uop_T_2794, _out_uop_T_2789) wire _out_uop_WIRE_231 : UInt<1> connect _out_uop_WIRE_231, _out_uop_T_2795 connect out_uop_1.valid, _out_uop_WIRE_231 connect io.deq[1].valid, out_uop_1.valid connect io.deq[1].bits, out_uop_1.bits node _T_35 = and(io.deq[1].ready, io.deq[1].valid) node _T_36 = or(_T_30, _T_34) node _T_37 = mux(_T_35, _T_36, _T_30) node _T_38 = shl(_T_34, 1) node _T_39 = bits(_T_34, 6, 6) node _T_40 = or(_T_38, _T_39) node _T_41 = bits(_T_40, 6, 0) node _out_uop_T_2796 = bits(_T_41, 0, 0) node _out_uop_T_2797 = bits(_T_41, 1, 1) node _out_uop_T_2798 = bits(_T_41, 2, 2) node _out_uop_T_2799 = bits(_T_41, 3, 3) node _out_uop_T_2800 = bits(_T_41, 4, 4) node _out_uop_T_2801 = bits(_T_41, 5, 5) node _out_uop_T_2802 = bits(_T_41, 6, 6) wire out_uop_2 : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _out_uop_WIRE_232 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _out_uop_T_2803 = mux(_out_uop_T_2796, ram[0].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2804 = mux(_out_uop_T_2797, ram[1].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2805 = mux(_out_uop_T_2798, ram[2].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2806 = mux(_out_uop_T_2799, ram[3].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2807 = mux(_out_uop_T_2800, ram[4].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2808 = mux(_out_uop_T_2801, ram[5].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2809 = mux(_out_uop_T_2802, ram[6].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_2810 = or(_out_uop_T_2803, _out_uop_T_2804) node _out_uop_T_2811 = or(_out_uop_T_2810, _out_uop_T_2805) node _out_uop_T_2812 = or(_out_uop_T_2811, _out_uop_T_2806) node _out_uop_T_2813 = or(_out_uop_T_2812, _out_uop_T_2807) node _out_uop_T_2814 = or(_out_uop_T_2813, _out_uop_T_2808) node _out_uop_T_2815 = or(_out_uop_T_2814, _out_uop_T_2809) wire _out_uop_WIRE_233 : UInt<1> connect _out_uop_WIRE_233, _out_uop_T_2815 connect _out_uop_WIRE_232.flush_pipe, _out_uop_WIRE_233 node _out_uop_T_2816 = mux(_out_uop_T_2796, ram[0].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2817 = mux(_out_uop_T_2797, ram[1].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2818 = mux(_out_uop_T_2798, ram[2].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2819 = mux(_out_uop_T_2799, ram[3].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2820 = mux(_out_uop_T_2800, ram[4].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2821 = mux(_out_uop_T_2801, ram[5].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2822 = mux(_out_uop_T_2802, ram[6].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_2823 = or(_out_uop_T_2816, _out_uop_T_2817) node _out_uop_T_2824 = or(_out_uop_T_2823, _out_uop_T_2818) node _out_uop_T_2825 = or(_out_uop_T_2824, _out_uop_T_2819) node _out_uop_T_2826 = or(_out_uop_T_2825, _out_uop_T_2820) node _out_uop_T_2827 = or(_out_uop_T_2826, _out_uop_T_2821) node _out_uop_T_2828 = or(_out_uop_T_2827, _out_uop_T_2822) wire _out_uop_WIRE_234 : UInt<2> connect _out_uop_WIRE_234, _out_uop_T_2828 connect _out_uop_WIRE_232.mem_size, _out_uop_WIRE_234 wire _out_uop_WIRE_235 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _out_uop_T_2829 = mux(_out_uop_T_2796, ram[0].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2830 = mux(_out_uop_T_2797, ram[1].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2831 = mux(_out_uop_T_2798, ram[2].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2832 = mux(_out_uop_T_2799, ram[3].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2833 = mux(_out_uop_T_2800, ram[4].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2834 = mux(_out_uop_T_2801, ram[5].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2835 = mux(_out_uop_T_2802, ram[6].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_2836 = or(_out_uop_T_2829, _out_uop_T_2830) node _out_uop_T_2837 = or(_out_uop_T_2836, _out_uop_T_2831) node _out_uop_T_2838 = or(_out_uop_T_2837, _out_uop_T_2832) node _out_uop_T_2839 = or(_out_uop_T_2838, _out_uop_T_2833) node _out_uop_T_2840 = or(_out_uop_T_2839, _out_uop_T_2834) node _out_uop_T_2841 = or(_out_uop_T_2840, _out_uop_T_2835) wire _out_uop_WIRE_236 : UInt<65> connect _out_uop_WIRE_236, _out_uop_T_2841 connect _out_uop_WIRE_235.in3, _out_uop_WIRE_236 node _out_uop_T_2842 = mux(_out_uop_T_2796, ram[0].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2843 = mux(_out_uop_T_2797, ram[1].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2844 = mux(_out_uop_T_2798, ram[2].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2845 = mux(_out_uop_T_2799, ram[3].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2846 = mux(_out_uop_T_2800, ram[4].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2847 = mux(_out_uop_T_2801, ram[5].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2848 = mux(_out_uop_T_2802, ram[6].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_2849 = or(_out_uop_T_2842, _out_uop_T_2843) node _out_uop_T_2850 = or(_out_uop_T_2849, _out_uop_T_2844) node _out_uop_T_2851 = or(_out_uop_T_2850, _out_uop_T_2845) node _out_uop_T_2852 = or(_out_uop_T_2851, _out_uop_T_2846) node _out_uop_T_2853 = or(_out_uop_T_2852, _out_uop_T_2847) node _out_uop_T_2854 = or(_out_uop_T_2853, _out_uop_T_2848) wire _out_uop_WIRE_237 : UInt<65> connect _out_uop_WIRE_237, _out_uop_T_2854 connect _out_uop_WIRE_235.in2, _out_uop_WIRE_237 node _out_uop_T_2855 = mux(_out_uop_T_2796, ram[0].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2856 = mux(_out_uop_T_2797, ram[1].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2857 = mux(_out_uop_T_2798, ram[2].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2858 = mux(_out_uop_T_2799, ram[3].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2859 = mux(_out_uop_T_2800, ram[4].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2860 = mux(_out_uop_T_2801, ram[5].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2861 = mux(_out_uop_T_2802, ram[6].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_2862 = or(_out_uop_T_2855, _out_uop_T_2856) node _out_uop_T_2863 = or(_out_uop_T_2862, _out_uop_T_2857) node _out_uop_T_2864 = or(_out_uop_T_2863, _out_uop_T_2858) node _out_uop_T_2865 = or(_out_uop_T_2864, _out_uop_T_2859) node _out_uop_T_2866 = or(_out_uop_T_2865, _out_uop_T_2860) node _out_uop_T_2867 = or(_out_uop_T_2866, _out_uop_T_2861) wire _out_uop_WIRE_238 : UInt<65> connect _out_uop_WIRE_238, _out_uop_T_2867 connect _out_uop_WIRE_235.in1, _out_uop_WIRE_238 node _out_uop_T_2868 = mux(_out_uop_T_2796, ram[0].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2869 = mux(_out_uop_T_2797, ram[1].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2870 = mux(_out_uop_T_2798, ram[2].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2871 = mux(_out_uop_T_2799, ram[3].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2872 = mux(_out_uop_T_2800, ram[4].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2873 = mux(_out_uop_T_2801, ram[5].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2874 = mux(_out_uop_T_2802, ram[6].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_2875 = or(_out_uop_T_2868, _out_uop_T_2869) node _out_uop_T_2876 = or(_out_uop_T_2875, _out_uop_T_2870) node _out_uop_T_2877 = or(_out_uop_T_2876, _out_uop_T_2871) node _out_uop_T_2878 = or(_out_uop_T_2877, _out_uop_T_2872) node _out_uop_T_2879 = or(_out_uop_T_2878, _out_uop_T_2873) node _out_uop_T_2880 = or(_out_uop_T_2879, _out_uop_T_2874) wire _out_uop_WIRE_239 : UInt<2> connect _out_uop_WIRE_239, _out_uop_T_2880 connect _out_uop_WIRE_235.fmt, _out_uop_WIRE_239 node _out_uop_T_2881 = mux(_out_uop_T_2796, ram[0].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2882 = mux(_out_uop_T_2797, ram[1].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2883 = mux(_out_uop_T_2798, ram[2].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2884 = mux(_out_uop_T_2799, ram[3].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2885 = mux(_out_uop_T_2800, ram[4].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2886 = mux(_out_uop_T_2801, ram[5].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2887 = mux(_out_uop_T_2802, ram[6].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_2888 = or(_out_uop_T_2881, _out_uop_T_2882) node _out_uop_T_2889 = or(_out_uop_T_2888, _out_uop_T_2883) node _out_uop_T_2890 = or(_out_uop_T_2889, _out_uop_T_2884) node _out_uop_T_2891 = or(_out_uop_T_2890, _out_uop_T_2885) node _out_uop_T_2892 = or(_out_uop_T_2891, _out_uop_T_2886) node _out_uop_T_2893 = or(_out_uop_T_2892, _out_uop_T_2887) wire _out_uop_WIRE_240 : UInt<2> connect _out_uop_WIRE_240, _out_uop_T_2893 connect _out_uop_WIRE_235.typ, _out_uop_WIRE_240 node _out_uop_T_2894 = mux(_out_uop_T_2796, ram[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2895 = mux(_out_uop_T_2797, ram[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2896 = mux(_out_uop_T_2798, ram[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2897 = mux(_out_uop_T_2799, ram[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2898 = mux(_out_uop_T_2800, ram[4].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2899 = mux(_out_uop_T_2801, ram[5].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2900 = mux(_out_uop_T_2802, ram[6].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_2901 = or(_out_uop_T_2894, _out_uop_T_2895) node _out_uop_T_2902 = or(_out_uop_T_2901, _out_uop_T_2896) node _out_uop_T_2903 = or(_out_uop_T_2902, _out_uop_T_2897) node _out_uop_T_2904 = or(_out_uop_T_2903, _out_uop_T_2898) node _out_uop_T_2905 = or(_out_uop_T_2904, _out_uop_T_2899) node _out_uop_T_2906 = or(_out_uop_T_2905, _out_uop_T_2900) wire _out_uop_WIRE_241 : UInt<2> connect _out_uop_WIRE_241, _out_uop_T_2906 connect _out_uop_WIRE_235.fmaCmd, _out_uop_WIRE_241 node _out_uop_T_2907 = mux(_out_uop_T_2796, ram[0].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2908 = mux(_out_uop_T_2797, ram[1].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2909 = mux(_out_uop_T_2798, ram[2].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2910 = mux(_out_uop_T_2799, ram[3].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2911 = mux(_out_uop_T_2800, ram[4].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2912 = mux(_out_uop_T_2801, ram[5].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2913 = mux(_out_uop_T_2802, ram[6].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_2914 = or(_out_uop_T_2907, _out_uop_T_2908) node _out_uop_T_2915 = or(_out_uop_T_2914, _out_uop_T_2909) node _out_uop_T_2916 = or(_out_uop_T_2915, _out_uop_T_2910) node _out_uop_T_2917 = or(_out_uop_T_2916, _out_uop_T_2911) node _out_uop_T_2918 = or(_out_uop_T_2917, _out_uop_T_2912) node _out_uop_T_2919 = or(_out_uop_T_2918, _out_uop_T_2913) wire _out_uop_WIRE_242 : UInt<3> connect _out_uop_WIRE_242, _out_uop_T_2919 connect _out_uop_WIRE_235.rm, _out_uop_WIRE_242 node _out_uop_T_2920 = mux(_out_uop_T_2796, ram[0].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2921 = mux(_out_uop_T_2797, ram[1].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2922 = mux(_out_uop_T_2798, ram[2].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2923 = mux(_out_uop_T_2799, ram[3].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2924 = mux(_out_uop_T_2800, ram[4].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2925 = mux(_out_uop_T_2801, ram[5].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2926 = mux(_out_uop_T_2802, ram[6].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_2927 = or(_out_uop_T_2920, _out_uop_T_2921) node _out_uop_T_2928 = or(_out_uop_T_2927, _out_uop_T_2922) node _out_uop_T_2929 = or(_out_uop_T_2928, _out_uop_T_2923) node _out_uop_T_2930 = or(_out_uop_T_2929, _out_uop_T_2924) node _out_uop_T_2931 = or(_out_uop_T_2930, _out_uop_T_2925) node _out_uop_T_2932 = or(_out_uop_T_2931, _out_uop_T_2926) wire _out_uop_WIRE_243 : UInt<1> connect _out_uop_WIRE_243, _out_uop_T_2932 connect _out_uop_WIRE_235.vec, _out_uop_WIRE_243 node _out_uop_T_2933 = mux(_out_uop_T_2796, ram[0].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2934 = mux(_out_uop_T_2797, ram[1].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2935 = mux(_out_uop_T_2798, ram[2].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2936 = mux(_out_uop_T_2799, ram[3].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2937 = mux(_out_uop_T_2800, ram[4].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2938 = mux(_out_uop_T_2801, ram[5].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2939 = mux(_out_uop_T_2802, ram[6].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_2940 = or(_out_uop_T_2933, _out_uop_T_2934) node _out_uop_T_2941 = or(_out_uop_T_2940, _out_uop_T_2935) node _out_uop_T_2942 = or(_out_uop_T_2941, _out_uop_T_2936) node _out_uop_T_2943 = or(_out_uop_T_2942, _out_uop_T_2937) node _out_uop_T_2944 = or(_out_uop_T_2943, _out_uop_T_2938) node _out_uop_T_2945 = or(_out_uop_T_2944, _out_uop_T_2939) wire _out_uop_WIRE_244 : UInt<1> connect _out_uop_WIRE_244, _out_uop_T_2945 connect _out_uop_WIRE_235.wflags, _out_uop_WIRE_244 node _out_uop_T_2946 = mux(_out_uop_T_2796, ram[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2947 = mux(_out_uop_T_2797, ram[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2948 = mux(_out_uop_T_2798, ram[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2949 = mux(_out_uop_T_2799, ram[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2950 = mux(_out_uop_T_2800, ram[4].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2951 = mux(_out_uop_T_2801, ram[5].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2952 = mux(_out_uop_T_2802, ram[6].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_2953 = or(_out_uop_T_2946, _out_uop_T_2947) node _out_uop_T_2954 = or(_out_uop_T_2953, _out_uop_T_2948) node _out_uop_T_2955 = or(_out_uop_T_2954, _out_uop_T_2949) node _out_uop_T_2956 = or(_out_uop_T_2955, _out_uop_T_2950) node _out_uop_T_2957 = or(_out_uop_T_2956, _out_uop_T_2951) node _out_uop_T_2958 = or(_out_uop_T_2957, _out_uop_T_2952) wire _out_uop_WIRE_245 : UInt<1> connect _out_uop_WIRE_245, _out_uop_T_2958 connect _out_uop_WIRE_235.sqrt, _out_uop_WIRE_245 node _out_uop_T_2959 = mux(_out_uop_T_2796, ram[0].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2960 = mux(_out_uop_T_2797, ram[1].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2961 = mux(_out_uop_T_2798, ram[2].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2962 = mux(_out_uop_T_2799, ram[3].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2963 = mux(_out_uop_T_2800, ram[4].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2964 = mux(_out_uop_T_2801, ram[5].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2965 = mux(_out_uop_T_2802, ram[6].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_2966 = or(_out_uop_T_2959, _out_uop_T_2960) node _out_uop_T_2967 = or(_out_uop_T_2966, _out_uop_T_2961) node _out_uop_T_2968 = or(_out_uop_T_2967, _out_uop_T_2962) node _out_uop_T_2969 = or(_out_uop_T_2968, _out_uop_T_2963) node _out_uop_T_2970 = or(_out_uop_T_2969, _out_uop_T_2964) node _out_uop_T_2971 = or(_out_uop_T_2970, _out_uop_T_2965) wire _out_uop_WIRE_246 : UInt<1> connect _out_uop_WIRE_246, _out_uop_T_2971 connect _out_uop_WIRE_235.div, _out_uop_WIRE_246 node _out_uop_T_2972 = mux(_out_uop_T_2796, ram[0].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2973 = mux(_out_uop_T_2797, ram[1].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2974 = mux(_out_uop_T_2798, ram[2].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2975 = mux(_out_uop_T_2799, ram[3].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2976 = mux(_out_uop_T_2800, ram[4].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2977 = mux(_out_uop_T_2801, ram[5].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2978 = mux(_out_uop_T_2802, ram[6].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_2979 = or(_out_uop_T_2972, _out_uop_T_2973) node _out_uop_T_2980 = or(_out_uop_T_2979, _out_uop_T_2974) node _out_uop_T_2981 = or(_out_uop_T_2980, _out_uop_T_2975) node _out_uop_T_2982 = or(_out_uop_T_2981, _out_uop_T_2976) node _out_uop_T_2983 = or(_out_uop_T_2982, _out_uop_T_2977) node _out_uop_T_2984 = or(_out_uop_T_2983, _out_uop_T_2978) wire _out_uop_WIRE_247 : UInt<1> connect _out_uop_WIRE_247, _out_uop_T_2984 connect _out_uop_WIRE_235.fma, _out_uop_WIRE_247 node _out_uop_T_2985 = mux(_out_uop_T_2796, ram[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2986 = mux(_out_uop_T_2797, ram[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2987 = mux(_out_uop_T_2798, ram[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2988 = mux(_out_uop_T_2799, ram[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2989 = mux(_out_uop_T_2800, ram[4].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2990 = mux(_out_uop_T_2801, ram[5].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2991 = mux(_out_uop_T_2802, ram[6].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_2992 = or(_out_uop_T_2985, _out_uop_T_2986) node _out_uop_T_2993 = or(_out_uop_T_2992, _out_uop_T_2987) node _out_uop_T_2994 = or(_out_uop_T_2993, _out_uop_T_2988) node _out_uop_T_2995 = or(_out_uop_T_2994, _out_uop_T_2989) node _out_uop_T_2996 = or(_out_uop_T_2995, _out_uop_T_2990) node _out_uop_T_2997 = or(_out_uop_T_2996, _out_uop_T_2991) wire _out_uop_WIRE_248 : UInt<1> connect _out_uop_WIRE_248, _out_uop_T_2997 connect _out_uop_WIRE_235.fastpipe, _out_uop_WIRE_248 node _out_uop_T_2998 = mux(_out_uop_T_2796, ram[0].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_2999 = mux(_out_uop_T_2797, ram[1].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_3000 = mux(_out_uop_T_2798, ram[2].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_3001 = mux(_out_uop_T_2799, ram[3].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_3002 = mux(_out_uop_T_2800, ram[4].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_3003 = mux(_out_uop_T_2801, ram[5].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_3004 = mux(_out_uop_T_2802, ram[6].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_3005 = or(_out_uop_T_2998, _out_uop_T_2999) node _out_uop_T_3006 = or(_out_uop_T_3005, _out_uop_T_3000) node _out_uop_T_3007 = or(_out_uop_T_3006, _out_uop_T_3001) node _out_uop_T_3008 = or(_out_uop_T_3007, _out_uop_T_3002) node _out_uop_T_3009 = or(_out_uop_T_3008, _out_uop_T_3003) node _out_uop_T_3010 = or(_out_uop_T_3009, _out_uop_T_3004) wire _out_uop_WIRE_249 : UInt<1> connect _out_uop_WIRE_249, _out_uop_T_3010 connect _out_uop_WIRE_235.toint, _out_uop_WIRE_249 node _out_uop_T_3011 = mux(_out_uop_T_2796, ram[0].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3012 = mux(_out_uop_T_2797, ram[1].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3013 = mux(_out_uop_T_2798, ram[2].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3014 = mux(_out_uop_T_2799, ram[3].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3015 = mux(_out_uop_T_2800, ram[4].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3016 = mux(_out_uop_T_2801, ram[5].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3017 = mux(_out_uop_T_2802, ram[6].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_3018 = or(_out_uop_T_3011, _out_uop_T_3012) node _out_uop_T_3019 = or(_out_uop_T_3018, _out_uop_T_3013) node _out_uop_T_3020 = or(_out_uop_T_3019, _out_uop_T_3014) node _out_uop_T_3021 = or(_out_uop_T_3020, _out_uop_T_3015) node _out_uop_T_3022 = or(_out_uop_T_3021, _out_uop_T_3016) node _out_uop_T_3023 = or(_out_uop_T_3022, _out_uop_T_3017) wire _out_uop_WIRE_250 : UInt<1> connect _out_uop_WIRE_250, _out_uop_T_3023 connect _out_uop_WIRE_235.fromint, _out_uop_WIRE_250 node _out_uop_T_3024 = mux(_out_uop_T_2796, ram[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3025 = mux(_out_uop_T_2797, ram[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3026 = mux(_out_uop_T_2798, ram[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3027 = mux(_out_uop_T_2799, ram[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3028 = mux(_out_uop_T_2800, ram[4].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3029 = mux(_out_uop_T_2801, ram[5].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3030 = mux(_out_uop_T_2802, ram[6].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3031 = or(_out_uop_T_3024, _out_uop_T_3025) node _out_uop_T_3032 = or(_out_uop_T_3031, _out_uop_T_3026) node _out_uop_T_3033 = or(_out_uop_T_3032, _out_uop_T_3027) node _out_uop_T_3034 = or(_out_uop_T_3033, _out_uop_T_3028) node _out_uop_T_3035 = or(_out_uop_T_3034, _out_uop_T_3029) node _out_uop_T_3036 = or(_out_uop_T_3035, _out_uop_T_3030) wire _out_uop_WIRE_251 : UInt<2> connect _out_uop_WIRE_251, _out_uop_T_3036 connect _out_uop_WIRE_235.typeTagOut, _out_uop_WIRE_251 node _out_uop_T_3037 = mux(_out_uop_T_2796, ram[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3038 = mux(_out_uop_T_2797, ram[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3039 = mux(_out_uop_T_2798, ram[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3040 = mux(_out_uop_T_2799, ram[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3041 = mux(_out_uop_T_2800, ram[4].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3042 = mux(_out_uop_T_2801, ram[5].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3043 = mux(_out_uop_T_2802, ram[6].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3044 = or(_out_uop_T_3037, _out_uop_T_3038) node _out_uop_T_3045 = or(_out_uop_T_3044, _out_uop_T_3039) node _out_uop_T_3046 = or(_out_uop_T_3045, _out_uop_T_3040) node _out_uop_T_3047 = or(_out_uop_T_3046, _out_uop_T_3041) node _out_uop_T_3048 = or(_out_uop_T_3047, _out_uop_T_3042) node _out_uop_T_3049 = or(_out_uop_T_3048, _out_uop_T_3043) wire _out_uop_WIRE_252 : UInt<2> connect _out_uop_WIRE_252, _out_uop_T_3049 connect _out_uop_WIRE_235.typeTagIn, _out_uop_WIRE_252 node _out_uop_T_3050 = mux(_out_uop_T_2796, ram[0].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3051 = mux(_out_uop_T_2797, ram[1].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3052 = mux(_out_uop_T_2798, ram[2].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3053 = mux(_out_uop_T_2799, ram[3].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3054 = mux(_out_uop_T_2800, ram[4].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3055 = mux(_out_uop_T_2801, ram[5].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3056 = mux(_out_uop_T_2802, ram[6].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_3057 = or(_out_uop_T_3050, _out_uop_T_3051) node _out_uop_T_3058 = or(_out_uop_T_3057, _out_uop_T_3052) node _out_uop_T_3059 = or(_out_uop_T_3058, _out_uop_T_3053) node _out_uop_T_3060 = or(_out_uop_T_3059, _out_uop_T_3054) node _out_uop_T_3061 = or(_out_uop_T_3060, _out_uop_T_3055) node _out_uop_T_3062 = or(_out_uop_T_3061, _out_uop_T_3056) wire _out_uop_WIRE_253 : UInt<1> connect _out_uop_WIRE_253, _out_uop_T_3062 connect _out_uop_WIRE_235.swap23, _out_uop_WIRE_253 node _out_uop_T_3063 = mux(_out_uop_T_2796, ram[0].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3064 = mux(_out_uop_T_2797, ram[1].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3065 = mux(_out_uop_T_2798, ram[2].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3066 = mux(_out_uop_T_2799, ram[3].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3067 = mux(_out_uop_T_2800, ram[4].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3068 = mux(_out_uop_T_2801, ram[5].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3069 = mux(_out_uop_T_2802, ram[6].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_3070 = or(_out_uop_T_3063, _out_uop_T_3064) node _out_uop_T_3071 = or(_out_uop_T_3070, _out_uop_T_3065) node _out_uop_T_3072 = or(_out_uop_T_3071, _out_uop_T_3066) node _out_uop_T_3073 = or(_out_uop_T_3072, _out_uop_T_3067) node _out_uop_T_3074 = or(_out_uop_T_3073, _out_uop_T_3068) node _out_uop_T_3075 = or(_out_uop_T_3074, _out_uop_T_3069) wire _out_uop_WIRE_254 : UInt<1> connect _out_uop_WIRE_254, _out_uop_T_3075 connect _out_uop_WIRE_235.swap12, _out_uop_WIRE_254 node _out_uop_T_3076 = mux(_out_uop_T_2796, ram[0].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3077 = mux(_out_uop_T_2797, ram[1].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3078 = mux(_out_uop_T_2798, ram[2].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3079 = mux(_out_uop_T_2799, ram[3].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3080 = mux(_out_uop_T_2800, ram[4].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3081 = mux(_out_uop_T_2801, ram[5].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3082 = mux(_out_uop_T_2802, ram[6].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_3083 = or(_out_uop_T_3076, _out_uop_T_3077) node _out_uop_T_3084 = or(_out_uop_T_3083, _out_uop_T_3078) node _out_uop_T_3085 = or(_out_uop_T_3084, _out_uop_T_3079) node _out_uop_T_3086 = or(_out_uop_T_3085, _out_uop_T_3080) node _out_uop_T_3087 = or(_out_uop_T_3086, _out_uop_T_3081) node _out_uop_T_3088 = or(_out_uop_T_3087, _out_uop_T_3082) wire _out_uop_WIRE_255 : UInt<1> connect _out_uop_WIRE_255, _out_uop_T_3088 connect _out_uop_WIRE_235.ren3, _out_uop_WIRE_255 node _out_uop_T_3089 = mux(_out_uop_T_2796, ram[0].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3090 = mux(_out_uop_T_2797, ram[1].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3091 = mux(_out_uop_T_2798, ram[2].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3092 = mux(_out_uop_T_2799, ram[3].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3093 = mux(_out_uop_T_2800, ram[4].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3094 = mux(_out_uop_T_2801, ram[5].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3095 = mux(_out_uop_T_2802, ram[6].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_3096 = or(_out_uop_T_3089, _out_uop_T_3090) node _out_uop_T_3097 = or(_out_uop_T_3096, _out_uop_T_3091) node _out_uop_T_3098 = or(_out_uop_T_3097, _out_uop_T_3092) node _out_uop_T_3099 = or(_out_uop_T_3098, _out_uop_T_3093) node _out_uop_T_3100 = or(_out_uop_T_3099, _out_uop_T_3094) node _out_uop_T_3101 = or(_out_uop_T_3100, _out_uop_T_3095) wire _out_uop_WIRE_256 : UInt<1> connect _out_uop_WIRE_256, _out_uop_T_3101 connect _out_uop_WIRE_235.ren2, _out_uop_WIRE_256 node _out_uop_T_3102 = mux(_out_uop_T_2796, ram[0].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3103 = mux(_out_uop_T_2797, ram[1].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3104 = mux(_out_uop_T_2798, ram[2].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3105 = mux(_out_uop_T_2799, ram[3].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3106 = mux(_out_uop_T_2800, ram[4].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3107 = mux(_out_uop_T_2801, ram[5].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3108 = mux(_out_uop_T_2802, ram[6].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_3109 = or(_out_uop_T_3102, _out_uop_T_3103) node _out_uop_T_3110 = or(_out_uop_T_3109, _out_uop_T_3104) node _out_uop_T_3111 = or(_out_uop_T_3110, _out_uop_T_3105) node _out_uop_T_3112 = or(_out_uop_T_3111, _out_uop_T_3106) node _out_uop_T_3113 = or(_out_uop_T_3112, _out_uop_T_3107) node _out_uop_T_3114 = or(_out_uop_T_3113, _out_uop_T_3108) wire _out_uop_WIRE_257 : UInt<1> connect _out_uop_WIRE_257, _out_uop_T_3114 connect _out_uop_WIRE_235.ren1, _out_uop_WIRE_257 node _out_uop_T_3115 = mux(_out_uop_T_2796, ram[0].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3116 = mux(_out_uop_T_2797, ram[1].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3117 = mux(_out_uop_T_2798, ram[2].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3118 = mux(_out_uop_T_2799, ram[3].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3119 = mux(_out_uop_T_2800, ram[4].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3120 = mux(_out_uop_T_2801, ram[5].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3121 = mux(_out_uop_T_2802, ram[6].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_3122 = or(_out_uop_T_3115, _out_uop_T_3116) node _out_uop_T_3123 = or(_out_uop_T_3122, _out_uop_T_3117) node _out_uop_T_3124 = or(_out_uop_T_3123, _out_uop_T_3118) node _out_uop_T_3125 = or(_out_uop_T_3124, _out_uop_T_3119) node _out_uop_T_3126 = or(_out_uop_T_3125, _out_uop_T_3120) node _out_uop_T_3127 = or(_out_uop_T_3126, _out_uop_T_3121) wire _out_uop_WIRE_258 : UInt<1> connect _out_uop_WIRE_258, _out_uop_T_3127 connect _out_uop_WIRE_235.wen, _out_uop_WIRE_258 node _out_uop_T_3128 = mux(_out_uop_T_2796, ram[0].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3129 = mux(_out_uop_T_2797, ram[1].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3130 = mux(_out_uop_T_2798, ram[2].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3131 = mux(_out_uop_T_2799, ram[3].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3132 = mux(_out_uop_T_2800, ram[4].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3133 = mux(_out_uop_T_2801, ram[5].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3134 = mux(_out_uop_T_2802, ram[6].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_3135 = or(_out_uop_T_3128, _out_uop_T_3129) node _out_uop_T_3136 = or(_out_uop_T_3135, _out_uop_T_3130) node _out_uop_T_3137 = or(_out_uop_T_3136, _out_uop_T_3131) node _out_uop_T_3138 = or(_out_uop_T_3137, _out_uop_T_3132) node _out_uop_T_3139 = or(_out_uop_T_3138, _out_uop_T_3133) node _out_uop_T_3140 = or(_out_uop_T_3139, _out_uop_T_3134) wire _out_uop_WIRE_259 : UInt<1> connect _out_uop_WIRE_259, _out_uop_T_3140 connect _out_uop_WIRE_235.ldst, _out_uop_WIRE_259 connect _out_uop_WIRE_232.fdivin, _out_uop_WIRE_235 node _out_uop_T_3141 = mux(_out_uop_T_2796, ram[0].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3142 = mux(_out_uop_T_2797, ram[1].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3143 = mux(_out_uop_T_2798, ram[2].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3144 = mux(_out_uop_T_2799, ram[3].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3145 = mux(_out_uop_T_2800, ram[4].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3146 = mux(_out_uop_T_2801, ram[5].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3147 = mux(_out_uop_T_2802, ram[6].bits.fexc, UInt<1>(0h0)) node _out_uop_T_3148 = or(_out_uop_T_3141, _out_uop_T_3142) node _out_uop_T_3149 = or(_out_uop_T_3148, _out_uop_T_3143) node _out_uop_T_3150 = or(_out_uop_T_3149, _out_uop_T_3144) node _out_uop_T_3151 = or(_out_uop_T_3150, _out_uop_T_3145) node _out_uop_T_3152 = or(_out_uop_T_3151, _out_uop_T_3146) node _out_uop_T_3153 = or(_out_uop_T_3152, _out_uop_T_3147) wire _out_uop_WIRE_260 : UInt<5> connect _out_uop_WIRE_260, _out_uop_T_3153 connect _out_uop_WIRE_232.fexc, _out_uop_WIRE_260 node _out_uop_T_3154 = mux(_out_uop_T_2796, ram[0].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3155 = mux(_out_uop_T_2797, ram[1].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3156 = mux(_out_uop_T_2798, ram[2].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3157 = mux(_out_uop_T_2799, ram[3].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3158 = mux(_out_uop_T_2800, ram[4].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3159 = mux(_out_uop_T_2801, ram[5].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3160 = mux(_out_uop_T_2802, ram[6].bits.fra3, UInt<1>(0h0)) node _out_uop_T_3161 = or(_out_uop_T_3154, _out_uop_T_3155) node _out_uop_T_3162 = or(_out_uop_T_3161, _out_uop_T_3156) node _out_uop_T_3163 = or(_out_uop_T_3162, _out_uop_T_3157) node _out_uop_T_3164 = or(_out_uop_T_3163, _out_uop_T_3158) node _out_uop_T_3165 = or(_out_uop_T_3164, _out_uop_T_3159) node _out_uop_T_3166 = or(_out_uop_T_3165, _out_uop_T_3160) wire _out_uop_WIRE_261 : UInt<5> connect _out_uop_WIRE_261, _out_uop_T_3166 connect _out_uop_WIRE_232.fra3, _out_uop_WIRE_261 node _out_uop_T_3167 = mux(_out_uop_T_2796, ram[0].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3168 = mux(_out_uop_T_2797, ram[1].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3169 = mux(_out_uop_T_2798, ram[2].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3170 = mux(_out_uop_T_2799, ram[3].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3171 = mux(_out_uop_T_2800, ram[4].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3172 = mux(_out_uop_T_2801, ram[5].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3173 = mux(_out_uop_T_2802, ram[6].bits.fra2, UInt<1>(0h0)) node _out_uop_T_3174 = or(_out_uop_T_3167, _out_uop_T_3168) node _out_uop_T_3175 = or(_out_uop_T_3174, _out_uop_T_3169) node _out_uop_T_3176 = or(_out_uop_T_3175, _out_uop_T_3170) node _out_uop_T_3177 = or(_out_uop_T_3176, _out_uop_T_3171) node _out_uop_T_3178 = or(_out_uop_T_3177, _out_uop_T_3172) node _out_uop_T_3179 = or(_out_uop_T_3178, _out_uop_T_3173) wire _out_uop_WIRE_262 : UInt<5> connect _out_uop_WIRE_262, _out_uop_T_3179 connect _out_uop_WIRE_232.fra2, _out_uop_WIRE_262 node _out_uop_T_3180 = mux(_out_uop_T_2796, ram[0].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3181 = mux(_out_uop_T_2797, ram[1].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3182 = mux(_out_uop_T_2798, ram[2].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3183 = mux(_out_uop_T_2799, ram[3].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3184 = mux(_out_uop_T_2800, ram[4].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3185 = mux(_out_uop_T_2801, ram[5].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3186 = mux(_out_uop_T_2802, ram[6].bits.fra1, UInt<1>(0h0)) node _out_uop_T_3187 = or(_out_uop_T_3180, _out_uop_T_3181) node _out_uop_T_3188 = or(_out_uop_T_3187, _out_uop_T_3182) node _out_uop_T_3189 = or(_out_uop_T_3188, _out_uop_T_3183) node _out_uop_T_3190 = or(_out_uop_T_3189, _out_uop_T_3184) node _out_uop_T_3191 = or(_out_uop_T_3190, _out_uop_T_3185) node _out_uop_T_3192 = or(_out_uop_T_3191, _out_uop_T_3186) wire _out_uop_WIRE_263 : UInt<5> connect _out_uop_WIRE_263, _out_uop_T_3192 connect _out_uop_WIRE_232.fra1, _out_uop_WIRE_263 wire _out_uop_WIRE_264 : { valid : UInt<1>, bits : UInt<64>} node _out_uop_T_3193 = mux(_out_uop_T_2796, ram[0].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3194 = mux(_out_uop_T_2797, ram[1].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3195 = mux(_out_uop_T_2798, ram[2].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3196 = mux(_out_uop_T_2799, ram[3].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3197 = mux(_out_uop_T_2800, ram[4].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3198 = mux(_out_uop_T_2801, ram[5].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3199 = mux(_out_uop_T_2802, ram[6].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_3200 = or(_out_uop_T_3193, _out_uop_T_3194) node _out_uop_T_3201 = or(_out_uop_T_3200, _out_uop_T_3195) node _out_uop_T_3202 = or(_out_uop_T_3201, _out_uop_T_3196) node _out_uop_T_3203 = or(_out_uop_T_3202, _out_uop_T_3197) node _out_uop_T_3204 = or(_out_uop_T_3203, _out_uop_T_3198) node _out_uop_T_3205 = or(_out_uop_T_3204, _out_uop_T_3199) wire _out_uop_WIRE_265 : UInt<64> connect _out_uop_WIRE_265, _out_uop_T_3205 connect _out_uop_WIRE_264.bits, _out_uop_WIRE_265 node _out_uop_T_3206 = mux(_out_uop_T_2796, ram[0].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3207 = mux(_out_uop_T_2797, ram[1].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3208 = mux(_out_uop_T_2798, ram[2].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3209 = mux(_out_uop_T_2799, ram[3].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3210 = mux(_out_uop_T_2800, ram[4].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3211 = mux(_out_uop_T_2801, ram[5].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3212 = mux(_out_uop_T_2802, ram[6].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_3213 = or(_out_uop_T_3206, _out_uop_T_3207) node _out_uop_T_3214 = or(_out_uop_T_3213, _out_uop_T_3208) node _out_uop_T_3215 = or(_out_uop_T_3214, _out_uop_T_3209) node _out_uop_T_3216 = or(_out_uop_T_3215, _out_uop_T_3210) node _out_uop_T_3217 = or(_out_uop_T_3216, _out_uop_T_3211) node _out_uop_T_3218 = or(_out_uop_T_3217, _out_uop_T_3212) wire _out_uop_WIRE_266 : UInt<1> connect _out_uop_WIRE_266, _out_uop_T_3218 connect _out_uop_WIRE_264.valid, _out_uop_WIRE_266 connect _out_uop_WIRE_232.wdata, _out_uop_WIRE_264 node _out_uop_T_3219 = mux(_out_uop_T_2796, ram[0].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3220 = mux(_out_uop_T_2797, ram[1].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3221 = mux(_out_uop_T_2798, ram[2].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3222 = mux(_out_uop_T_2799, ram[3].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3223 = mux(_out_uop_T_2800, ram[4].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3224 = mux(_out_uop_T_2801, ram[5].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3225 = mux(_out_uop_T_2802, ram[6].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_3226 = or(_out_uop_T_3219, _out_uop_T_3220) node _out_uop_T_3227 = or(_out_uop_T_3226, _out_uop_T_3221) node _out_uop_T_3228 = or(_out_uop_T_3227, _out_uop_T_3222) node _out_uop_T_3229 = or(_out_uop_T_3228, _out_uop_T_3223) node _out_uop_T_3230 = or(_out_uop_T_3229, _out_uop_T_3224) node _out_uop_T_3231 = or(_out_uop_T_3230, _out_uop_T_3225) wire _out_uop_WIRE_267 : UInt<1> connect _out_uop_WIRE_267, _out_uop_T_3231 connect _out_uop_WIRE_232.uses_latealu, _out_uop_WIRE_267 node _out_uop_T_3232 = mux(_out_uop_T_2796, ram[0].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3233 = mux(_out_uop_T_2797, ram[1].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3234 = mux(_out_uop_T_2798, ram[2].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3235 = mux(_out_uop_T_2799, ram[3].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3236 = mux(_out_uop_T_2800, ram[4].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3237 = mux(_out_uop_T_2801, ram[5].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3238 = mux(_out_uop_T_2802, ram[6].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_3239 = or(_out_uop_T_3232, _out_uop_T_3233) node _out_uop_T_3240 = or(_out_uop_T_3239, _out_uop_T_3234) node _out_uop_T_3241 = or(_out_uop_T_3240, _out_uop_T_3235) node _out_uop_T_3242 = or(_out_uop_T_3241, _out_uop_T_3236) node _out_uop_T_3243 = or(_out_uop_T_3242, _out_uop_T_3237) node _out_uop_T_3244 = or(_out_uop_T_3243, _out_uop_T_3238) wire _out_uop_WIRE_268 : UInt<1> connect _out_uop_WIRE_268, _out_uop_T_3244 connect _out_uop_WIRE_232.uses_memalu, _out_uop_WIRE_268 node _out_uop_T_3245 = mux(_out_uop_T_2796, ram[0].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3246 = mux(_out_uop_T_2797, ram[1].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3247 = mux(_out_uop_T_2798, ram[2].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3248 = mux(_out_uop_T_2799, ram[3].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3249 = mux(_out_uop_T_2800, ram[4].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3250 = mux(_out_uop_T_2801, ram[5].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3251 = mux(_out_uop_T_2802, ram[6].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_3252 = or(_out_uop_T_3245, _out_uop_T_3246) node _out_uop_T_3253 = or(_out_uop_T_3252, _out_uop_T_3247) node _out_uop_T_3254 = or(_out_uop_T_3253, _out_uop_T_3248) node _out_uop_T_3255 = or(_out_uop_T_3254, _out_uop_T_3249) node _out_uop_T_3256 = or(_out_uop_T_3255, _out_uop_T_3250) node _out_uop_T_3257 = or(_out_uop_T_3256, _out_uop_T_3251) wire _out_uop_WIRE_269 : UInt<64> connect _out_uop_WIRE_269, _out_uop_T_3257 connect _out_uop_WIRE_232.rs3_data, _out_uop_WIRE_269 node _out_uop_T_3258 = mux(_out_uop_T_2796, ram[0].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3259 = mux(_out_uop_T_2797, ram[1].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3260 = mux(_out_uop_T_2798, ram[2].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3261 = mux(_out_uop_T_2799, ram[3].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3262 = mux(_out_uop_T_2800, ram[4].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3263 = mux(_out_uop_T_2801, ram[5].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3264 = mux(_out_uop_T_2802, ram[6].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_3265 = or(_out_uop_T_3258, _out_uop_T_3259) node _out_uop_T_3266 = or(_out_uop_T_3265, _out_uop_T_3260) node _out_uop_T_3267 = or(_out_uop_T_3266, _out_uop_T_3261) node _out_uop_T_3268 = or(_out_uop_T_3267, _out_uop_T_3262) node _out_uop_T_3269 = or(_out_uop_T_3268, _out_uop_T_3263) node _out_uop_T_3270 = or(_out_uop_T_3269, _out_uop_T_3264) wire _out_uop_WIRE_270 : UInt<64> connect _out_uop_WIRE_270, _out_uop_T_3270 connect _out_uop_WIRE_232.rs2_data, _out_uop_WIRE_270 node _out_uop_T_3271 = mux(_out_uop_T_2796, ram[0].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3272 = mux(_out_uop_T_2797, ram[1].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3273 = mux(_out_uop_T_2798, ram[2].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3274 = mux(_out_uop_T_2799, ram[3].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3275 = mux(_out_uop_T_2800, ram[4].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3276 = mux(_out_uop_T_2801, ram[5].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3277 = mux(_out_uop_T_2802, ram[6].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_3278 = or(_out_uop_T_3271, _out_uop_T_3272) node _out_uop_T_3279 = or(_out_uop_T_3278, _out_uop_T_3273) node _out_uop_T_3280 = or(_out_uop_T_3279, _out_uop_T_3274) node _out_uop_T_3281 = or(_out_uop_T_3280, _out_uop_T_3275) node _out_uop_T_3282 = or(_out_uop_T_3281, _out_uop_T_3276) node _out_uop_T_3283 = or(_out_uop_T_3282, _out_uop_T_3277) wire _out_uop_WIRE_271 : UInt<64> connect _out_uop_WIRE_271, _out_uop_T_3283 connect _out_uop_WIRE_232.rs1_data, _out_uop_WIRE_271 node _out_uop_T_3284 = mux(_out_uop_T_2796, ram[0].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3285 = mux(_out_uop_T_2797, ram[1].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3286 = mux(_out_uop_T_2798, ram[2].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3287 = mux(_out_uop_T_2799, ram[3].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3288 = mux(_out_uop_T_2800, ram[4].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3289 = mux(_out_uop_T_2801, ram[5].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3290 = mux(_out_uop_T_2802, ram[6].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_3291 = or(_out_uop_T_3284, _out_uop_T_3285) node _out_uop_T_3292 = or(_out_uop_T_3291, _out_uop_T_3286) node _out_uop_T_3293 = or(_out_uop_T_3292, _out_uop_T_3287) node _out_uop_T_3294 = or(_out_uop_T_3293, _out_uop_T_3288) node _out_uop_T_3295 = or(_out_uop_T_3294, _out_uop_T_3289) node _out_uop_T_3296 = or(_out_uop_T_3295, _out_uop_T_3290) wire _out_uop_WIRE_272 : UInt<1> connect _out_uop_WIRE_272, _out_uop_T_3296 connect _out_uop_WIRE_232.needs_replay, _out_uop_WIRE_272 node _out_uop_T_3297 = mux(_out_uop_T_2796, ram[0].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3298 = mux(_out_uop_T_2797, ram[1].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3299 = mux(_out_uop_T_2798, ram[2].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3300 = mux(_out_uop_T_2799, ram[3].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3301 = mux(_out_uop_T_2800, ram[4].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3302 = mux(_out_uop_T_2801, ram[5].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3303 = mux(_out_uop_T_2802, ram[6].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_3304 = or(_out_uop_T_3297, _out_uop_T_3298) node _out_uop_T_3305 = or(_out_uop_T_3304, _out_uop_T_3299) node _out_uop_T_3306 = or(_out_uop_T_3305, _out_uop_T_3300) node _out_uop_T_3307 = or(_out_uop_T_3306, _out_uop_T_3301) node _out_uop_T_3308 = or(_out_uop_T_3307, _out_uop_T_3302) node _out_uop_T_3309 = or(_out_uop_T_3308, _out_uop_T_3303) wire _out_uop_WIRE_273 : UInt<64> connect _out_uop_WIRE_273, _out_uop_T_3309 connect _out_uop_WIRE_232.xcpt_cause, _out_uop_WIRE_273 node _out_uop_T_3310 = mux(_out_uop_T_2796, ram[0].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3311 = mux(_out_uop_T_2797, ram[1].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3312 = mux(_out_uop_T_2798, ram[2].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3313 = mux(_out_uop_T_2799, ram[3].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3314 = mux(_out_uop_T_2800, ram[4].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3315 = mux(_out_uop_T_2801, ram[5].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3316 = mux(_out_uop_T_2802, ram[6].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_3317 = or(_out_uop_T_3310, _out_uop_T_3311) node _out_uop_T_3318 = or(_out_uop_T_3317, _out_uop_T_3312) node _out_uop_T_3319 = or(_out_uop_T_3318, _out_uop_T_3313) node _out_uop_T_3320 = or(_out_uop_T_3319, _out_uop_T_3314) node _out_uop_T_3321 = or(_out_uop_T_3320, _out_uop_T_3315) node _out_uop_T_3322 = or(_out_uop_T_3321, _out_uop_T_3316) wire _out_uop_WIRE_274 : UInt<1> connect _out_uop_WIRE_274, _out_uop_T_3322 connect _out_uop_WIRE_232.xcpt, _out_uop_WIRE_274 node _out_uop_T_3323 = mux(_out_uop_T_2796, ram[0].bits.taken, UInt<1>(0h0)) node _out_uop_T_3324 = mux(_out_uop_T_2797, ram[1].bits.taken, UInt<1>(0h0)) node _out_uop_T_3325 = mux(_out_uop_T_2798, ram[2].bits.taken, UInt<1>(0h0)) node _out_uop_T_3326 = mux(_out_uop_T_2799, ram[3].bits.taken, UInt<1>(0h0)) node _out_uop_T_3327 = mux(_out_uop_T_2800, ram[4].bits.taken, UInt<1>(0h0)) node _out_uop_T_3328 = mux(_out_uop_T_2801, ram[5].bits.taken, UInt<1>(0h0)) node _out_uop_T_3329 = mux(_out_uop_T_2802, ram[6].bits.taken, UInt<1>(0h0)) node _out_uop_T_3330 = or(_out_uop_T_3323, _out_uop_T_3324) node _out_uop_T_3331 = or(_out_uop_T_3330, _out_uop_T_3325) node _out_uop_T_3332 = or(_out_uop_T_3331, _out_uop_T_3326) node _out_uop_T_3333 = or(_out_uop_T_3332, _out_uop_T_3327) node _out_uop_T_3334 = or(_out_uop_T_3333, _out_uop_T_3328) node _out_uop_T_3335 = or(_out_uop_T_3334, _out_uop_T_3329) wire _out_uop_WIRE_275 : UInt<1> connect _out_uop_WIRE_275, _out_uop_T_3335 connect _out_uop_WIRE_232.taken, _out_uop_WIRE_275 node _out_uop_T_3336 = mux(_out_uop_T_2796, ram[0].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3337 = mux(_out_uop_T_2797, ram[1].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3338 = mux(_out_uop_T_2798, ram[2].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3339 = mux(_out_uop_T_2799, ram[3].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3340 = mux(_out_uop_T_2800, ram[4].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3341 = mux(_out_uop_T_2801, ram[5].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3342 = mux(_out_uop_T_2802, ram[6].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_3343 = or(_out_uop_T_3336, _out_uop_T_3337) node _out_uop_T_3344 = or(_out_uop_T_3343, _out_uop_T_3338) node _out_uop_T_3345 = or(_out_uop_T_3344, _out_uop_T_3339) node _out_uop_T_3346 = or(_out_uop_T_3345, _out_uop_T_3340) node _out_uop_T_3347 = or(_out_uop_T_3346, _out_uop_T_3341) node _out_uop_T_3348 = or(_out_uop_T_3347, _out_uop_T_3342) wire _out_uop_WIRE_276 : UInt<3> connect _out_uop_WIRE_276, _out_uop_T_3348 connect _out_uop_WIRE_232.ras_head, _out_uop_WIRE_276 wire _out_uop_WIRE_277 : { valid : UInt<1>, bits : UInt<40>} node _out_uop_T_3349 = mux(_out_uop_T_2796, ram[0].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3350 = mux(_out_uop_T_2797, ram[1].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3351 = mux(_out_uop_T_2798, ram[2].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3352 = mux(_out_uop_T_2799, ram[3].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3353 = mux(_out_uop_T_2800, ram[4].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3354 = mux(_out_uop_T_2801, ram[5].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3355 = mux(_out_uop_T_2802, ram[6].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_3356 = or(_out_uop_T_3349, _out_uop_T_3350) node _out_uop_T_3357 = or(_out_uop_T_3356, _out_uop_T_3351) node _out_uop_T_3358 = or(_out_uop_T_3357, _out_uop_T_3352) node _out_uop_T_3359 = or(_out_uop_T_3358, _out_uop_T_3353) node _out_uop_T_3360 = or(_out_uop_T_3359, _out_uop_T_3354) node _out_uop_T_3361 = or(_out_uop_T_3360, _out_uop_T_3355) wire _out_uop_WIRE_278 : UInt<40> connect _out_uop_WIRE_278, _out_uop_T_3361 connect _out_uop_WIRE_277.bits, _out_uop_WIRE_278 node _out_uop_T_3362 = mux(_out_uop_T_2796, ram[0].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3363 = mux(_out_uop_T_2797, ram[1].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3364 = mux(_out_uop_T_2798, ram[2].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3365 = mux(_out_uop_T_2799, ram[3].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3366 = mux(_out_uop_T_2800, ram[4].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3367 = mux(_out_uop_T_2801, ram[5].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3368 = mux(_out_uop_T_2802, ram[6].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_3369 = or(_out_uop_T_3362, _out_uop_T_3363) node _out_uop_T_3370 = or(_out_uop_T_3369, _out_uop_T_3364) node _out_uop_T_3371 = or(_out_uop_T_3370, _out_uop_T_3365) node _out_uop_T_3372 = or(_out_uop_T_3371, _out_uop_T_3366) node _out_uop_T_3373 = or(_out_uop_T_3372, _out_uop_T_3367) node _out_uop_T_3374 = or(_out_uop_T_3373, _out_uop_T_3368) wire _out_uop_WIRE_279 : UInt<1> connect _out_uop_WIRE_279, _out_uop_T_3374 connect _out_uop_WIRE_277.valid, _out_uop_WIRE_279 connect _out_uop_WIRE_232.next_pc, _out_uop_WIRE_277 node _out_uop_T_3375 = mux(_out_uop_T_2796, ram[0].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3376 = mux(_out_uop_T_2797, ram[1].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3377 = mux(_out_uop_T_2798, ram[2].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3378 = mux(_out_uop_T_2799, ram[3].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3379 = mux(_out_uop_T_2800, ram[4].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3380 = mux(_out_uop_T_2801, ram[5].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3381 = mux(_out_uop_T_2802, ram[6].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_3382 = or(_out_uop_T_3375, _out_uop_T_3376) node _out_uop_T_3383 = or(_out_uop_T_3382, _out_uop_T_3377) node _out_uop_T_3384 = or(_out_uop_T_3383, _out_uop_T_3378) node _out_uop_T_3385 = or(_out_uop_T_3384, _out_uop_T_3379) node _out_uop_T_3386 = or(_out_uop_T_3385, _out_uop_T_3380) node _out_uop_T_3387 = or(_out_uop_T_3386, _out_uop_T_3381) wire _out_uop_WIRE_280 : UInt<1> connect _out_uop_WIRE_280, _out_uop_T_3387 connect _out_uop_WIRE_232.sfb_shadow, _out_uop_WIRE_280 node _out_uop_T_3388 = mux(_out_uop_T_2796, ram[0].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3389 = mux(_out_uop_T_2797, ram[1].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3390 = mux(_out_uop_T_2798, ram[2].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3391 = mux(_out_uop_T_2799, ram[3].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3392 = mux(_out_uop_T_2800, ram[4].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3393 = mux(_out_uop_T_2801, ram[5].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3394 = mux(_out_uop_T_2802, ram[6].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_3395 = or(_out_uop_T_3388, _out_uop_T_3389) node _out_uop_T_3396 = or(_out_uop_T_3395, _out_uop_T_3390) node _out_uop_T_3397 = or(_out_uop_T_3396, _out_uop_T_3391) node _out_uop_T_3398 = or(_out_uop_T_3397, _out_uop_T_3392) node _out_uop_T_3399 = or(_out_uop_T_3398, _out_uop_T_3393) node _out_uop_T_3400 = or(_out_uop_T_3399, _out_uop_T_3394) wire _out_uop_WIRE_281 : UInt<1> connect _out_uop_WIRE_281, _out_uop_T_3400 connect _out_uop_WIRE_232.sfb_br, _out_uop_WIRE_281 wire _out_uop_WIRE_282 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _out_uop_WIRE_283 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _out_uop_WIRE_284 : { history : UInt<8>, value : UInt<2>} node _out_uop_T_3401 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3402 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3403 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3404 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3405 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3406 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3407 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_3408 = or(_out_uop_T_3401, _out_uop_T_3402) node _out_uop_T_3409 = or(_out_uop_T_3408, _out_uop_T_3403) node _out_uop_T_3410 = or(_out_uop_T_3409, _out_uop_T_3404) node _out_uop_T_3411 = or(_out_uop_T_3410, _out_uop_T_3405) node _out_uop_T_3412 = or(_out_uop_T_3411, _out_uop_T_3406) node _out_uop_T_3413 = or(_out_uop_T_3412, _out_uop_T_3407) wire _out_uop_WIRE_285 : UInt<2> connect _out_uop_WIRE_285, _out_uop_T_3413 connect _out_uop_WIRE_284.value, _out_uop_WIRE_285 node _out_uop_T_3414 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3415 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3416 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3417 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3418 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3419 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3420 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_3421 = or(_out_uop_T_3414, _out_uop_T_3415) node _out_uop_T_3422 = or(_out_uop_T_3421, _out_uop_T_3416) node _out_uop_T_3423 = or(_out_uop_T_3422, _out_uop_T_3417) node _out_uop_T_3424 = or(_out_uop_T_3423, _out_uop_T_3418) node _out_uop_T_3425 = or(_out_uop_T_3424, _out_uop_T_3419) node _out_uop_T_3426 = or(_out_uop_T_3425, _out_uop_T_3420) wire _out_uop_WIRE_286 : UInt<8> connect _out_uop_WIRE_286, _out_uop_T_3426 connect _out_uop_WIRE_284.history, _out_uop_WIRE_286 connect _out_uop_WIRE_283.bht, _out_uop_WIRE_284 node _out_uop_T_3427 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3428 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3429 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3430 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3431 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3432 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3433 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_3434 = or(_out_uop_T_3427, _out_uop_T_3428) node _out_uop_T_3435 = or(_out_uop_T_3434, _out_uop_T_3429) node _out_uop_T_3436 = or(_out_uop_T_3435, _out_uop_T_3430) node _out_uop_T_3437 = or(_out_uop_T_3436, _out_uop_T_3431) node _out_uop_T_3438 = or(_out_uop_T_3437, _out_uop_T_3432) node _out_uop_T_3439 = or(_out_uop_T_3438, _out_uop_T_3433) wire _out_uop_WIRE_287 : UInt<6> connect _out_uop_WIRE_287, _out_uop_T_3439 connect _out_uop_WIRE_283.entry, _out_uop_WIRE_287 node _out_uop_T_3440 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3441 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3442 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3443 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3444 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3445 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3446 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_3447 = or(_out_uop_T_3440, _out_uop_T_3441) node _out_uop_T_3448 = or(_out_uop_T_3447, _out_uop_T_3442) node _out_uop_T_3449 = or(_out_uop_T_3448, _out_uop_T_3443) node _out_uop_T_3450 = or(_out_uop_T_3449, _out_uop_T_3444) node _out_uop_T_3451 = or(_out_uop_T_3450, _out_uop_T_3445) node _out_uop_T_3452 = or(_out_uop_T_3451, _out_uop_T_3446) wire _out_uop_WIRE_288 : UInt<39> connect _out_uop_WIRE_288, _out_uop_T_3452 connect _out_uop_WIRE_283.target, _out_uop_WIRE_288 node _out_uop_T_3453 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3454 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3455 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3456 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3457 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3458 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3459 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_3460 = or(_out_uop_T_3453, _out_uop_T_3454) node _out_uop_T_3461 = or(_out_uop_T_3460, _out_uop_T_3455) node _out_uop_T_3462 = or(_out_uop_T_3461, _out_uop_T_3456) node _out_uop_T_3463 = or(_out_uop_T_3462, _out_uop_T_3457) node _out_uop_T_3464 = or(_out_uop_T_3463, _out_uop_T_3458) node _out_uop_T_3465 = or(_out_uop_T_3464, _out_uop_T_3459) wire _out_uop_WIRE_289 : UInt<2> connect _out_uop_WIRE_289, _out_uop_T_3465 connect _out_uop_WIRE_283.bridx, _out_uop_WIRE_289 node _out_uop_T_3466 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3467 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3468 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3469 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3470 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3471 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3472 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_3473 = or(_out_uop_T_3466, _out_uop_T_3467) node _out_uop_T_3474 = or(_out_uop_T_3473, _out_uop_T_3468) node _out_uop_T_3475 = or(_out_uop_T_3474, _out_uop_T_3469) node _out_uop_T_3476 = or(_out_uop_T_3475, _out_uop_T_3470) node _out_uop_T_3477 = or(_out_uop_T_3476, _out_uop_T_3471) node _out_uop_T_3478 = or(_out_uop_T_3477, _out_uop_T_3472) wire _out_uop_WIRE_290 : UInt<4> connect _out_uop_WIRE_290, _out_uop_T_3478 connect _out_uop_WIRE_283.mask, _out_uop_WIRE_290 node _out_uop_T_3479 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3480 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3481 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3482 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3483 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3484 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3485 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_3486 = or(_out_uop_T_3479, _out_uop_T_3480) node _out_uop_T_3487 = or(_out_uop_T_3486, _out_uop_T_3481) node _out_uop_T_3488 = or(_out_uop_T_3487, _out_uop_T_3482) node _out_uop_T_3489 = or(_out_uop_T_3488, _out_uop_T_3483) node _out_uop_T_3490 = or(_out_uop_T_3489, _out_uop_T_3484) node _out_uop_T_3491 = or(_out_uop_T_3490, _out_uop_T_3485) wire _out_uop_WIRE_291 : UInt<1> connect _out_uop_WIRE_291, _out_uop_T_3491 connect _out_uop_WIRE_283.taken, _out_uop_WIRE_291 node _out_uop_T_3492 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3493 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3494 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3495 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3496 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3497 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3498 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_3499 = or(_out_uop_T_3492, _out_uop_T_3493) node _out_uop_T_3500 = or(_out_uop_T_3499, _out_uop_T_3494) node _out_uop_T_3501 = or(_out_uop_T_3500, _out_uop_T_3495) node _out_uop_T_3502 = or(_out_uop_T_3501, _out_uop_T_3496) node _out_uop_T_3503 = or(_out_uop_T_3502, _out_uop_T_3497) node _out_uop_T_3504 = or(_out_uop_T_3503, _out_uop_T_3498) wire _out_uop_WIRE_292 : UInt<2> connect _out_uop_WIRE_292, _out_uop_T_3504 connect _out_uop_WIRE_283.cfiType, _out_uop_WIRE_292 connect _out_uop_WIRE_282.bits, _out_uop_WIRE_283 node _out_uop_T_3505 = mux(_out_uop_T_2796, ram[0].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3506 = mux(_out_uop_T_2797, ram[1].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3507 = mux(_out_uop_T_2798, ram[2].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3508 = mux(_out_uop_T_2799, ram[3].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3509 = mux(_out_uop_T_2800, ram[4].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3510 = mux(_out_uop_T_2801, ram[5].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3511 = mux(_out_uop_T_2802, ram[6].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_3512 = or(_out_uop_T_3505, _out_uop_T_3506) node _out_uop_T_3513 = or(_out_uop_T_3512, _out_uop_T_3507) node _out_uop_T_3514 = or(_out_uop_T_3513, _out_uop_T_3508) node _out_uop_T_3515 = or(_out_uop_T_3514, _out_uop_T_3509) node _out_uop_T_3516 = or(_out_uop_T_3515, _out_uop_T_3510) node _out_uop_T_3517 = or(_out_uop_T_3516, _out_uop_T_3511) wire _out_uop_WIRE_293 : UInt<1> connect _out_uop_WIRE_293, _out_uop_T_3517 connect _out_uop_WIRE_282.valid, _out_uop_WIRE_293 connect _out_uop_WIRE_232.btb_resp, _out_uop_WIRE_282 node _out_uop_T_3518 = mux(_out_uop_T_2796, ram[0].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3519 = mux(_out_uop_T_2797, ram[1].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3520 = mux(_out_uop_T_2798, ram[2].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3521 = mux(_out_uop_T_2799, ram[3].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3522 = mux(_out_uop_T_2800, ram[4].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3523 = mux(_out_uop_T_2801, ram[5].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3524 = mux(_out_uop_T_2802, ram[6].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_3525 = or(_out_uop_T_3518, _out_uop_T_3519) node _out_uop_T_3526 = or(_out_uop_T_3525, _out_uop_T_3520) node _out_uop_T_3527 = or(_out_uop_T_3526, _out_uop_T_3521) node _out_uop_T_3528 = or(_out_uop_T_3527, _out_uop_T_3522) node _out_uop_T_3529 = or(_out_uop_T_3528, _out_uop_T_3523) node _out_uop_T_3530 = or(_out_uop_T_3529, _out_uop_T_3524) wire _out_uop_WIRE_294 : UInt<1> connect _out_uop_WIRE_294, _out_uop_T_3530 connect _out_uop_WIRE_232.sets_vcfg, _out_uop_WIRE_294 node _out_uop_T_3531 = mux(_out_uop_T_2796, ram[0].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3532 = mux(_out_uop_T_2797, ram[1].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3533 = mux(_out_uop_T_2798, ram[2].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3534 = mux(_out_uop_T_2799, ram[3].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3535 = mux(_out_uop_T_2800, ram[4].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3536 = mux(_out_uop_T_2801, ram[5].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3537 = mux(_out_uop_T_2802, ram[6].bits.rvc, UInt<1>(0h0)) node _out_uop_T_3538 = or(_out_uop_T_3531, _out_uop_T_3532) node _out_uop_T_3539 = or(_out_uop_T_3538, _out_uop_T_3533) node _out_uop_T_3540 = or(_out_uop_T_3539, _out_uop_T_3534) node _out_uop_T_3541 = or(_out_uop_T_3540, _out_uop_T_3535) node _out_uop_T_3542 = or(_out_uop_T_3541, _out_uop_T_3536) node _out_uop_T_3543 = or(_out_uop_T_3542, _out_uop_T_3537) wire _out_uop_WIRE_295 : UInt<1> connect _out_uop_WIRE_295, _out_uop_T_3543 connect _out_uop_WIRE_232.rvc, _out_uop_WIRE_295 wire _out_uop_WIRE_296 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _out_uop_T_3544 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3545 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3546 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3547 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3548 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3549 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3550 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3551 = or(_out_uop_T_3544, _out_uop_T_3545) node _out_uop_T_3552 = or(_out_uop_T_3551, _out_uop_T_3546) node _out_uop_T_3553 = or(_out_uop_T_3552, _out_uop_T_3547) node _out_uop_T_3554 = or(_out_uop_T_3553, _out_uop_T_3548) node _out_uop_T_3555 = or(_out_uop_T_3554, _out_uop_T_3549) node _out_uop_T_3556 = or(_out_uop_T_3555, _out_uop_T_3550) wire _out_uop_WIRE_297 : UInt<1> connect _out_uop_WIRE_297, _out_uop_T_3556 connect _out_uop_WIRE_296.vec, _out_uop_WIRE_297 node _out_uop_T_3557 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3558 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3559 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3560 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3561 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3562 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3563 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_3564 = or(_out_uop_T_3557, _out_uop_T_3558) node _out_uop_T_3565 = or(_out_uop_T_3564, _out_uop_T_3559) node _out_uop_T_3566 = or(_out_uop_T_3565, _out_uop_T_3560) node _out_uop_T_3567 = or(_out_uop_T_3566, _out_uop_T_3561) node _out_uop_T_3568 = or(_out_uop_T_3567, _out_uop_T_3562) node _out_uop_T_3569 = or(_out_uop_T_3568, _out_uop_T_3563) wire _out_uop_WIRE_298 : UInt<1> connect _out_uop_WIRE_298, _out_uop_T_3569 connect _out_uop_WIRE_296.wflags, _out_uop_WIRE_298 node _out_uop_T_3570 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3571 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3572 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3573 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3574 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3575 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3576 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_3577 = or(_out_uop_T_3570, _out_uop_T_3571) node _out_uop_T_3578 = or(_out_uop_T_3577, _out_uop_T_3572) node _out_uop_T_3579 = or(_out_uop_T_3578, _out_uop_T_3573) node _out_uop_T_3580 = or(_out_uop_T_3579, _out_uop_T_3574) node _out_uop_T_3581 = or(_out_uop_T_3580, _out_uop_T_3575) node _out_uop_T_3582 = or(_out_uop_T_3581, _out_uop_T_3576) wire _out_uop_WIRE_299 : UInt<1> connect _out_uop_WIRE_299, _out_uop_T_3582 connect _out_uop_WIRE_296.sqrt, _out_uop_WIRE_299 node _out_uop_T_3583 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3584 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3585 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3586 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3587 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3588 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3589 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_3590 = or(_out_uop_T_3583, _out_uop_T_3584) node _out_uop_T_3591 = or(_out_uop_T_3590, _out_uop_T_3585) node _out_uop_T_3592 = or(_out_uop_T_3591, _out_uop_T_3586) node _out_uop_T_3593 = or(_out_uop_T_3592, _out_uop_T_3587) node _out_uop_T_3594 = or(_out_uop_T_3593, _out_uop_T_3588) node _out_uop_T_3595 = or(_out_uop_T_3594, _out_uop_T_3589) wire _out_uop_WIRE_300 : UInt<1> connect _out_uop_WIRE_300, _out_uop_T_3595 connect _out_uop_WIRE_296.div, _out_uop_WIRE_300 node _out_uop_T_3596 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3597 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3598 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3599 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3600 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3601 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3602 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_3603 = or(_out_uop_T_3596, _out_uop_T_3597) node _out_uop_T_3604 = or(_out_uop_T_3603, _out_uop_T_3598) node _out_uop_T_3605 = or(_out_uop_T_3604, _out_uop_T_3599) node _out_uop_T_3606 = or(_out_uop_T_3605, _out_uop_T_3600) node _out_uop_T_3607 = or(_out_uop_T_3606, _out_uop_T_3601) node _out_uop_T_3608 = or(_out_uop_T_3607, _out_uop_T_3602) wire _out_uop_WIRE_301 : UInt<1> connect _out_uop_WIRE_301, _out_uop_T_3608 connect _out_uop_WIRE_296.fma, _out_uop_WIRE_301 node _out_uop_T_3609 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3610 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3611 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3612 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3613 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3614 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3615 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_3616 = or(_out_uop_T_3609, _out_uop_T_3610) node _out_uop_T_3617 = or(_out_uop_T_3616, _out_uop_T_3611) node _out_uop_T_3618 = or(_out_uop_T_3617, _out_uop_T_3612) node _out_uop_T_3619 = or(_out_uop_T_3618, _out_uop_T_3613) node _out_uop_T_3620 = or(_out_uop_T_3619, _out_uop_T_3614) node _out_uop_T_3621 = or(_out_uop_T_3620, _out_uop_T_3615) wire _out_uop_WIRE_302 : UInt<1> connect _out_uop_WIRE_302, _out_uop_T_3621 connect _out_uop_WIRE_296.fastpipe, _out_uop_WIRE_302 node _out_uop_T_3622 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3623 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3624 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3625 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3626 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3627 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3628 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_3629 = or(_out_uop_T_3622, _out_uop_T_3623) node _out_uop_T_3630 = or(_out_uop_T_3629, _out_uop_T_3624) node _out_uop_T_3631 = or(_out_uop_T_3630, _out_uop_T_3625) node _out_uop_T_3632 = or(_out_uop_T_3631, _out_uop_T_3626) node _out_uop_T_3633 = or(_out_uop_T_3632, _out_uop_T_3627) node _out_uop_T_3634 = or(_out_uop_T_3633, _out_uop_T_3628) wire _out_uop_WIRE_303 : UInt<1> connect _out_uop_WIRE_303, _out_uop_T_3634 connect _out_uop_WIRE_296.toint, _out_uop_WIRE_303 node _out_uop_T_3635 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3636 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3637 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3638 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3639 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3640 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3641 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_3642 = or(_out_uop_T_3635, _out_uop_T_3636) node _out_uop_T_3643 = or(_out_uop_T_3642, _out_uop_T_3637) node _out_uop_T_3644 = or(_out_uop_T_3643, _out_uop_T_3638) node _out_uop_T_3645 = or(_out_uop_T_3644, _out_uop_T_3639) node _out_uop_T_3646 = or(_out_uop_T_3645, _out_uop_T_3640) node _out_uop_T_3647 = or(_out_uop_T_3646, _out_uop_T_3641) wire _out_uop_WIRE_304 : UInt<1> connect _out_uop_WIRE_304, _out_uop_T_3647 connect _out_uop_WIRE_296.fromint, _out_uop_WIRE_304 node _out_uop_T_3648 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3649 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3650 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3651 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3652 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3653 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3654 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_3655 = or(_out_uop_T_3648, _out_uop_T_3649) node _out_uop_T_3656 = or(_out_uop_T_3655, _out_uop_T_3650) node _out_uop_T_3657 = or(_out_uop_T_3656, _out_uop_T_3651) node _out_uop_T_3658 = or(_out_uop_T_3657, _out_uop_T_3652) node _out_uop_T_3659 = or(_out_uop_T_3658, _out_uop_T_3653) node _out_uop_T_3660 = or(_out_uop_T_3659, _out_uop_T_3654) wire _out_uop_WIRE_305 : UInt<2> connect _out_uop_WIRE_305, _out_uop_T_3660 connect _out_uop_WIRE_296.typeTagOut, _out_uop_WIRE_305 node _out_uop_T_3661 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3662 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3663 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3664 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3665 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3666 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3667 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_3668 = or(_out_uop_T_3661, _out_uop_T_3662) node _out_uop_T_3669 = or(_out_uop_T_3668, _out_uop_T_3663) node _out_uop_T_3670 = or(_out_uop_T_3669, _out_uop_T_3664) node _out_uop_T_3671 = or(_out_uop_T_3670, _out_uop_T_3665) node _out_uop_T_3672 = or(_out_uop_T_3671, _out_uop_T_3666) node _out_uop_T_3673 = or(_out_uop_T_3672, _out_uop_T_3667) wire _out_uop_WIRE_306 : UInt<2> connect _out_uop_WIRE_306, _out_uop_T_3673 connect _out_uop_WIRE_296.typeTagIn, _out_uop_WIRE_306 node _out_uop_T_3674 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3675 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3676 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3677 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3678 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3679 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3680 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_3681 = or(_out_uop_T_3674, _out_uop_T_3675) node _out_uop_T_3682 = or(_out_uop_T_3681, _out_uop_T_3676) node _out_uop_T_3683 = or(_out_uop_T_3682, _out_uop_T_3677) node _out_uop_T_3684 = or(_out_uop_T_3683, _out_uop_T_3678) node _out_uop_T_3685 = or(_out_uop_T_3684, _out_uop_T_3679) node _out_uop_T_3686 = or(_out_uop_T_3685, _out_uop_T_3680) wire _out_uop_WIRE_307 : UInt<1> connect _out_uop_WIRE_307, _out_uop_T_3686 connect _out_uop_WIRE_296.swap23, _out_uop_WIRE_307 node _out_uop_T_3687 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3688 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3689 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3690 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3691 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3692 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3693 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_3694 = or(_out_uop_T_3687, _out_uop_T_3688) node _out_uop_T_3695 = or(_out_uop_T_3694, _out_uop_T_3689) node _out_uop_T_3696 = or(_out_uop_T_3695, _out_uop_T_3690) node _out_uop_T_3697 = or(_out_uop_T_3696, _out_uop_T_3691) node _out_uop_T_3698 = or(_out_uop_T_3697, _out_uop_T_3692) node _out_uop_T_3699 = or(_out_uop_T_3698, _out_uop_T_3693) wire _out_uop_WIRE_308 : UInt<1> connect _out_uop_WIRE_308, _out_uop_T_3699 connect _out_uop_WIRE_296.swap12, _out_uop_WIRE_308 node _out_uop_T_3700 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3701 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3702 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3703 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3704 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3705 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3706 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_3707 = or(_out_uop_T_3700, _out_uop_T_3701) node _out_uop_T_3708 = or(_out_uop_T_3707, _out_uop_T_3702) node _out_uop_T_3709 = or(_out_uop_T_3708, _out_uop_T_3703) node _out_uop_T_3710 = or(_out_uop_T_3709, _out_uop_T_3704) node _out_uop_T_3711 = or(_out_uop_T_3710, _out_uop_T_3705) node _out_uop_T_3712 = or(_out_uop_T_3711, _out_uop_T_3706) wire _out_uop_WIRE_309 : UInt<1> connect _out_uop_WIRE_309, _out_uop_T_3712 connect _out_uop_WIRE_296.ren3, _out_uop_WIRE_309 node _out_uop_T_3713 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3714 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3715 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3716 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3717 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3718 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3719 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_3720 = or(_out_uop_T_3713, _out_uop_T_3714) node _out_uop_T_3721 = or(_out_uop_T_3720, _out_uop_T_3715) node _out_uop_T_3722 = or(_out_uop_T_3721, _out_uop_T_3716) node _out_uop_T_3723 = or(_out_uop_T_3722, _out_uop_T_3717) node _out_uop_T_3724 = or(_out_uop_T_3723, _out_uop_T_3718) node _out_uop_T_3725 = or(_out_uop_T_3724, _out_uop_T_3719) wire _out_uop_WIRE_310 : UInt<1> connect _out_uop_WIRE_310, _out_uop_T_3725 connect _out_uop_WIRE_296.ren2, _out_uop_WIRE_310 node _out_uop_T_3726 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3727 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3728 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3729 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3730 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3731 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3732 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_3733 = or(_out_uop_T_3726, _out_uop_T_3727) node _out_uop_T_3734 = or(_out_uop_T_3733, _out_uop_T_3728) node _out_uop_T_3735 = or(_out_uop_T_3734, _out_uop_T_3729) node _out_uop_T_3736 = or(_out_uop_T_3735, _out_uop_T_3730) node _out_uop_T_3737 = or(_out_uop_T_3736, _out_uop_T_3731) node _out_uop_T_3738 = or(_out_uop_T_3737, _out_uop_T_3732) wire _out_uop_WIRE_311 : UInt<1> connect _out_uop_WIRE_311, _out_uop_T_3738 connect _out_uop_WIRE_296.ren1, _out_uop_WIRE_311 node _out_uop_T_3739 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3740 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3741 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3742 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3743 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3744 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3745 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_3746 = or(_out_uop_T_3739, _out_uop_T_3740) node _out_uop_T_3747 = or(_out_uop_T_3746, _out_uop_T_3741) node _out_uop_T_3748 = or(_out_uop_T_3747, _out_uop_T_3742) node _out_uop_T_3749 = or(_out_uop_T_3748, _out_uop_T_3743) node _out_uop_T_3750 = or(_out_uop_T_3749, _out_uop_T_3744) node _out_uop_T_3751 = or(_out_uop_T_3750, _out_uop_T_3745) wire _out_uop_WIRE_312 : UInt<1> connect _out_uop_WIRE_312, _out_uop_T_3751 connect _out_uop_WIRE_296.wen, _out_uop_WIRE_312 node _out_uop_T_3752 = mux(_out_uop_T_2796, ram[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3753 = mux(_out_uop_T_2797, ram[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3754 = mux(_out_uop_T_2798, ram[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3755 = mux(_out_uop_T_2799, ram[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3756 = mux(_out_uop_T_2800, ram[4].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3757 = mux(_out_uop_T_2801, ram[5].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3758 = mux(_out_uop_T_2802, ram[6].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_3759 = or(_out_uop_T_3752, _out_uop_T_3753) node _out_uop_T_3760 = or(_out_uop_T_3759, _out_uop_T_3754) node _out_uop_T_3761 = or(_out_uop_T_3760, _out_uop_T_3755) node _out_uop_T_3762 = or(_out_uop_T_3761, _out_uop_T_3756) node _out_uop_T_3763 = or(_out_uop_T_3762, _out_uop_T_3757) node _out_uop_T_3764 = or(_out_uop_T_3763, _out_uop_T_3758) wire _out_uop_WIRE_313 : UInt<1> connect _out_uop_WIRE_313, _out_uop_T_3764 connect _out_uop_WIRE_296.ldst, _out_uop_WIRE_313 connect _out_uop_WIRE_232.fp_ctrl, _out_uop_WIRE_296 wire _out_uop_WIRE_314 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _out_uop_T_3765 = mux(_out_uop_T_2796, ram[0].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3766 = mux(_out_uop_T_2797, ram[1].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3767 = mux(_out_uop_T_2798, ram[2].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3768 = mux(_out_uop_T_2799, ram[3].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3769 = mux(_out_uop_T_2800, ram[4].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3770 = mux(_out_uop_T_2801, ram[5].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3771 = mux(_out_uop_T_2802, ram[6].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_3772 = or(_out_uop_T_3765, _out_uop_T_3766) node _out_uop_T_3773 = or(_out_uop_T_3772, _out_uop_T_3767) node _out_uop_T_3774 = or(_out_uop_T_3773, _out_uop_T_3768) node _out_uop_T_3775 = or(_out_uop_T_3774, _out_uop_T_3769) node _out_uop_T_3776 = or(_out_uop_T_3775, _out_uop_T_3770) node _out_uop_T_3777 = or(_out_uop_T_3776, _out_uop_T_3771) wire _out_uop_WIRE_315 : UInt<1> connect _out_uop_WIRE_315, _out_uop_T_3777 connect _out_uop_WIRE_314.vec, _out_uop_WIRE_315 node _out_uop_T_3778 = mux(_out_uop_T_2796, ram[0].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3779 = mux(_out_uop_T_2797, ram[1].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3780 = mux(_out_uop_T_2798, ram[2].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3781 = mux(_out_uop_T_2799, ram[3].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3782 = mux(_out_uop_T_2800, ram[4].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3783 = mux(_out_uop_T_2801, ram[5].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3784 = mux(_out_uop_T_2802, ram[6].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_3785 = or(_out_uop_T_3778, _out_uop_T_3779) node _out_uop_T_3786 = or(_out_uop_T_3785, _out_uop_T_3780) node _out_uop_T_3787 = or(_out_uop_T_3786, _out_uop_T_3781) node _out_uop_T_3788 = or(_out_uop_T_3787, _out_uop_T_3782) node _out_uop_T_3789 = or(_out_uop_T_3788, _out_uop_T_3783) node _out_uop_T_3790 = or(_out_uop_T_3789, _out_uop_T_3784) wire _out_uop_WIRE_316 : UInt<1> connect _out_uop_WIRE_316, _out_uop_T_3790 connect _out_uop_WIRE_314.dp, _out_uop_WIRE_316 node _out_uop_T_3791 = mux(_out_uop_T_2796, ram[0].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3792 = mux(_out_uop_T_2797, ram[1].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3793 = mux(_out_uop_T_2798, ram[2].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3794 = mux(_out_uop_T_2799, ram[3].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3795 = mux(_out_uop_T_2800, ram[4].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3796 = mux(_out_uop_T_2801, ram[5].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3797 = mux(_out_uop_T_2802, ram[6].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_3798 = or(_out_uop_T_3791, _out_uop_T_3792) node _out_uop_T_3799 = or(_out_uop_T_3798, _out_uop_T_3793) node _out_uop_T_3800 = or(_out_uop_T_3799, _out_uop_T_3794) node _out_uop_T_3801 = or(_out_uop_T_3800, _out_uop_T_3795) node _out_uop_T_3802 = or(_out_uop_T_3801, _out_uop_T_3796) node _out_uop_T_3803 = or(_out_uop_T_3802, _out_uop_T_3797) wire _out_uop_WIRE_317 : UInt<1> connect _out_uop_WIRE_317, _out_uop_T_3803 connect _out_uop_WIRE_314.amo, _out_uop_WIRE_317 node _out_uop_T_3804 = mux(_out_uop_T_2796, ram[0].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3805 = mux(_out_uop_T_2797, ram[1].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3806 = mux(_out_uop_T_2798, ram[2].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3807 = mux(_out_uop_T_2799, ram[3].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3808 = mux(_out_uop_T_2800, ram[4].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3809 = mux(_out_uop_T_2801, ram[5].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3810 = mux(_out_uop_T_2802, ram[6].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_3811 = or(_out_uop_T_3804, _out_uop_T_3805) node _out_uop_T_3812 = or(_out_uop_T_3811, _out_uop_T_3806) node _out_uop_T_3813 = or(_out_uop_T_3812, _out_uop_T_3807) node _out_uop_T_3814 = or(_out_uop_T_3813, _out_uop_T_3808) node _out_uop_T_3815 = or(_out_uop_T_3814, _out_uop_T_3809) node _out_uop_T_3816 = or(_out_uop_T_3815, _out_uop_T_3810) wire _out_uop_WIRE_318 : UInt<1> connect _out_uop_WIRE_318, _out_uop_T_3816 connect _out_uop_WIRE_314.fence, _out_uop_WIRE_318 node _out_uop_T_3817 = mux(_out_uop_T_2796, ram[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3818 = mux(_out_uop_T_2797, ram[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3819 = mux(_out_uop_T_2798, ram[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3820 = mux(_out_uop_T_2799, ram[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3821 = mux(_out_uop_T_2800, ram[4].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3822 = mux(_out_uop_T_2801, ram[5].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3823 = mux(_out_uop_T_2802, ram[6].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_3824 = or(_out_uop_T_3817, _out_uop_T_3818) node _out_uop_T_3825 = or(_out_uop_T_3824, _out_uop_T_3819) node _out_uop_T_3826 = or(_out_uop_T_3825, _out_uop_T_3820) node _out_uop_T_3827 = or(_out_uop_T_3826, _out_uop_T_3821) node _out_uop_T_3828 = or(_out_uop_T_3827, _out_uop_T_3822) node _out_uop_T_3829 = or(_out_uop_T_3828, _out_uop_T_3823) wire _out_uop_WIRE_319 : UInt<1> connect _out_uop_WIRE_319, _out_uop_T_3829 connect _out_uop_WIRE_314.fence_i, _out_uop_WIRE_319 node _out_uop_T_3830 = mux(_out_uop_T_2796, ram[0].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3831 = mux(_out_uop_T_2797, ram[1].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3832 = mux(_out_uop_T_2798, ram[2].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3833 = mux(_out_uop_T_2799, ram[3].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3834 = mux(_out_uop_T_2800, ram[4].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3835 = mux(_out_uop_T_2801, ram[5].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3836 = mux(_out_uop_T_2802, ram[6].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_3837 = or(_out_uop_T_3830, _out_uop_T_3831) node _out_uop_T_3838 = or(_out_uop_T_3837, _out_uop_T_3832) node _out_uop_T_3839 = or(_out_uop_T_3838, _out_uop_T_3833) node _out_uop_T_3840 = or(_out_uop_T_3839, _out_uop_T_3834) node _out_uop_T_3841 = or(_out_uop_T_3840, _out_uop_T_3835) node _out_uop_T_3842 = or(_out_uop_T_3841, _out_uop_T_3836) wire _out_uop_WIRE_320 : UInt<3> connect _out_uop_WIRE_320, _out_uop_T_3842 connect _out_uop_WIRE_314.csr, _out_uop_WIRE_320 node _out_uop_T_3843 = mux(_out_uop_T_2796, ram[0].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3844 = mux(_out_uop_T_2797, ram[1].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3845 = mux(_out_uop_T_2798, ram[2].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3846 = mux(_out_uop_T_2799, ram[3].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3847 = mux(_out_uop_T_2800, ram[4].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3848 = mux(_out_uop_T_2801, ram[5].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3849 = mux(_out_uop_T_2802, ram[6].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_3850 = or(_out_uop_T_3843, _out_uop_T_3844) node _out_uop_T_3851 = or(_out_uop_T_3850, _out_uop_T_3845) node _out_uop_T_3852 = or(_out_uop_T_3851, _out_uop_T_3846) node _out_uop_T_3853 = or(_out_uop_T_3852, _out_uop_T_3847) node _out_uop_T_3854 = or(_out_uop_T_3853, _out_uop_T_3848) node _out_uop_T_3855 = or(_out_uop_T_3854, _out_uop_T_3849) wire _out_uop_WIRE_321 : UInt<1> connect _out_uop_WIRE_321, _out_uop_T_3855 connect _out_uop_WIRE_314.wxd, _out_uop_WIRE_321 node _out_uop_T_3856 = mux(_out_uop_T_2796, ram[0].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3857 = mux(_out_uop_T_2797, ram[1].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3858 = mux(_out_uop_T_2798, ram[2].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3859 = mux(_out_uop_T_2799, ram[3].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3860 = mux(_out_uop_T_2800, ram[4].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3861 = mux(_out_uop_T_2801, ram[5].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3862 = mux(_out_uop_T_2802, ram[6].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_3863 = or(_out_uop_T_3856, _out_uop_T_3857) node _out_uop_T_3864 = or(_out_uop_T_3863, _out_uop_T_3858) node _out_uop_T_3865 = or(_out_uop_T_3864, _out_uop_T_3859) node _out_uop_T_3866 = or(_out_uop_T_3865, _out_uop_T_3860) node _out_uop_T_3867 = or(_out_uop_T_3866, _out_uop_T_3861) node _out_uop_T_3868 = or(_out_uop_T_3867, _out_uop_T_3862) wire _out_uop_WIRE_322 : UInt<1> connect _out_uop_WIRE_322, _out_uop_T_3868 connect _out_uop_WIRE_314.div, _out_uop_WIRE_322 node _out_uop_T_3869 = mux(_out_uop_T_2796, ram[0].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3870 = mux(_out_uop_T_2797, ram[1].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3871 = mux(_out_uop_T_2798, ram[2].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3872 = mux(_out_uop_T_2799, ram[3].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3873 = mux(_out_uop_T_2800, ram[4].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3874 = mux(_out_uop_T_2801, ram[5].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3875 = mux(_out_uop_T_2802, ram[6].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_3876 = or(_out_uop_T_3869, _out_uop_T_3870) node _out_uop_T_3877 = or(_out_uop_T_3876, _out_uop_T_3871) node _out_uop_T_3878 = or(_out_uop_T_3877, _out_uop_T_3872) node _out_uop_T_3879 = or(_out_uop_T_3878, _out_uop_T_3873) node _out_uop_T_3880 = or(_out_uop_T_3879, _out_uop_T_3874) node _out_uop_T_3881 = or(_out_uop_T_3880, _out_uop_T_3875) wire _out_uop_WIRE_323 : UInt<1> connect _out_uop_WIRE_323, _out_uop_T_3881 connect _out_uop_WIRE_314.mul, _out_uop_WIRE_323 node _out_uop_T_3882 = mux(_out_uop_T_2796, ram[0].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3883 = mux(_out_uop_T_2797, ram[1].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3884 = mux(_out_uop_T_2798, ram[2].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3885 = mux(_out_uop_T_2799, ram[3].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3886 = mux(_out_uop_T_2800, ram[4].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3887 = mux(_out_uop_T_2801, ram[5].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3888 = mux(_out_uop_T_2802, ram[6].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_3889 = or(_out_uop_T_3882, _out_uop_T_3883) node _out_uop_T_3890 = or(_out_uop_T_3889, _out_uop_T_3884) node _out_uop_T_3891 = or(_out_uop_T_3890, _out_uop_T_3885) node _out_uop_T_3892 = or(_out_uop_T_3891, _out_uop_T_3886) node _out_uop_T_3893 = or(_out_uop_T_3892, _out_uop_T_3887) node _out_uop_T_3894 = or(_out_uop_T_3893, _out_uop_T_3888) wire _out_uop_WIRE_324 : UInt<1> connect _out_uop_WIRE_324, _out_uop_T_3894 connect _out_uop_WIRE_314.wfd, _out_uop_WIRE_324 node _out_uop_T_3895 = mux(_out_uop_T_2796, ram[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3896 = mux(_out_uop_T_2797, ram[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3897 = mux(_out_uop_T_2798, ram[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3898 = mux(_out_uop_T_2799, ram[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3899 = mux(_out_uop_T_2800, ram[4].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3900 = mux(_out_uop_T_2801, ram[5].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3901 = mux(_out_uop_T_2802, ram[6].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_3902 = or(_out_uop_T_3895, _out_uop_T_3896) node _out_uop_T_3903 = or(_out_uop_T_3902, _out_uop_T_3897) node _out_uop_T_3904 = or(_out_uop_T_3903, _out_uop_T_3898) node _out_uop_T_3905 = or(_out_uop_T_3904, _out_uop_T_3899) node _out_uop_T_3906 = or(_out_uop_T_3905, _out_uop_T_3900) node _out_uop_T_3907 = or(_out_uop_T_3906, _out_uop_T_3901) wire _out_uop_WIRE_325 : UInt<1> connect _out_uop_WIRE_325, _out_uop_T_3907 connect _out_uop_WIRE_314.rfs3, _out_uop_WIRE_325 node _out_uop_T_3908 = mux(_out_uop_T_2796, ram[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3909 = mux(_out_uop_T_2797, ram[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3910 = mux(_out_uop_T_2798, ram[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3911 = mux(_out_uop_T_2799, ram[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3912 = mux(_out_uop_T_2800, ram[4].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3913 = mux(_out_uop_T_2801, ram[5].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3914 = mux(_out_uop_T_2802, ram[6].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_3915 = or(_out_uop_T_3908, _out_uop_T_3909) node _out_uop_T_3916 = or(_out_uop_T_3915, _out_uop_T_3910) node _out_uop_T_3917 = or(_out_uop_T_3916, _out_uop_T_3911) node _out_uop_T_3918 = or(_out_uop_T_3917, _out_uop_T_3912) node _out_uop_T_3919 = or(_out_uop_T_3918, _out_uop_T_3913) node _out_uop_T_3920 = or(_out_uop_T_3919, _out_uop_T_3914) wire _out_uop_WIRE_326 : UInt<1> connect _out_uop_WIRE_326, _out_uop_T_3920 connect _out_uop_WIRE_314.rfs2, _out_uop_WIRE_326 node _out_uop_T_3921 = mux(_out_uop_T_2796, ram[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3922 = mux(_out_uop_T_2797, ram[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3923 = mux(_out_uop_T_2798, ram[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3924 = mux(_out_uop_T_2799, ram[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3925 = mux(_out_uop_T_2800, ram[4].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3926 = mux(_out_uop_T_2801, ram[5].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3927 = mux(_out_uop_T_2802, ram[6].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_3928 = or(_out_uop_T_3921, _out_uop_T_3922) node _out_uop_T_3929 = or(_out_uop_T_3928, _out_uop_T_3923) node _out_uop_T_3930 = or(_out_uop_T_3929, _out_uop_T_3924) node _out_uop_T_3931 = or(_out_uop_T_3930, _out_uop_T_3925) node _out_uop_T_3932 = or(_out_uop_T_3931, _out_uop_T_3926) node _out_uop_T_3933 = or(_out_uop_T_3932, _out_uop_T_3927) wire _out_uop_WIRE_327 : UInt<1> connect _out_uop_WIRE_327, _out_uop_T_3933 connect _out_uop_WIRE_314.rfs1, _out_uop_WIRE_327 node _out_uop_T_3934 = mux(_out_uop_T_2796, ram[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3935 = mux(_out_uop_T_2797, ram[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3936 = mux(_out_uop_T_2798, ram[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3937 = mux(_out_uop_T_2799, ram[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3938 = mux(_out_uop_T_2800, ram[4].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3939 = mux(_out_uop_T_2801, ram[5].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3940 = mux(_out_uop_T_2802, ram[6].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_3941 = or(_out_uop_T_3934, _out_uop_T_3935) node _out_uop_T_3942 = or(_out_uop_T_3941, _out_uop_T_3936) node _out_uop_T_3943 = or(_out_uop_T_3942, _out_uop_T_3937) node _out_uop_T_3944 = or(_out_uop_T_3943, _out_uop_T_3938) node _out_uop_T_3945 = or(_out_uop_T_3944, _out_uop_T_3939) node _out_uop_T_3946 = or(_out_uop_T_3945, _out_uop_T_3940) wire _out_uop_WIRE_328 : UInt<5> connect _out_uop_WIRE_328, _out_uop_T_3946 connect _out_uop_WIRE_314.mem_cmd, _out_uop_WIRE_328 node _out_uop_T_3947 = mux(_out_uop_T_2796, ram[0].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3948 = mux(_out_uop_T_2797, ram[1].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3949 = mux(_out_uop_T_2798, ram[2].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3950 = mux(_out_uop_T_2799, ram[3].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3951 = mux(_out_uop_T_2800, ram[4].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3952 = mux(_out_uop_T_2801, ram[5].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3953 = mux(_out_uop_T_2802, ram[6].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_3954 = or(_out_uop_T_3947, _out_uop_T_3948) node _out_uop_T_3955 = or(_out_uop_T_3954, _out_uop_T_3949) node _out_uop_T_3956 = or(_out_uop_T_3955, _out_uop_T_3950) node _out_uop_T_3957 = or(_out_uop_T_3956, _out_uop_T_3951) node _out_uop_T_3958 = or(_out_uop_T_3957, _out_uop_T_3952) node _out_uop_T_3959 = or(_out_uop_T_3958, _out_uop_T_3953) wire _out_uop_WIRE_329 : UInt<1> connect _out_uop_WIRE_329, _out_uop_T_3959 connect _out_uop_WIRE_314.mem, _out_uop_WIRE_329 node _out_uop_T_3960 = mux(_out_uop_T_2796, ram[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3961 = mux(_out_uop_T_2797, ram[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3962 = mux(_out_uop_T_2798, ram[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3963 = mux(_out_uop_T_2799, ram[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3964 = mux(_out_uop_T_2800, ram[4].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3965 = mux(_out_uop_T_2801, ram[5].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3966 = mux(_out_uop_T_2802, ram[6].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_3967 = or(_out_uop_T_3960, _out_uop_T_3961) node _out_uop_T_3968 = or(_out_uop_T_3967, _out_uop_T_3962) node _out_uop_T_3969 = or(_out_uop_T_3968, _out_uop_T_3963) node _out_uop_T_3970 = or(_out_uop_T_3969, _out_uop_T_3964) node _out_uop_T_3971 = or(_out_uop_T_3970, _out_uop_T_3965) node _out_uop_T_3972 = or(_out_uop_T_3971, _out_uop_T_3966) wire _out_uop_WIRE_330 : UInt<5> connect _out_uop_WIRE_330, _out_uop_T_3972 connect _out_uop_WIRE_314.alu_fn, _out_uop_WIRE_330 node _out_uop_T_3973 = mux(_out_uop_T_2796, ram[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3974 = mux(_out_uop_T_2797, ram[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3975 = mux(_out_uop_T_2798, ram[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3976 = mux(_out_uop_T_2799, ram[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3977 = mux(_out_uop_T_2800, ram[4].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3978 = mux(_out_uop_T_2801, ram[5].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3979 = mux(_out_uop_T_2802, ram[6].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_3980 = or(_out_uop_T_3973, _out_uop_T_3974) node _out_uop_T_3981 = or(_out_uop_T_3980, _out_uop_T_3975) node _out_uop_T_3982 = or(_out_uop_T_3981, _out_uop_T_3976) node _out_uop_T_3983 = or(_out_uop_T_3982, _out_uop_T_3977) node _out_uop_T_3984 = or(_out_uop_T_3983, _out_uop_T_3978) node _out_uop_T_3985 = or(_out_uop_T_3984, _out_uop_T_3979) wire _out_uop_WIRE_331 : UInt<1> connect _out_uop_WIRE_331, _out_uop_T_3985 connect _out_uop_WIRE_314.alu_dw, _out_uop_WIRE_331 node _out_uop_T_3986 = mux(_out_uop_T_2796, ram[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3987 = mux(_out_uop_T_2797, ram[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3988 = mux(_out_uop_T_2798, ram[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3989 = mux(_out_uop_T_2799, ram[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3990 = mux(_out_uop_T_2800, ram[4].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3991 = mux(_out_uop_T_2801, ram[5].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3992 = mux(_out_uop_T_2802, ram[6].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_3993 = or(_out_uop_T_3986, _out_uop_T_3987) node _out_uop_T_3994 = or(_out_uop_T_3993, _out_uop_T_3988) node _out_uop_T_3995 = or(_out_uop_T_3994, _out_uop_T_3989) node _out_uop_T_3996 = or(_out_uop_T_3995, _out_uop_T_3990) node _out_uop_T_3997 = or(_out_uop_T_3996, _out_uop_T_3991) node _out_uop_T_3998 = or(_out_uop_T_3997, _out_uop_T_3992) wire _out_uop_WIRE_332 : UInt<3> connect _out_uop_WIRE_332, _out_uop_T_3998 connect _out_uop_WIRE_314.sel_imm, _out_uop_WIRE_332 node _out_uop_T_3999 = mux(_out_uop_T_2796, ram[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4000 = mux(_out_uop_T_2797, ram[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4001 = mux(_out_uop_T_2798, ram[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4002 = mux(_out_uop_T_2799, ram[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4003 = mux(_out_uop_T_2800, ram[4].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4004 = mux(_out_uop_T_2801, ram[5].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4005 = mux(_out_uop_T_2802, ram[6].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_4006 = or(_out_uop_T_3999, _out_uop_T_4000) node _out_uop_T_4007 = or(_out_uop_T_4006, _out_uop_T_4001) node _out_uop_T_4008 = or(_out_uop_T_4007, _out_uop_T_4002) node _out_uop_T_4009 = or(_out_uop_T_4008, _out_uop_T_4003) node _out_uop_T_4010 = or(_out_uop_T_4009, _out_uop_T_4004) node _out_uop_T_4011 = or(_out_uop_T_4010, _out_uop_T_4005) wire _out_uop_WIRE_333 : UInt<2> connect _out_uop_WIRE_333, _out_uop_T_4011 connect _out_uop_WIRE_314.sel_alu1, _out_uop_WIRE_333 node _out_uop_T_4012 = mux(_out_uop_T_2796, ram[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4013 = mux(_out_uop_T_2797, ram[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4014 = mux(_out_uop_T_2798, ram[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4015 = mux(_out_uop_T_2799, ram[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4016 = mux(_out_uop_T_2800, ram[4].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4017 = mux(_out_uop_T_2801, ram[5].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4018 = mux(_out_uop_T_2802, ram[6].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_4019 = or(_out_uop_T_4012, _out_uop_T_4013) node _out_uop_T_4020 = or(_out_uop_T_4019, _out_uop_T_4014) node _out_uop_T_4021 = or(_out_uop_T_4020, _out_uop_T_4015) node _out_uop_T_4022 = or(_out_uop_T_4021, _out_uop_T_4016) node _out_uop_T_4023 = or(_out_uop_T_4022, _out_uop_T_4017) node _out_uop_T_4024 = or(_out_uop_T_4023, _out_uop_T_4018) wire _out_uop_WIRE_334 : UInt<3> connect _out_uop_WIRE_334, _out_uop_T_4024 connect _out_uop_WIRE_314.sel_alu2, _out_uop_WIRE_334 node _out_uop_T_4025 = mux(_out_uop_T_2796, ram[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4026 = mux(_out_uop_T_2797, ram[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4027 = mux(_out_uop_T_2798, ram[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4028 = mux(_out_uop_T_2799, ram[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4029 = mux(_out_uop_T_2800, ram[4].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4030 = mux(_out_uop_T_2801, ram[5].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4031 = mux(_out_uop_T_2802, ram[6].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_4032 = or(_out_uop_T_4025, _out_uop_T_4026) node _out_uop_T_4033 = or(_out_uop_T_4032, _out_uop_T_4027) node _out_uop_T_4034 = or(_out_uop_T_4033, _out_uop_T_4028) node _out_uop_T_4035 = or(_out_uop_T_4034, _out_uop_T_4029) node _out_uop_T_4036 = or(_out_uop_T_4035, _out_uop_T_4030) node _out_uop_T_4037 = or(_out_uop_T_4036, _out_uop_T_4031) wire _out_uop_WIRE_335 : UInt<1> connect _out_uop_WIRE_335, _out_uop_T_4037 connect _out_uop_WIRE_314.rxs1, _out_uop_WIRE_335 node _out_uop_T_4038 = mux(_out_uop_T_2796, ram[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4039 = mux(_out_uop_T_2797, ram[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4040 = mux(_out_uop_T_2798, ram[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4041 = mux(_out_uop_T_2799, ram[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4042 = mux(_out_uop_T_2800, ram[4].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4043 = mux(_out_uop_T_2801, ram[5].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4044 = mux(_out_uop_T_2802, ram[6].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_4045 = or(_out_uop_T_4038, _out_uop_T_4039) node _out_uop_T_4046 = or(_out_uop_T_4045, _out_uop_T_4040) node _out_uop_T_4047 = or(_out_uop_T_4046, _out_uop_T_4041) node _out_uop_T_4048 = or(_out_uop_T_4047, _out_uop_T_4042) node _out_uop_T_4049 = or(_out_uop_T_4048, _out_uop_T_4043) node _out_uop_T_4050 = or(_out_uop_T_4049, _out_uop_T_4044) wire _out_uop_WIRE_336 : UInt<1> connect _out_uop_WIRE_336, _out_uop_T_4050 connect _out_uop_WIRE_314.rxs2, _out_uop_WIRE_336 node _out_uop_T_4051 = mux(_out_uop_T_2796, ram[0].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4052 = mux(_out_uop_T_2797, ram[1].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4053 = mux(_out_uop_T_2798, ram[2].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4054 = mux(_out_uop_T_2799, ram[3].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4055 = mux(_out_uop_T_2800, ram[4].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4056 = mux(_out_uop_T_2801, ram[5].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4057 = mux(_out_uop_T_2802, ram[6].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_4058 = or(_out_uop_T_4051, _out_uop_T_4052) node _out_uop_T_4059 = or(_out_uop_T_4058, _out_uop_T_4053) node _out_uop_T_4060 = or(_out_uop_T_4059, _out_uop_T_4054) node _out_uop_T_4061 = or(_out_uop_T_4060, _out_uop_T_4055) node _out_uop_T_4062 = or(_out_uop_T_4061, _out_uop_T_4056) node _out_uop_T_4063 = or(_out_uop_T_4062, _out_uop_T_4057) wire _out_uop_WIRE_337 : UInt<1> connect _out_uop_WIRE_337, _out_uop_T_4063 connect _out_uop_WIRE_314.jalr, _out_uop_WIRE_337 node _out_uop_T_4064 = mux(_out_uop_T_2796, ram[0].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4065 = mux(_out_uop_T_2797, ram[1].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4066 = mux(_out_uop_T_2798, ram[2].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4067 = mux(_out_uop_T_2799, ram[3].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4068 = mux(_out_uop_T_2800, ram[4].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4069 = mux(_out_uop_T_2801, ram[5].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4070 = mux(_out_uop_T_2802, ram[6].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_4071 = or(_out_uop_T_4064, _out_uop_T_4065) node _out_uop_T_4072 = or(_out_uop_T_4071, _out_uop_T_4066) node _out_uop_T_4073 = or(_out_uop_T_4072, _out_uop_T_4067) node _out_uop_T_4074 = or(_out_uop_T_4073, _out_uop_T_4068) node _out_uop_T_4075 = or(_out_uop_T_4074, _out_uop_T_4069) node _out_uop_T_4076 = or(_out_uop_T_4075, _out_uop_T_4070) wire _out_uop_WIRE_338 : UInt<1> connect _out_uop_WIRE_338, _out_uop_T_4076 connect _out_uop_WIRE_314.jal, _out_uop_WIRE_338 node _out_uop_T_4077 = mux(_out_uop_T_2796, ram[0].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4078 = mux(_out_uop_T_2797, ram[1].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4079 = mux(_out_uop_T_2798, ram[2].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4080 = mux(_out_uop_T_2799, ram[3].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4081 = mux(_out_uop_T_2800, ram[4].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4082 = mux(_out_uop_T_2801, ram[5].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4083 = mux(_out_uop_T_2802, ram[6].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_4084 = or(_out_uop_T_4077, _out_uop_T_4078) node _out_uop_T_4085 = or(_out_uop_T_4084, _out_uop_T_4079) node _out_uop_T_4086 = or(_out_uop_T_4085, _out_uop_T_4080) node _out_uop_T_4087 = or(_out_uop_T_4086, _out_uop_T_4081) node _out_uop_T_4088 = or(_out_uop_T_4087, _out_uop_T_4082) node _out_uop_T_4089 = or(_out_uop_T_4088, _out_uop_T_4083) wire _out_uop_WIRE_339 : UInt<1> connect _out_uop_WIRE_339, _out_uop_T_4089 connect _out_uop_WIRE_314.branch, _out_uop_WIRE_339 node _out_uop_T_4090 = mux(_out_uop_T_2796, ram[0].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4091 = mux(_out_uop_T_2797, ram[1].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4092 = mux(_out_uop_T_2798, ram[2].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4093 = mux(_out_uop_T_2799, ram[3].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4094 = mux(_out_uop_T_2800, ram[4].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4095 = mux(_out_uop_T_2801, ram[5].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4096 = mux(_out_uop_T_2802, ram[6].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_4097 = or(_out_uop_T_4090, _out_uop_T_4091) node _out_uop_T_4098 = or(_out_uop_T_4097, _out_uop_T_4092) node _out_uop_T_4099 = or(_out_uop_T_4098, _out_uop_T_4093) node _out_uop_T_4100 = or(_out_uop_T_4099, _out_uop_T_4094) node _out_uop_T_4101 = or(_out_uop_T_4100, _out_uop_T_4095) node _out_uop_T_4102 = or(_out_uop_T_4101, _out_uop_T_4096) wire _out_uop_WIRE_340 : UInt<1> connect _out_uop_WIRE_340, _out_uop_T_4102 connect _out_uop_WIRE_314.rocc, _out_uop_WIRE_340 node _out_uop_T_4103 = mux(_out_uop_T_2796, ram[0].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4104 = mux(_out_uop_T_2797, ram[1].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4105 = mux(_out_uop_T_2798, ram[2].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4106 = mux(_out_uop_T_2799, ram[3].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4107 = mux(_out_uop_T_2800, ram[4].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4108 = mux(_out_uop_T_2801, ram[5].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4109 = mux(_out_uop_T_2802, ram[6].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_4110 = or(_out_uop_T_4103, _out_uop_T_4104) node _out_uop_T_4111 = or(_out_uop_T_4110, _out_uop_T_4105) node _out_uop_T_4112 = or(_out_uop_T_4111, _out_uop_T_4106) node _out_uop_T_4113 = or(_out_uop_T_4112, _out_uop_T_4107) node _out_uop_T_4114 = or(_out_uop_T_4113, _out_uop_T_4108) node _out_uop_T_4115 = or(_out_uop_T_4114, _out_uop_T_4109) wire _out_uop_WIRE_341 : UInt<1> connect _out_uop_WIRE_341, _out_uop_T_4115 connect _out_uop_WIRE_314.fp, _out_uop_WIRE_341 node _out_uop_T_4116 = mux(_out_uop_T_2796, ram[0].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4117 = mux(_out_uop_T_2797, ram[1].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4118 = mux(_out_uop_T_2798, ram[2].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4119 = mux(_out_uop_T_2799, ram[3].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4120 = mux(_out_uop_T_2800, ram[4].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4121 = mux(_out_uop_T_2801, ram[5].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4122 = mux(_out_uop_T_2802, ram[6].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_4123 = or(_out_uop_T_4116, _out_uop_T_4117) node _out_uop_T_4124 = or(_out_uop_T_4123, _out_uop_T_4118) node _out_uop_T_4125 = or(_out_uop_T_4124, _out_uop_T_4119) node _out_uop_T_4126 = or(_out_uop_T_4125, _out_uop_T_4120) node _out_uop_T_4127 = or(_out_uop_T_4126, _out_uop_T_4121) node _out_uop_T_4128 = or(_out_uop_T_4127, _out_uop_T_4122) wire _out_uop_WIRE_342 : UInt<1> connect _out_uop_WIRE_342, _out_uop_T_4128 connect _out_uop_WIRE_314.legal, _out_uop_WIRE_342 connect _out_uop_WIRE_232.ctrl, _out_uop_WIRE_314 node _out_uop_T_4129 = mux(_out_uop_T_2796, ram[0].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4130 = mux(_out_uop_T_2797, ram[1].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4131 = mux(_out_uop_T_2798, ram[2].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4132 = mux(_out_uop_T_2799, ram[3].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4133 = mux(_out_uop_T_2800, ram[4].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4134 = mux(_out_uop_T_2801, ram[5].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4135 = mux(_out_uop_T_2802, ram[6].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_4136 = or(_out_uop_T_4129, _out_uop_T_4130) node _out_uop_T_4137 = or(_out_uop_T_4136, _out_uop_T_4131) node _out_uop_T_4138 = or(_out_uop_T_4137, _out_uop_T_4132) node _out_uop_T_4139 = or(_out_uop_T_4138, _out_uop_T_4133) node _out_uop_T_4140 = or(_out_uop_T_4139, _out_uop_T_4134) node _out_uop_T_4141 = or(_out_uop_T_4140, _out_uop_T_4135) wire _out_uop_WIRE_343 : UInt<1> connect _out_uop_WIRE_343, _out_uop_T_4141 connect _out_uop_WIRE_232.edge_inst, _out_uop_WIRE_343 node _out_uop_T_4142 = mux(_out_uop_T_2796, ram[0].bits.pc, UInt<1>(0h0)) node _out_uop_T_4143 = mux(_out_uop_T_2797, ram[1].bits.pc, UInt<1>(0h0)) node _out_uop_T_4144 = mux(_out_uop_T_2798, ram[2].bits.pc, UInt<1>(0h0)) node _out_uop_T_4145 = mux(_out_uop_T_2799, ram[3].bits.pc, UInt<1>(0h0)) node _out_uop_T_4146 = mux(_out_uop_T_2800, ram[4].bits.pc, UInt<1>(0h0)) node _out_uop_T_4147 = mux(_out_uop_T_2801, ram[5].bits.pc, UInt<1>(0h0)) node _out_uop_T_4148 = mux(_out_uop_T_2802, ram[6].bits.pc, UInt<1>(0h0)) node _out_uop_T_4149 = or(_out_uop_T_4142, _out_uop_T_4143) node _out_uop_T_4150 = or(_out_uop_T_4149, _out_uop_T_4144) node _out_uop_T_4151 = or(_out_uop_T_4150, _out_uop_T_4145) node _out_uop_T_4152 = or(_out_uop_T_4151, _out_uop_T_4146) node _out_uop_T_4153 = or(_out_uop_T_4152, _out_uop_T_4147) node _out_uop_T_4154 = or(_out_uop_T_4153, _out_uop_T_4148) wire _out_uop_WIRE_344 : UInt<40> connect _out_uop_WIRE_344, _out_uop_T_4154 connect _out_uop_WIRE_232.pc, _out_uop_WIRE_344 node _out_uop_T_4155 = mux(_out_uop_T_2796, ram[0].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4156 = mux(_out_uop_T_2797, ram[1].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4157 = mux(_out_uop_T_2798, ram[2].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4158 = mux(_out_uop_T_2799, ram[3].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4159 = mux(_out_uop_T_2800, ram[4].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4160 = mux(_out_uop_T_2801, ram[5].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4161 = mux(_out_uop_T_2802, ram[6].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_4162 = or(_out_uop_T_4155, _out_uop_T_4156) node _out_uop_T_4163 = or(_out_uop_T_4162, _out_uop_T_4157) node _out_uop_T_4164 = or(_out_uop_T_4163, _out_uop_T_4158) node _out_uop_T_4165 = or(_out_uop_T_4164, _out_uop_T_4159) node _out_uop_T_4166 = or(_out_uop_T_4165, _out_uop_T_4160) node _out_uop_T_4167 = or(_out_uop_T_4166, _out_uop_T_4161) wire _out_uop_WIRE_345 : UInt<32> connect _out_uop_WIRE_345, _out_uop_T_4167 connect _out_uop_WIRE_232.raw_inst, _out_uop_WIRE_345 node _out_uop_T_4168 = mux(_out_uop_T_2796, ram[0].bits.inst, UInt<1>(0h0)) node _out_uop_T_4169 = mux(_out_uop_T_2797, ram[1].bits.inst, UInt<1>(0h0)) node _out_uop_T_4170 = mux(_out_uop_T_2798, ram[2].bits.inst, UInt<1>(0h0)) node _out_uop_T_4171 = mux(_out_uop_T_2799, ram[3].bits.inst, UInt<1>(0h0)) node _out_uop_T_4172 = mux(_out_uop_T_2800, ram[4].bits.inst, UInt<1>(0h0)) node _out_uop_T_4173 = mux(_out_uop_T_2801, ram[5].bits.inst, UInt<1>(0h0)) node _out_uop_T_4174 = mux(_out_uop_T_2802, ram[6].bits.inst, UInt<1>(0h0)) node _out_uop_T_4175 = or(_out_uop_T_4168, _out_uop_T_4169) node _out_uop_T_4176 = or(_out_uop_T_4175, _out_uop_T_4170) node _out_uop_T_4177 = or(_out_uop_T_4176, _out_uop_T_4171) node _out_uop_T_4178 = or(_out_uop_T_4177, _out_uop_T_4172) node _out_uop_T_4179 = or(_out_uop_T_4178, _out_uop_T_4173) node _out_uop_T_4180 = or(_out_uop_T_4179, _out_uop_T_4174) wire _out_uop_WIRE_346 : UInt<32> connect _out_uop_WIRE_346, _out_uop_T_4180 connect _out_uop_WIRE_232.inst, _out_uop_WIRE_346 connect out_uop_2.bits, _out_uop_WIRE_232 node _out_uop_T_4181 = mux(_out_uop_T_2796, ram[0].valid, UInt<1>(0h0)) node _out_uop_T_4182 = mux(_out_uop_T_2797, ram[1].valid, UInt<1>(0h0)) node _out_uop_T_4183 = mux(_out_uop_T_2798, ram[2].valid, UInt<1>(0h0)) node _out_uop_T_4184 = mux(_out_uop_T_2799, ram[3].valid, UInt<1>(0h0)) node _out_uop_T_4185 = mux(_out_uop_T_2800, ram[4].valid, UInt<1>(0h0)) node _out_uop_T_4186 = mux(_out_uop_T_2801, ram[5].valid, UInt<1>(0h0)) node _out_uop_T_4187 = mux(_out_uop_T_2802, ram[6].valid, UInt<1>(0h0)) node _out_uop_T_4188 = or(_out_uop_T_4181, _out_uop_T_4182) node _out_uop_T_4189 = or(_out_uop_T_4188, _out_uop_T_4183) node _out_uop_T_4190 = or(_out_uop_T_4189, _out_uop_T_4184) node _out_uop_T_4191 = or(_out_uop_T_4190, _out_uop_T_4185) node _out_uop_T_4192 = or(_out_uop_T_4191, _out_uop_T_4186) node _out_uop_T_4193 = or(_out_uop_T_4192, _out_uop_T_4187) wire _out_uop_WIRE_347 : UInt<1> connect _out_uop_WIRE_347, _out_uop_T_4193 connect out_uop_2.valid, _out_uop_WIRE_347 connect io.peek[0].valid, out_uop_2.valid connect io.peek[0].bits, out_uop_2.bits node _T_42 = shl(_T_41, 1) node _T_43 = bits(_T_41, 6, 6) node _T_44 = or(_T_42, _T_43) node _T_45 = bits(_T_44, 6, 0) node _out_uop_T_4194 = bits(_T_45, 0, 0) node _out_uop_T_4195 = bits(_T_45, 1, 1) node _out_uop_T_4196 = bits(_T_45, 2, 2) node _out_uop_T_4197 = bits(_T_45, 3, 3) node _out_uop_T_4198 = bits(_T_45, 4, 4) node _out_uop_T_4199 = bits(_T_45, 5, 5) node _out_uop_T_4200 = bits(_T_45, 6, 6) wire out_uop_3 : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _out_uop_WIRE_348 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _out_uop_T_4201 = mux(_out_uop_T_4194, ram[0].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4202 = mux(_out_uop_T_4195, ram[1].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4203 = mux(_out_uop_T_4196, ram[2].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4204 = mux(_out_uop_T_4197, ram[3].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4205 = mux(_out_uop_T_4198, ram[4].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4206 = mux(_out_uop_T_4199, ram[5].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4207 = mux(_out_uop_T_4200, ram[6].bits.flush_pipe, UInt<1>(0h0)) node _out_uop_T_4208 = or(_out_uop_T_4201, _out_uop_T_4202) node _out_uop_T_4209 = or(_out_uop_T_4208, _out_uop_T_4203) node _out_uop_T_4210 = or(_out_uop_T_4209, _out_uop_T_4204) node _out_uop_T_4211 = or(_out_uop_T_4210, _out_uop_T_4205) node _out_uop_T_4212 = or(_out_uop_T_4211, _out_uop_T_4206) node _out_uop_T_4213 = or(_out_uop_T_4212, _out_uop_T_4207) wire _out_uop_WIRE_349 : UInt<1> connect _out_uop_WIRE_349, _out_uop_T_4213 connect _out_uop_WIRE_348.flush_pipe, _out_uop_WIRE_349 node _out_uop_T_4214 = mux(_out_uop_T_4194, ram[0].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4215 = mux(_out_uop_T_4195, ram[1].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4216 = mux(_out_uop_T_4196, ram[2].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4217 = mux(_out_uop_T_4197, ram[3].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4218 = mux(_out_uop_T_4198, ram[4].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4219 = mux(_out_uop_T_4199, ram[5].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4220 = mux(_out_uop_T_4200, ram[6].bits.mem_size, UInt<1>(0h0)) node _out_uop_T_4221 = or(_out_uop_T_4214, _out_uop_T_4215) node _out_uop_T_4222 = or(_out_uop_T_4221, _out_uop_T_4216) node _out_uop_T_4223 = or(_out_uop_T_4222, _out_uop_T_4217) node _out_uop_T_4224 = or(_out_uop_T_4223, _out_uop_T_4218) node _out_uop_T_4225 = or(_out_uop_T_4224, _out_uop_T_4219) node _out_uop_T_4226 = or(_out_uop_T_4225, _out_uop_T_4220) wire _out_uop_WIRE_350 : UInt<2> connect _out_uop_WIRE_350, _out_uop_T_4226 connect _out_uop_WIRE_348.mem_size, _out_uop_WIRE_350 wire _out_uop_WIRE_351 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _out_uop_T_4227 = mux(_out_uop_T_4194, ram[0].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4228 = mux(_out_uop_T_4195, ram[1].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4229 = mux(_out_uop_T_4196, ram[2].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4230 = mux(_out_uop_T_4197, ram[3].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4231 = mux(_out_uop_T_4198, ram[4].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4232 = mux(_out_uop_T_4199, ram[5].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4233 = mux(_out_uop_T_4200, ram[6].bits.fdivin.in3, UInt<1>(0h0)) node _out_uop_T_4234 = or(_out_uop_T_4227, _out_uop_T_4228) node _out_uop_T_4235 = or(_out_uop_T_4234, _out_uop_T_4229) node _out_uop_T_4236 = or(_out_uop_T_4235, _out_uop_T_4230) node _out_uop_T_4237 = or(_out_uop_T_4236, _out_uop_T_4231) node _out_uop_T_4238 = or(_out_uop_T_4237, _out_uop_T_4232) node _out_uop_T_4239 = or(_out_uop_T_4238, _out_uop_T_4233) wire _out_uop_WIRE_352 : UInt<65> connect _out_uop_WIRE_352, _out_uop_T_4239 connect _out_uop_WIRE_351.in3, _out_uop_WIRE_352 node _out_uop_T_4240 = mux(_out_uop_T_4194, ram[0].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4241 = mux(_out_uop_T_4195, ram[1].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4242 = mux(_out_uop_T_4196, ram[2].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4243 = mux(_out_uop_T_4197, ram[3].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4244 = mux(_out_uop_T_4198, ram[4].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4245 = mux(_out_uop_T_4199, ram[5].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4246 = mux(_out_uop_T_4200, ram[6].bits.fdivin.in2, UInt<1>(0h0)) node _out_uop_T_4247 = or(_out_uop_T_4240, _out_uop_T_4241) node _out_uop_T_4248 = or(_out_uop_T_4247, _out_uop_T_4242) node _out_uop_T_4249 = or(_out_uop_T_4248, _out_uop_T_4243) node _out_uop_T_4250 = or(_out_uop_T_4249, _out_uop_T_4244) node _out_uop_T_4251 = or(_out_uop_T_4250, _out_uop_T_4245) node _out_uop_T_4252 = or(_out_uop_T_4251, _out_uop_T_4246) wire _out_uop_WIRE_353 : UInt<65> connect _out_uop_WIRE_353, _out_uop_T_4252 connect _out_uop_WIRE_351.in2, _out_uop_WIRE_353 node _out_uop_T_4253 = mux(_out_uop_T_4194, ram[0].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4254 = mux(_out_uop_T_4195, ram[1].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4255 = mux(_out_uop_T_4196, ram[2].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4256 = mux(_out_uop_T_4197, ram[3].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4257 = mux(_out_uop_T_4198, ram[4].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4258 = mux(_out_uop_T_4199, ram[5].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4259 = mux(_out_uop_T_4200, ram[6].bits.fdivin.in1, UInt<1>(0h0)) node _out_uop_T_4260 = or(_out_uop_T_4253, _out_uop_T_4254) node _out_uop_T_4261 = or(_out_uop_T_4260, _out_uop_T_4255) node _out_uop_T_4262 = or(_out_uop_T_4261, _out_uop_T_4256) node _out_uop_T_4263 = or(_out_uop_T_4262, _out_uop_T_4257) node _out_uop_T_4264 = or(_out_uop_T_4263, _out_uop_T_4258) node _out_uop_T_4265 = or(_out_uop_T_4264, _out_uop_T_4259) wire _out_uop_WIRE_354 : UInt<65> connect _out_uop_WIRE_354, _out_uop_T_4265 connect _out_uop_WIRE_351.in1, _out_uop_WIRE_354 node _out_uop_T_4266 = mux(_out_uop_T_4194, ram[0].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4267 = mux(_out_uop_T_4195, ram[1].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4268 = mux(_out_uop_T_4196, ram[2].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4269 = mux(_out_uop_T_4197, ram[3].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4270 = mux(_out_uop_T_4198, ram[4].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4271 = mux(_out_uop_T_4199, ram[5].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4272 = mux(_out_uop_T_4200, ram[6].bits.fdivin.fmt, UInt<1>(0h0)) node _out_uop_T_4273 = or(_out_uop_T_4266, _out_uop_T_4267) node _out_uop_T_4274 = or(_out_uop_T_4273, _out_uop_T_4268) node _out_uop_T_4275 = or(_out_uop_T_4274, _out_uop_T_4269) node _out_uop_T_4276 = or(_out_uop_T_4275, _out_uop_T_4270) node _out_uop_T_4277 = or(_out_uop_T_4276, _out_uop_T_4271) node _out_uop_T_4278 = or(_out_uop_T_4277, _out_uop_T_4272) wire _out_uop_WIRE_355 : UInt<2> connect _out_uop_WIRE_355, _out_uop_T_4278 connect _out_uop_WIRE_351.fmt, _out_uop_WIRE_355 node _out_uop_T_4279 = mux(_out_uop_T_4194, ram[0].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4280 = mux(_out_uop_T_4195, ram[1].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4281 = mux(_out_uop_T_4196, ram[2].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4282 = mux(_out_uop_T_4197, ram[3].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4283 = mux(_out_uop_T_4198, ram[4].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4284 = mux(_out_uop_T_4199, ram[5].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4285 = mux(_out_uop_T_4200, ram[6].bits.fdivin.typ, UInt<1>(0h0)) node _out_uop_T_4286 = or(_out_uop_T_4279, _out_uop_T_4280) node _out_uop_T_4287 = or(_out_uop_T_4286, _out_uop_T_4281) node _out_uop_T_4288 = or(_out_uop_T_4287, _out_uop_T_4282) node _out_uop_T_4289 = or(_out_uop_T_4288, _out_uop_T_4283) node _out_uop_T_4290 = or(_out_uop_T_4289, _out_uop_T_4284) node _out_uop_T_4291 = or(_out_uop_T_4290, _out_uop_T_4285) wire _out_uop_WIRE_356 : UInt<2> connect _out_uop_WIRE_356, _out_uop_T_4291 connect _out_uop_WIRE_351.typ, _out_uop_WIRE_356 node _out_uop_T_4292 = mux(_out_uop_T_4194, ram[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4293 = mux(_out_uop_T_4195, ram[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4294 = mux(_out_uop_T_4196, ram[2].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4295 = mux(_out_uop_T_4197, ram[3].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4296 = mux(_out_uop_T_4198, ram[4].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4297 = mux(_out_uop_T_4199, ram[5].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4298 = mux(_out_uop_T_4200, ram[6].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _out_uop_T_4299 = or(_out_uop_T_4292, _out_uop_T_4293) node _out_uop_T_4300 = or(_out_uop_T_4299, _out_uop_T_4294) node _out_uop_T_4301 = or(_out_uop_T_4300, _out_uop_T_4295) node _out_uop_T_4302 = or(_out_uop_T_4301, _out_uop_T_4296) node _out_uop_T_4303 = or(_out_uop_T_4302, _out_uop_T_4297) node _out_uop_T_4304 = or(_out_uop_T_4303, _out_uop_T_4298) wire _out_uop_WIRE_357 : UInt<2> connect _out_uop_WIRE_357, _out_uop_T_4304 connect _out_uop_WIRE_351.fmaCmd, _out_uop_WIRE_357 node _out_uop_T_4305 = mux(_out_uop_T_4194, ram[0].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4306 = mux(_out_uop_T_4195, ram[1].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4307 = mux(_out_uop_T_4196, ram[2].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4308 = mux(_out_uop_T_4197, ram[3].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4309 = mux(_out_uop_T_4198, ram[4].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4310 = mux(_out_uop_T_4199, ram[5].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4311 = mux(_out_uop_T_4200, ram[6].bits.fdivin.rm, UInt<1>(0h0)) node _out_uop_T_4312 = or(_out_uop_T_4305, _out_uop_T_4306) node _out_uop_T_4313 = or(_out_uop_T_4312, _out_uop_T_4307) node _out_uop_T_4314 = or(_out_uop_T_4313, _out_uop_T_4308) node _out_uop_T_4315 = or(_out_uop_T_4314, _out_uop_T_4309) node _out_uop_T_4316 = or(_out_uop_T_4315, _out_uop_T_4310) node _out_uop_T_4317 = or(_out_uop_T_4316, _out_uop_T_4311) wire _out_uop_WIRE_358 : UInt<3> connect _out_uop_WIRE_358, _out_uop_T_4317 connect _out_uop_WIRE_351.rm, _out_uop_WIRE_358 node _out_uop_T_4318 = mux(_out_uop_T_4194, ram[0].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4319 = mux(_out_uop_T_4195, ram[1].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4320 = mux(_out_uop_T_4196, ram[2].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4321 = mux(_out_uop_T_4197, ram[3].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4322 = mux(_out_uop_T_4198, ram[4].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4323 = mux(_out_uop_T_4199, ram[5].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4324 = mux(_out_uop_T_4200, ram[6].bits.fdivin.vec, UInt<1>(0h0)) node _out_uop_T_4325 = or(_out_uop_T_4318, _out_uop_T_4319) node _out_uop_T_4326 = or(_out_uop_T_4325, _out_uop_T_4320) node _out_uop_T_4327 = or(_out_uop_T_4326, _out_uop_T_4321) node _out_uop_T_4328 = or(_out_uop_T_4327, _out_uop_T_4322) node _out_uop_T_4329 = or(_out_uop_T_4328, _out_uop_T_4323) node _out_uop_T_4330 = or(_out_uop_T_4329, _out_uop_T_4324) wire _out_uop_WIRE_359 : UInt<1> connect _out_uop_WIRE_359, _out_uop_T_4330 connect _out_uop_WIRE_351.vec, _out_uop_WIRE_359 node _out_uop_T_4331 = mux(_out_uop_T_4194, ram[0].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4332 = mux(_out_uop_T_4195, ram[1].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4333 = mux(_out_uop_T_4196, ram[2].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4334 = mux(_out_uop_T_4197, ram[3].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4335 = mux(_out_uop_T_4198, ram[4].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4336 = mux(_out_uop_T_4199, ram[5].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4337 = mux(_out_uop_T_4200, ram[6].bits.fdivin.wflags, UInt<1>(0h0)) node _out_uop_T_4338 = or(_out_uop_T_4331, _out_uop_T_4332) node _out_uop_T_4339 = or(_out_uop_T_4338, _out_uop_T_4333) node _out_uop_T_4340 = or(_out_uop_T_4339, _out_uop_T_4334) node _out_uop_T_4341 = or(_out_uop_T_4340, _out_uop_T_4335) node _out_uop_T_4342 = or(_out_uop_T_4341, _out_uop_T_4336) node _out_uop_T_4343 = or(_out_uop_T_4342, _out_uop_T_4337) wire _out_uop_WIRE_360 : UInt<1> connect _out_uop_WIRE_360, _out_uop_T_4343 connect _out_uop_WIRE_351.wflags, _out_uop_WIRE_360 node _out_uop_T_4344 = mux(_out_uop_T_4194, ram[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4345 = mux(_out_uop_T_4195, ram[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4346 = mux(_out_uop_T_4196, ram[2].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4347 = mux(_out_uop_T_4197, ram[3].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4348 = mux(_out_uop_T_4198, ram[4].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4349 = mux(_out_uop_T_4199, ram[5].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4350 = mux(_out_uop_T_4200, ram[6].bits.fdivin.sqrt, UInt<1>(0h0)) node _out_uop_T_4351 = or(_out_uop_T_4344, _out_uop_T_4345) node _out_uop_T_4352 = or(_out_uop_T_4351, _out_uop_T_4346) node _out_uop_T_4353 = or(_out_uop_T_4352, _out_uop_T_4347) node _out_uop_T_4354 = or(_out_uop_T_4353, _out_uop_T_4348) node _out_uop_T_4355 = or(_out_uop_T_4354, _out_uop_T_4349) node _out_uop_T_4356 = or(_out_uop_T_4355, _out_uop_T_4350) wire _out_uop_WIRE_361 : UInt<1> connect _out_uop_WIRE_361, _out_uop_T_4356 connect _out_uop_WIRE_351.sqrt, _out_uop_WIRE_361 node _out_uop_T_4357 = mux(_out_uop_T_4194, ram[0].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4358 = mux(_out_uop_T_4195, ram[1].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4359 = mux(_out_uop_T_4196, ram[2].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4360 = mux(_out_uop_T_4197, ram[3].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4361 = mux(_out_uop_T_4198, ram[4].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4362 = mux(_out_uop_T_4199, ram[5].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4363 = mux(_out_uop_T_4200, ram[6].bits.fdivin.div, UInt<1>(0h0)) node _out_uop_T_4364 = or(_out_uop_T_4357, _out_uop_T_4358) node _out_uop_T_4365 = or(_out_uop_T_4364, _out_uop_T_4359) node _out_uop_T_4366 = or(_out_uop_T_4365, _out_uop_T_4360) node _out_uop_T_4367 = or(_out_uop_T_4366, _out_uop_T_4361) node _out_uop_T_4368 = or(_out_uop_T_4367, _out_uop_T_4362) node _out_uop_T_4369 = or(_out_uop_T_4368, _out_uop_T_4363) wire _out_uop_WIRE_362 : UInt<1> connect _out_uop_WIRE_362, _out_uop_T_4369 connect _out_uop_WIRE_351.div, _out_uop_WIRE_362 node _out_uop_T_4370 = mux(_out_uop_T_4194, ram[0].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4371 = mux(_out_uop_T_4195, ram[1].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4372 = mux(_out_uop_T_4196, ram[2].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4373 = mux(_out_uop_T_4197, ram[3].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4374 = mux(_out_uop_T_4198, ram[4].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4375 = mux(_out_uop_T_4199, ram[5].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4376 = mux(_out_uop_T_4200, ram[6].bits.fdivin.fma, UInt<1>(0h0)) node _out_uop_T_4377 = or(_out_uop_T_4370, _out_uop_T_4371) node _out_uop_T_4378 = or(_out_uop_T_4377, _out_uop_T_4372) node _out_uop_T_4379 = or(_out_uop_T_4378, _out_uop_T_4373) node _out_uop_T_4380 = or(_out_uop_T_4379, _out_uop_T_4374) node _out_uop_T_4381 = or(_out_uop_T_4380, _out_uop_T_4375) node _out_uop_T_4382 = or(_out_uop_T_4381, _out_uop_T_4376) wire _out_uop_WIRE_363 : UInt<1> connect _out_uop_WIRE_363, _out_uop_T_4382 connect _out_uop_WIRE_351.fma, _out_uop_WIRE_363 node _out_uop_T_4383 = mux(_out_uop_T_4194, ram[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4384 = mux(_out_uop_T_4195, ram[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4385 = mux(_out_uop_T_4196, ram[2].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4386 = mux(_out_uop_T_4197, ram[3].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4387 = mux(_out_uop_T_4198, ram[4].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4388 = mux(_out_uop_T_4199, ram[5].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4389 = mux(_out_uop_T_4200, ram[6].bits.fdivin.fastpipe, UInt<1>(0h0)) node _out_uop_T_4390 = or(_out_uop_T_4383, _out_uop_T_4384) node _out_uop_T_4391 = or(_out_uop_T_4390, _out_uop_T_4385) node _out_uop_T_4392 = or(_out_uop_T_4391, _out_uop_T_4386) node _out_uop_T_4393 = or(_out_uop_T_4392, _out_uop_T_4387) node _out_uop_T_4394 = or(_out_uop_T_4393, _out_uop_T_4388) node _out_uop_T_4395 = or(_out_uop_T_4394, _out_uop_T_4389) wire _out_uop_WIRE_364 : UInt<1> connect _out_uop_WIRE_364, _out_uop_T_4395 connect _out_uop_WIRE_351.fastpipe, _out_uop_WIRE_364 node _out_uop_T_4396 = mux(_out_uop_T_4194, ram[0].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4397 = mux(_out_uop_T_4195, ram[1].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4398 = mux(_out_uop_T_4196, ram[2].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4399 = mux(_out_uop_T_4197, ram[3].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4400 = mux(_out_uop_T_4198, ram[4].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4401 = mux(_out_uop_T_4199, ram[5].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4402 = mux(_out_uop_T_4200, ram[6].bits.fdivin.toint, UInt<1>(0h0)) node _out_uop_T_4403 = or(_out_uop_T_4396, _out_uop_T_4397) node _out_uop_T_4404 = or(_out_uop_T_4403, _out_uop_T_4398) node _out_uop_T_4405 = or(_out_uop_T_4404, _out_uop_T_4399) node _out_uop_T_4406 = or(_out_uop_T_4405, _out_uop_T_4400) node _out_uop_T_4407 = or(_out_uop_T_4406, _out_uop_T_4401) node _out_uop_T_4408 = or(_out_uop_T_4407, _out_uop_T_4402) wire _out_uop_WIRE_365 : UInt<1> connect _out_uop_WIRE_365, _out_uop_T_4408 connect _out_uop_WIRE_351.toint, _out_uop_WIRE_365 node _out_uop_T_4409 = mux(_out_uop_T_4194, ram[0].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4410 = mux(_out_uop_T_4195, ram[1].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4411 = mux(_out_uop_T_4196, ram[2].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4412 = mux(_out_uop_T_4197, ram[3].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4413 = mux(_out_uop_T_4198, ram[4].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4414 = mux(_out_uop_T_4199, ram[5].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4415 = mux(_out_uop_T_4200, ram[6].bits.fdivin.fromint, UInt<1>(0h0)) node _out_uop_T_4416 = or(_out_uop_T_4409, _out_uop_T_4410) node _out_uop_T_4417 = or(_out_uop_T_4416, _out_uop_T_4411) node _out_uop_T_4418 = or(_out_uop_T_4417, _out_uop_T_4412) node _out_uop_T_4419 = or(_out_uop_T_4418, _out_uop_T_4413) node _out_uop_T_4420 = or(_out_uop_T_4419, _out_uop_T_4414) node _out_uop_T_4421 = or(_out_uop_T_4420, _out_uop_T_4415) wire _out_uop_WIRE_366 : UInt<1> connect _out_uop_WIRE_366, _out_uop_T_4421 connect _out_uop_WIRE_351.fromint, _out_uop_WIRE_366 node _out_uop_T_4422 = mux(_out_uop_T_4194, ram[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4423 = mux(_out_uop_T_4195, ram[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4424 = mux(_out_uop_T_4196, ram[2].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4425 = mux(_out_uop_T_4197, ram[3].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4426 = mux(_out_uop_T_4198, ram[4].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4427 = mux(_out_uop_T_4199, ram[5].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4428 = mux(_out_uop_T_4200, ram[6].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _out_uop_T_4429 = or(_out_uop_T_4422, _out_uop_T_4423) node _out_uop_T_4430 = or(_out_uop_T_4429, _out_uop_T_4424) node _out_uop_T_4431 = or(_out_uop_T_4430, _out_uop_T_4425) node _out_uop_T_4432 = or(_out_uop_T_4431, _out_uop_T_4426) node _out_uop_T_4433 = or(_out_uop_T_4432, _out_uop_T_4427) node _out_uop_T_4434 = or(_out_uop_T_4433, _out_uop_T_4428) wire _out_uop_WIRE_367 : UInt<2> connect _out_uop_WIRE_367, _out_uop_T_4434 connect _out_uop_WIRE_351.typeTagOut, _out_uop_WIRE_367 node _out_uop_T_4435 = mux(_out_uop_T_4194, ram[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4436 = mux(_out_uop_T_4195, ram[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4437 = mux(_out_uop_T_4196, ram[2].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4438 = mux(_out_uop_T_4197, ram[3].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4439 = mux(_out_uop_T_4198, ram[4].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4440 = mux(_out_uop_T_4199, ram[5].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4441 = mux(_out_uop_T_4200, ram[6].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _out_uop_T_4442 = or(_out_uop_T_4435, _out_uop_T_4436) node _out_uop_T_4443 = or(_out_uop_T_4442, _out_uop_T_4437) node _out_uop_T_4444 = or(_out_uop_T_4443, _out_uop_T_4438) node _out_uop_T_4445 = or(_out_uop_T_4444, _out_uop_T_4439) node _out_uop_T_4446 = or(_out_uop_T_4445, _out_uop_T_4440) node _out_uop_T_4447 = or(_out_uop_T_4446, _out_uop_T_4441) wire _out_uop_WIRE_368 : UInt<2> connect _out_uop_WIRE_368, _out_uop_T_4447 connect _out_uop_WIRE_351.typeTagIn, _out_uop_WIRE_368 node _out_uop_T_4448 = mux(_out_uop_T_4194, ram[0].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4449 = mux(_out_uop_T_4195, ram[1].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4450 = mux(_out_uop_T_4196, ram[2].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4451 = mux(_out_uop_T_4197, ram[3].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4452 = mux(_out_uop_T_4198, ram[4].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4453 = mux(_out_uop_T_4199, ram[5].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4454 = mux(_out_uop_T_4200, ram[6].bits.fdivin.swap23, UInt<1>(0h0)) node _out_uop_T_4455 = or(_out_uop_T_4448, _out_uop_T_4449) node _out_uop_T_4456 = or(_out_uop_T_4455, _out_uop_T_4450) node _out_uop_T_4457 = or(_out_uop_T_4456, _out_uop_T_4451) node _out_uop_T_4458 = or(_out_uop_T_4457, _out_uop_T_4452) node _out_uop_T_4459 = or(_out_uop_T_4458, _out_uop_T_4453) node _out_uop_T_4460 = or(_out_uop_T_4459, _out_uop_T_4454) wire _out_uop_WIRE_369 : UInt<1> connect _out_uop_WIRE_369, _out_uop_T_4460 connect _out_uop_WIRE_351.swap23, _out_uop_WIRE_369 node _out_uop_T_4461 = mux(_out_uop_T_4194, ram[0].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4462 = mux(_out_uop_T_4195, ram[1].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4463 = mux(_out_uop_T_4196, ram[2].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4464 = mux(_out_uop_T_4197, ram[3].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4465 = mux(_out_uop_T_4198, ram[4].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4466 = mux(_out_uop_T_4199, ram[5].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4467 = mux(_out_uop_T_4200, ram[6].bits.fdivin.swap12, UInt<1>(0h0)) node _out_uop_T_4468 = or(_out_uop_T_4461, _out_uop_T_4462) node _out_uop_T_4469 = or(_out_uop_T_4468, _out_uop_T_4463) node _out_uop_T_4470 = or(_out_uop_T_4469, _out_uop_T_4464) node _out_uop_T_4471 = or(_out_uop_T_4470, _out_uop_T_4465) node _out_uop_T_4472 = or(_out_uop_T_4471, _out_uop_T_4466) node _out_uop_T_4473 = or(_out_uop_T_4472, _out_uop_T_4467) wire _out_uop_WIRE_370 : UInt<1> connect _out_uop_WIRE_370, _out_uop_T_4473 connect _out_uop_WIRE_351.swap12, _out_uop_WIRE_370 node _out_uop_T_4474 = mux(_out_uop_T_4194, ram[0].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4475 = mux(_out_uop_T_4195, ram[1].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4476 = mux(_out_uop_T_4196, ram[2].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4477 = mux(_out_uop_T_4197, ram[3].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4478 = mux(_out_uop_T_4198, ram[4].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4479 = mux(_out_uop_T_4199, ram[5].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4480 = mux(_out_uop_T_4200, ram[6].bits.fdivin.ren3, UInt<1>(0h0)) node _out_uop_T_4481 = or(_out_uop_T_4474, _out_uop_T_4475) node _out_uop_T_4482 = or(_out_uop_T_4481, _out_uop_T_4476) node _out_uop_T_4483 = or(_out_uop_T_4482, _out_uop_T_4477) node _out_uop_T_4484 = or(_out_uop_T_4483, _out_uop_T_4478) node _out_uop_T_4485 = or(_out_uop_T_4484, _out_uop_T_4479) node _out_uop_T_4486 = or(_out_uop_T_4485, _out_uop_T_4480) wire _out_uop_WIRE_371 : UInt<1> connect _out_uop_WIRE_371, _out_uop_T_4486 connect _out_uop_WIRE_351.ren3, _out_uop_WIRE_371 node _out_uop_T_4487 = mux(_out_uop_T_4194, ram[0].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4488 = mux(_out_uop_T_4195, ram[1].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4489 = mux(_out_uop_T_4196, ram[2].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4490 = mux(_out_uop_T_4197, ram[3].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4491 = mux(_out_uop_T_4198, ram[4].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4492 = mux(_out_uop_T_4199, ram[5].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4493 = mux(_out_uop_T_4200, ram[6].bits.fdivin.ren2, UInt<1>(0h0)) node _out_uop_T_4494 = or(_out_uop_T_4487, _out_uop_T_4488) node _out_uop_T_4495 = or(_out_uop_T_4494, _out_uop_T_4489) node _out_uop_T_4496 = or(_out_uop_T_4495, _out_uop_T_4490) node _out_uop_T_4497 = or(_out_uop_T_4496, _out_uop_T_4491) node _out_uop_T_4498 = or(_out_uop_T_4497, _out_uop_T_4492) node _out_uop_T_4499 = or(_out_uop_T_4498, _out_uop_T_4493) wire _out_uop_WIRE_372 : UInt<1> connect _out_uop_WIRE_372, _out_uop_T_4499 connect _out_uop_WIRE_351.ren2, _out_uop_WIRE_372 node _out_uop_T_4500 = mux(_out_uop_T_4194, ram[0].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4501 = mux(_out_uop_T_4195, ram[1].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4502 = mux(_out_uop_T_4196, ram[2].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4503 = mux(_out_uop_T_4197, ram[3].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4504 = mux(_out_uop_T_4198, ram[4].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4505 = mux(_out_uop_T_4199, ram[5].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4506 = mux(_out_uop_T_4200, ram[6].bits.fdivin.ren1, UInt<1>(0h0)) node _out_uop_T_4507 = or(_out_uop_T_4500, _out_uop_T_4501) node _out_uop_T_4508 = or(_out_uop_T_4507, _out_uop_T_4502) node _out_uop_T_4509 = or(_out_uop_T_4508, _out_uop_T_4503) node _out_uop_T_4510 = or(_out_uop_T_4509, _out_uop_T_4504) node _out_uop_T_4511 = or(_out_uop_T_4510, _out_uop_T_4505) node _out_uop_T_4512 = or(_out_uop_T_4511, _out_uop_T_4506) wire _out_uop_WIRE_373 : UInt<1> connect _out_uop_WIRE_373, _out_uop_T_4512 connect _out_uop_WIRE_351.ren1, _out_uop_WIRE_373 node _out_uop_T_4513 = mux(_out_uop_T_4194, ram[0].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4514 = mux(_out_uop_T_4195, ram[1].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4515 = mux(_out_uop_T_4196, ram[2].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4516 = mux(_out_uop_T_4197, ram[3].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4517 = mux(_out_uop_T_4198, ram[4].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4518 = mux(_out_uop_T_4199, ram[5].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4519 = mux(_out_uop_T_4200, ram[6].bits.fdivin.wen, UInt<1>(0h0)) node _out_uop_T_4520 = or(_out_uop_T_4513, _out_uop_T_4514) node _out_uop_T_4521 = or(_out_uop_T_4520, _out_uop_T_4515) node _out_uop_T_4522 = or(_out_uop_T_4521, _out_uop_T_4516) node _out_uop_T_4523 = or(_out_uop_T_4522, _out_uop_T_4517) node _out_uop_T_4524 = or(_out_uop_T_4523, _out_uop_T_4518) node _out_uop_T_4525 = or(_out_uop_T_4524, _out_uop_T_4519) wire _out_uop_WIRE_374 : UInt<1> connect _out_uop_WIRE_374, _out_uop_T_4525 connect _out_uop_WIRE_351.wen, _out_uop_WIRE_374 node _out_uop_T_4526 = mux(_out_uop_T_4194, ram[0].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4527 = mux(_out_uop_T_4195, ram[1].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4528 = mux(_out_uop_T_4196, ram[2].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4529 = mux(_out_uop_T_4197, ram[3].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4530 = mux(_out_uop_T_4198, ram[4].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4531 = mux(_out_uop_T_4199, ram[5].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4532 = mux(_out_uop_T_4200, ram[6].bits.fdivin.ldst, UInt<1>(0h0)) node _out_uop_T_4533 = or(_out_uop_T_4526, _out_uop_T_4527) node _out_uop_T_4534 = or(_out_uop_T_4533, _out_uop_T_4528) node _out_uop_T_4535 = or(_out_uop_T_4534, _out_uop_T_4529) node _out_uop_T_4536 = or(_out_uop_T_4535, _out_uop_T_4530) node _out_uop_T_4537 = or(_out_uop_T_4536, _out_uop_T_4531) node _out_uop_T_4538 = or(_out_uop_T_4537, _out_uop_T_4532) wire _out_uop_WIRE_375 : UInt<1> connect _out_uop_WIRE_375, _out_uop_T_4538 connect _out_uop_WIRE_351.ldst, _out_uop_WIRE_375 connect _out_uop_WIRE_348.fdivin, _out_uop_WIRE_351 node _out_uop_T_4539 = mux(_out_uop_T_4194, ram[0].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4540 = mux(_out_uop_T_4195, ram[1].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4541 = mux(_out_uop_T_4196, ram[2].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4542 = mux(_out_uop_T_4197, ram[3].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4543 = mux(_out_uop_T_4198, ram[4].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4544 = mux(_out_uop_T_4199, ram[5].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4545 = mux(_out_uop_T_4200, ram[6].bits.fexc, UInt<1>(0h0)) node _out_uop_T_4546 = or(_out_uop_T_4539, _out_uop_T_4540) node _out_uop_T_4547 = or(_out_uop_T_4546, _out_uop_T_4541) node _out_uop_T_4548 = or(_out_uop_T_4547, _out_uop_T_4542) node _out_uop_T_4549 = or(_out_uop_T_4548, _out_uop_T_4543) node _out_uop_T_4550 = or(_out_uop_T_4549, _out_uop_T_4544) node _out_uop_T_4551 = or(_out_uop_T_4550, _out_uop_T_4545) wire _out_uop_WIRE_376 : UInt<5> connect _out_uop_WIRE_376, _out_uop_T_4551 connect _out_uop_WIRE_348.fexc, _out_uop_WIRE_376 node _out_uop_T_4552 = mux(_out_uop_T_4194, ram[0].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4553 = mux(_out_uop_T_4195, ram[1].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4554 = mux(_out_uop_T_4196, ram[2].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4555 = mux(_out_uop_T_4197, ram[3].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4556 = mux(_out_uop_T_4198, ram[4].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4557 = mux(_out_uop_T_4199, ram[5].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4558 = mux(_out_uop_T_4200, ram[6].bits.fra3, UInt<1>(0h0)) node _out_uop_T_4559 = or(_out_uop_T_4552, _out_uop_T_4553) node _out_uop_T_4560 = or(_out_uop_T_4559, _out_uop_T_4554) node _out_uop_T_4561 = or(_out_uop_T_4560, _out_uop_T_4555) node _out_uop_T_4562 = or(_out_uop_T_4561, _out_uop_T_4556) node _out_uop_T_4563 = or(_out_uop_T_4562, _out_uop_T_4557) node _out_uop_T_4564 = or(_out_uop_T_4563, _out_uop_T_4558) wire _out_uop_WIRE_377 : UInt<5> connect _out_uop_WIRE_377, _out_uop_T_4564 connect _out_uop_WIRE_348.fra3, _out_uop_WIRE_377 node _out_uop_T_4565 = mux(_out_uop_T_4194, ram[0].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4566 = mux(_out_uop_T_4195, ram[1].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4567 = mux(_out_uop_T_4196, ram[2].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4568 = mux(_out_uop_T_4197, ram[3].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4569 = mux(_out_uop_T_4198, ram[4].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4570 = mux(_out_uop_T_4199, ram[5].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4571 = mux(_out_uop_T_4200, ram[6].bits.fra2, UInt<1>(0h0)) node _out_uop_T_4572 = or(_out_uop_T_4565, _out_uop_T_4566) node _out_uop_T_4573 = or(_out_uop_T_4572, _out_uop_T_4567) node _out_uop_T_4574 = or(_out_uop_T_4573, _out_uop_T_4568) node _out_uop_T_4575 = or(_out_uop_T_4574, _out_uop_T_4569) node _out_uop_T_4576 = or(_out_uop_T_4575, _out_uop_T_4570) node _out_uop_T_4577 = or(_out_uop_T_4576, _out_uop_T_4571) wire _out_uop_WIRE_378 : UInt<5> connect _out_uop_WIRE_378, _out_uop_T_4577 connect _out_uop_WIRE_348.fra2, _out_uop_WIRE_378 node _out_uop_T_4578 = mux(_out_uop_T_4194, ram[0].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4579 = mux(_out_uop_T_4195, ram[1].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4580 = mux(_out_uop_T_4196, ram[2].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4581 = mux(_out_uop_T_4197, ram[3].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4582 = mux(_out_uop_T_4198, ram[4].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4583 = mux(_out_uop_T_4199, ram[5].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4584 = mux(_out_uop_T_4200, ram[6].bits.fra1, UInt<1>(0h0)) node _out_uop_T_4585 = or(_out_uop_T_4578, _out_uop_T_4579) node _out_uop_T_4586 = or(_out_uop_T_4585, _out_uop_T_4580) node _out_uop_T_4587 = or(_out_uop_T_4586, _out_uop_T_4581) node _out_uop_T_4588 = or(_out_uop_T_4587, _out_uop_T_4582) node _out_uop_T_4589 = or(_out_uop_T_4588, _out_uop_T_4583) node _out_uop_T_4590 = or(_out_uop_T_4589, _out_uop_T_4584) wire _out_uop_WIRE_379 : UInt<5> connect _out_uop_WIRE_379, _out_uop_T_4590 connect _out_uop_WIRE_348.fra1, _out_uop_WIRE_379 wire _out_uop_WIRE_380 : { valid : UInt<1>, bits : UInt<64>} node _out_uop_T_4591 = mux(_out_uop_T_4194, ram[0].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4592 = mux(_out_uop_T_4195, ram[1].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4593 = mux(_out_uop_T_4196, ram[2].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4594 = mux(_out_uop_T_4197, ram[3].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4595 = mux(_out_uop_T_4198, ram[4].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4596 = mux(_out_uop_T_4199, ram[5].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4597 = mux(_out_uop_T_4200, ram[6].bits.wdata.bits, UInt<1>(0h0)) node _out_uop_T_4598 = or(_out_uop_T_4591, _out_uop_T_4592) node _out_uop_T_4599 = or(_out_uop_T_4598, _out_uop_T_4593) node _out_uop_T_4600 = or(_out_uop_T_4599, _out_uop_T_4594) node _out_uop_T_4601 = or(_out_uop_T_4600, _out_uop_T_4595) node _out_uop_T_4602 = or(_out_uop_T_4601, _out_uop_T_4596) node _out_uop_T_4603 = or(_out_uop_T_4602, _out_uop_T_4597) wire _out_uop_WIRE_381 : UInt<64> connect _out_uop_WIRE_381, _out_uop_T_4603 connect _out_uop_WIRE_380.bits, _out_uop_WIRE_381 node _out_uop_T_4604 = mux(_out_uop_T_4194, ram[0].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4605 = mux(_out_uop_T_4195, ram[1].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4606 = mux(_out_uop_T_4196, ram[2].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4607 = mux(_out_uop_T_4197, ram[3].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4608 = mux(_out_uop_T_4198, ram[4].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4609 = mux(_out_uop_T_4199, ram[5].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4610 = mux(_out_uop_T_4200, ram[6].bits.wdata.valid, UInt<1>(0h0)) node _out_uop_T_4611 = or(_out_uop_T_4604, _out_uop_T_4605) node _out_uop_T_4612 = or(_out_uop_T_4611, _out_uop_T_4606) node _out_uop_T_4613 = or(_out_uop_T_4612, _out_uop_T_4607) node _out_uop_T_4614 = or(_out_uop_T_4613, _out_uop_T_4608) node _out_uop_T_4615 = or(_out_uop_T_4614, _out_uop_T_4609) node _out_uop_T_4616 = or(_out_uop_T_4615, _out_uop_T_4610) wire _out_uop_WIRE_382 : UInt<1> connect _out_uop_WIRE_382, _out_uop_T_4616 connect _out_uop_WIRE_380.valid, _out_uop_WIRE_382 connect _out_uop_WIRE_348.wdata, _out_uop_WIRE_380 node _out_uop_T_4617 = mux(_out_uop_T_4194, ram[0].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4618 = mux(_out_uop_T_4195, ram[1].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4619 = mux(_out_uop_T_4196, ram[2].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4620 = mux(_out_uop_T_4197, ram[3].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4621 = mux(_out_uop_T_4198, ram[4].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4622 = mux(_out_uop_T_4199, ram[5].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4623 = mux(_out_uop_T_4200, ram[6].bits.uses_latealu, UInt<1>(0h0)) node _out_uop_T_4624 = or(_out_uop_T_4617, _out_uop_T_4618) node _out_uop_T_4625 = or(_out_uop_T_4624, _out_uop_T_4619) node _out_uop_T_4626 = or(_out_uop_T_4625, _out_uop_T_4620) node _out_uop_T_4627 = or(_out_uop_T_4626, _out_uop_T_4621) node _out_uop_T_4628 = or(_out_uop_T_4627, _out_uop_T_4622) node _out_uop_T_4629 = or(_out_uop_T_4628, _out_uop_T_4623) wire _out_uop_WIRE_383 : UInt<1> connect _out_uop_WIRE_383, _out_uop_T_4629 connect _out_uop_WIRE_348.uses_latealu, _out_uop_WIRE_383 node _out_uop_T_4630 = mux(_out_uop_T_4194, ram[0].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4631 = mux(_out_uop_T_4195, ram[1].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4632 = mux(_out_uop_T_4196, ram[2].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4633 = mux(_out_uop_T_4197, ram[3].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4634 = mux(_out_uop_T_4198, ram[4].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4635 = mux(_out_uop_T_4199, ram[5].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4636 = mux(_out_uop_T_4200, ram[6].bits.uses_memalu, UInt<1>(0h0)) node _out_uop_T_4637 = or(_out_uop_T_4630, _out_uop_T_4631) node _out_uop_T_4638 = or(_out_uop_T_4637, _out_uop_T_4632) node _out_uop_T_4639 = or(_out_uop_T_4638, _out_uop_T_4633) node _out_uop_T_4640 = or(_out_uop_T_4639, _out_uop_T_4634) node _out_uop_T_4641 = or(_out_uop_T_4640, _out_uop_T_4635) node _out_uop_T_4642 = or(_out_uop_T_4641, _out_uop_T_4636) wire _out_uop_WIRE_384 : UInt<1> connect _out_uop_WIRE_384, _out_uop_T_4642 connect _out_uop_WIRE_348.uses_memalu, _out_uop_WIRE_384 node _out_uop_T_4643 = mux(_out_uop_T_4194, ram[0].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4644 = mux(_out_uop_T_4195, ram[1].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4645 = mux(_out_uop_T_4196, ram[2].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4646 = mux(_out_uop_T_4197, ram[3].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4647 = mux(_out_uop_T_4198, ram[4].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4648 = mux(_out_uop_T_4199, ram[5].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4649 = mux(_out_uop_T_4200, ram[6].bits.rs3_data, UInt<1>(0h0)) node _out_uop_T_4650 = or(_out_uop_T_4643, _out_uop_T_4644) node _out_uop_T_4651 = or(_out_uop_T_4650, _out_uop_T_4645) node _out_uop_T_4652 = or(_out_uop_T_4651, _out_uop_T_4646) node _out_uop_T_4653 = or(_out_uop_T_4652, _out_uop_T_4647) node _out_uop_T_4654 = or(_out_uop_T_4653, _out_uop_T_4648) node _out_uop_T_4655 = or(_out_uop_T_4654, _out_uop_T_4649) wire _out_uop_WIRE_385 : UInt<64> connect _out_uop_WIRE_385, _out_uop_T_4655 connect _out_uop_WIRE_348.rs3_data, _out_uop_WIRE_385 node _out_uop_T_4656 = mux(_out_uop_T_4194, ram[0].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4657 = mux(_out_uop_T_4195, ram[1].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4658 = mux(_out_uop_T_4196, ram[2].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4659 = mux(_out_uop_T_4197, ram[3].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4660 = mux(_out_uop_T_4198, ram[4].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4661 = mux(_out_uop_T_4199, ram[5].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4662 = mux(_out_uop_T_4200, ram[6].bits.rs2_data, UInt<1>(0h0)) node _out_uop_T_4663 = or(_out_uop_T_4656, _out_uop_T_4657) node _out_uop_T_4664 = or(_out_uop_T_4663, _out_uop_T_4658) node _out_uop_T_4665 = or(_out_uop_T_4664, _out_uop_T_4659) node _out_uop_T_4666 = or(_out_uop_T_4665, _out_uop_T_4660) node _out_uop_T_4667 = or(_out_uop_T_4666, _out_uop_T_4661) node _out_uop_T_4668 = or(_out_uop_T_4667, _out_uop_T_4662) wire _out_uop_WIRE_386 : UInt<64> connect _out_uop_WIRE_386, _out_uop_T_4668 connect _out_uop_WIRE_348.rs2_data, _out_uop_WIRE_386 node _out_uop_T_4669 = mux(_out_uop_T_4194, ram[0].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4670 = mux(_out_uop_T_4195, ram[1].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4671 = mux(_out_uop_T_4196, ram[2].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4672 = mux(_out_uop_T_4197, ram[3].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4673 = mux(_out_uop_T_4198, ram[4].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4674 = mux(_out_uop_T_4199, ram[5].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4675 = mux(_out_uop_T_4200, ram[6].bits.rs1_data, UInt<1>(0h0)) node _out_uop_T_4676 = or(_out_uop_T_4669, _out_uop_T_4670) node _out_uop_T_4677 = or(_out_uop_T_4676, _out_uop_T_4671) node _out_uop_T_4678 = or(_out_uop_T_4677, _out_uop_T_4672) node _out_uop_T_4679 = or(_out_uop_T_4678, _out_uop_T_4673) node _out_uop_T_4680 = or(_out_uop_T_4679, _out_uop_T_4674) node _out_uop_T_4681 = or(_out_uop_T_4680, _out_uop_T_4675) wire _out_uop_WIRE_387 : UInt<64> connect _out_uop_WIRE_387, _out_uop_T_4681 connect _out_uop_WIRE_348.rs1_data, _out_uop_WIRE_387 node _out_uop_T_4682 = mux(_out_uop_T_4194, ram[0].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4683 = mux(_out_uop_T_4195, ram[1].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4684 = mux(_out_uop_T_4196, ram[2].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4685 = mux(_out_uop_T_4197, ram[3].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4686 = mux(_out_uop_T_4198, ram[4].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4687 = mux(_out_uop_T_4199, ram[5].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4688 = mux(_out_uop_T_4200, ram[6].bits.needs_replay, UInt<1>(0h0)) node _out_uop_T_4689 = or(_out_uop_T_4682, _out_uop_T_4683) node _out_uop_T_4690 = or(_out_uop_T_4689, _out_uop_T_4684) node _out_uop_T_4691 = or(_out_uop_T_4690, _out_uop_T_4685) node _out_uop_T_4692 = or(_out_uop_T_4691, _out_uop_T_4686) node _out_uop_T_4693 = or(_out_uop_T_4692, _out_uop_T_4687) node _out_uop_T_4694 = or(_out_uop_T_4693, _out_uop_T_4688) wire _out_uop_WIRE_388 : UInt<1> connect _out_uop_WIRE_388, _out_uop_T_4694 connect _out_uop_WIRE_348.needs_replay, _out_uop_WIRE_388 node _out_uop_T_4695 = mux(_out_uop_T_4194, ram[0].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4696 = mux(_out_uop_T_4195, ram[1].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4697 = mux(_out_uop_T_4196, ram[2].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4698 = mux(_out_uop_T_4197, ram[3].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4699 = mux(_out_uop_T_4198, ram[4].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4700 = mux(_out_uop_T_4199, ram[5].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4701 = mux(_out_uop_T_4200, ram[6].bits.xcpt_cause, UInt<1>(0h0)) node _out_uop_T_4702 = or(_out_uop_T_4695, _out_uop_T_4696) node _out_uop_T_4703 = or(_out_uop_T_4702, _out_uop_T_4697) node _out_uop_T_4704 = or(_out_uop_T_4703, _out_uop_T_4698) node _out_uop_T_4705 = or(_out_uop_T_4704, _out_uop_T_4699) node _out_uop_T_4706 = or(_out_uop_T_4705, _out_uop_T_4700) node _out_uop_T_4707 = or(_out_uop_T_4706, _out_uop_T_4701) wire _out_uop_WIRE_389 : UInt<64> connect _out_uop_WIRE_389, _out_uop_T_4707 connect _out_uop_WIRE_348.xcpt_cause, _out_uop_WIRE_389 node _out_uop_T_4708 = mux(_out_uop_T_4194, ram[0].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4709 = mux(_out_uop_T_4195, ram[1].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4710 = mux(_out_uop_T_4196, ram[2].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4711 = mux(_out_uop_T_4197, ram[3].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4712 = mux(_out_uop_T_4198, ram[4].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4713 = mux(_out_uop_T_4199, ram[5].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4714 = mux(_out_uop_T_4200, ram[6].bits.xcpt, UInt<1>(0h0)) node _out_uop_T_4715 = or(_out_uop_T_4708, _out_uop_T_4709) node _out_uop_T_4716 = or(_out_uop_T_4715, _out_uop_T_4710) node _out_uop_T_4717 = or(_out_uop_T_4716, _out_uop_T_4711) node _out_uop_T_4718 = or(_out_uop_T_4717, _out_uop_T_4712) node _out_uop_T_4719 = or(_out_uop_T_4718, _out_uop_T_4713) node _out_uop_T_4720 = or(_out_uop_T_4719, _out_uop_T_4714) wire _out_uop_WIRE_390 : UInt<1> connect _out_uop_WIRE_390, _out_uop_T_4720 connect _out_uop_WIRE_348.xcpt, _out_uop_WIRE_390 node _out_uop_T_4721 = mux(_out_uop_T_4194, ram[0].bits.taken, UInt<1>(0h0)) node _out_uop_T_4722 = mux(_out_uop_T_4195, ram[1].bits.taken, UInt<1>(0h0)) node _out_uop_T_4723 = mux(_out_uop_T_4196, ram[2].bits.taken, UInt<1>(0h0)) node _out_uop_T_4724 = mux(_out_uop_T_4197, ram[3].bits.taken, UInt<1>(0h0)) node _out_uop_T_4725 = mux(_out_uop_T_4198, ram[4].bits.taken, UInt<1>(0h0)) node _out_uop_T_4726 = mux(_out_uop_T_4199, ram[5].bits.taken, UInt<1>(0h0)) node _out_uop_T_4727 = mux(_out_uop_T_4200, ram[6].bits.taken, UInt<1>(0h0)) node _out_uop_T_4728 = or(_out_uop_T_4721, _out_uop_T_4722) node _out_uop_T_4729 = or(_out_uop_T_4728, _out_uop_T_4723) node _out_uop_T_4730 = or(_out_uop_T_4729, _out_uop_T_4724) node _out_uop_T_4731 = or(_out_uop_T_4730, _out_uop_T_4725) node _out_uop_T_4732 = or(_out_uop_T_4731, _out_uop_T_4726) node _out_uop_T_4733 = or(_out_uop_T_4732, _out_uop_T_4727) wire _out_uop_WIRE_391 : UInt<1> connect _out_uop_WIRE_391, _out_uop_T_4733 connect _out_uop_WIRE_348.taken, _out_uop_WIRE_391 node _out_uop_T_4734 = mux(_out_uop_T_4194, ram[0].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4735 = mux(_out_uop_T_4195, ram[1].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4736 = mux(_out_uop_T_4196, ram[2].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4737 = mux(_out_uop_T_4197, ram[3].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4738 = mux(_out_uop_T_4198, ram[4].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4739 = mux(_out_uop_T_4199, ram[5].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4740 = mux(_out_uop_T_4200, ram[6].bits.ras_head, UInt<1>(0h0)) node _out_uop_T_4741 = or(_out_uop_T_4734, _out_uop_T_4735) node _out_uop_T_4742 = or(_out_uop_T_4741, _out_uop_T_4736) node _out_uop_T_4743 = or(_out_uop_T_4742, _out_uop_T_4737) node _out_uop_T_4744 = or(_out_uop_T_4743, _out_uop_T_4738) node _out_uop_T_4745 = or(_out_uop_T_4744, _out_uop_T_4739) node _out_uop_T_4746 = or(_out_uop_T_4745, _out_uop_T_4740) wire _out_uop_WIRE_392 : UInt<3> connect _out_uop_WIRE_392, _out_uop_T_4746 connect _out_uop_WIRE_348.ras_head, _out_uop_WIRE_392 wire _out_uop_WIRE_393 : { valid : UInt<1>, bits : UInt<40>} node _out_uop_T_4747 = mux(_out_uop_T_4194, ram[0].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4748 = mux(_out_uop_T_4195, ram[1].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4749 = mux(_out_uop_T_4196, ram[2].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4750 = mux(_out_uop_T_4197, ram[3].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4751 = mux(_out_uop_T_4198, ram[4].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4752 = mux(_out_uop_T_4199, ram[5].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4753 = mux(_out_uop_T_4200, ram[6].bits.next_pc.bits, UInt<1>(0h0)) node _out_uop_T_4754 = or(_out_uop_T_4747, _out_uop_T_4748) node _out_uop_T_4755 = or(_out_uop_T_4754, _out_uop_T_4749) node _out_uop_T_4756 = or(_out_uop_T_4755, _out_uop_T_4750) node _out_uop_T_4757 = or(_out_uop_T_4756, _out_uop_T_4751) node _out_uop_T_4758 = or(_out_uop_T_4757, _out_uop_T_4752) node _out_uop_T_4759 = or(_out_uop_T_4758, _out_uop_T_4753) wire _out_uop_WIRE_394 : UInt<40> connect _out_uop_WIRE_394, _out_uop_T_4759 connect _out_uop_WIRE_393.bits, _out_uop_WIRE_394 node _out_uop_T_4760 = mux(_out_uop_T_4194, ram[0].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4761 = mux(_out_uop_T_4195, ram[1].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4762 = mux(_out_uop_T_4196, ram[2].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4763 = mux(_out_uop_T_4197, ram[3].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4764 = mux(_out_uop_T_4198, ram[4].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4765 = mux(_out_uop_T_4199, ram[5].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4766 = mux(_out_uop_T_4200, ram[6].bits.next_pc.valid, UInt<1>(0h0)) node _out_uop_T_4767 = or(_out_uop_T_4760, _out_uop_T_4761) node _out_uop_T_4768 = or(_out_uop_T_4767, _out_uop_T_4762) node _out_uop_T_4769 = or(_out_uop_T_4768, _out_uop_T_4763) node _out_uop_T_4770 = or(_out_uop_T_4769, _out_uop_T_4764) node _out_uop_T_4771 = or(_out_uop_T_4770, _out_uop_T_4765) node _out_uop_T_4772 = or(_out_uop_T_4771, _out_uop_T_4766) wire _out_uop_WIRE_395 : UInt<1> connect _out_uop_WIRE_395, _out_uop_T_4772 connect _out_uop_WIRE_393.valid, _out_uop_WIRE_395 connect _out_uop_WIRE_348.next_pc, _out_uop_WIRE_393 node _out_uop_T_4773 = mux(_out_uop_T_4194, ram[0].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4774 = mux(_out_uop_T_4195, ram[1].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4775 = mux(_out_uop_T_4196, ram[2].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4776 = mux(_out_uop_T_4197, ram[3].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4777 = mux(_out_uop_T_4198, ram[4].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4778 = mux(_out_uop_T_4199, ram[5].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4779 = mux(_out_uop_T_4200, ram[6].bits.sfb_shadow, UInt<1>(0h0)) node _out_uop_T_4780 = or(_out_uop_T_4773, _out_uop_T_4774) node _out_uop_T_4781 = or(_out_uop_T_4780, _out_uop_T_4775) node _out_uop_T_4782 = or(_out_uop_T_4781, _out_uop_T_4776) node _out_uop_T_4783 = or(_out_uop_T_4782, _out_uop_T_4777) node _out_uop_T_4784 = or(_out_uop_T_4783, _out_uop_T_4778) node _out_uop_T_4785 = or(_out_uop_T_4784, _out_uop_T_4779) wire _out_uop_WIRE_396 : UInt<1> connect _out_uop_WIRE_396, _out_uop_T_4785 connect _out_uop_WIRE_348.sfb_shadow, _out_uop_WIRE_396 node _out_uop_T_4786 = mux(_out_uop_T_4194, ram[0].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4787 = mux(_out_uop_T_4195, ram[1].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4788 = mux(_out_uop_T_4196, ram[2].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4789 = mux(_out_uop_T_4197, ram[3].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4790 = mux(_out_uop_T_4198, ram[4].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4791 = mux(_out_uop_T_4199, ram[5].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4792 = mux(_out_uop_T_4200, ram[6].bits.sfb_br, UInt<1>(0h0)) node _out_uop_T_4793 = or(_out_uop_T_4786, _out_uop_T_4787) node _out_uop_T_4794 = or(_out_uop_T_4793, _out_uop_T_4788) node _out_uop_T_4795 = or(_out_uop_T_4794, _out_uop_T_4789) node _out_uop_T_4796 = or(_out_uop_T_4795, _out_uop_T_4790) node _out_uop_T_4797 = or(_out_uop_T_4796, _out_uop_T_4791) node _out_uop_T_4798 = or(_out_uop_T_4797, _out_uop_T_4792) wire _out_uop_WIRE_397 : UInt<1> connect _out_uop_WIRE_397, _out_uop_T_4798 connect _out_uop_WIRE_348.sfb_br, _out_uop_WIRE_397 wire _out_uop_WIRE_398 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _out_uop_WIRE_399 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _out_uop_WIRE_400 : { history : UInt<8>, value : UInt<2>} node _out_uop_T_4799 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4800 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4801 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4802 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4803 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4804 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4805 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _out_uop_T_4806 = or(_out_uop_T_4799, _out_uop_T_4800) node _out_uop_T_4807 = or(_out_uop_T_4806, _out_uop_T_4801) node _out_uop_T_4808 = or(_out_uop_T_4807, _out_uop_T_4802) node _out_uop_T_4809 = or(_out_uop_T_4808, _out_uop_T_4803) node _out_uop_T_4810 = or(_out_uop_T_4809, _out_uop_T_4804) node _out_uop_T_4811 = or(_out_uop_T_4810, _out_uop_T_4805) wire _out_uop_WIRE_401 : UInt<2> connect _out_uop_WIRE_401, _out_uop_T_4811 connect _out_uop_WIRE_400.value, _out_uop_WIRE_401 node _out_uop_T_4812 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4813 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4814 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4815 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4816 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4817 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4818 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _out_uop_T_4819 = or(_out_uop_T_4812, _out_uop_T_4813) node _out_uop_T_4820 = or(_out_uop_T_4819, _out_uop_T_4814) node _out_uop_T_4821 = or(_out_uop_T_4820, _out_uop_T_4815) node _out_uop_T_4822 = or(_out_uop_T_4821, _out_uop_T_4816) node _out_uop_T_4823 = or(_out_uop_T_4822, _out_uop_T_4817) node _out_uop_T_4824 = or(_out_uop_T_4823, _out_uop_T_4818) wire _out_uop_WIRE_402 : UInt<8> connect _out_uop_WIRE_402, _out_uop_T_4824 connect _out_uop_WIRE_400.history, _out_uop_WIRE_402 connect _out_uop_WIRE_399.bht, _out_uop_WIRE_400 node _out_uop_T_4825 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4826 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4827 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4828 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4829 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4830 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4831 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _out_uop_T_4832 = or(_out_uop_T_4825, _out_uop_T_4826) node _out_uop_T_4833 = or(_out_uop_T_4832, _out_uop_T_4827) node _out_uop_T_4834 = or(_out_uop_T_4833, _out_uop_T_4828) node _out_uop_T_4835 = or(_out_uop_T_4834, _out_uop_T_4829) node _out_uop_T_4836 = or(_out_uop_T_4835, _out_uop_T_4830) node _out_uop_T_4837 = or(_out_uop_T_4836, _out_uop_T_4831) wire _out_uop_WIRE_403 : UInt<6> connect _out_uop_WIRE_403, _out_uop_T_4837 connect _out_uop_WIRE_399.entry, _out_uop_WIRE_403 node _out_uop_T_4838 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4839 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4840 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4841 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4842 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4843 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4844 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.target, UInt<1>(0h0)) node _out_uop_T_4845 = or(_out_uop_T_4838, _out_uop_T_4839) node _out_uop_T_4846 = or(_out_uop_T_4845, _out_uop_T_4840) node _out_uop_T_4847 = or(_out_uop_T_4846, _out_uop_T_4841) node _out_uop_T_4848 = or(_out_uop_T_4847, _out_uop_T_4842) node _out_uop_T_4849 = or(_out_uop_T_4848, _out_uop_T_4843) node _out_uop_T_4850 = or(_out_uop_T_4849, _out_uop_T_4844) wire _out_uop_WIRE_404 : UInt<39> connect _out_uop_WIRE_404, _out_uop_T_4850 connect _out_uop_WIRE_399.target, _out_uop_WIRE_404 node _out_uop_T_4851 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4852 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4853 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4854 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4855 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4856 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4857 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _out_uop_T_4858 = or(_out_uop_T_4851, _out_uop_T_4852) node _out_uop_T_4859 = or(_out_uop_T_4858, _out_uop_T_4853) node _out_uop_T_4860 = or(_out_uop_T_4859, _out_uop_T_4854) node _out_uop_T_4861 = or(_out_uop_T_4860, _out_uop_T_4855) node _out_uop_T_4862 = or(_out_uop_T_4861, _out_uop_T_4856) node _out_uop_T_4863 = or(_out_uop_T_4862, _out_uop_T_4857) wire _out_uop_WIRE_405 : UInt<2> connect _out_uop_WIRE_405, _out_uop_T_4863 connect _out_uop_WIRE_399.bridx, _out_uop_WIRE_405 node _out_uop_T_4864 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4865 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4866 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4867 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4868 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4869 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4870 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _out_uop_T_4871 = or(_out_uop_T_4864, _out_uop_T_4865) node _out_uop_T_4872 = or(_out_uop_T_4871, _out_uop_T_4866) node _out_uop_T_4873 = or(_out_uop_T_4872, _out_uop_T_4867) node _out_uop_T_4874 = or(_out_uop_T_4873, _out_uop_T_4868) node _out_uop_T_4875 = or(_out_uop_T_4874, _out_uop_T_4869) node _out_uop_T_4876 = or(_out_uop_T_4875, _out_uop_T_4870) wire _out_uop_WIRE_406 : UInt<4> connect _out_uop_WIRE_406, _out_uop_T_4876 connect _out_uop_WIRE_399.mask, _out_uop_WIRE_406 node _out_uop_T_4877 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4878 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4879 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4880 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4881 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4882 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4883 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _out_uop_T_4884 = or(_out_uop_T_4877, _out_uop_T_4878) node _out_uop_T_4885 = or(_out_uop_T_4884, _out_uop_T_4879) node _out_uop_T_4886 = or(_out_uop_T_4885, _out_uop_T_4880) node _out_uop_T_4887 = or(_out_uop_T_4886, _out_uop_T_4881) node _out_uop_T_4888 = or(_out_uop_T_4887, _out_uop_T_4882) node _out_uop_T_4889 = or(_out_uop_T_4888, _out_uop_T_4883) wire _out_uop_WIRE_407 : UInt<1> connect _out_uop_WIRE_407, _out_uop_T_4889 connect _out_uop_WIRE_399.taken, _out_uop_WIRE_407 node _out_uop_T_4890 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4891 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4892 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4893 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4894 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4895 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4896 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _out_uop_T_4897 = or(_out_uop_T_4890, _out_uop_T_4891) node _out_uop_T_4898 = or(_out_uop_T_4897, _out_uop_T_4892) node _out_uop_T_4899 = or(_out_uop_T_4898, _out_uop_T_4893) node _out_uop_T_4900 = or(_out_uop_T_4899, _out_uop_T_4894) node _out_uop_T_4901 = or(_out_uop_T_4900, _out_uop_T_4895) node _out_uop_T_4902 = or(_out_uop_T_4901, _out_uop_T_4896) wire _out_uop_WIRE_408 : UInt<2> connect _out_uop_WIRE_408, _out_uop_T_4902 connect _out_uop_WIRE_399.cfiType, _out_uop_WIRE_408 connect _out_uop_WIRE_398.bits, _out_uop_WIRE_399 node _out_uop_T_4903 = mux(_out_uop_T_4194, ram[0].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4904 = mux(_out_uop_T_4195, ram[1].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4905 = mux(_out_uop_T_4196, ram[2].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4906 = mux(_out_uop_T_4197, ram[3].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4907 = mux(_out_uop_T_4198, ram[4].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4908 = mux(_out_uop_T_4199, ram[5].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4909 = mux(_out_uop_T_4200, ram[6].bits.btb_resp.valid, UInt<1>(0h0)) node _out_uop_T_4910 = or(_out_uop_T_4903, _out_uop_T_4904) node _out_uop_T_4911 = or(_out_uop_T_4910, _out_uop_T_4905) node _out_uop_T_4912 = or(_out_uop_T_4911, _out_uop_T_4906) node _out_uop_T_4913 = or(_out_uop_T_4912, _out_uop_T_4907) node _out_uop_T_4914 = or(_out_uop_T_4913, _out_uop_T_4908) node _out_uop_T_4915 = or(_out_uop_T_4914, _out_uop_T_4909) wire _out_uop_WIRE_409 : UInt<1> connect _out_uop_WIRE_409, _out_uop_T_4915 connect _out_uop_WIRE_398.valid, _out_uop_WIRE_409 connect _out_uop_WIRE_348.btb_resp, _out_uop_WIRE_398 node _out_uop_T_4916 = mux(_out_uop_T_4194, ram[0].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4917 = mux(_out_uop_T_4195, ram[1].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4918 = mux(_out_uop_T_4196, ram[2].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4919 = mux(_out_uop_T_4197, ram[3].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4920 = mux(_out_uop_T_4198, ram[4].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4921 = mux(_out_uop_T_4199, ram[5].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4922 = mux(_out_uop_T_4200, ram[6].bits.sets_vcfg, UInt<1>(0h0)) node _out_uop_T_4923 = or(_out_uop_T_4916, _out_uop_T_4917) node _out_uop_T_4924 = or(_out_uop_T_4923, _out_uop_T_4918) node _out_uop_T_4925 = or(_out_uop_T_4924, _out_uop_T_4919) node _out_uop_T_4926 = or(_out_uop_T_4925, _out_uop_T_4920) node _out_uop_T_4927 = or(_out_uop_T_4926, _out_uop_T_4921) node _out_uop_T_4928 = or(_out_uop_T_4927, _out_uop_T_4922) wire _out_uop_WIRE_410 : UInt<1> connect _out_uop_WIRE_410, _out_uop_T_4928 connect _out_uop_WIRE_348.sets_vcfg, _out_uop_WIRE_410 node _out_uop_T_4929 = mux(_out_uop_T_4194, ram[0].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4930 = mux(_out_uop_T_4195, ram[1].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4931 = mux(_out_uop_T_4196, ram[2].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4932 = mux(_out_uop_T_4197, ram[3].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4933 = mux(_out_uop_T_4198, ram[4].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4934 = mux(_out_uop_T_4199, ram[5].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4935 = mux(_out_uop_T_4200, ram[6].bits.rvc, UInt<1>(0h0)) node _out_uop_T_4936 = or(_out_uop_T_4929, _out_uop_T_4930) node _out_uop_T_4937 = or(_out_uop_T_4936, _out_uop_T_4931) node _out_uop_T_4938 = or(_out_uop_T_4937, _out_uop_T_4932) node _out_uop_T_4939 = or(_out_uop_T_4938, _out_uop_T_4933) node _out_uop_T_4940 = or(_out_uop_T_4939, _out_uop_T_4934) node _out_uop_T_4941 = or(_out_uop_T_4940, _out_uop_T_4935) wire _out_uop_WIRE_411 : UInt<1> connect _out_uop_WIRE_411, _out_uop_T_4941 connect _out_uop_WIRE_348.rvc, _out_uop_WIRE_411 wire _out_uop_WIRE_412 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _out_uop_T_4942 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4943 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4944 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4945 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4946 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4947 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4948 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.vec, UInt<1>(0h0)) node _out_uop_T_4949 = or(_out_uop_T_4942, _out_uop_T_4943) node _out_uop_T_4950 = or(_out_uop_T_4949, _out_uop_T_4944) node _out_uop_T_4951 = or(_out_uop_T_4950, _out_uop_T_4945) node _out_uop_T_4952 = or(_out_uop_T_4951, _out_uop_T_4946) node _out_uop_T_4953 = or(_out_uop_T_4952, _out_uop_T_4947) node _out_uop_T_4954 = or(_out_uop_T_4953, _out_uop_T_4948) wire _out_uop_WIRE_413 : UInt<1> connect _out_uop_WIRE_413, _out_uop_T_4954 connect _out_uop_WIRE_412.vec, _out_uop_WIRE_413 node _out_uop_T_4955 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4956 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4957 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4958 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4959 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4960 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4961 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _out_uop_T_4962 = or(_out_uop_T_4955, _out_uop_T_4956) node _out_uop_T_4963 = or(_out_uop_T_4962, _out_uop_T_4957) node _out_uop_T_4964 = or(_out_uop_T_4963, _out_uop_T_4958) node _out_uop_T_4965 = or(_out_uop_T_4964, _out_uop_T_4959) node _out_uop_T_4966 = or(_out_uop_T_4965, _out_uop_T_4960) node _out_uop_T_4967 = or(_out_uop_T_4966, _out_uop_T_4961) wire _out_uop_WIRE_414 : UInt<1> connect _out_uop_WIRE_414, _out_uop_T_4967 connect _out_uop_WIRE_412.wflags, _out_uop_WIRE_414 node _out_uop_T_4968 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4969 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4970 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4971 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4972 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4973 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4974 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _out_uop_T_4975 = or(_out_uop_T_4968, _out_uop_T_4969) node _out_uop_T_4976 = or(_out_uop_T_4975, _out_uop_T_4970) node _out_uop_T_4977 = or(_out_uop_T_4976, _out_uop_T_4971) node _out_uop_T_4978 = or(_out_uop_T_4977, _out_uop_T_4972) node _out_uop_T_4979 = or(_out_uop_T_4978, _out_uop_T_4973) node _out_uop_T_4980 = or(_out_uop_T_4979, _out_uop_T_4974) wire _out_uop_WIRE_415 : UInt<1> connect _out_uop_WIRE_415, _out_uop_T_4980 connect _out_uop_WIRE_412.sqrt, _out_uop_WIRE_415 node _out_uop_T_4981 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4982 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4983 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4984 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4985 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4986 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4987 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.div, UInt<1>(0h0)) node _out_uop_T_4988 = or(_out_uop_T_4981, _out_uop_T_4982) node _out_uop_T_4989 = or(_out_uop_T_4988, _out_uop_T_4983) node _out_uop_T_4990 = or(_out_uop_T_4989, _out_uop_T_4984) node _out_uop_T_4991 = or(_out_uop_T_4990, _out_uop_T_4985) node _out_uop_T_4992 = or(_out_uop_T_4991, _out_uop_T_4986) node _out_uop_T_4993 = or(_out_uop_T_4992, _out_uop_T_4987) wire _out_uop_WIRE_416 : UInt<1> connect _out_uop_WIRE_416, _out_uop_T_4993 connect _out_uop_WIRE_412.div, _out_uop_WIRE_416 node _out_uop_T_4994 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_4995 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_4996 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_4997 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_4998 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_4999 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_5000 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.fma, UInt<1>(0h0)) node _out_uop_T_5001 = or(_out_uop_T_4994, _out_uop_T_4995) node _out_uop_T_5002 = or(_out_uop_T_5001, _out_uop_T_4996) node _out_uop_T_5003 = or(_out_uop_T_5002, _out_uop_T_4997) node _out_uop_T_5004 = or(_out_uop_T_5003, _out_uop_T_4998) node _out_uop_T_5005 = or(_out_uop_T_5004, _out_uop_T_4999) node _out_uop_T_5006 = or(_out_uop_T_5005, _out_uop_T_5000) wire _out_uop_WIRE_417 : UInt<1> connect _out_uop_WIRE_417, _out_uop_T_5006 connect _out_uop_WIRE_412.fma, _out_uop_WIRE_417 node _out_uop_T_5007 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5008 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5009 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5010 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5011 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5012 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5013 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _out_uop_T_5014 = or(_out_uop_T_5007, _out_uop_T_5008) node _out_uop_T_5015 = or(_out_uop_T_5014, _out_uop_T_5009) node _out_uop_T_5016 = or(_out_uop_T_5015, _out_uop_T_5010) node _out_uop_T_5017 = or(_out_uop_T_5016, _out_uop_T_5011) node _out_uop_T_5018 = or(_out_uop_T_5017, _out_uop_T_5012) node _out_uop_T_5019 = or(_out_uop_T_5018, _out_uop_T_5013) wire _out_uop_WIRE_418 : UInt<1> connect _out_uop_WIRE_418, _out_uop_T_5019 connect _out_uop_WIRE_412.fastpipe, _out_uop_WIRE_418 node _out_uop_T_5020 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5021 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5022 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5023 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5024 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5025 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5026 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.toint, UInt<1>(0h0)) node _out_uop_T_5027 = or(_out_uop_T_5020, _out_uop_T_5021) node _out_uop_T_5028 = or(_out_uop_T_5027, _out_uop_T_5022) node _out_uop_T_5029 = or(_out_uop_T_5028, _out_uop_T_5023) node _out_uop_T_5030 = or(_out_uop_T_5029, _out_uop_T_5024) node _out_uop_T_5031 = or(_out_uop_T_5030, _out_uop_T_5025) node _out_uop_T_5032 = or(_out_uop_T_5031, _out_uop_T_5026) wire _out_uop_WIRE_419 : UInt<1> connect _out_uop_WIRE_419, _out_uop_T_5032 connect _out_uop_WIRE_412.toint, _out_uop_WIRE_419 node _out_uop_T_5033 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5034 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5035 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5036 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5037 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5038 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5039 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _out_uop_T_5040 = or(_out_uop_T_5033, _out_uop_T_5034) node _out_uop_T_5041 = or(_out_uop_T_5040, _out_uop_T_5035) node _out_uop_T_5042 = or(_out_uop_T_5041, _out_uop_T_5036) node _out_uop_T_5043 = or(_out_uop_T_5042, _out_uop_T_5037) node _out_uop_T_5044 = or(_out_uop_T_5043, _out_uop_T_5038) node _out_uop_T_5045 = or(_out_uop_T_5044, _out_uop_T_5039) wire _out_uop_WIRE_420 : UInt<1> connect _out_uop_WIRE_420, _out_uop_T_5045 connect _out_uop_WIRE_412.fromint, _out_uop_WIRE_420 node _out_uop_T_5046 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5047 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5048 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5049 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5050 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5051 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5052 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _out_uop_T_5053 = or(_out_uop_T_5046, _out_uop_T_5047) node _out_uop_T_5054 = or(_out_uop_T_5053, _out_uop_T_5048) node _out_uop_T_5055 = or(_out_uop_T_5054, _out_uop_T_5049) node _out_uop_T_5056 = or(_out_uop_T_5055, _out_uop_T_5050) node _out_uop_T_5057 = or(_out_uop_T_5056, _out_uop_T_5051) node _out_uop_T_5058 = or(_out_uop_T_5057, _out_uop_T_5052) wire _out_uop_WIRE_421 : UInt<2> connect _out_uop_WIRE_421, _out_uop_T_5058 connect _out_uop_WIRE_412.typeTagOut, _out_uop_WIRE_421 node _out_uop_T_5059 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5060 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5061 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5062 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5063 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5064 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5065 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _out_uop_T_5066 = or(_out_uop_T_5059, _out_uop_T_5060) node _out_uop_T_5067 = or(_out_uop_T_5066, _out_uop_T_5061) node _out_uop_T_5068 = or(_out_uop_T_5067, _out_uop_T_5062) node _out_uop_T_5069 = or(_out_uop_T_5068, _out_uop_T_5063) node _out_uop_T_5070 = or(_out_uop_T_5069, _out_uop_T_5064) node _out_uop_T_5071 = or(_out_uop_T_5070, _out_uop_T_5065) wire _out_uop_WIRE_422 : UInt<2> connect _out_uop_WIRE_422, _out_uop_T_5071 connect _out_uop_WIRE_412.typeTagIn, _out_uop_WIRE_422 node _out_uop_T_5072 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5073 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5074 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5075 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5076 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5077 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5078 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _out_uop_T_5079 = or(_out_uop_T_5072, _out_uop_T_5073) node _out_uop_T_5080 = or(_out_uop_T_5079, _out_uop_T_5074) node _out_uop_T_5081 = or(_out_uop_T_5080, _out_uop_T_5075) node _out_uop_T_5082 = or(_out_uop_T_5081, _out_uop_T_5076) node _out_uop_T_5083 = or(_out_uop_T_5082, _out_uop_T_5077) node _out_uop_T_5084 = or(_out_uop_T_5083, _out_uop_T_5078) wire _out_uop_WIRE_423 : UInt<1> connect _out_uop_WIRE_423, _out_uop_T_5084 connect _out_uop_WIRE_412.swap23, _out_uop_WIRE_423 node _out_uop_T_5085 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5086 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5087 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5088 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5089 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5090 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5091 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _out_uop_T_5092 = or(_out_uop_T_5085, _out_uop_T_5086) node _out_uop_T_5093 = or(_out_uop_T_5092, _out_uop_T_5087) node _out_uop_T_5094 = or(_out_uop_T_5093, _out_uop_T_5088) node _out_uop_T_5095 = or(_out_uop_T_5094, _out_uop_T_5089) node _out_uop_T_5096 = or(_out_uop_T_5095, _out_uop_T_5090) node _out_uop_T_5097 = or(_out_uop_T_5096, _out_uop_T_5091) wire _out_uop_WIRE_424 : UInt<1> connect _out_uop_WIRE_424, _out_uop_T_5097 connect _out_uop_WIRE_412.swap12, _out_uop_WIRE_424 node _out_uop_T_5098 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5099 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5100 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5101 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5102 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5103 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5104 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _out_uop_T_5105 = or(_out_uop_T_5098, _out_uop_T_5099) node _out_uop_T_5106 = or(_out_uop_T_5105, _out_uop_T_5100) node _out_uop_T_5107 = or(_out_uop_T_5106, _out_uop_T_5101) node _out_uop_T_5108 = or(_out_uop_T_5107, _out_uop_T_5102) node _out_uop_T_5109 = or(_out_uop_T_5108, _out_uop_T_5103) node _out_uop_T_5110 = or(_out_uop_T_5109, _out_uop_T_5104) wire _out_uop_WIRE_425 : UInt<1> connect _out_uop_WIRE_425, _out_uop_T_5110 connect _out_uop_WIRE_412.ren3, _out_uop_WIRE_425 node _out_uop_T_5111 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5112 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5113 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5114 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5115 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5116 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5117 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _out_uop_T_5118 = or(_out_uop_T_5111, _out_uop_T_5112) node _out_uop_T_5119 = or(_out_uop_T_5118, _out_uop_T_5113) node _out_uop_T_5120 = or(_out_uop_T_5119, _out_uop_T_5114) node _out_uop_T_5121 = or(_out_uop_T_5120, _out_uop_T_5115) node _out_uop_T_5122 = or(_out_uop_T_5121, _out_uop_T_5116) node _out_uop_T_5123 = or(_out_uop_T_5122, _out_uop_T_5117) wire _out_uop_WIRE_426 : UInt<1> connect _out_uop_WIRE_426, _out_uop_T_5123 connect _out_uop_WIRE_412.ren2, _out_uop_WIRE_426 node _out_uop_T_5124 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5125 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5126 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5127 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5128 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5129 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5130 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _out_uop_T_5131 = or(_out_uop_T_5124, _out_uop_T_5125) node _out_uop_T_5132 = or(_out_uop_T_5131, _out_uop_T_5126) node _out_uop_T_5133 = or(_out_uop_T_5132, _out_uop_T_5127) node _out_uop_T_5134 = or(_out_uop_T_5133, _out_uop_T_5128) node _out_uop_T_5135 = or(_out_uop_T_5134, _out_uop_T_5129) node _out_uop_T_5136 = or(_out_uop_T_5135, _out_uop_T_5130) wire _out_uop_WIRE_427 : UInt<1> connect _out_uop_WIRE_427, _out_uop_T_5136 connect _out_uop_WIRE_412.ren1, _out_uop_WIRE_427 node _out_uop_T_5137 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5138 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5139 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5140 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5141 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5142 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5143 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.wen, UInt<1>(0h0)) node _out_uop_T_5144 = or(_out_uop_T_5137, _out_uop_T_5138) node _out_uop_T_5145 = or(_out_uop_T_5144, _out_uop_T_5139) node _out_uop_T_5146 = or(_out_uop_T_5145, _out_uop_T_5140) node _out_uop_T_5147 = or(_out_uop_T_5146, _out_uop_T_5141) node _out_uop_T_5148 = or(_out_uop_T_5147, _out_uop_T_5142) node _out_uop_T_5149 = or(_out_uop_T_5148, _out_uop_T_5143) wire _out_uop_WIRE_428 : UInt<1> connect _out_uop_WIRE_428, _out_uop_T_5149 connect _out_uop_WIRE_412.wen, _out_uop_WIRE_428 node _out_uop_T_5150 = mux(_out_uop_T_4194, ram[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5151 = mux(_out_uop_T_4195, ram[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5152 = mux(_out_uop_T_4196, ram[2].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5153 = mux(_out_uop_T_4197, ram[3].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5154 = mux(_out_uop_T_4198, ram[4].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5155 = mux(_out_uop_T_4199, ram[5].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5156 = mux(_out_uop_T_4200, ram[6].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _out_uop_T_5157 = or(_out_uop_T_5150, _out_uop_T_5151) node _out_uop_T_5158 = or(_out_uop_T_5157, _out_uop_T_5152) node _out_uop_T_5159 = or(_out_uop_T_5158, _out_uop_T_5153) node _out_uop_T_5160 = or(_out_uop_T_5159, _out_uop_T_5154) node _out_uop_T_5161 = or(_out_uop_T_5160, _out_uop_T_5155) node _out_uop_T_5162 = or(_out_uop_T_5161, _out_uop_T_5156) wire _out_uop_WIRE_429 : UInt<1> connect _out_uop_WIRE_429, _out_uop_T_5162 connect _out_uop_WIRE_412.ldst, _out_uop_WIRE_429 connect _out_uop_WIRE_348.fp_ctrl, _out_uop_WIRE_412 wire _out_uop_WIRE_430 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _out_uop_T_5163 = mux(_out_uop_T_4194, ram[0].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5164 = mux(_out_uop_T_4195, ram[1].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5165 = mux(_out_uop_T_4196, ram[2].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5166 = mux(_out_uop_T_4197, ram[3].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5167 = mux(_out_uop_T_4198, ram[4].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5168 = mux(_out_uop_T_4199, ram[5].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5169 = mux(_out_uop_T_4200, ram[6].bits.ctrl.vec, UInt<1>(0h0)) node _out_uop_T_5170 = or(_out_uop_T_5163, _out_uop_T_5164) node _out_uop_T_5171 = or(_out_uop_T_5170, _out_uop_T_5165) node _out_uop_T_5172 = or(_out_uop_T_5171, _out_uop_T_5166) node _out_uop_T_5173 = or(_out_uop_T_5172, _out_uop_T_5167) node _out_uop_T_5174 = or(_out_uop_T_5173, _out_uop_T_5168) node _out_uop_T_5175 = or(_out_uop_T_5174, _out_uop_T_5169) wire _out_uop_WIRE_431 : UInt<1> connect _out_uop_WIRE_431, _out_uop_T_5175 connect _out_uop_WIRE_430.vec, _out_uop_WIRE_431 node _out_uop_T_5176 = mux(_out_uop_T_4194, ram[0].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5177 = mux(_out_uop_T_4195, ram[1].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5178 = mux(_out_uop_T_4196, ram[2].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5179 = mux(_out_uop_T_4197, ram[3].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5180 = mux(_out_uop_T_4198, ram[4].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5181 = mux(_out_uop_T_4199, ram[5].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5182 = mux(_out_uop_T_4200, ram[6].bits.ctrl.dp, UInt<1>(0h0)) node _out_uop_T_5183 = or(_out_uop_T_5176, _out_uop_T_5177) node _out_uop_T_5184 = or(_out_uop_T_5183, _out_uop_T_5178) node _out_uop_T_5185 = or(_out_uop_T_5184, _out_uop_T_5179) node _out_uop_T_5186 = or(_out_uop_T_5185, _out_uop_T_5180) node _out_uop_T_5187 = or(_out_uop_T_5186, _out_uop_T_5181) node _out_uop_T_5188 = or(_out_uop_T_5187, _out_uop_T_5182) wire _out_uop_WIRE_432 : UInt<1> connect _out_uop_WIRE_432, _out_uop_T_5188 connect _out_uop_WIRE_430.dp, _out_uop_WIRE_432 node _out_uop_T_5189 = mux(_out_uop_T_4194, ram[0].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5190 = mux(_out_uop_T_4195, ram[1].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5191 = mux(_out_uop_T_4196, ram[2].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5192 = mux(_out_uop_T_4197, ram[3].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5193 = mux(_out_uop_T_4198, ram[4].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5194 = mux(_out_uop_T_4199, ram[5].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5195 = mux(_out_uop_T_4200, ram[6].bits.ctrl.amo, UInt<1>(0h0)) node _out_uop_T_5196 = or(_out_uop_T_5189, _out_uop_T_5190) node _out_uop_T_5197 = or(_out_uop_T_5196, _out_uop_T_5191) node _out_uop_T_5198 = or(_out_uop_T_5197, _out_uop_T_5192) node _out_uop_T_5199 = or(_out_uop_T_5198, _out_uop_T_5193) node _out_uop_T_5200 = or(_out_uop_T_5199, _out_uop_T_5194) node _out_uop_T_5201 = or(_out_uop_T_5200, _out_uop_T_5195) wire _out_uop_WIRE_433 : UInt<1> connect _out_uop_WIRE_433, _out_uop_T_5201 connect _out_uop_WIRE_430.amo, _out_uop_WIRE_433 node _out_uop_T_5202 = mux(_out_uop_T_4194, ram[0].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5203 = mux(_out_uop_T_4195, ram[1].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5204 = mux(_out_uop_T_4196, ram[2].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5205 = mux(_out_uop_T_4197, ram[3].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5206 = mux(_out_uop_T_4198, ram[4].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5207 = mux(_out_uop_T_4199, ram[5].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5208 = mux(_out_uop_T_4200, ram[6].bits.ctrl.fence, UInt<1>(0h0)) node _out_uop_T_5209 = or(_out_uop_T_5202, _out_uop_T_5203) node _out_uop_T_5210 = or(_out_uop_T_5209, _out_uop_T_5204) node _out_uop_T_5211 = or(_out_uop_T_5210, _out_uop_T_5205) node _out_uop_T_5212 = or(_out_uop_T_5211, _out_uop_T_5206) node _out_uop_T_5213 = or(_out_uop_T_5212, _out_uop_T_5207) node _out_uop_T_5214 = or(_out_uop_T_5213, _out_uop_T_5208) wire _out_uop_WIRE_434 : UInt<1> connect _out_uop_WIRE_434, _out_uop_T_5214 connect _out_uop_WIRE_430.fence, _out_uop_WIRE_434 node _out_uop_T_5215 = mux(_out_uop_T_4194, ram[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5216 = mux(_out_uop_T_4195, ram[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5217 = mux(_out_uop_T_4196, ram[2].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5218 = mux(_out_uop_T_4197, ram[3].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5219 = mux(_out_uop_T_4198, ram[4].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5220 = mux(_out_uop_T_4199, ram[5].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5221 = mux(_out_uop_T_4200, ram[6].bits.ctrl.fence_i, UInt<1>(0h0)) node _out_uop_T_5222 = or(_out_uop_T_5215, _out_uop_T_5216) node _out_uop_T_5223 = or(_out_uop_T_5222, _out_uop_T_5217) node _out_uop_T_5224 = or(_out_uop_T_5223, _out_uop_T_5218) node _out_uop_T_5225 = or(_out_uop_T_5224, _out_uop_T_5219) node _out_uop_T_5226 = or(_out_uop_T_5225, _out_uop_T_5220) node _out_uop_T_5227 = or(_out_uop_T_5226, _out_uop_T_5221) wire _out_uop_WIRE_435 : UInt<1> connect _out_uop_WIRE_435, _out_uop_T_5227 connect _out_uop_WIRE_430.fence_i, _out_uop_WIRE_435 node _out_uop_T_5228 = mux(_out_uop_T_4194, ram[0].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5229 = mux(_out_uop_T_4195, ram[1].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5230 = mux(_out_uop_T_4196, ram[2].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5231 = mux(_out_uop_T_4197, ram[3].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5232 = mux(_out_uop_T_4198, ram[4].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5233 = mux(_out_uop_T_4199, ram[5].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5234 = mux(_out_uop_T_4200, ram[6].bits.ctrl.csr, UInt<1>(0h0)) node _out_uop_T_5235 = or(_out_uop_T_5228, _out_uop_T_5229) node _out_uop_T_5236 = or(_out_uop_T_5235, _out_uop_T_5230) node _out_uop_T_5237 = or(_out_uop_T_5236, _out_uop_T_5231) node _out_uop_T_5238 = or(_out_uop_T_5237, _out_uop_T_5232) node _out_uop_T_5239 = or(_out_uop_T_5238, _out_uop_T_5233) node _out_uop_T_5240 = or(_out_uop_T_5239, _out_uop_T_5234) wire _out_uop_WIRE_436 : UInt<3> connect _out_uop_WIRE_436, _out_uop_T_5240 connect _out_uop_WIRE_430.csr, _out_uop_WIRE_436 node _out_uop_T_5241 = mux(_out_uop_T_4194, ram[0].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5242 = mux(_out_uop_T_4195, ram[1].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5243 = mux(_out_uop_T_4196, ram[2].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5244 = mux(_out_uop_T_4197, ram[3].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5245 = mux(_out_uop_T_4198, ram[4].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5246 = mux(_out_uop_T_4199, ram[5].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5247 = mux(_out_uop_T_4200, ram[6].bits.ctrl.wxd, UInt<1>(0h0)) node _out_uop_T_5248 = or(_out_uop_T_5241, _out_uop_T_5242) node _out_uop_T_5249 = or(_out_uop_T_5248, _out_uop_T_5243) node _out_uop_T_5250 = or(_out_uop_T_5249, _out_uop_T_5244) node _out_uop_T_5251 = or(_out_uop_T_5250, _out_uop_T_5245) node _out_uop_T_5252 = or(_out_uop_T_5251, _out_uop_T_5246) node _out_uop_T_5253 = or(_out_uop_T_5252, _out_uop_T_5247) wire _out_uop_WIRE_437 : UInt<1> connect _out_uop_WIRE_437, _out_uop_T_5253 connect _out_uop_WIRE_430.wxd, _out_uop_WIRE_437 node _out_uop_T_5254 = mux(_out_uop_T_4194, ram[0].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5255 = mux(_out_uop_T_4195, ram[1].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5256 = mux(_out_uop_T_4196, ram[2].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5257 = mux(_out_uop_T_4197, ram[3].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5258 = mux(_out_uop_T_4198, ram[4].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5259 = mux(_out_uop_T_4199, ram[5].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5260 = mux(_out_uop_T_4200, ram[6].bits.ctrl.div, UInt<1>(0h0)) node _out_uop_T_5261 = or(_out_uop_T_5254, _out_uop_T_5255) node _out_uop_T_5262 = or(_out_uop_T_5261, _out_uop_T_5256) node _out_uop_T_5263 = or(_out_uop_T_5262, _out_uop_T_5257) node _out_uop_T_5264 = or(_out_uop_T_5263, _out_uop_T_5258) node _out_uop_T_5265 = or(_out_uop_T_5264, _out_uop_T_5259) node _out_uop_T_5266 = or(_out_uop_T_5265, _out_uop_T_5260) wire _out_uop_WIRE_438 : UInt<1> connect _out_uop_WIRE_438, _out_uop_T_5266 connect _out_uop_WIRE_430.div, _out_uop_WIRE_438 node _out_uop_T_5267 = mux(_out_uop_T_4194, ram[0].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5268 = mux(_out_uop_T_4195, ram[1].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5269 = mux(_out_uop_T_4196, ram[2].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5270 = mux(_out_uop_T_4197, ram[3].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5271 = mux(_out_uop_T_4198, ram[4].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5272 = mux(_out_uop_T_4199, ram[5].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5273 = mux(_out_uop_T_4200, ram[6].bits.ctrl.mul, UInt<1>(0h0)) node _out_uop_T_5274 = or(_out_uop_T_5267, _out_uop_T_5268) node _out_uop_T_5275 = or(_out_uop_T_5274, _out_uop_T_5269) node _out_uop_T_5276 = or(_out_uop_T_5275, _out_uop_T_5270) node _out_uop_T_5277 = or(_out_uop_T_5276, _out_uop_T_5271) node _out_uop_T_5278 = or(_out_uop_T_5277, _out_uop_T_5272) node _out_uop_T_5279 = or(_out_uop_T_5278, _out_uop_T_5273) wire _out_uop_WIRE_439 : UInt<1> connect _out_uop_WIRE_439, _out_uop_T_5279 connect _out_uop_WIRE_430.mul, _out_uop_WIRE_439 node _out_uop_T_5280 = mux(_out_uop_T_4194, ram[0].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5281 = mux(_out_uop_T_4195, ram[1].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5282 = mux(_out_uop_T_4196, ram[2].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5283 = mux(_out_uop_T_4197, ram[3].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5284 = mux(_out_uop_T_4198, ram[4].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5285 = mux(_out_uop_T_4199, ram[5].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5286 = mux(_out_uop_T_4200, ram[6].bits.ctrl.wfd, UInt<1>(0h0)) node _out_uop_T_5287 = or(_out_uop_T_5280, _out_uop_T_5281) node _out_uop_T_5288 = or(_out_uop_T_5287, _out_uop_T_5282) node _out_uop_T_5289 = or(_out_uop_T_5288, _out_uop_T_5283) node _out_uop_T_5290 = or(_out_uop_T_5289, _out_uop_T_5284) node _out_uop_T_5291 = or(_out_uop_T_5290, _out_uop_T_5285) node _out_uop_T_5292 = or(_out_uop_T_5291, _out_uop_T_5286) wire _out_uop_WIRE_440 : UInt<1> connect _out_uop_WIRE_440, _out_uop_T_5292 connect _out_uop_WIRE_430.wfd, _out_uop_WIRE_440 node _out_uop_T_5293 = mux(_out_uop_T_4194, ram[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5294 = mux(_out_uop_T_4195, ram[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5295 = mux(_out_uop_T_4196, ram[2].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5296 = mux(_out_uop_T_4197, ram[3].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5297 = mux(_out_uop_T_4198, ram[4].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5298 = mux(_out_uop_T_4199, ram[5].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5299 = mux(_out_uop_T_4200, ram[6].bits.ctrl.rfs3, UInt<1>(0h0)) node _out_uop_T_5300 = or(_out_uop_T_5293, _out_uop_T_5294) node _out_uop_T_5301 = or(_out_uop_T_5300, _out_uop_T_5295) node _out_uop_T_5302 = or(_out_uop_T_5301, _out_uop_T_5296) node _out_uop_T_5303 = or(_out_uop_T_5302, _out_uop_T_5297) node _out_uop_T_5304 = or(_out_uop_T_5303, _out_uop_T_5298) node _out_uop_T_5305 = or(_out_uop_T_5304, _out_uop_T_5299) wire _out_uop_WIRE_441 : UInt<1> connect _out_uop_WIRE_441, _out_uop_T_5305 connect _out_uop_WIRE_430.rfs3, _out_uop_WIRE_441 node _out_uop_T_5306 = mux(_out_uop_T_4194, ram[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5307 = mux(_out_uop_T_4195, ram[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5308 = mux(_out_uop_T_4196, ram[2].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5309 = mux(_out_uop_T_4197, ram[3].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5310 = mux(_out_uop_T_4198, ram[4].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5311 = mux(_out_uop_T_4199, ram[5].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5312 = mux(_out_uop_T_4200, ram[6].bits.ctrl.rfs2, UInt<1>(0h0)) node _out_uop_T_5313 = or(_out_uop_T_5306, _out_uop_T_5307) node _out_uop_T_5314 = or(_out_uop_T_5313, _out_uop_T_5308) node _out_uop_T_5315 = or(_out_uop_T_5314, _out_uop_T_5309) node _out_uop_T_5316 = or(_out_uop_T_5315, _out_uop_T_5310) node _out_uop_T_5317 = or(_out_uop_T_5316, _out_uop_T_5311) node _out_uop_T_5318 = or(_out_uop_T_5317, _out_uop_T_5312) wire _out_uop_WIRE_442 : UInt<1> connect _out_uop_WIRE_442, _out_uop_T_5318 connect _out_uop_WIRE_430.rfs2, _out_uop_WIRE_442 node _out_uop_T_5319 = mux(_out_uop_T_4194, ram[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5320 = mux(_out_uop_T_4195, ram[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5321 = mux(_out_uop_T_4196, ram[2].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5322 = mux(_out_uop_T_4197, ram[3].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5323 = mux(_out_uop_T_4198, ram[4].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5324 = mux(_out_uop_T_4199, ram[5].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5325 = mux(_out_uop_T_4200, ram[6].bits.ctrl.rfs1, UInt<1>(0h0)) node _out_uop_T_5326 = or(_out_uop_T_5319, _out_uop_T_5320) node _out_uop_T_5327 = or(_out_uop_T_5326, _out_uop_T_5321) node _out_uop_T_5328 = or(_out_uop_T_5327, _out_uop_T_5322) node _out_uop_T_5329 = or(_out_uop_T_5328, _out_uop_T_5323) node _out_uop_T_5330 = or(_out_uop_T_5329, _out_uop_T_5324) node _out_uop_T_5331 = or(_out_uop_T_5330, _out_uop_T_5325) wire _out_uop_WIRE_443 : UInt<1> connect _out_uop_WIRE_443, _out_uop_T_5331 connect _out_uop_WIRE_430.rfs1, _out_uop_WIRE_443 node _out_uop_T_5332 = mux(_out_uop_T_4194, ram[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5333 = mux(_out_uop_T_4195, ram[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5334 = mux(_out_uop_T_4196, ram[2].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5335 = mux(_out_uop_T_4197, ram[3].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5336 = mux(_out_uop_T_4198, ram[4].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5337 = mux(_out_uop_T_4199, ram[5].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5338 = mux(_out_uop_T_4200, ram[6].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _out_uop_T_5339 = or(_out_uop_T_5332, _out_uop_T_5333) node _out_uop_T_5340 = or(_out_uop_T_5339, _out_uop_T_5334) node _out_uop_T_5341 = or(_out_uop_T_5340, _out_uop_T_5335) node _out_uop_T_5342 = or(_out_uop_T_5341, _out_uop_T_5336) node _out_uop_T_5343 = or(_out_uop_T_5342, _out_uop_T_5337) node _out_uop_T_5344 = or(_out_uop_T_5343, _out_uop_T_5338) wire _out_uop_WIRE_444 : UInt<5> connect _out_uop_WIRE_444, _out_uop_T_5344 connect _out_uop_WIRE_430.mem_cmd, _out_uop_WIRE_444 node _out_uop_T_5345 = mux(_out_uop_T_4194, ram[0].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5346 = mux(_out_uop_T_4195, ram[1].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5347 = mux(_out_uop_T_4196, ram[2].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5348 = mux(_out_uop_T_4197, ram[3].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5349 = mux(_out_uop_T_4198, ram[4].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5350 = mux(_out_uop_T_4199, ram[5].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5351 = mux(_out_uop_T_4200, ram[6].bits.ctrl.mem, UInt<1>(0h0)) node _out_uop_T_5352 = or(_out_uop_T_5345, _out_uop_T_5346) node _out_uop_T_5353 = or(_out_uop_T_5352, _out_uop_T_5347) node _out_uop_T_5354 = or(_out_uop_T_5353, _out_uop_T_5348) node _out_uop_T_5355 = or(_out_uop_T_5354, _out_uop_T_5349) node _out_uop_T_5356 = or(_out_uop_T_5355, _out_uop_T_5350) node _out_uop_T_5357 = or(_out_uop_T_5356, _out_uop_T_5351) wire _out_uop_WIRE_445 : UInt<1> connect _out_uop_WIRE_445, _out_uop_T_5357 connect _out_uop_WIRE_430.mem, _out_uop_WIRE_445 node _out_uop_T_5358 = mux(_out_uop_T_4194, ram[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5359 = mux(_out_uop_T_4195, ram[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5360 = mux(_out_uop_T_4196, ram[2].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5361 = mux(_out_uop_T_4197, ram[3].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5362 = mux(_out_uop_T_4198, ram[4].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5363 = mux(_out_uop_T_4199, ram[5].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5364 = mux(_out_uop_T_4200, ram[6].bits.ctrl.alu_fn, UInt<1>(0h0)) node _out_uop_T_5365 = or(_out_uop_T_5358, _out_uop_T_5359) node _out_uop_T_5366 = or(_out_uop_T_5365, _out_uop_T_5360) node _out_uop_T_5367 = or(_out_uop_T_5366, _out_uop_T_5361) node _out_uop_T_5368 = or(_out_uop_T_5367, _out_uop_T_5362) node _out_uop_T_5369 = or(_out_uop_T_5368, _out_uop_T_5363) node _out_uop_T_5370 = or(_out_uop_T_5369, _out_uop_T_5364) wire _out_uop_WIRE_446 : UInt<5> connect _out_uop_WIRE_446, _out_uop_T_5370 connect _out_uop_WIRE_430.alu_fn, _out_uop_WIRE_446 node _out_uop_T_5371 = mux(_out_uop_T_4194, ram[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5372 = mux(_out_uop_T_4195, ram[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5373 = mux(_out_uop_T_4196, ram[2].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5374 = mux(_out_uop_T_4197, ram[3].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5375 = mux(_out_uop_T_4198, ram[4].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5376 = mux(_out_uop_T_4199, ram[5].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5377 = mux(_out_uop_T_4200, ram[6].bits.ctrl.alu_dw, UInt<1>(0h0)) node _out_uop_T_5378 = or(_out_uop_T_5371, _out_uop_T_5372) node _out_uop_T_5379 = or(_out_uop_T_5378, _out_uop_T_5373) node _out_uop_T_5380 = or(_out_uop_T_5379, _out_uop_T_5374) node _out_uop_T_5381 = or(_out_uop_T_5380, _out_uop_T_5375) node _out_uop_T_5382 = or(_out_uop_T_5381, _out_uop_T_5376) node _out_uop_T_5383 = or(_out_uop_T_5382, _out_uop_T_5377) wire _out_uop_WIRE_447 : UInt<1> connect _out_uop_WIRE_447, _out_uop_T_5383 connect _out_uop_WIRE_430.alu_dw, _out_uop_WIRE_447 node _out_uop_T_5384 = mux(_out_uop_T_4194, ram[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5385 = mux(_out_uop_T_4195, ram[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5386 = mux(_out_uop_T_4196, ram[2].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5387 = mux(_out_uop_T_4197, ram[3].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5388 = mux(_out_uop_T_4198, ram[4].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5389 = mux(_out_uop_T_4199, ram[5].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5390 = mux(_out_uop_T_4200, ram[6].bits.ctrl.sel_imm, UInt<1>(0h0)) node _out_uop_T_5391 = or(_out_uop_T_5384, _out_uop_T_5385) node _out_uop_T_5392 = or(_out_uop_T_5391, _out_uop_T_5386) node _out_uop_T_5393 = or(_out_uop_T_5392, _out_uop_T_5387) node _out_uop_T_5394 = or(_out_uop_T_5393, _out_uop_T_5388) node _out_uop_T_5395 = or(_out_uop_T_5394, _out_uop_T_5389) node _out_uop_T_5396 = or(_out_uop_T_5395, _out_uop_T_5390) wire _out_uop_WIRE_448 : UInt<3> connect _out_uop_WIRE_448, _out_uop_T_5396 connect _out_uop_WIRE_430.sel_imm, _out_uop_WIRE_448 node _out_uop_T_5397 = mux(_out_uop_T_4194, ram[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5398 = mux(_out_uop_T_4195, ram[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5399 = mux(_out_uop_T_4196, ram[2].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5400 = mux(_out_uop_T_4197, ram[3].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5401 = mux(_out_uop_T_4198, ram[4].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5402 = mux(_out_uop_T_4199, ram[5].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5403 = mux(_out_uop_T_4200, ram[6].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _out_uop_T_5404 = or(_out_uop_T_5397, _out_uop_T_5398) node _out_uop_T_5405 = or(_out_uop_T_5404, _out_uop_T_5399) node _out_uop_T_5406 = or(_out_uop_T_5405, _out_uop_T_5400) node _out_uop_T_5407 = or(_out_uop_T_5406, _out_uop_T_5401) node _out_uop_T_5408 = or(_out_uop_T_5407, _out_uop_T_5402) node _out_uop_T_5409 = or(_out_uop_T_5408, _out_uop_T_5403) wire _out_uop_WIRE_449 : UInt<2> connect _out_uop_WIRE_449, _out_uop_T_5409 connect _out_uop_WIRE_430.sel_alu1, _out_uop_WIRE_449 node _out_uop_T_5410 = mux(_out_uop_T_4194, ram[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5411 = mux(_out_uop_T_4195, ram[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5412 = mux(_out_uop_T_4196, ram[2].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5413 = mux(_out_uop_T_4197, ram[3].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5414 = mux(_out_uop_T_4198, ram[4].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5415 = mux(_out_uop_T_4199, ram[5].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5416 = mux(_out_uop_T_4200, ram[6].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _out_uop_T_5417 = or(_out_uop_T_5410, _out_uop_T_5411) node _out_uop_T_5418 = or(_out_uop_T_5417, _out_uop_T_5412) node _out_uop_T_5419 = or(_out_uop_T_5418, _out_uop_T_5413) node _out_uop_T_5420 = or(_out_uop_T_5419, _out_uop_T_5414) node _out_uop_T_5421 = or(_out_uop_T_5420, _out_uop_T_5415) node _out_uop_T_5422 = or(_out_uop_T_5421, _out_uop_T_5416) wire _out_uop_WIRE_450 : UInt<3> connect _out_uop_WIRE_450, _out_uop_T_5422 connect _out_uop_WIRE_430.sel_alu2, _out_uop_WIRE_450 node _out_uop_T_5423 = mux(_out_uop_T_4194, ram[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5424 = mux(_out_uop_T_4195, ram[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5425 = mux(_out_uop_T_4196, ram[2].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5426 = mux(_out_uop_T_4197, ram[3].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5427 = mux(_out_uop_T_4198, ram[4].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5428 = mux(_out_uop_T_4199, ram[5].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5429 = mux(_out_uop_T_4200, ram[6].bits.ctrl.rxs1, UInt<1>(0h0)) node _out_uop_T_5430 = or(_out_uop_T_5423, _out_uop_T_5424) node _out_uop_T_5431 = or(_out_uop_T_5430, _out_uop_T_5425) node _out_uop_T_5432 = or(_out_uop_T_5431, _out_uop_T_5426) node _out_uop_T_5433 = or(_out_uop_T_5432, _out_uop_T_5427) node _out_uop_T_5434 = or(_out_uop_T_5433, _out_uop_T_5428) node _out_uop_T_5435 = or(_out_uop_T_5434, _out_uop_T_5429) wire _out_uop_WIRE_451 : UInt<1> connect _out_uop_WIRE_451, _out_uop_T_5435 connect _out_uop_WIRE_430.rxs1, _out_uop_WIRE_451 node _out_uop_T_5436 = mux(_out_uop_T_4194, ram[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5437 = mux(_out_uop_T_4195, ram[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5438 = mux(_out_uop_T_4196, ram[2].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5439 = mux(_out_uop_T_4197, ram[3].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5440 = mux(_out_uop_T_4198, ram[4].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5441 = mux(_out_uop_T_4199, ram[5].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5442 = mux(_out_uop_T_4200, ram[6].bits.ctrl.rxs2, UInt<1>(0h0)) node _out_uop_T_5443 = or(_out_uop_T_5436, _out_uop_T_5437) node _out_uop_T_5444 = or(_out_uop_T_5443, _out_uop_T_5438) node _out_uop_T_5445 = or(_out_uop_T_5444, _out_uop_T_5439) node _out_uop_T_5446 = or(_out_uop_T_5445, _out_uop_T_5440) node _out_uop_T_5447 = or(_out_uop_T_5446, _out_uop_T_5441) node _out_uop_T_5448 = or(_out_uop_T_5447, _out_uop_T_5442) wire _out_uop_WIRE_452 : UInt<1> connect _out_uop_WIRE_452, _out_uop_T_5448 connect _out_uop_WIRE_430.rxs2, _out_uop_WIRE_452 node _out_uop_T_5449 = mux(_out_uop_T_4194, ram[0].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5450 = mux(_out_uop_T_4195, ram[1].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5451 = mux(_out_uop_T_4196, ram[2].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5452 = mux(_out_uop_T_4197, ram[3].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5453 = mux(_out_uop_T_4198, ram[4].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5454 = mux(_out_uop_T_4199, ram[5].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5455 = mux(_out_uop_T_4200, ram[6].bits.ctrl.jalr, UInt<1>(0h0)) node _out_uop_T_5456 = or(_out_uop_T_5449, _out_uop_T_5450) node _out_uop_T_5457 = or(_out_uop_T_5456, _out_uop_T_5451) node _out_uop_T_5458 = or(_out_uop_T_5457, _out_uop_T_5452) node _out_uop_T_5459 = or(_out_uop_T_5458, _out_uop_T_5453) node _out_uop_T_5460 = or(_out_uop_T_5459, _out_uop_T_5454) node _out_uop_T_5461 = or(_out_uop_T_5460, _out_uop_T_5455) wire _out_uop_WIRE_453 : UInt<1> connect _out_uop_WIRE_453, _out_uop_T_5461 connect _out_uop_WIRE_430.jalr, _out_uop_WIRE_453 node _out_uop_T_5462 = mux(_out_uop_T_4194, ram[0].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5463 = mux(_out_uop_T_4195, ram[1].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5464 = mux(_out_uop_T_4196, ram[2].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5465 = mux(_out_uop_T_4197, ram[3].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5466 = mux(_out_uop_T_4198, ram[4].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5467 = mux(_out_uop_T_4199, ram[5].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5468 = mux(_out_uop_T_4200, ram[6].bits.ctrl.jal, UInt<1>(0h0)) node _out_uop_T_5469 = or(_out_uop_T_5462, _out_uop_T_5463) node _out_uop_T_5470 = or(_out_uop_T_5469, _out_uop_T_5464) node _out_uop_T_5471 = or(_out_uop_T_5470, _out_uop_T_5465) node _out_uop_T_5472 = or(_out_uop_T_5471, _out_uop_T_5466) node _out_uop_T_5473 = or(_out_uop_T_5472, _out_uop_T_5467) node _out_uop_T_5474 = or(_out_uop_T_5473, _out_uop_T_5468) wire _out_uop_WIRE_454 : UInt<1> connect _out_uop_WIRE_454, _out_uop_T_5474 connect _out_uop_WIRE_430.jal, _out_uop_WIRE_454 node _out_uop_T_5475 = mux(_out_uop_T_4194, ram[0].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5476 = mux(_out_uop_T_4195, ram[1].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5477 = mux(_out_uop_T_4196, ram[2].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5478 = mux(_out_uop_T_4197, ram[3].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5479 = mux(_out_uop_T_4198, ram[4].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5480 = mux(_out_uop_T_4199, ram[5].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5481 = mux(_out_uop_T_4200, ram[6].bits.ctrl.branch, UInt<1>(0h0)) node _out_uop_T_5482 = or(_out_uop_T_5475, _out_uop_T_5476) node _out_uop_T_5483 = or(_out_uop_T_5482, _out_uop_T_5477) node _out_uop_T_5484 = or(_out_uop_T_5483, _out_uop_T_5478) node _out_uop_T_5485 = or(_out_uop_T_5484, _out_uop_T_5479) node _out_uop_T_5486 = or(_out_uop_T_5485, _out_uop_T_5480) node _out_uop_T_5487 = or(_out_uop_T_5486, _out_uop_T_5481) wire _out_uop_WIRE_455 : UInt<1> connect _out_uop_WIRE_455, _out_uop_T_5487 connect _out_uop_WIRE_430.branch, _out_uop_WIRE_455 node _out_uop_T_5488 = mux(_out_uop_T_4194, ram[0].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5489 = mux(_out_uop_T_4195, ram[1].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5490 = mux(_out_uop_T_4196, ram[2].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5491 = mux(_out_uop_T_4197, ram[3].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5492 = mux(_out_uop_T_4198, ram[4].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5493 = mux(_out_uop_T_4199, ram[5].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5494 = mux(_out_uop_T_4200, ram[6].bits.ctrl.rocc, UInt<1>(0h0)) node _out_uop_T_5495 = or(_out_uop_T_5488, _out_uop_T_5489) node _out_uop_T_5496 = or(_out_uop_T_5495, _out_uop_T_5490) node _out_uop_T_5497 = or(_out_uop_T_5496, _out_uop_T_5491) node _out_uop_T_5498 = or(_out_uop_T_5497, _out_uop_T_5492) node _out_uop_T_5499 = or(_out_uop_T_5498, _out_uop_T_5493) node _out_uop_T_5500 = or(_out_uop_T_5499, _out_uop_T_5494) wire _out_uop_WIRE_456 : UInt<1> connect _out_uop_WIRE_456, _out_uop_T_5500 connect _out_uop_WIRE_430.rocc, _out_uop_WIRE_456 node _out_uop_T_5501 = mux(_out_uop_T_4194, ram[0].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5502 = mux(_out_uop_T_4195, ram[1].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5503 = mux(_out_uop_T_4196, ram[2].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5504 = mux(_out_uop_T_4197, ram[3].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5505 = mux(_out_uop_T_4198, ram[4].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5506 = mux(_out_uop_T_4199, ram[5].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5507 = mux(_out_uop_T_4200, ram[6].bits.ctrl.fp, UInt<1>(0h0)) node _out_uop_T_5508 = or(_out_uop_T_5501, _out_uop_T_5502) node _out_uop_T_5509 = or(_out_uop_T_5508, _out_uop_T_5503) node _out_uop_T_5510 = or(_out_uop_T_5509, _out_uop_T_5504) node _out_uop_T_5511 = or(_out_uop_T_5510, _out_uop_T_5505) node _out_uop_T_5512 = or(_out_uop_T_5511, _out_uop_T_5506) node _out_uop_T_5513 = or(_out_uop_T_5512, _out_uop_T_5507) wire _out_uop_WIRE_457 : UInt<1> connect _out_uop_WIRE_457, _out_uop_T_5513 connect _out_uop_WIRE_430.fp, _out_uop_WIRE_457 node _out_uop_T_5514 = mux(_out_uop_T_4194, ram[0].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5515 = mux(_out_uop_T_4195, ram[1].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5516 = mux(_out_uop_T_4196, ram[2].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5517 = mux(_out_uop_T_4197, ram[3].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5518 = mux(_out_uop_T_4198, ram[4].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5519 = mux(_out_uop_T_4199, ram[5].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5520 = mux(_out_uop_T_4200, ram[6].bits.ctrl.legal, UInt<1>(0h0)) node _out_uop_T_5521 = or(_out_uop_T_5514, _out_uop_T_5515) node _out_uop_T_5522 = or(_out_uop_T_5521, _out_uop_T_5516) node _out_uop_T_5523 = or(_out_uop_T_5522, _out_uop_T_5517) node _out_uop_T_5524 = or(_out_uop_T_5523, _out_uop_T_5518) node _out_uop_T_5525 = or(_out_uop_T_5524, _out_uop_T_5519) node _out_uop_T_5526 = or(_out_uop_T_5525, _out_uop_T_5520) wire _out_uop_WIRE_458 : UInt<1> connect _out_uop_WIRE_458, _out_uop_T_5526 connect _out_uop_WIRE_430.legal, _out_uop_WIRE_458 connect _out_uop_WIRE_348.ctrl, _out_uop_WIRE_430 node _out_uop_T_5527 = mux(_out_uop_T_4194, ram[0].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5528 = mux(_out_uop_T_4195, ram[1].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5529 = mux(_out_uop_T_4196, ram[2].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5530 = mux(_out_uop_T_4197, ram[3].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5531 = mux(_out_uop_T_4198, ram[4].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5532 = mux(_out_uop_T_4199, ram[5].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5533 = mux(_out_uop_T_4200, ram[6].bits.edge_inst, UInt<1>(0h0)) node _out_uop_T_5534 = or(_out_uop_T_5527, _out_uop_T_5528) node _out_uop_T_5535 = or(_out_uop_T_5534, _out_uop_T_5529) node _out_uop_T_5536 = or(_out_uop_T_5535, _out_uop_T_5530) node _out_uop_T_5537 = or(_out_uop_T_5536, _out_uop_T_5531) node _out_uop_T_5538 = or(_out_uop_T_5537, _out_uop_T_5532) node _out_uop_T_5539 = or(_out_uop_T_5538, _out_uop_T_5533) wire _out_uop_WIRE_459 : UInt<1> connect _out_uop_WIRE_459, _out_uop_T_5539 connect _out_uop_WIRE_348.edge_inst, _out_uop_WIRE_459 node _out_uop_T_5540 = mux(_out_uop_T_4194, ram[0].bits.pc, UInt<1>(0h0)) node _out_uop_T_5541 = mux(_out_uop_T_4195, ram[1].bits.pc, UInt<1>(0h0)) node _out_uop_T_5542 = mux(_out_uop_T_4196, ram[2].bits.pc, UInt<1>(0h0)) node _out_uop_T_5543 = mux(_out_uop_T_4197, ram[3].bits.pc, UInt<1>(0h0)) node _out_uop_T_5544 = mux(_out_uop_T_4198, ram[4].bits.pc, UInt<1>(0h0)) node _out_uop_T_5545 = mux(_out_uop_T_4199, ram[5].bits.pc, UInt<1>(0h0)) node _out_uop_T_5546 = mux(_out_uop_T_4200, ram[6].bits.pc, UInt<1>(0h0)) node _out_uop_T_5547 = or(_out_uop_T_5540, _out_uop_T_5541) node _out_uop_T_5548 = or(_out_uop_T_5547, _out_uop_T_5542) node _out_uop_T_5549 = or(_out_uop_T_5548, _out_uop_T_5543) node _out_uop_T_5550 = or(_out_uop_T_5549, _out_uop_T_5544) node _out_uop_T_5551 = or(_out_uop_T_5550, _out_uop_T_5545) node _out_uop_T_5552 = or(_out_uop_T_5551, _out_uop_T_5546) wire _out_uop_WIRE_460 : UInt<40> connect _out_uop_WIRE_460, _out_uop_T_5552 connect _out_uop_WIRE_348.pc, _out_uop_WIRE_460 node _out_uop_T_5553 = mux(_out_uop_T_4194, ram[0].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5554 = mux(_out_uop_T_4195, ram[1].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5555 = mux(_out_uop_T_4196, ram[2].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5556 = mux(_out_uop_T_4197, ram[3].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5557 = mux(_out_uop_T_4198, ram[4].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5558 = mux(_out_uop_T_4199, ram[5].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5559 = mux(_out_uop_T_4200, ram[6].bits.raw_inst, UInt<1>(0h0)) node _out_uop_T_5560 = or(_out_uop_T_5553, _out_uop_T_5554) node _out_uop_T_5561 = or(_out_uop_T_5560, _out_uop_T_5555) node _out_uop_T_5562 = or(_out_uop_T_5561, _out_uop_T_5556) node _out_uop_T_5563 = or(_out_uop_T_5562, _out_uop_T_5557) node _out_uop_T_5564 = or(_out_uop_T_5563, _out_uop_T_5558) node _out_uop_T_5565 = or(_out_uop_T_5564, _out_uop_T_5559) wire _out_uop_WIRE_461 : UInt<32> connect _out_uop_WIRE_461, _out_uop_T_5565 connect _out_uop_WIRE_348.raw_inst, _out_uop_WIRE_461 node _out_uop_T_5566 = mux(_out_uop_T_4194, ram[0].bits.inst, UInt<1>(0h0)) node _out_uop_T_5567 = mux(_out_uop_T_4195, ram[1].bits.inst, UInt<1>(0h0)) node _out_uop_T_5568 = mux(_out_uop_T_4196, ram[2].bits.inst, UInt<1>(0h0)) node _out_uop_T_5569 = mux(_out_uop_T_4197, ram[3].bits.inst, UInt<1>(0h0)) node _out_uop_T_5570 = mux(_out_uop_T_4198, ram[4].bits.inst, UInt<1>(0h0)) node _out_uop_T_5571 = mux(_out_uop_T_4199, ram[5].bits.inst, UInt<1>(0h0)) node _out_uop_T_5572 = mux(_out_uop_T_4200, ram[6].bits.inst, UInt<1>(0h0)) node _out_uop_T_5573 = or(_out_uop_T_5566, _out_uop_T_5567) node _out_uop_T_5574 = or(_out_uop_T_5573, _out_uop_T_5568) node _out_uop_T_5575 = or(_out_uop_T_5574, _out_uop_T_5569) node _out_uop_T_5576 = or(_out_uop_T_5575, _out_uop_T_5570) node _out_uop_T_5577 = or(_out_uop_T_5576, _out_uop_T_5571) node _out_uop_T_5578 = or(_out_uop_T_5577, _out_uop_T_5572) wire _out_uop_WIRE_462 : UInt<32> connect _out_uop_WIRE_462, _out_uop_T_5578 connect _out_uop_WIRE_348.inst, _out_uop_WIRE_462 connect out_uop_3.bits, _out_uop_WIRE_348 node _out_uop_T_5579 = mux(_out_uop_T_4194, ram[0].valid, UInt<1>(0h0)) node _out_uop_T_5580 = mux(_out_uop_T_4195, ram[1].valid, UInt<1>(0h0)) node _out_uop_T_5581 = mux(_out_uop_T_4196, ram[2].valid, UInt<1>(0h0)) node _out_uop_T_5582 = mux(_out_uop_T_4197, ram[3].valid, UInt<1>(0h0)) node _out_uop_T_5583 = mux(_out_uop_T_4198, ram[4].valid, UInt<1>(0h0)) node _out_uop_T_5584 = mux(_out_uop_T_4199, ram[5].valid, UInt<1>(0h0)) node _out_uop_T_5585 = mux(_out_uop_T_4200, ram[6].valid, UInt<1>(0h0)) node _out_uop_T_5586 = or(_out_uop_T_5579, _out_uop_T_5580) node _out_uop_T_5587 = or(_out_uop_T_5586, _out_uop_T_5581) node _out_uop_T_5588 = or(_out_uop_T_5587, _out_uop_T_5582) node _out_uop_T_5589 = or(_out_uop_T_5588, _out_uop_T_5583) node _out_uop_T_5590 = or(_out_uop_T_5589, _out_uop_T_5584) node _out_uop_T_5591 = or(_out_uop_T_5590, _out_uop_T_5585) wire _out_uop_WIRE_463 : UInt<1> connect _out_uop_WIRE_463, _out_uop_T_5591 connect out_uop_3.valid, _out_uop_WIRE_463 connect io.peek[1].valid, out_uop_3.valid connect io.peek[1].bits, out_uop_3.bits node _T_46 = shl(_T_45, 1) node _T_47 = bits(_T_45, 6, 6) node _T_48 = or(_T_46, _T_47) node _T_49 = bits(_T_48, 6, 0) node _T_50 = bits(_T_37, 0, 0) when _T_50 : connect ram[0].valid, UInt<1>(0h0) node _T_51 = bits(_T_37, 1, 1) when _T_51 : connect ram[1].valid, UInt<1>(0h0) node _T_52 = bits(_T_37, 2, 2) when _T_52 : connect ram[2].valid, UInt<1>(0h0) node _T_53 = bits(_T_37, 3, 3) when _T_53 : connect ram[3].valid, UInt<1>(0h0) node _T_54 = bits(_T_37, 4, 4) when _T_54 : connect ram[4].valid, UInt<1>(0h0) node _T_55 = bits(_T_37, 5, 5) when _T_55 : connect ram[5].valid, UInt<1>(0h0) node _T_56 = bits(_T_37, 6, 6) when _T_56 : connect ram[6].valid, UInt<1>(0h0) node _deq_ptr_T = and(io.deq[0].ready, io.deq[0].valid) node _deq_ptr_T_1 = and(io.deq[1].ready, io.deq[1].valid) node _deq_ptr_T_2 = add(_deq_ptr_T, _deq_ptr_T_1) node _deq_ptr_T_3 = bits(_deq_ptr_T_2, 1, 0) wire deq_ptr_full : UInt<14> node _deq_ptr_full_T = dshl(deq_ptr, _deq_ptr_T_3) connect deq_ptr_full, _deq_ptr_full_T node _deq_ptr_T_4 = bits(deq_ptr_full, 6, 0) node _deq_ptr_T_5 = shr(deq_ptr_full, 7) node _deq_ptr_T_6 = or(_deq_ptr_T_4, _deq_ptr_T_5) node _deq_ptr_T_7 = bits(_deq_ptr_T_6, 6, 0) connect deq_ptr, _deq_ptr_T_7 when io.deq[1].ready : node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(io.deq[0].ready, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at FetchBuffer.scala:120 assert(io.deq.take(i).map(_.ready).reduce(_&&_))\n") : printf assert(clock, io.deq[0].ready, UInt<1>(0h1), "") : assert when io.clear : connect enq_ptr, UInt<1>(0h1) connect deq_ptr, UInt<1>(0h1) connect ram[0].valid, UInt<1>(0h0) connect ram[1].valid, UInt<1>(0h0) connect ram[2].valid, UInt<1>(0h0) connect ram[3].valid, UInt<1>(0h0) connect ram[4].valid, UInt<1>(0h0) connect ram[5].valid, UInt<1>(0h0) connect ram[6].valid, UInt<1>(0h0)
module ShuttleFetchBuffer( // @[FetchBuffer.scala:16:7] input clock, // @[FetchBuffer.scala:16:7] input reset, // @[FetchBuffer.scala:16:7] output io_enq_ready, // @[FetchBuffer.scala:21:14] input io_enq_valid, // @[FetchBuffer.scala:21:14] input [39:0] io_enq_bits_pc, // @[FetchBuffer.scala:21:14] input io_enq_bits_next_pc_valid, // @[FetchBuffer.scala:21:14] input [39:0] io_enq_bits_next_pc_bits, // @[FetchBuffer.scala:21:14] input io_enq_bits_edge_inst, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_insts_0, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_insts_1, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_insts_2, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_insts_3, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_exp_insts_0, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_exp_insts_1, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_exp_insts_2, // @[FetchBuffer.scala:21:14] input [31:0] io_enq_bits_exp_insts_3, // @[FetchBuffer.scala:21:14] input [39:0] io_enq_bits_pcs_0, // @[FetchBuffer.scala:21:14] input [39:0] io_enq_bits_pcs_1, // @[FetchBuffer.scala:21:14] input [39:0] io_enq_bits_pcs_2, // @[FetchBuffer.scala:21:14] input [39:0] io_enq_bits_pcs_3, // @[FetchBuffer.scala:21:14] input [3:0] io_enq_bits_mask, // @[FetchBuffer.scala:21:14] input io_enq_bits_btb_resp_valid, // @[FetchBuffer.scala:21:14] input [1:0] io_enq_bits_btb_resp_bits_cfiType, // @[FetchBuffer.scala:21:14] input io_enq_bits_btb_resp_bits_taken, // @[FetchBuffer.scala:21:14] input [3:0] io_enq_bits_btb_resp_bits_mask, // @[FetchBuffer.scala:21:14] input [1:0] io_enq_bits_btb_resp_bits_bridx, // @[FetchBuffer.scala:21:14] input [38:0] io_enq_bits_btb_resp_bits_target, // @[FetchBuffer.scala:21:14] input [5:0] io_enq_bits_btb_resp_bits_entry, // @[FetchBuffer.scala:21:14] input [7:0] io_enq_bits_btb_resp_bits_bht_history, // @[FetchBuffer.scala:21:14] input [1:0] io_enq_bits_btb_resp_bits_bht_value, // @[FetchBuffer.scala:21:14] input [2:0] io_enq_bits_ras_head, // @[FetchBuffer.scala:21:14] input io_enq_bits_xcpt_pf_if, // @[FetchBuffer.scala:21:14] input io_enq_bits_xcpt_ae_if, // @[FetchBuffer.scala:21:14] input io_enq_bits_end_half_valid, // @[FetchBuffer.scala:21:14] input [15:0] io_enq_bits_end_half_bits, // @[FetchBuffer.scala:21:14] input io_deq_0_ready, // @[FetchBuffer.scala:21:14] output io_deq_0_valid, // @[FetchBuffer.scala:21:14] output [31:0] io_deq_0_bits_inst, // @[FetchBuffer.scala:21:14] output [31:0] io_deq_0_bits_raw_inst, // @[FetchBuffer.scala:21:14] output [39:0] io_deq_0_bits_pc, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_edge_inst, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_rvc, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_btb_resp_valid, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_0_bits_btb_resp_bits_cfiType, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_btb_resp_bits_taken, // @[FetchBuffer.scala:21:14] output [3:0] io_deq_0_bits_btb_resp_bits_mask, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_0_bits_btb_resp_bits_bridx, // @[FetchBuffer.scala:21:14] output [38:0] io_deq_0_bits_btb_resp_bits_target, // @[FetchBuffer.scala:21:14] output [5:0] io_deq_0_bits_btb_resp_bits_entry, // @[FetchBuffer.scala:21:14] output [7:0] io_deq_0_bits_btb_resp_bits_bht_history, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_0_bits_btb_resp_bits_bht_value, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_sfb_br, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_next_pc_valid, // @[FetchBuffer.scala:21:14] output [39:0] io_deq_0_bits_next_pc_bits, // @[FetchBuffer.scala:21:14] output [2:0] io_deq_0_bits_ras_head, // @[FetchBuffer.scala:21:14] output io_deq_0_bits_xcpt, // @[FetchBuffer.scala:21:14] output [63:0] io_deq_0_bits_xcpt_cause, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_0_bits_mem_size, // @[FetchBuffer.scala:21:14] input io_deq_1_ready, // @[FetchBuffer.scala:21:14] output io_deq_1_valid, // @[FetchBuffer.scala:21:14] output [31:0] io_deq_1_bits_inst, // @[FetchBuffer.scala:21:14] output [31:0] io_deq_1_bits_raw_inst, // @[FetchBuffer.scala:21:14] output [39:0] io_deq_1_bits_pc, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_edge_inst, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_rvc, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_btb_resp_valid, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_1_bits_btb_resp_bits_cfiType, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_btb_resp_bits_taken, // @[FetchBuffer.scala:21:14] output [3:0] io_deq_1_bits_btb_resp_bits_mask, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_1_bits_btb_resp_bits_bridx, // @[FetchBuffer.scala:21:14] output [38:0] io_deq_1_bits_btb_resp_bits_target, // @[FetchBuffer.scala:21:14] output [5:0] io_deq_1_bits_btb_resp_bits_entry, // @[FetchBuffer.scala:21:14] output [7:0] io_deq_1_bits_btb_resp_bits_bht_history, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_1_bits_btb_resp_bits_bht_value, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_sfb_br, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_next_pc_valid, // @[FetchBuffer.scala:21:14] output [39:0] io_deq_1_bits_next_pc_bits, // @[FetchBuffer.scala:21:14] output [2:0] io_deq_1_bits_ras_head, // @[FetchBuffer.scala:21:14] output io_deq_1_bits_xcpt, // @[FetchBuffer.scala:21:14] output [63:0] io_deq_1_bits_xcpt_cause, // @[FetchBuffer.scala:21:14] output [1:0] io_deq_1_bits_mem_size, // @[FetchBuffer.scala:21:14] output io_peek_0_valid, // @[FetchBuffer.scala:21:14] output [31:0] io_peek_0_bits_inst, // @[FetchBuffer.scala:21:14] output [31:0] io_peek_0_bits_raw_inst, // @[FetchBuffer.scala:21:14] output [39:0] io_peek_0_bits_pc, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_edge_inst, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_rvc, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_btb_resp_valid, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_0_bits_btb_resp_bits_cfiType, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_btb_resp_bits_taken, // @[FetchBuffer.scala:21:14] output [3:0] io_peek_0_bits_btb_resp_bits_mask, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_0_bits_btb_resp_bits_bridx, // @[FetchBuffer.scala:21:14] output [38:0] io_peek_0_bits_btb_resp_bits_target, // @[FetchBuffer.scala:21:14] output [5:0] io_peek_0_bits_btb_resp_bits_entry, // @[FetchBuffer.scala:21:14] output [7:0] io_peek_0_bits_btb_resp_bits_bht_history, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_0_bits_btb_resp_bits_bht_value, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_sfb_br, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_next_pc_valid, // @[FetchBuffer.scala:21:14] output [39:0] io_peek_0_bits_next_pc_bits, // @[FetchBuffer.scala:21:14] output [2:0] io_peek_0_bits_ras_head, // @[FetchBuffer.scala:21:14] output io_peek_0_bits_xcpt, // @[FetchBuffer.scala:21:14] output [63:0] io_peek_0_bits_xcpt_cause, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_0_bits_mem_size, // @[FetchBuffer.scala:21:14] output io_peek_1_valid, // @[FetchBuffer.scala:21:14] output [31:0] io_peek_1_bits_inst, // @[FetchBuffer.scala:21:14] output [31:0] io_peek_1_bits_raw_inst, // @[FetchBuffer.scala:21:14] output [39:0] io_peek_1_bits_pc, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_edge_inst, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_rvc, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_btb_resp_valid, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_1_bits_btb_resp_bits_cfiType, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_btb_resp_bits_taken, // @[FetchBuffer.scala:21:14] output [3:0] io_peek_1_bits_btb_resp_bits_mask, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_1_bits_btb_resp_bits_bridx, // @[FetchBuffer.scala:21:14] output [38:0] io_peek_1_bits_btb_resp_bits_target, // @[FetchBuffer.scala:21:14] output [5:0] io_peek_1_bits_btb_resp_bits_entry, // @[FetchBuffer.scala:21:14] output [7:0] io_peek_1_bits_btb_resp_bits_bht_history, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_1_bits_btb_resp_bits_bht_value, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_sfb_br, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_next_pc_valid, // @[FetchBuffer.scala:21:14] output [39:0] io_peek_1_bits_next_pc_bits, // @[FetchBuffer.scala:21:14] output [2:0] io_peek_1_bits_ras_head, // @[FetchBuffer.scala:21:14] output io_peek_1_bits_xcpt, // @[FetchBuffer.scala:21:14] output [63:0] io_peek_1_bits_xcpt_cause, // @[FetchBuffer.scala:21:14] output [1:0] io_peek_1_bits_mem_size, // @[FetchBuffer.scala:21:14] input io_clear // @[FetchBuffer.scala:21:14] ); wire io_enq_valid_0 = io_enq_valid; // @[FetchBuffer.scala:16:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[FetchBuffer.scala:16:7] wire io_enq_bits_next_pc_valid_0 = io_enq_bits_next_pc_valid; // @[FetchBuffer.scala:16:7] wire [39:0] io_enq_bits_next_pc_bits_0 = io_enq_bits_next_pc_bits; // @[FetchBuffer.scala:16:7] wire io_enq_bits_edge_inst_0 = io_enq_bits_edge_inst; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_insts_0_0 = io_enq_bits_insts_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_insts_1_0 = io_enq_bits_insts_1; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_insts_2_0 = io_enq_bits_insts_2; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_insts_3_0 = io_enq_bits_insts_3; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_exp_insts_0_0 = io_enq_bits_exp_insts_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_exp_insts_1_0 = io_enq_bits_exp_insts_1; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_exp_insts_2_0 = io_enq_bits_exp_insts_2; // @[FetchBuffer.scala:16:7] wire [31:0] io_enq_bits_exp_insts_3_0 = io_enq_bits_exp_insts_3; // @[FetchBuffer.scala:16:7] wire [39:0] io_enq_bits_pcs_0_0 = io_enq_bits_pcs_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_enq_bits_pcs_1_0 = io_enq_bits_pcs_1; // @[FetchBuffer.scala:16:7] wire [39:0] io_enq_bits_pcs_2_0 = io_enq_bits_pcs_2; // @[FetchBuffer.scala:16:7] wire [39:0] io_enq_bits_pcs_3_0 = io_enq_bits_pcs_3; // @[FetchBuffer.scala:16:7] wire [3:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[FetchBuffer.scala:16:7] wire io_enq_bits_btb_resp_valid_0 = io_enq_bits_btb_resp_valid; // @[FetchBuffer.scala:16:7] wire [1:0] io_enq_bits_btb_resp_bits_cfiType_0 = io_enq_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:16:7] wire io_enq_bits_btb_resp_bits_taken_0 = io_enq_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:16:7] wire [3:0] io_enq_bits_btb_resp_bits_mask_0 = io_enq_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:16:7] wire [1:0] io_enq_bits_btb_resp_bits_bridx_0 = io_enq_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:16:7] wire [38:0] io_enq_bits_btb_resp_bits_target_0 = io_enq_bits_btb_resp_bits_target; // @[FetchBuffer.scala:16:7] wire [5:0] io_enq_bits_btb_resp_bits_entry_0 = io_enq_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:16:7] wire [7:0] io_enq_bits_btb_resp_bits_bht_history_0 = io_enq_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:16:7] wire [1:0] io_enq_bits_btb_resp_bits_bht_value_0 = io_enq_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:16:7] wire [2:0] io_enq_bits_ras_head_0 = io_enq_bits_ras_head; // @[FetchBuffer.scala:16:7] wire io_enq_bits_xcpt_pf_if_0 = io_enq_bits_xcpt_pf_if; // @[FetchBuffer.scala:16:7] wire io_enq_bits_xcpt_ae_if_0 = io_enq_bits_xcpt_ae_if; // @[FetchBuffer.scala:16:7] wire io_enq_bits_end_half_valid_0 = io_enq_bits_end_half_valid; // @[FetchBuffer.scala:16:7] wire [15:0] io_enq_bits_end_half_bits_0 = io_enq_bits_end_half_bits; // @[FetchBuffer.scala:16:7] wire io_deq_0_ready_0 = io_deq_0_ready; // @[FetchBuffer.scala:16:7] wire io_deq_1_ready_0 = io_deq_1_ready; // @[FetchBuffer.scala:16:7] wire io_clear_0 = io_clear; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_taken = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_taken = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_taken = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_taken = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:16:7] wire in_uops_0_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_taken = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_edge_inst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_taken = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_edge_inst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_taken = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_edge_inst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_legal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_fp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_rocc = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_branch = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_jal = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_jalr = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_rxs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_rxs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_alu_dw = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_mem = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_rfs1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_rfs2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_rfs3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_wfd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_mul = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_wxd = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_fence_i = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_fence = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_amo = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_dp = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fp_ctrl_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_sets_vcfg = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_sfb_shadow = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_taken = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_needs_replay = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_uses_memalu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_uses_latealu = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_wdata_valid = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_ldst = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_wen = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_ren1 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_ren2 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_ren3 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_swap12 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_swap23 = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_fromint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_toint = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_fastpipe = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_fma = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_div = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_sqrt = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_wflags = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_fdivin_vec = 1'h0; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_flush_pipe = 1'h0; // @[FetchBuffer.scala:35:21] wire _in_uops_0_bits_sfb_br_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _in_uops_0_bits_sfb_br_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _in_uops_0_bits_sfb_br_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _in_uops_0_bits_sfb_br_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _in_uops_0_bits_sfb_br_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _in_uops_0_bits_sfb_br_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _in_uops_0_bits_sfb_br_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _in_uops_0_bits_sfb_br_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _in_uops_0_bits_sfb_br_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _in_uops_0_bits_sfb_br_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _in_uops_0_bits_sfb_br_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _in_uops_0_bits_sfb_br_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _in_uops_0_bits_sfb_br_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _in_uops_0_bits_sfb_br_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _in_uops_0_bits_sfb_br_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _in_uops_0_bits_sfb_br_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _in_uops_0_bits_sfb_br_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire in_uops_0_bits_sfb_br_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _in_uops_1_bits_sfb_br_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _in_uops_1_bits_sfb_br_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _in_uops_1_bits_sfb_br_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _in_uops_1_bits_sfb_br_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _in_uops_1_bits_sfb_br_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _in_uops_1_bits_sfb_br_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _in_uops_1_bits_sfb_br_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _in_uops_1_bits_sfb_br_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _in_uops_1_bits_sfb_br_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _in_uops_1_bits_sfb_br_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _in_uops_1_bits_sfb_br_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _in_uops_1_bits_sfb_br_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _in_uops_1_bits_sfb_br_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _in_uops_1_bits_sfb_br_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _in_uops_1_bits_sfb_br_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _in_uops_1_bits_sfb_br_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _in_uops_1_bits_sfb_br_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire in_uops_1_bits_sfb_br_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _in_uops_1_bits_edge_inst_T = 1'h0; // @[FetchBuffer.scala:61:45] wire _in_uops_2_bits_sfb_br_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _in_uops_2_bits_sfb_br_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _in_uops_2_bits_sfb_br_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _in_uops_2_bits_sfb_br_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _in_uops_2_bits_sfb_br_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _in_uops_2_bits_sfb_br_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _in_uops_2_bits_sfb_br_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _in_uops_2_bits_sfb_br_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _in_uops_2_bits_sfb_br_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _in_uops_2_bits_sfb_br_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _in_uops_2_bits_sfb_br_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _in_uops_2_bits_sfb_br_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _in_uops_2_bits_sfb_br_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _in_uops_2_bits_sfb_br_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _in_uops_2_bits_sfb_br_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _in_uops_2_bits_sfb_br_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _in_uops_2_bits_sfb_br_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire in_uops_2_bits_sfb_br_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _in_uops_2_bits_edge_inst_T = 1'h0; // @[FetchBuffer.scala:61:45] wire _in_uops_3_bits_sfb_br_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _in_uops_3_bits_sfb_br_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _in_uops_3_bits_sfb_br_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _in_uops_3_bits_sfb_br_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _in_uops_3_bits_sfb_br_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _in_uops_3_bits_sfb_br_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _in_uops_3_bits_sfb_br_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _in_uops_3_bits_sfb_br_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _in_uops_3_bits_sfb_br_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _in_uops_3_bits_sfb_br_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _in_uops_3_bits_sfb_br_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _in_uops_3_bits_sfb_br_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _in_uops_3_bits_sfb_br_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _in_uops_3_bits_sfb_br_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _in_uops_3_bits_sfb_br_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _in_uops_3_bits_sfb_br_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _in_uops_3_bits_sfb_br_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire in_uops_3_bits_sfb_br_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _in_uops_3_bits_edge_inst_T = 1'h0; // @[FetchBuffer.scala:61:45] wire _ram_0_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_0_T_717 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_1_T_717 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_2_T_717 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_3_T_717 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_4_T_717 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_5_T_717 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_4 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_5 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_6 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_83 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_89 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_102 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_103 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_114 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_115 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_116 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_138 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_139 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_140 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_141 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_142 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_143 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_144 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_145 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_146 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_147 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_148 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_149 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_150 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_151 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_152 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_153 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_154 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_155 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_159 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_160 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_161 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_237 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_261 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_262 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_263 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_280 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_281 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_309 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_310 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_311 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_312 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_313 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_314 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_385 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_386 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_387 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_388 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_389 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_390 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_391 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_399 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_400 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_401 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_402 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_403 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_404 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_405 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_406 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_407 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_408 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_409 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_410 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_411 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_412 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_413 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_414 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_415 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_416 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_417 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_418 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_419 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_420 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_421 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_422 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_423 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_424 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_425 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_426 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_427 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_428 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_429 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_430 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_431 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_432 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_433 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_434 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_435 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_436 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_437 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_438 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_439 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_440 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_441 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_442 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_443 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_444 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_445 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_446 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_447 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_448 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_449 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_450 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_451 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_452 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_453 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_454 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_469 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_470 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_471 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_472 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_473 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_474 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_475 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_476 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_477 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_478 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_479 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_480 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_481 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_482 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_483 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_484 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_485 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_486 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_487 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_488 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_489 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_490 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_491 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_492 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_493 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_494 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_495 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_496 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_497 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_498 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_499 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_500 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_501 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_502 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_503 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_504 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_505 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_506 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_507 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_508 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_509 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_510 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_511 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_512 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_513 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_514 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_515 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_516 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_517 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_518 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_519 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_520 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_521 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_522 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_523 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_524 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_525 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_526 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_527 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_528 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_529 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_530 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_531 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_532 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_533 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_534 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_535 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_536 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_537 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_538 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_539 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_540 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_541 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_542 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_543 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_544 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_545 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_546 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_547 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_548 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_549 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_550 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_551 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_552 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_560 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_561 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_562 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_563 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_564 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_565 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_566 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_567 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_568 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_569 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_570 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_571 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_572 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_573 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_574 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_575 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_576 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_577 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_578 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_579 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_580 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_581 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_582 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_583 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_584 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_585 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_586 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_587 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_588 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_589 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_590 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_591 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_592 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_593 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_594 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_595 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_596 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_597 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_598 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_599 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_600 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_601 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_602 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_603 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_604 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_605 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_606 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_607 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_608 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_616 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_617 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_618 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_619 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_620 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_621 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_622 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_630 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_631 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_632 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_633 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_634 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_635 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_636 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_658 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_659 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_660 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_661 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_662 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_663 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_664 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_665 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_666 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_667 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_668 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_669 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_670 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_671 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_672 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_673 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_674 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_675 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_676 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_677 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_678 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_679 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_680 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_681 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_682 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_683 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_684 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_685 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_686 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_687 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_688 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_689 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_690 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_691 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_692 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_693 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_694 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_695 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_696 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_697 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_698 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_699 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_700 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_701 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_702 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_703 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_704 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_705 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_706 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_707 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_708 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_709 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_710 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_711 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_712 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_713 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_715 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_716 = 1'h0; // @[Mux.scala:30:73] wire _ram_6_T_717 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_taken = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_taken = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_7 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_8 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_9 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_10 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_11 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_13 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_14 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_15 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_16 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_17 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_18 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_19 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_3_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_124 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_125 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_126 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_129 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_130 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_131 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_132 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_133 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_134 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_135 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_136 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_11 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_137 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_138 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_139 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_140 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_141 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_142 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_143 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_144 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_145 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_146 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_147 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_148 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_149 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_150 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_151 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_152 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_153 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_154 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_155 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_156 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_157 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_158 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_159 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_160 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_161 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_162 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_163 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_164 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_165 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_166 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_167 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_168 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_169 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_170 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_171 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_172 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_173 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_174 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_175 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_176 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_177 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_178 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_179 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_180 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_181 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_182 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_183 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_184 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_185 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_186 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_187 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_188 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_189 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_190 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_191 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_192 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_193 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_194 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_195 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_196 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_197 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_198 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_199 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_200 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_201 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_202 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_203 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_204 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_205 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_206 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_207 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_208 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_209 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_210 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_211 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_212 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_213 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_214 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_215 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_216 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_217 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_218 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_219 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_220 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_221 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_222 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_223 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_224 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_225 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_226 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_227 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_254 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_255 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_256 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_257 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_258 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_259 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_260 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_261 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_262 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_263 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_264 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_265 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_266 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_21 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_267 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_268 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_269 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_270 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_271 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_272 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_273 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_274 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_275 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_276 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_277 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_278 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_279 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_280 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_281 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_282 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_283 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_284 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_285 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_286 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_287 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_288 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_289 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_290 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_291 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_292 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_293 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_294 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_295 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_296 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_297 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_298 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_299 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_300 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_301 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_302 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_303 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_304 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_305 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_306 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_307 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_308 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_309 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_310 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_311 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_312 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_313 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_314 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_315 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_316 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_317 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_318 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_319 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_320 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_321 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_322 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_328 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_330 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_332 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_333 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_334 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_335 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_336 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_337 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_338 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_339 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_340 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_341 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_342 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_343 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_344 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_32_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_410 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_411 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_412 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_413 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_414 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_415 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_416 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_417 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_418 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_419 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_420 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_421 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_422 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_34 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_423 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_424 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_425 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_426 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_427 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_428 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_429 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_430 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_431 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_432 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_433 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_434 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_435 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_436 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_437 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_438 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_439 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_440 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_441 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_442 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_443 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_444 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_445 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_446 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_447 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_448 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_488 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_489 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_490 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_491 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_492 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_493 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_494 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_495 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_496 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_497 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_498 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_499 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_500 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_40 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_527 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_528 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_529 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_530 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_531 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_532 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_533 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_534 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_535 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_536 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_537 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_538 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_539 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_43 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_579 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_580 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_581 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_582 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_583 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_584 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_585 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_586 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_587 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_588 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_589 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_590 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_591 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_48 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_722 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_723 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_724 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_725 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_726 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_727 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_728 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_729 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_730 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_731 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_732 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_733 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_734 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_62 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_64_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_748 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_749 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_750 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_751 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_752 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_753 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_754 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_755 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_756 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_757 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_758 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_759 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_760 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_65 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_761 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_762 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_763 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_764 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_765 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_766 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_767 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_768 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_769 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_770 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_771 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_772 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_773 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_774 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_775 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_776 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_777 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_778 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_779 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_780 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_781 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_782 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_783 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_784 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_785 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_786 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_787 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_788 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_789 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_790 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_791 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_792 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_793 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_794 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_795 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_796 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_797 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_798 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_799 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_800 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_801 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_802 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_803 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_804 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_805 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_806 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_807 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_808 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_809 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_810 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_811 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_812 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_813 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_814 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_815 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_816 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_817 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_818 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_819 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_820 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_821 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_822 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_823 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_824 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_825 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_826 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_827 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_828 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_829 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_830 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_831 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_832 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_833 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_834 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_835 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_836 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_837 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_838 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_839 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_840 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_841 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_842 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_843 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_844 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_845 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_846 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_847 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_848 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_849 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_850 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_851 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_878 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_879 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_880 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_881 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_882 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_883 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_884 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_885 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_886 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_887 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_888 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_889 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_890 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_75 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_891 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_892 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_893 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_894 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_895 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_896 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_897 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_898 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_899 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_900 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_901 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_902 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_903 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_904 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_905 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_906 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_907 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_908 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_909 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_910 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_911 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_912 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_913 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_914 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_915 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_916 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_917 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_918 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_919 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_920 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_921 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_922 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_923 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_924 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_925 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_926 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_927 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_928 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_929 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_930 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_931 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_932 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_933 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_934 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_935 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_936 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_937 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_938 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_939 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_940 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_941 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_942 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_943 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_944 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_945 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_946 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_947 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_948 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_949 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_950 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_951 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_952 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_953 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_954 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_955 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_956 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_957 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_958 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_959 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_960 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_961 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_962 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_963 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_964 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_965 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_966 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_967 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_968 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_82_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_969 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_970 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_971 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_972 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_973 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_974 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_975 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_976 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_977 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_978 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_979 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_980 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_981 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_83 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_982 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_983 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_984 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_985 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_986 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_987 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_988 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_989 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_990 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_991 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_992 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_993 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_994 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_995 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_996 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_997 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_998 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_999 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1000 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1001 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1002 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1003 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1004 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1005 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1006 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1007 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1008 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1009 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1010 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1011 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1012 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1013 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1014 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1015 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1016 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1017 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1018 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1019 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1020 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1021 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1022 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1023 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1024 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1025 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1026 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1027 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1028 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1029 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1030 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1031 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1032 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1033 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1047 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1048 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1049 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1050 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1051 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1052 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1053 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1054 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1055 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1056 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1057 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1058 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1059 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_89 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1060 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1061 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1062 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1063 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1064 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1065 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1066 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1067 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1068 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1069 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1070 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1071 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1072 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1073 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1074 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1075 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1076 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1077 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1078 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1079 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1080 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1081 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1082 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1083 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1084 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1085 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1086 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1087 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1088 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1089 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1090 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1091 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1092 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1093 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1094 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1095 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1096 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1097 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1098 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1099 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1100 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1101 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1102 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1103 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1104 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1105 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1106 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1107 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1108 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1109 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1110 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1111 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1112 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1113 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1114 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1115 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1116 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1117 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1118 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1119 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1120 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1121 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1122 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1123 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1124 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1125 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1126 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1129 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1130 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1131 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1132 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1133 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1134 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1135 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1136 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1137 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1151 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1152 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1153 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1154 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1155 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1156 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1157 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1158 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1159 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1160 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1161 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1162 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1163 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_97 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1177 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1178 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1179 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1180 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1181 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1182 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1183 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1184 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1185 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1186 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1187 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1188 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1189 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_99 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1229 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1230 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1231 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1232 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1233 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1234 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1235 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1236 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1237 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1238 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1239 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1240 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1241 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_103 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1242 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1243 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1244 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1245 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1246 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1247 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1248 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1249 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1250 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1251 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1252 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1253 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1254 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1255 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1256 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1257 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1258 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1259 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1260 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1261 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1262 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1263 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1264 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1265 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1266 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1267 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1268 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1269 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1270 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1271 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1272 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1273 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1274 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1275 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1276 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1277 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1278 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1279 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1280 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1281 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1282 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1283 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1284 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1285 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1286 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1287 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1288 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1289 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1290 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1291 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1292 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1293 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1294 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1295 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1296 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1297 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1298 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1299 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1300 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1301 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1302 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1303 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1304 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1305 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1306 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1307 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1308 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1309 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1310 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1311 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1312 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1313 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1314 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1315 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1316 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1317 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1318 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1319 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1320 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1321 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1322 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1328 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1330 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1332 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_taken = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_1_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_taken = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1405 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1406 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1407 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1408 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1409 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1410 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1411 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1412 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1413 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1414 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1415 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1416 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1417 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_117 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_119_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1522 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1523 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1524 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1525 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1526 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1527 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1528 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1529 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1530 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1531 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1532 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1533 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1534 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1535 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1536 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1537 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1538 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1539 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1540 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1541 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1542 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1543 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1544 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1545 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1546 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1547 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1548 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1549 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1550 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1551 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1552 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1553 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1554 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1555 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1556 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1557 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1558 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1559 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1560 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_129 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1561 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1562 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1563 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1564 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1565 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1566 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1567 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1568 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1569 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1570 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1571 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1572 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1573 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_130 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1574 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1575 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1576 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1577 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1578 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1579 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1580 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1581 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1582 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1583 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1584 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1585 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1586 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_131 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1587 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1588 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1589 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1590 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1591 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1592 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1593 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1594 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1595 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1596 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1597 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1598 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1599 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_132 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1600 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1601 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1602 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1603 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1604 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1605 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1606 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1607 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1608 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1609 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1610 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1611 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1612 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_133 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1613 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1614 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1615 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1616 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1617 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1618 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1619 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1620 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1621 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1622 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1623 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1624 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1625 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_134 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1652 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1653 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1654 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1655 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1656 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1657 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1658 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1659 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1660 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1661 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1662 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1663 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1664 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_137 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1665 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1666 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1667 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1668 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1669 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1670 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1671 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1672 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1673 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1674 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1675 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1676 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1677 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_138 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1678 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1679 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1680 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1681 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1682 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1683 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1684 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1685 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1686 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1687 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1688 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1689 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1690 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_139 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1691 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1692 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1693 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1694 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1695 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1696 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1697 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1698 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1699 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1700 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1701 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1702 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1703 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_140 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1704 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1705 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1706 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1707 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1708 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1709 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1710 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1711 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1712 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1713 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1714 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1715 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1716 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_141 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1717 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1718 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1719 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1720 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1721 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1722 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1723 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1724 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1725 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1726 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1727 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1728 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1729 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_142 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1730 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1731 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1732 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1733 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1734 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1735 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1736 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1737 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1738 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1739 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1740 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1741 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1742 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_143 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_148_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1808 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1809 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1810 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1811 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1812 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1813 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1814 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1815 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1816 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1817 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1818 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1819 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1820 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_150 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1821 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1822 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1823 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1824 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1825 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1826 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1827 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1828 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1829 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1830 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1831 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1832 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1833 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_151 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1834 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1835 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1836 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1837 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1838 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1839 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1840 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1841 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1842 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1843 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1844 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1845 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1846 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_152 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1886 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1887 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1888 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1889 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1890 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1891 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1892 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1893 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1894 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1895 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1896 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1897 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1898 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_156 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1925 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1926 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1927 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1928 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1929 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1930 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1931 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1932 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1933 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1934 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1935 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1936 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1937 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_159 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1977 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1978 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1979 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1980 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1981 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1982 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1983 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1984 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1985 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1986 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1987 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1988 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_1989 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_164 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2120 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2121 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2122 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2123 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2124 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2125 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2126 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2129 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2130 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2131 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2132 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_178 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_180_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2146 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2147 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2148 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2149 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2150 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2151 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2152 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2153 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2154 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2155 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2156 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2157 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2158 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_181 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2159 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2160 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2161 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2162 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2163 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2164 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2165 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2166 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2167 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2168 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2169 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2170 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2171 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_182 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2172 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2173 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2174 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2175 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2176 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2177 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2178 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2179 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2180 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2181 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2182 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2183 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2184 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_183 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2185 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2186 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2187 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2188 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2189 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2190 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2191 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2192 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2193 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2194 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2195 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2196 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2197 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_184 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2198 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2199 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2200 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2201 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2202 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2203 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2204 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2205 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2206 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2207 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2208 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2209 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2210 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_185 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2211 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2212 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2213 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2214 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2215 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2216 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2217 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2218 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2219 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2220 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2221 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2222 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2223 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_186 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2224 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2225 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2226 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2227 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2228 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2229 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2230 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2231 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2232 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2233 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2234 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2235 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2236 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_187 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2237 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2238 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2239 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2240 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2241 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2242 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2243 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2244 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2245 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2246 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2247 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2248 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2249 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_188 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2276 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2277 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2278 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2279 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2280 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2281 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2282 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2283 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2284 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2285 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2286 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2287 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2288 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_191 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2289 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2290 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2291 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2292 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2293 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2294 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2295 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2296 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2297 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2298 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2299 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2300 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2301 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_192 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2302 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2303 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2304 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2305 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2306 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2307 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2308 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2309 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2310 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2311 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2312 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2313 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2314 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_193 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2315 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2316 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2317 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2318 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2319 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2320 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2321 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2322 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_194 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2328 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2330 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2332 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2333 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2334 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2335 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2336 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2337 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2338 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2339 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2340 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_195 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2341 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2342 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2343 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2344 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2345 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2346 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2347 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2348 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2349 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2350 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2351 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2352 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2353 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_196 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2354 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2355 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2356 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2357 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2358 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2359 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2360 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2361 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2362 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2363 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2364 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2365 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2366 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_197 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_198_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2367 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2368 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2369 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2370 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2371 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2372 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2373 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2374 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2375 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2376 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2377 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2378 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2379 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_199 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2380 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2381 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2382 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2383 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2384 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2385 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2386 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2387 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2388 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2389 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2390 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2391 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2392 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_200 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2393 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2394 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2395 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2396 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2397 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2398 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2399 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2400 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2401 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2402 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2403 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2404 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2405 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_201 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2406 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2407 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2408 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2409 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2410 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2411 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2412 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2413 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2414 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2415 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2416 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2417 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2418 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_202 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2419 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2420 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2421 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2422 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2423 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2424 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2425 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2426 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2427 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2428 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2429 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2430 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2431 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_203 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2445 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2446 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2447 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2448 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2449 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2450 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2451 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2452 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2453 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2454 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2455 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2456 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2457 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_205 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2458 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2459 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2460 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2461 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2462 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2463 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2464 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2465 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2466 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2467 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2468 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2469 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2470 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_206 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2471 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2472 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2473 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2474 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2475 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2476 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2477 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2478 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2479 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2480 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2481 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2482 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2483 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_207 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2484 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2485 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2486 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2487 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2488 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2489 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2490 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2491 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2492 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2493 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2494 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2495 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2496 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_208 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2497 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2498 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2499 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2500 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2501 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2502 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2503 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2504 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2505 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2506 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2507 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2508 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2509 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_209 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2510 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2511 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2512 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2513 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2514 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2515 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2516 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2517 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2518 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2519 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2520 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2521 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2522 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_210 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2523 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2524 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2525 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2526 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2527 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2528 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2529 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2530 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2531 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2532 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2533 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2534 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2535 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_211 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2549 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2550 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2551 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2552 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2553 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2554 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2555 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2556 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2557 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2558 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2559 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2560 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2561 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_213 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2575 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2576 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2577 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2578 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2579 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2580 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2581 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2582 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2583 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2584 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2585 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2586 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2587 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_215 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2627 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2628 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2629 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2630 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2631 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2632 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2633 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2634 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2635 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2636 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2637 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2638 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2639 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_219 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2640 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2641 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2642 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2643 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2644 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2645 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2646 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2647 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2648 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2649 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2650 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2651 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2652 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_220 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2653 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2654 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2655 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2656 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2657 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2658 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2659 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2660 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2661 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2662 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2663 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2664 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2665 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_221 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2666 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2667 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2668 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2669 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2670 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2671 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2672 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2673 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2674 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2675 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2676 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2677 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2678 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_222 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2679 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2680 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2681 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2682 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2683 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2684 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2685 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2686 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2687 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2688 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2689 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2690 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2691 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_223 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2692 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2693 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2694 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2695 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2696 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2697 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2698 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2699 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2700 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2701 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2702 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2703 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2704 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_224 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2705 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2706 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2707 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2708 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2709 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2710 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2711 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2712 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2713 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2714 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2715 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2716 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2717 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_225 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2718 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2719 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2720 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2721 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2722 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2723 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2724 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2725 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2726 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2727 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2728 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2729 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2730 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_226 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_taken = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_2_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_taken = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2803 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2804 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2805 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2806 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2807 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2808 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2809 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2810 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2811 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2812 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2813 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2814 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2815 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_233 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_235_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2920 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2921 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2922 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2923 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2924 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2925 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2926 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2927 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2928 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2929 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2930 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2931 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2932 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_243 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2933 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2934 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2935 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2936 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2937 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2938 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2939 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2940 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2941 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2942 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2943 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2944 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2945 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_244 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2946 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2947 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2948 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2949 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2950 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2951 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2952 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2953 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2954 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2955 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2956 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2957 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2958 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_245 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2959 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2960 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2961 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2962 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2963 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2964 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2965 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2966 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2967 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2968 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2969 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2970 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2971 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_246 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2972 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2973 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2974 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2975 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2976 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2977 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2978 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2979 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2980 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2981 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2982 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2983 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2984 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_247 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2985 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2986 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2987 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2988 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2989 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2990 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2991 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2992 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2993 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2994 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2995 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2996 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2997 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_248 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2998 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_2999 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3000 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3001 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3002 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3003 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3004 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3005 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3006 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3007 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3008 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3009 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3010 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_249 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3011 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3012 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3013 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3014 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3015 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3016 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3017 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3018 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3019 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3020 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3021 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3022 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3023 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_250 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3050 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3051 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3052 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3053 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3054 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3055 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3056 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3057 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3058 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3059 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3060 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3061 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3062 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_253 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3063 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3064 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3065 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3066 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3067 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3068 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3069 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3070 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3071 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3072 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3073 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3074 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3075 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_254 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3076 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3077 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3078 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3079 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3080 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3081 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3082 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3083 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3084 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3085 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3086 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3087 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3088 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_255 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3089 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3090 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3091 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3092 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3093 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3094 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3095 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3096 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3097 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3098 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3099 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3100 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3101 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_256 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3102 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3103 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3104 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3105 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3106 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3107 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3108 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3109 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3110 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3111 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3112 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3113 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3114 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_257 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3115 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3116 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3117 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3118 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3119 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3120 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3121 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3122 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3123 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3124 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3125 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3126 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_258 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3129 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3130 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3131 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3132 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3133 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3134 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3135 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3136 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3137 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3138 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3139 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3140 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_259 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_264_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3206 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3207 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3208 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3209 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3210 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3211 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3212 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3213 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3214 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3215 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3216 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3217 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3218 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_266 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3219 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3220 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3221 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3222 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3223 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3224 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3225 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3226 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3227 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3228 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3229 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3230 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3231 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_267 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3232 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3233 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3234 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3235 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3236 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3237 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3238 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3239 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3240 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3241 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3242 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3243 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3244 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_268 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3284 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3285 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3286 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3287 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3288 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3289 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3290 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3291 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3292 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3293 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3294 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3295 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3296 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_272 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3328 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3330 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3332 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3333 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3334 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3335 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_275 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3375 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3376 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3377 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3378 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3379 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3380 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3381 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3382 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3383 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3384 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3385 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3386 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3387 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_280 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3518 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3519 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3520 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3521 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3522 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3523 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3524 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3525 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3526 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3527 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3528 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3529 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3530 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_294 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_296_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3544 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3545 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3546 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3547 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3548 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3549 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3550 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3551 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3552 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3553 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3554 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3555 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3556 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_297 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3557 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3558 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3559 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3560 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3561 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3562 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3563 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3564 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3565 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3566 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3567 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3568 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3569 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_298 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3570 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3571 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3572 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3573 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3574 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3575 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3576 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3577 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3578 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3579 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3580 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3581 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3582 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_299 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3583 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3584 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3585 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3586 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3587 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3588 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3589 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3590 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3591 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3592 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3593 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3594 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3595 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_300 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3596 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3597 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3598 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3599 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3600 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3601 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3602 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3603 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3604 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3605 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3606 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3607 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3608 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_301 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3609 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3610 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3611 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3612 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3613 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3614 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3615 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3616 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3617 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3618 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3619 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3620 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3621 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_302 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3622 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3623 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3624 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3625 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3626 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3627 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3628 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3629 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3630 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3631 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3632 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3633 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3634 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_303 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3635 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3636 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3637 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3638 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3639 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3640 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3641 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3642 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3643 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3644 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3645 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3646 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3647 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_304 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3674 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3675 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3676 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3677 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3678 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3679 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3680 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3681 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3682 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3683 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3684 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3685 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3686 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_307 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3687 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3688 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3689 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3690 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3691 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3692 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3693 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3694 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3695 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3696 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3697 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3698 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3699 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_308 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3700 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3701 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3702 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3703 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3704 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3705 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3706 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3707 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3708 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3709 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3710 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3711 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3712 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_309 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3713 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3714 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3715 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3716 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3717 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3718 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3719 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3720 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3721 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3722 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3723 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3724 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3725 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_310 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3726 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3727 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3728 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3729 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3730 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3731 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3732 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3733 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3734 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3735 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3736 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3737 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3738 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_311 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3739 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3740 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3741 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3742 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3743 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3744 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3745 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3746 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3747 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3748 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3749 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3750 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3751 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_312 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3752 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3753 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3754 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3755 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3756 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3757 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3758 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3759 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3760 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3761 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3762 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3763 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3764 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_313 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_314_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3765 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3766 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3767 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3768 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3769 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3770 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3771 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3772 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3773 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3774 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3775 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3776 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3777 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_315 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3778 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3779 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3780 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3781 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3782 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3783 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3784 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3785 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3786 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3787 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3788 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3789 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3790 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_316 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3791 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3792 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3793 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3794 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3795 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3796 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3797 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3798 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3799 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3800 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3801 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3802 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3803 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_317 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3804 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3805 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3806 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3807 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3808 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3809 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3810 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3811 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3812 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3813 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3814 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3815 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3816 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_318 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3817 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3818 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3819 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3820 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3821 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3822 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3823 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3824 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3825 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3826 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3827 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3828 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3829 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_319 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3843 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3844 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3845 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3846 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3847 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3848 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3849 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3850 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3851 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3852 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3853 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3854 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3855 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_321 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3856 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3857 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3858 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3859 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3860 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3861 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3862 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3863 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3864 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3865 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3866 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3867 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3868 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_322 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3869 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3870 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3871 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3872 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3873 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3874 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3875 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3876 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3877 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3878 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3879 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3880 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3881 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3882 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3883 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3884 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3885 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3886 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3887 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3888 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3889 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3890 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3891 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3892 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3893 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3894 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3895 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3896 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3897 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3898 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3899 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3900 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3901 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3902 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3903 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3904 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3905 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3906 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3907 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3908 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3909 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3910 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3911 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3912 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3913 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3914 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3915 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3916 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3917 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3918 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3919 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3920 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3921 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3922 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3923 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3924 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3925 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3926 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3927 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3928 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3929 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3930 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3931 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3932 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3933 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3947 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3948 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3949 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3950 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3951 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3952 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3953 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3954 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3955 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3956 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3957 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3958 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3959 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3973 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3974 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3975 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3976 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3977 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3978 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3979 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3980 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3981 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3982 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3983 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3984 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_3985 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4025 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4026 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4027 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4028 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4029 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4030 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4031 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4032 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4033 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4034 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4035 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4036 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4037 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_335 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4038 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4039 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4040 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4041 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4042 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4043 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4044 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4045 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4046 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4047 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4048 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4049 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4050 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_336 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4051 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4052 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4053 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4054 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4055 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4056 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4057 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4058 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4059 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4060 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4061 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4062 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4063 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_337 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4064 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4065 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4066 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4067 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4068 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4069 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4070 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4071 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4072 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4073 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4074 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4075 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4076 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_338 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4077 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4078 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4079 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4080 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4081 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4082 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4083 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4084 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4085 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4086 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4087 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4088 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4089 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_339 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4090 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4091 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4092 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4093 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4094 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4095 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4096 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4097 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4098 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4099 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4100 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4101 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4102 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_340 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4103 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4104 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4105 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4106 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4107 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4108 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4109 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4110 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4111 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4112 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4113 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4114 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4115 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_341 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4116 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4117 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4118 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4119 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4120 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4121 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4122 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4123 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4124 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4125 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4126 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_342 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_taken = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire out_uop_3_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_taken = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4201 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4202 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4203 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4204 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4205 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4206 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4207 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4208 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4209 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4210 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4211 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4212 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4213 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_349 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_351_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4318 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4319 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4320 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4321 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4322 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4328 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4330 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_359 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4332 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4333 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4334 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4335 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4336 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4337 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4338 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4339 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4340 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4341 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4342 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4343 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_360 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4344 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4345 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4346 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4347 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4348 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4349 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4350 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4351 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4352 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4353 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4354 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4355 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4356 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_361 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4357 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4358 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4359 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4360 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4361 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4362 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4363 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4364 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4365 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4366 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4367 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4368 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4369 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_362 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4370 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4371 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4372 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4373 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4374 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4375 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4376 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4377 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4378 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4379 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4380 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4381 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4382 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_363 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4383 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4384 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4385 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4386 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4387 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4388 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4389 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4390 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4391 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4392 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4393 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4394 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4395 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_364 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4396 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4397 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4398 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4399 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4400 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4401 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4402 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4403 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4404 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4405 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4406 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4407 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4408 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_365 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4409 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4410 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4411 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4412 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4413 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4414 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4415 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4416 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4417 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4418 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4419 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4420 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4421 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_366 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4448 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4449 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4450 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4451 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4452 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4453 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4454 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4455 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4456 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4457 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4458 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4459 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4460 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_369 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4461 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4462 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4463 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4464 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4465 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4466 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4467 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4468 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4469 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4470 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4471 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4472 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4473 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_370 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4474 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4475 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4476 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4477 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4478 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4479 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4480 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4481 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4482 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4483 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4484 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4485 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4486 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_371 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4487 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4488 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4489 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4490 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4491 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4492 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4493 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4494 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4495 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4496 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4497 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4498 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4499 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_372 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4500 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4501 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4502 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4503 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4504 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4505 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4506 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4507 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4508 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4509 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4510 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4511 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4512 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_373 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4513 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4514 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4515 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4516 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4517 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4518 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4519 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4520 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4521 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4522 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4523 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4524 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4525 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_374 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4526 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4527 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4528 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4529 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4530 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4531 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4532 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4533 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4534 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4535 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4536 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4537 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4538 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_375 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_380_valid = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4604 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4605 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4606 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4607 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4608 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4609 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4610 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4611 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4612 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4613 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4614 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4615 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4616 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_382 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4617 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4618 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4619 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4620 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4621 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4622 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4623 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4624 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4625 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4626 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4627 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4628 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4629 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_383 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4630 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4631 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4632 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4633 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4634 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4635 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4636 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4637 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4638 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4639 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4640 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4641 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4642 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_384 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4682 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4683 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4684 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4685 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4686 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4687 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4688 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4689 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4690 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4691 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4692 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4693 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4694 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_388 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4721 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4722 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4723 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4724 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4725 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4726 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4727 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4728 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4729 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4730 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4731 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4732 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4733 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_391 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4773 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4774 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4775 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4776 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4777 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4778 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4779 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4780 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4781 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4782 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4783 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4784 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4785 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_396 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4916 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4917 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4918 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4919 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4920 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4921 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4922 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4923 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4924 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4925 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4926 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4927 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4928 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_410 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_ldst = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_wen = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_ren1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_ren2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_ren3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_swap12 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_swap23 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_fromint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_toint = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_fma = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_sqrt = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_wflags = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_412_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4942 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4943 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4944 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4945 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4946 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4947 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4948 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4949 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4950 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4951 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4952 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4953 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4954 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_413 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4955 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4956 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4957 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4958 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4959 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4960 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4961 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4962 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4963 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4964 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4965 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4966 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4967 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_414 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4968 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4969 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4970 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4971 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4972 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4973 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4974 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4975 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4976 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4977 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4978 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4979 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4980 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_415 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4981 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4982 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4983 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4984 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4985 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4986 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4987 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4988 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4989 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4990 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4991 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4992 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4993 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_416 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4994 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4995 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4996 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4997 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4998 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_4999 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5000 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5001 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5002 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5003 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5004 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5005 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5006 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_417 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5007 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5008 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5009 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5010 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5011 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5012 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5013 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5014 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5015 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5016 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5017 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5018 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5019 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_418 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5020 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5021 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5022 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5023 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5024 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5025 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5026 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5027 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5028 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5029 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5030 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5031 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5032 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_419 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5033 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5034 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5035 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5036 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5037 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5038 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5039 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5040 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5041 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5042 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5043 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5044 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5045 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_420 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5072 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5073 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5074 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5075 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5076 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5077 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5078 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5079 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5080 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5081 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5082 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5083 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5084 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_423 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5085 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5086 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5087 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5088 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5089 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5090 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5091 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5092 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5093 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5094 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5095 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5096 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5097 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_424 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5098 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5099 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5100 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5101 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5102 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5103 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5104 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5105 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5106 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5107 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5108 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5109 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5110 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_425 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5111 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5112 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5113 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5114 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5115 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5116 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5117 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5118 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5119 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5120 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5121 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5122 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5123 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_426 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5124 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5125 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5126 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5127 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5128 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5129 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5130 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5131 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5132 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5133 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5134 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5135 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5136 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_427 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5137 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5138 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5139 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5140 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5141 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5142 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5143 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5144 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5145 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5146 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5147 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5148 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5149 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_428 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5150 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5151 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5152 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5153 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5154 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5155 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5156 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5157 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5158 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5159 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5160 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5161 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5162 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_429 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_legal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_fp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_rocc = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_branch = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_jal = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_jalr = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_mem = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_wfd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_mul = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_div = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_wxd = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_fence_i = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_fence = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_amo = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_dp = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_430_vec = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5163 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5164 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5165 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5166 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5167 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5168 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5169 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5170 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5171 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5172 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5173 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5174 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5175 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_431 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5176 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5177 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5178 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5179 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5180 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5181 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5182 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5183 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5184 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5185 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5186 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5187 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5188 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_432 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5189 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5190 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5191 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5192 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5193 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5194 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5195 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5196 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5197 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5198 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5199 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5200 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5201 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_433 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5202 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5203 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5204 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5205 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5206 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5207 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5208 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5209 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5210 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5211 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5212 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5213 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5214 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_434 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5215 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5216 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5217 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5218 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5219 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5220 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5221 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5222 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5223 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5224 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5225 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5226 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5227 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_435 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5241 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5242 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5243 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5244 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5245 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5246 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5247 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5248 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5249 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5250 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5251 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5252 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5253 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_437 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5254 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5255 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5256 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5257 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5258 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5259 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5260 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5261 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5262 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5263 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5264 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5265 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5266 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_438 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5267 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5268 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5269 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5270 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5271 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5272 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5273 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5274 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5275 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5276 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5277 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5278 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5279 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_439 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5280 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5281 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5282 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5283 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5284 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5285 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5286 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5287 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5288 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5289 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5290 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5291 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5292 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_440 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5293 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5294 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5295 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5296 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5297 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5298 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5299 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5300 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5301 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5302 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5303 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5304 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5305 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_441 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5306 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5307 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5308 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5309 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5310 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5311 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5312 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5313 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5314 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5315 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5316 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5317 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5318 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_442 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5319 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5320 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5321 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5322 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5323 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5324 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5325 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5326 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5327 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5328 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5329 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5330 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5331 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_443 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5345 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5346 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5347 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5348 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5349 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5350 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5351 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5352 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5353 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5354 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5355 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5356 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5357 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_445 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5371 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5372 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5373 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5374 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5375 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5376 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5377 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5378 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5379 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5380 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5381 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5382 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5383 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_447 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5423 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5424 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5425 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5426 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5427 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5428 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5429 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5430 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5431 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5432 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5433 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5434 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5435 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_451 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5436 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5437 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5438 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5439 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5440 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5441 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5442 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5443 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5444 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5445 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5446 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5447 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5448 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_452 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5449 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5450 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5451 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5452 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5453 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5454 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5455 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5456 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5457 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5458 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5459 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5460 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5461 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_453 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5462 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5463 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5464 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5465 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5466 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5467 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5468 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5469 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5470 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5471 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5472 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5473 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5474 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_454 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5475 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5476 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5477 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5478 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5479 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5480 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5481 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5482 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5483 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5484 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5485 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5486 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5487 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_455 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5488 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5489 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5490 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5491 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5492 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5493 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5494 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5495 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5496 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5497 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5498 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5499 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5500 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_456 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5501 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5502 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5503 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5504 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5505 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5506 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5507 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5508 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5509 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5510 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5511 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5512 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5513 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_457 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5514 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5515 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5516 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5517 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5518 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5519 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5520 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5521 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5522 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5523 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5524 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5525 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_T_5526 = 1'h0; // @[Mux.scala:30:73] wire _out_uop_WIRE_458 = 1'h0; // @[Mux.scala:30:73] wire [2:0] io_deq_0_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_0_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_0_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_0_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_1_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_1_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_1_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_1_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_0_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_0_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_0_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_0_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_1_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_1_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_1_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_1_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:16:7] wire [2:0] in_uops_0_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_0_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_0_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_0_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_1_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_1_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_1_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_1_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_2_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_2_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_2_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_2_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_3_bits_ctrl_sel_alu2 = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_3_bits_ctrl_sel_imm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_3_bits_ctrl_csr = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] in_uops_3_bits_fdivin_rm = 3'h0; // @[FetchBuffer.scala:35:21] wire [2:0] _ram_0_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_56 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_57 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_58 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_59 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_60 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_61 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_62 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_637 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_638 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_639 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_640 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_641 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_642 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_643 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_651 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_652 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_653 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_654 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_655 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_656 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_657 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_3_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_111 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_112 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_113 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_114 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_115 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_116 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_117 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_118 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_119 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_120 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_121 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_122 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_123 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_10 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_82_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_82_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_82_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1034 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1035 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1036 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1037 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1038 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1039 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1040 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1041 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1042 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1043 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1044 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1045 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1046 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_88 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1190 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1191 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1192 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1193 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1194 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1195 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1196 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1197 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1198 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1199 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1200 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1201 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1202 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_100 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1216 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1217 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1218 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1219 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1220 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1221 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1222 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1223 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1224 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1225 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1226 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1227 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1228 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_102 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_1_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_1_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_1_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_1_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_116_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_116_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_116_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_116_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_119_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1509 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1510 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1511 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1512 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1513 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1514 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1515 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1516 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1517 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1518 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1519 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1520 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1521 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_126 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_198_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_198_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_198_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2432 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2433 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2434 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2435 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2436 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2437 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2438 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2439 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2440 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2441 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2442 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2443 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2444 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_204 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2588 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2589 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2590 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2591 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2592 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2593 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2594 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2595 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2596 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2597 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2598 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2599 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2600 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_216 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2614 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2615 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2616 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2617 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2618 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2619 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2620 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2621 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2622 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2623 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2624 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2625 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2626 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_218 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_2_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_2_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_2_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_2_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_232_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_232_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_232_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_232_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_235_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2907 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2908 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2909 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2910 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2911 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2912 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2913 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2914 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2915 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2916 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2917 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2918 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_2919 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_242 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_314_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_314_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_314_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3830 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3831 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3832 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3833 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3834 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3835 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3836 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3837 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3838 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3839 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3840 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3841 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3842 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_320 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3986 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3987 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3988 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3989 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3990 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3991 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3992 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3993 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3994 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3995 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3996 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3997 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3998 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_332 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4012 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4013 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4014 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4015 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4016 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4017 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4018 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4019 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4020 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4021 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4022 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4023 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4024 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_334 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_3_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_3_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_3_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] out_uop_3_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_348_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_348_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_348_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_348_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_351_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4305 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4306 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4307 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4308 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4309 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4310 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4311 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4312 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4313 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4314 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4315 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4316 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4317 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_358 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_430_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_430_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_430_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5228 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5229 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5230 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5231 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5232 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5233 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5234 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5235 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5236 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5237 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5238 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5239 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5240 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_436 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5384 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5385 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5386 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5387 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5388 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5389 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5390 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5391 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5392 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5393 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5394 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5395 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5396 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_448 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5410 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5411 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5412 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5413 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5414 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5415 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5416 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5417 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5418 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5419 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5420 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5421 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_5422 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_450 = 3'h0; // @[Mux.scala:30:73] wire [1:0] io_deq_0_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:16:7] wire [1:0] in_uops_0_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_ctrl_sel_alu1 = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fp_ctrl_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fp_ctrl_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fdivin_typeTagIn = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fdivin_typeTagOut = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fdivin_fmaCmd = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fdivin_typ = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_fdivin_fmt = 2'h0; // @[FetchBuffer.scala:35:21] wire [1:0] _ram_0_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_35 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_36 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_37 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_38 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_39 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_40 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_41 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_42 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_43 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_44 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_45 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_46 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_47 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_48 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_49 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_50 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_119 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_120 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_121 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_122 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_126 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_127 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_128 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_129 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_130 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_131 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_132 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_455 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_456 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_457 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_458 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_459 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_460 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_461 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_462 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_463 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_464 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_465 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_466 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_467 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_468 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_3_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_3_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_3_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_3_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_3_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_72 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_73 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_76 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_77 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_78 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_79 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_80 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_81 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_82 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_83 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_84 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_7 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_85 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_86 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_87 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_88 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_89 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_90 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_91 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_92 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_93 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_94 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_95 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_96 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_97 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_98 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_99 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_100 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_101 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_102 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_103 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_104 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_105 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_106 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_107 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_108 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_109 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_110 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_228 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_229 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_230 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_231 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_232 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_233 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_234 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_235 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_236 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_237 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_238 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_239 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_240 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_241 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_242 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_243 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_244 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_245 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_246 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_247 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_248 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_249 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_250 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_251 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_252 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_253 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_64_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_64_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_852 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_853 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_854 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_855 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_856 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_857 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_858 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_859 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_860 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_861 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_862 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_863 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_864 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_73 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_865 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_866 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_867 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_868 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_869 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_870 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_871 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_872 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_873 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_874 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_875 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_876 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_877 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_82_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1203 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1204 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1205 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1206 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1207 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1208 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1209 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1210 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1211 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1212 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1213 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1214 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1215 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_101 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_119_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_119_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_119_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_119_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_119_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1470 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1471 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1472 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1473 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1474 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1475 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1476 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1477 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1478 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1479 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1480 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1481 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1482 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_123 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1483 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1484 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1485 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1486 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1487 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1488 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1489 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1490 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1491 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1492 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1493 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1494 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1495 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_124 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1496 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1497 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1498 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1499 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1500 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1501 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1502 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1503 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1504 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1505 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1506 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1507 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1508 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_125 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1626 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1627 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1628 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1629 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1630 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1631 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1632 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1633 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1634 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1635 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1636 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1637 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1638 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_135 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1639 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1640 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1641 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1642 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1643 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1644 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1645 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1646 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1647 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1651 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_136 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_180_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_180_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2250 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2251 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2252 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2253 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2254 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2255 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2256 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2257 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2258 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2259 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2260 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2261 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2262 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_189 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2263 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2264 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2265 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2266 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2267 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2268 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2269 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2270 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2271 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2272 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2273 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2274 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2275 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_190 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_198_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2601 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2602 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2603 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2604 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2605 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2606 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2607 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2608 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2609 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2610 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2611 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2612 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2613 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_217 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_235_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_235_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_235_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_235_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_235_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2868 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2869 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2870 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2871 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2872 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2873 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2874 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2875 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2876 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2877 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2878 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2879 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2880 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_239 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2881 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2882 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2883 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2884 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2885 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2886 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2887 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2888 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2889 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2890 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2891 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2892 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2893 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_240 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2894 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2895 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2896 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2897 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2898 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2899 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2900 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2901 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2902 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2903 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2904 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2905 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2906 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_241 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3024 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3025 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3026 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3027 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3028 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3029 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3030 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3031 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3032 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3033 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3034 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3035 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3036 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_251 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3037 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3038 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3039 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3040 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3041 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3042 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3043 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3044 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3045 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3046 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3047 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3048 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3049 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_252 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_296_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_296_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3648 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3649 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3650 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3651 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3652 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3653 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3654 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3655 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3656 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3657 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3658 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3659 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3660 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_305 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3661 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3662 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3663 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3664 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3665 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3666 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3667 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3668 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3669 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3670 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3671 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3672 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3673 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_306 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_314_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3999 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4000 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4001 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4002 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4003 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4004 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4005 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4006 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4007 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4008 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4009 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4010 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4011 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_333 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_351_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_351_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_351_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_351_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_351_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4266 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4267 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4268 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4269 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4270 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4271 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4272 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4273 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4274 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4275 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4276 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4277 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4278 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_355 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4279 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4280 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4281 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4282 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4283 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4284 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4285 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4286 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4287 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4288 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4289 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4290 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4291 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_356 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4292 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4293 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4294 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4295 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4296 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4297 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4298 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4299 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4300 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4301 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4302 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4303 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4304 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_357 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4422 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4423 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4424 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4425 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4426 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4427 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4428 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4429 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4430 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4431 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4432 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4433 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4434 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_367 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4435 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4436 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4437 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4438 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4439 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4440 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4441 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4442 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4443 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4444 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4445 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4446 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4447 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_368 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_412_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_412_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5046 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5047 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5048 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5049 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5050 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5051 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5052 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5053 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5054 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5055 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5056 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5057 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5058 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_421 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5059 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5060 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5061 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5062 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5063 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5064 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5065 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5066 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5067 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5068 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5069 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5070 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5071 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_422 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_430_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5397 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5398 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5399 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5400 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5401 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5402 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5403 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5404 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5405 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5406 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5407 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5408 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_5409 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_449 = 2'h0; // @[Mux.scala:30:73] wire [4:0] io_deq_0_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_0_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_0_bits_fra1 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_0_bits_fra2 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_0_bits_fra3 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_0_bits_fexc = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_1_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_1_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_1_bits_fra1 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_1_bits_fra2 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_1_bits_fra3 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_deq_1_bits_fexc = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_0_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_0_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_0_bits_fra1 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_0_bits_fra2 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_0_bits_fra3 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_0_bits_fexc = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_1_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_1_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_1_bits_fra1 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_1_bits_fra2 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_1_bits_fra3 = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] io_peek_1_bits_fexc = 5'h0; // @[FetchBuffer.scala:16:7] wire [4:0] in_uops_0_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_0_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_0_bits_fra1 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_0_bits_fra2 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_0_bits_fra3 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_0_bits_fexc = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_1_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_1_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_1_bits_fra1 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_1_bits_fra2 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_1_bits_fra3 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_1_bits_fexc = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_2_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_2_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_2_bits_fra1 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_2_bits_fra2 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_2_bits_fra3 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_2_bits_fexc = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_3_bits_ctrl_alu_fn = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_3_bits_ctrl_mem_cmd = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_3_bits_fra1 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_3_bits_fra2 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_3_bits_fra3 = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] in_uops_3_bits_fexc = 5'h0; // @[FetchBuffer.scala:35:21] wire [4:0] _ram_0_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_0_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_1_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_2_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_3_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_4_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_5_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_193 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_194 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_195 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_196 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_197 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_198 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_199 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_200 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_201 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_202 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_203 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_204 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_205 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_206 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_207 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_208 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_209 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_609 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_610 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_611 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_612 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_613 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_614 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_615 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_623 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_624 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_625 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_626 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_627 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_628 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_T_629 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ram_6_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_345 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_346 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_347 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_348 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_349 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_350 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_351 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_352 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_353 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_354 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_355 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_356 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_357 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_28 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_358 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_359 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_360 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_361 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_362 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_363 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_364 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_365 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_366 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_367 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_368 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_369 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_370 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_371 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_372 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_373 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_374 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_375 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_376 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_377 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_378 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_379 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_380 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_381 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_382 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_383 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_384 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_385 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_386 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_387 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_388 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_389 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_390 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_391 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_392 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_393 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_394 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_395 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_396 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_82_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_82_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1138 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1139 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1140 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1141 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1142 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1143 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1144 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1145 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1146 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1147 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1148 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1149 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1150 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_96 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1164 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1165 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1166 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1167 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1168 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1169 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1170 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1171 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1172 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1173 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1174 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1175 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1176 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_98 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_1_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_1_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_1_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_1_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_1_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_1_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_116_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_116_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_116_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_116_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_116_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_116_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1743 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1744 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1745 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1746 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1747 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1748 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1749 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1750 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1751 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1752 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1753 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1754 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1755 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_144 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1756 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1757 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1758 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1759 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1760 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1761 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1762 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1763 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1764 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1765 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1766 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1767 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1768 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_145 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1769 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1770 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1771 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1772 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1773 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1774 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1775 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1776 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1777 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1778 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1779 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1780 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1781 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_146 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1782 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1783 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1784 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1785 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1786 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1787 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1788 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1789 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1790 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1791 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1792 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1793 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_1794 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_147 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_198_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_198_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2536 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2537 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2538 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2539 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2540 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2541 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2542 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2543 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2544 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2545 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2546 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2547 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2548 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_212 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2562 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2563 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2564 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2565 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2566 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2567 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2568 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2569 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2570 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2571 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2572 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2573 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_2574 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_214 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_2_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_2_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_2_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_2_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_2_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_2_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_232_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_232_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_232_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_232_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_232_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_232_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3141 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3142 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3143 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3144 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3145 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3146 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3147 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3148 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3149 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3150 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3151 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3152 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3153 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_260 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3154 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3155 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3156 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3157 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3158 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3159 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3160 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3161 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3162 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3163 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3164 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3165 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3166 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_261 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3167 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3168 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3169 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3170 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3171 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3172 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3173 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3174 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3175 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3176 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3177 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3178 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3179 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_262 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3180 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3181 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3182 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3183 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3184 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3185 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3186 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3187 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3188 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3189 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3190 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3191 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3192 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_263 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_314_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_314_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3934 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3935 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3936 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3937 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3938 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3939 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3940 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3941 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3942 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3943 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3944 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3945 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3946 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_328 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3960 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3961 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3962 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3963 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3964 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3965 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3966 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3967 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3968 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3969 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3970 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3971 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_3972 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_330 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_3_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_3_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_3_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_3_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_3_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] out_uop_3_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_348_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_348_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_348_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_348_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_348_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_348_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4539 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4540 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4541 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4542 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4543 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4544 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4545 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4546 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4547 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4548 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4549 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4550 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4551 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_376 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4552 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4553 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4554 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4555 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4556 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4557 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4558 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4559 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4560 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4561 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4562 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4563 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4564 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_377 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4565 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4566 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4567 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4568 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4569 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4570 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4571 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4572 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4573 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4574 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4575 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4576 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4577 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_378 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4578 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4579 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4580 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4581 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4582 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4583 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4584 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4585 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4586 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4587 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4588 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4589 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_4590 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_379 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_430_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_430_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5332 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5333 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5334 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5335 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5336 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5337 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5338 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5339 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5340 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5341 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5342 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5343 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5344 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_444 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5358 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5359 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5360 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5361 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5362 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5363 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5364 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5365 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5366 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5367 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5368 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5369 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_T_5370 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _out_uop_WIRE_446 = 5'h0; // @[Mux.scala:30:73] wire [63:0] io_deq_0_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_0_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_0_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_0_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_1_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_1_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_1_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_1_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_0_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_0_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_0_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_0_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_1_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_1_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_1_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_1_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:16:7] wire [63:0] in_uops_0_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_0_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_0_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_0_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_1_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_1_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_1_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_1_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_2_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_2_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_2_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_2_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_3_bits_rs1_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_3_bits_rs2_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_3_bits_rs3_data = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_3_bits_wdata_bits = 64'h0; // @[FetchBuffer.scala:35:21] wire [63:0] _ram_0_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_210 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_211 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_212 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_213 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_214 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_215 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_216 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_238 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_239 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_240 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_241 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_242 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_243 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_244 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_32_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_397 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_398 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_399 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_400 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_401 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_402 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_403 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_404 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_405 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_406 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_407 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_408 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_409 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_33 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_449 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_450 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_451 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_452 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_453 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_454 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_455 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_456 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_457 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_458 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_459 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_460 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_461 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_37 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_462 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_463 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_464 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_465 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_466 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_467 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_468 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_469 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_470 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_471 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_472 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_473 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_474 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_475 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_476 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_477 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_478 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_479 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_480 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_481 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_482 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_483 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_484 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_485 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_486 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_487 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_1_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_1_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_1_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_1_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_116_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_116_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_116_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_116_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_148_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1795 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1796 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1797 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1798 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1799 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1800 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1801 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1802 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1803 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1804 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1805 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1806 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1807 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_149 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1847 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1848 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1849 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1850 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1851 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1852 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1853 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1854 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1855 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1856 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1857 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1858 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1859 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_153 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1860 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1861 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1862 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1863 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1864 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1865 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1866 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1867 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1868 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1869 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1870 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1871 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1872 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_154 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1873 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1874 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1875 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1876 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1877 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1878 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1879 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1880 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1881 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1882 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1883 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1884 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1885 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_155 = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_2_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_2_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_2_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_2_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_232_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_232_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_232_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_232_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_264_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3193 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3194 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3195 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3196 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3197 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3198 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3199 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3200 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3201 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3202 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3203 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3204 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3205 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_265 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3245 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3246 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3247 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3248 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3249 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3250 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3251 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3252 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3253 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3254 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3255 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3256 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3257 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_269 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3258 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3259 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3260 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3261 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3262 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3263 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3264 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3265 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3266 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3267 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3268 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3269 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3270 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_270 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3271 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3272 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3273 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3274 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3275 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3276 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3277 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3278 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3279 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3280 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3281 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3282 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3283 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_271 = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_3_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_3_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_3_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] out_uop_3_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_348_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_348_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_348_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_348_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_380_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4591 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4592 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4593 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4594 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4595 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4596 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4597 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4598 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4599 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4600 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4601 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4602 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4603 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_381 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4643 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4644 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4645 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4646 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4647 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4648 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4649 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4650 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4651 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4652 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4653 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4654 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4655 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_385 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4656 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4657 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4658 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4659 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4660 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4661 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4662 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4663 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4664 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4665 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4666 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4667 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4668 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_386 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4669 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4670 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4671 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4672 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4673 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4674 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4675 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4676 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4677 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4678 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4679 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4680 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4681 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_387 = 64'h0; // @[Mux.scala:30:73] wire [64:0] io_deq_0_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_deq_0_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_deq_0_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_deq_1_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_deq_1_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_deq_1_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_peek_0_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_peek_0_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_peek_0_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_peek_1_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_peek_1_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] io_peek_1_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:16:7] wire [64:0] in_uops_0_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_0_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_0_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_1_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_1_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_1_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_2_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_2_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_2_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_3_bits_fdivin_in1 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_3_bits_fdivin_in2 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] in_uops_3_bits_fdivin_in3 = 65'h0; // @[FetchBuffer.scala:35:21] wire [64:0] _ram_0_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_0_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_1_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_2_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_3_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_4_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_5_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_15 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_16 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_17 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_18 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_19 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_20 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_21 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_22 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_23 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_24 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_25 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_26 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_27 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_28 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_29 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_30 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_31 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_32 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ram_6_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_3_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_3_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_3_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_33 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_34 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_35 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_36 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_37 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_38 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_39 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_40 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_41 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_42 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_43 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_44 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_45 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_4 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_46 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_47 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_48 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_49 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_50 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_51 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_52 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_53 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_54 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_55 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_56 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_57 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_58 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_59 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_60 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_61 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_62 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_63 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_64 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_65 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_66 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_67 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_68 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_69 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_70 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_71 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_1_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_1_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_1_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_116_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_116_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_116_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_119_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_119_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_119_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1431 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1432 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1433 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1434 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1435 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1436 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1437 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1438 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1439 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1440 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1441 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1442 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1443 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_120 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1444 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1445 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1446 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1447 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1448 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1449 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1450 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1451 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1452 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1453 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1454 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1455 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1456 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_121 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1457 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1458 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1459 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1460 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1461 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1462 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1463 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1464 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1465 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1466 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1467 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1468 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_1469 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_122 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_2_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_2_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_2_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_232_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_232_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_232_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_235_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_235_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_235_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2829 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2830 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2831 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2832 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2833 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2834 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2835 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2836 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2837 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2838 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2839 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2840 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2841 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_236 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2842 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2843 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2844 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2845 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2846 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2847 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2848 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2849 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2850 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2851 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2852 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2853 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2854 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_237 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2855 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2856 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2857 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2858 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2859 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2860 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2861 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2862 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2863 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2864 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2865 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2866 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_2867 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_238 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_3_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_3_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] out_uop_3_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_348_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_348_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_348_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_351_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_351_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_351_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4227 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4228 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4229 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4230 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4231 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4232 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4233 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4234 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4235 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4236 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4237 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4238 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4239 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_352 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4240 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4241 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4242 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4243 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4244 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4245 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4246 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4247 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4248 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4249 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4250 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4251 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4252 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_353 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4253 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4254 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4255 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4256 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4257 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4258 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4259 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4260 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4261 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4262 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4263 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4264 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_T_4265 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _out_uop_WIRE_354 = 65'h0; // @[Mux.scala:30:73] wire [3:0] io_enq_bits_br_mask = 4'h0; // @[FetchBuffer.scala:16:7] wire _in_uops_0_bits_sfb_br_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _in_uops_0_bits_sfb_br_b19_12_T_1 = 1'h1; // @[RocketCore.scala:1343:43] wire _in_uops_0_bits_sfb_br_b19_12_T_2 = 1'h1; // @[RocketCore.scala:1343:36] wire _in_uops_0_bits_sfb_br_b11_T_6 = 1'h1; // @[RocketCore.scala:1346:23] wire _in_uops_0_bits_sfb_br_b4_1_T_2 = 1'h1; // @[RocketCore.scala:1349:41] wire _in_uops_0_bits_sfb_br_b4_1_T_3 = 1'h1; // @[RocketCore.scala:1349:34] wire _in_uops_1_bits_sfb_br_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _in_uops_1_bits_sfb_br_b19_12_T_1 = 1'h1; // @[RocketCore.scala:1343:43] wire _in_uops_1_bits_sfb_br_b19_12_T_2 = 1'h1; // @[RocketCore.scala:1343:36] wire _in_uops_1_bits_sfb_br_b11_T_6 = 1'h1; // @[RocketCore.scala:1346:23] wire _in_uops_1_bits_sfb_br_b4_1_T_2 = 1'h1; // @[RocketCore.scala:1349:41] wire _in_uops_1_bits_sfb_br_b4_1_T_3 = 1'h1; // @[RocketCore.scala:1349:34] wire _in_uops_2_bits_sfb_br_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _in_uops_2_bits_sfb_br_b19_12_T_1 = 1'h1; // @[RocketCore.scala:1343:43] wire _in_uops_2_bits_sfb_br_b19_12_T_2 = 1'h1; // @[RocketCore.scala:1343:36] wire _in_uops_2_bits_sfb_br_b11_T_6 = 1'h1; // @[RocketCore.scala:1346:23] wire _in_uops_2_bits_sfb_br_b4_1_T_2 = 1'h1; // @[RocketCore.scala:1349:41] wire _in_uops_2_bits_sfb_br_b4_1_T_3 = 1'h1; // @[RocketCore.scala:1349:34] wire _in_uops_3_bits_sfb_br_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _in_uops_3_bits_sfb_br_b19_12_T_1 = 1'h1; // @[RocketCore.scala:1343:43] wire _in_uops_3_bits_sfb_br_b19_12_T_2 = 1'h1; // @[RocketCore.scala:1343:36] wire _in_uops_3_bits_sfb_br_b11_T_6 = 1'h1; // @[RocketCore.scala:1346:23] wire _in_uops_3_bits_sfb_br_b4_1_T_2 = 1'h1; // @[RocketCore.scala:1349:41] wire _in_uops_3_bits_sfb_br_b4_1_T_3 = 1'h1; // @[RocketCore.scala:1349:34] wire _io_enq_ready_T_23; // @[FetchBuffer.scala:32:76] wire [39:0] in_uops_0_bits_next_pc_bits = io_enq_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_1_bits_next_pc_bits = io_enq_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_2_bits_next_pc_bits = io_enq_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_3_bits_next_pc_bits = io_enq_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7, :35:21] wire _in_uops_0_bits_edge_inst_T = io_enq_bits_edge_inst_0; // @[FetchBuffer.scala:16:7, :61:45] wire [31:0] in_uops_0_bits_raw_inst = io_enq_bits_insts_0_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_1_bits_raw_inst = io_enq_bits_insts_1_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_2_bits_raw_inst = io_enq_bits_insts_2_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_3_bits_raw_inst = io_enq_bits_insts_3_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_0_bits_inst = io_enq_bits_exp_insts_0_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_1_bits_inst = io_enq_bits_exp_insts_1_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_2_bits_inst = io_enq_bits_exp_insts_2_0; // @[FetchBuffer.scala:16:7, :35:21] wire [31:0] in_uops_3_bits_inst = io_enq_bits_exp_insts_3_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_0_bits_pc = io_enq_bits_pcs_0_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_1_bits_pc = io_enq_bits_pcs_1_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_2_bits_pc = io_enq_bits_pcs_2_0; // @[FetchBuffer.scala:16:7, :35:21] wire [39:0] in_uops_3_bits_pc = io_enq_bits_pcs_3_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_0_bits_btb_resp_valid = io_enq_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_1_bits_btb_resp_valid = io_enq_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_2_bits_btb_resp_valid = io_enq_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_3_bits_btb_resp_valid = io_enq_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_0_bits_btb_resp_bits_cfiType = io_enq_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_1_bits_btb_resp_bits_cfiType = io_enq_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_2_bits_btb_resp_bits_cfiType = io_enq_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_3_bits_btb_resp_bits_cfiType = io_enq_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_0_bits_btb_resp_bits_taken = io_enq_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_1_bits_btb_resp_bits_taken = io_enq_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_2_bits_btb_resp_bits_taken = io_enq_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7, :35:21] wire in_uops_3_bits_btb_resp_bits_taken = io_enq_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7, :35:21] wire [3:0] in_uops_0_bits_btb_resp_bits_mask = io_enq_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7, :35:21] wire [3:0] in_uops_1_bits_btb_resp_bits_mask = io_enq_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7, :35:21] wire [3:0] in_uops_2_bits_btb_resp_bits_mask = io_enq_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7, :35:21] wire [3:0] in_uops_3_bits_btb_resp_bits_mask = io_enq_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_0_bits_btb_resp_bits_bridx = io_enq_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_1_bits_btb_resp_bits_bridx = io_enq_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_2_bits_btb_resp_bits_bridx = io_enq_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_3_bits_btb_resp_bits_bridx = io_enq_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7, :35:21] wire [38:0] in_uops_0_bits_btb_resp_bits_target = io_enq_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7, :35:21] wire [38:0] in_uops_1_bits_btb_resp_bits_target = io_enq_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7, :35:21] wire [38:0] in_uops_2_bits_btb_resp_bits_target = io_enq_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7, :35:21] wire [38:0] in_uops_3_bits_btb_resp_bits_target = io_enq_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7, :35:21] wire [5:0] in_uops_0_bits_btb_resp_bits_entry = io_enq_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7, :35:21] wire [5:0] in_uops_1_bits_btb_resp_bits_entry = io_enq_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7, :35:21] wire [5:0] in_uops_2_bits_btb_resp_bits_entry = io_enq_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7, :35:21] wire [5:0] in_uops_3_bits_btb_resp_bits_entry = io_enq_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7, :35:21] wire [7:0] in_uops_0_bits_btb_resp_bits_bht_history = io_enq_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7, :35:21] wire [7:0] in_uops_1_bits_btb_resp_bits_bht_history = io_enq_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7, :35:21] wire [7:0] in_uops_2_bits_btb_resp_bits_bht_history = io_enq_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7, :35:21] wire [7:0] in_uops_3_bits_btb_resp_bits_bht_history = io_enq_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_0_bits_btb_resp_bits_bht_value = io_enq_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_1_bits_btb_resp_bits_bht_value = io_enq_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_2_bits_btb_resp_bits_bht_value = io_enq_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7, :35:21] wire [1:0] in_uops_3_bits_btb_resp_bits_bht_value = io_enq_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7, :35:21] wire [2:0] in_uops_0_bits_ras_head = io_enq_bits_ras_head_0; // @[FetchBuffer.scala:16:7, :35:21] wire [2:0] in_uops_1_bits_ras_head = io_enq_bits_ras_head_0; // @[FetchBuffer.scala:16:7, :35:21] wire [2:0] in_uops_2_bits_ras_head = io_enq_bits_ras_head_0; // @[FetchBuffer.scala:16:7, :35:21] wire [2:0] in_uops_3_bits_ras_head = io_enq_bits_ras_head_0; // @[FetchBuffer.scala:16:7, :35:21] wire out_uop_valid; // @[Mux.scala:30:73] wire [31:0] out_uop_bits_inst; // @[Mux.scala:30:73] wire [31:0] out_uop_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] out_uop_bits_pc; // @[Mux.scala:30:73] wire out_uop_bits_edge_inst; // @[Mux.scala:30:73] wire out_uop_bits_rvc; // @[Mux.scala:30:73] wire out_uop_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire out_uop_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] out_uop_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] out_uop_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] out_uop_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] out_uop_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire out_uop_bits_sfb_br; // @[Mux.scala:30:73] wire out_uop_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] out_uop_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] out_uop_bits_ras_head; // @[Mux.scala:30:73] wire out_uop_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] out_uop_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] out_uop_bits_mem_size; // @[Mux.scala:30:73] wire out_uop_1_valid; // @[Mux.scala:30:73] wire [31:0] out_uop_1_bits_inst; // @[Mux.scala:30:73] wire [31:0] out_uop_1_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] out_uop_1_bits_pc; // @[Mux.scala:30:73] wire out_uop_1_bits_edge_inst; // @[Mux.scala:30:73] wire out_uop_1_bits_rvc; // @[Mux.scala:30:73] wire out_uop_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire out_uop_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] out_uop_1_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] out_uop_1_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] out_uop_1_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] out_uop_1_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire out_uop_1_bits_sfb_br; // @[Mux.scala:30:73] wire out_uop_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] out_uop_1_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] out_uop_1_bits_ras_head; // @[Mux.scala:30:73] wire out_uop_1_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] out_uop_1_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] out_uop_1_bits_mem_size; // @[Mux.scala:30:73] wire out_uop_2_valid; // @[Mux.scala:30:73] wire [31:0] out_uop_2_bits_inst; // @[Mux.scala:30:73] wire [31:0] out_uop_2_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] out_uop_2_bits_pc; // @[Mux.scala:30:73] wire out_uop_2_bits_edge_inst; // @[Mux.scala:30:73] wire out_uop_2_bits_rvc; // @[Mux.scala:30:73] wire out_uop_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire out_uop_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] out_uop_2_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] out_uop_2_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] out_uop_2_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] out_uop_2_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire out_uop_2_bits_sfb_br; // @[Mux.scala:30:73] wire out_uop_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] out_uop_2_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] out_uop_2_bits_ras_head; // @[Mux.scala:30:73] wire out_uop_2_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] out_uop_2_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] out_uop_2_bits_mem_size; // @[Mux.scala:30:73] wire out_uop_3_valid; // @[Mux.scala:30:73] wire [31:0] out_uop_3_bits_inst; // @[Mux.scala:30:73] wire [31:0] out_uop_3_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] out_uop_3_bits_pc; // @[Mux.scala:30:73] wire out_uop_3_bits_edge_inst; // @[Mux.scala:30:73] wire out_uop_3_bits_rvc; // @[Mux.scala:30:73] wire out_uop_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire out_uop_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] out_uop_3_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] out_uop_3_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] out_uop_3_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] out_uop_3_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire out_uop_3_bits_sfb_br; // @[Mux.scala:30:73] wire out_uop_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] out_uop_3_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] out_uop_3_bits_ras_head; // @[Mux.scala:30:73] wire out_uop_3_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] out_uop_3_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] out_uop_3_bits_mem_size; // @[Mux.scala:30:73] wire io_enq_ready_0; // @[FetchBuffer.scala:16:7] wire [7:0] io_deq_0_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7] wire [3:0] io_deq_0_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7] wire [38:0] io_deq_0_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7] wire [5:0] io_deq_0_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_deq_0_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_deq_0_bits_inst_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_deq_0_bits_raw_inst_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_deq_0_bits_pc_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_edge_inst_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_rvc_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_sfb_br_0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_0_bits_ras_head_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_bits_xcpt_0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_0_bits_xcpt_cause_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_0_bits_mem_size_0; // @[FetchBuffer.scala:16:7] wire io_deq_0_valid_0; // @[FetchBuffer.scala:16:7] wire [7:0] io_deq_1_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7] wire [3:0] io_deq_1_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7] wire [38:0] io_deq_1_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7] wire [5:0] io_deq_1_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_deq_1_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_deq_1_bits_inst_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_deq_1_bits_raw_inst_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_deq_1_bits_pc_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_edge_inst_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_rvc_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_sfb_br_0; // @[FetchBuffer.scala:16:7] wire [2:0] io_deq_1_bits_ras_head_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_bits_xcpt_0; // @[FetchBuffer.scala:16:7] wire [63:0] io_deq_1_bits_xcpt_cause_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_deq_1_bits_mem_size_0; // @[FetchBuffer.scala:16:7] wire io_deq_1_valid_0; // @[FetchBuffer.scala:16:7] wire [7:0] io_peek_0_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7] wire [3:0] io_peek_0_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7] wire [38:0] io_peek_0_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7] wire [5:0] io_peek_0_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_peek_0_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_peek_0_bits_inst_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_peek_0_bits_raw_inst_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_peek_0_bits_pc_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_edge_inst_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_rvc_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_sfb_br_0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_0_bits_ras_head_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_bits_xcpt_0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_0_bits_xcpt_cause_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_0_bits_mem_size_0; // @[FetchBuffer.scala:16:7] wire io_peek_0_valid_0; // @[FetchBuffer.scala:16:7] wire [7:0] io_peek_1_bits_btb_resp_bits_bht_history_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_btb_resp_bits_bht_value_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_btb_resp_bits_cfiType_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_btb_resp_bits_taken_0; // @[FetchBuffer.scala:16:7] wire [3:0] io_peek_1_bits_btb_resp_bits_mask_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_btb_resp_bits_bridx_0; // @[FetchBuffer.scala:16:7] wire [38:0] io_peek_1_bits_btb_resp_bits_target_0; // @[FetchBuffer.scala:16:7] wire [5:0] io_peek_1_bits_btb_resp_bits_entry_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_btb_resp_valid_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_peek_1_bits_next_pc_bits_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_peek_1_bits_inst_0; // @[FetchBuffer.scala:16:7] wire [31:0] io_peek_1_bits_raw_inst_0; // @[FetchBuffer.scala:16:7] wire [39:0] io_peek_1_bits_pc_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_edge_inst_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_rvc_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_sfb_br_0; // @[FetchBuffer.scala:16:7] wire [2:0] io_peek_1_bits_ras_head_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_bits_xcpt_0; // @[FetchBuffer.scala:16:7] wire [63:0] io_peek_1_bits_xcpt_cause_0; // @[FetchBuffer.scala:16:7] wire [1:0] io_peek_1_bits_mem_size_0; // @[FetchBuffer.scala:16:7] wire io_peek_1_valid_0; // @[FetchBuffer.scala:16:7] reg ram_0_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_0_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_0_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_0_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_0_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_0_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_0_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_0_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_0_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_0_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_0_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_0_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_0_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_0_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_0_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_0_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_0_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_0_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_0_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_0_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_0_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_0_bits_mem_size; // @[FetchBuffer.scala:28:16] reg ram_1_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_1_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_1_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_1_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_1_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_1_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_1_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_1_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_1_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_1_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_1_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_1_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_1_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_1_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_1_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_1_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_1_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_1_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_1_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_1_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_1_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_1_bits_mem_size; // @[FetchBuffer.scala:28:16] reg ram_2_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_2_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_2_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_2_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_2_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_2_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_2_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_2_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_2_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_2_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_2_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_2_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_2_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_2_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_2_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_2_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_2_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_2_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_2_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_2_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_2_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_2_bits_mem_size; // @[FetchBuffer.scala:28:16] reg ram_3_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_3_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_3_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_3_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_3_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_3_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_3_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_3_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_3_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_3_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_3_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_3_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_3_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_3_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_3_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_3_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_3_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_3_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_3_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_3_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_3_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_3_bits_mem_size; // @[FetchBuffer.scala:28:16] reg ram_4_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_4_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_4_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_4_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_4_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_4_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_4_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_4_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_4_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_4_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_4_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_4_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_4_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_4_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_4_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_4_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_4_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_4_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_4_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_4_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_4_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_4_bits_mem_size; // @[FetchBuffer.scala:28:16] reg ram_5_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_5_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_5_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_5_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_5_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_5_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_5_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_5_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_5_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_5_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_5_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_5_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_5_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_5_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_5_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_5_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_5_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_5_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_5_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_5_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_5_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_5_bits_mem_size; // @[FetchBuffer.scala:28:16] reg ram_6_valid; // @[FetchBuffer.scala:28:16] reg [31:0] ram_6_bits_inst; // @[FetchBuffer.scala:28:16] reg [31:0] ram_6_bits_raw_inst; // @[FetchBuffer.scala:28:16] reg [39:0] ram_6_bits_pc; // @[FetchBuffer.scala:28:16] reg ram_6_bits_edge_inst; // @[FetchBuffer.scala:28:16] reg ram_6_bits_rvc; // @[FetchBuffer.scala:28:16] reg ram_6_bits_btb_resp_valid; // @[FetchBuffer.scala:28:16] reg [1:0] ram_6_bits_btb_resp_bits_cfiType; // @[FetchBuffer.scala:28:16] reg ram_6_bits_btb_resp_bits_taken; // @[FetchBuffer.scala:28:16] reg [3:0] ram_6_bits_btb_resp_bits_mask; // @[FetchBuffer.scala:28:16] reg [1:0] ram_6_bits_btb_resp_bits_bridx; // @[FetchBuffer.scala:28:16] reg [38:0] ram_6_bits_btb_resp_bits_target; // @[FetchBuffer.scala:28:16] reg [5:0] ram_6_bits_btb_resp_bits_entry; // @[FetchBuffer.scala:28:16] reg [7:0] ram_6_bits_btb_resp_bits_bht_history; // @[FetchBuffer.scala:28:16] reg [1:0] ram_6_bits_btb_resp_bits_bht_value; // @[FetchBuffer.scala:28:16] reg ram_6_bits_sfb_br; // @[FetchBuffer.scala:28:16] reg ram_6_bits_next_pc_valid; // @[FetchBuffer.scala:28:16] reg [39:0] ram_6_bits_next_pc_bits; // @[FetchBuffer.scala:28:16] reg [2:0] ram_6_bits_ras_head; // @[FetchBuffer.scala:28:16] reg ram_6_bits_xcpt; // @[FetchBuffer.scala:28:16] reg [63:0] ram_6_bits_xcpt_cause; // @[FetchBuffer.scala:28:16] reg [1:0] ram_6_bits_mem_size; // @[FetchBuffer.scala:28:16] reg [6:0] enq_ptr; // @[FetchBuffer.scala:29:24] reg [6:0] deq_ptr; // @[FetchBuffer.scala:30:24] wire [1:0] _io_enq_ready_T = {1'h0, ram_1_valid} + {1'h0, ram_2_valid}; // @[FetchBuffer.scala:28:16, :32:27] wire [1:0] _io_enq_ready_T_1 = _io_enq_ready_T; // @[FetchBuffer.scala:32:27] wire [2:0] _io_enq_ready_T_2 = {2'h0, ram_0_valid} + {1'h0, _io_enq_ready_T_1}; // @[FetchBuffer.scala:28:16, :32:27] wire [1:0] _io_enq_ready_T_3 = _io_enq_ready_T_2[1:0]; // @[FetchBuffer.scala:32:27] wire [1:0] _io_enq_ready_T_4 = {1'h0, ram_3_valid} + {1'h0, ram_4_valid}; // @[FetchBuffer.scala:28:16, :32:27] wire [1:0] _io_enq_ready_T_5 = _io_enq_ready_T_4; // @[FetchBuffer.scala:32:27] wire [1:0] _io_enq_ready_T_6 = {1'h0, ram_5_valid} + {1'h0, ram_6_valid}; // @[FetchBuffer.scala:28:16, :32:27] wire [1:0] _io_enq_ready_T_7 = _io_enq_ready_T_6; // @[FetchBuffer.scala:32:27] wire [2:0] _io_enq_ready_T_8 = {1'h0, _io_enq_ready_T_5} + {1'h0, _io_enq_ready_T_7}; // @[FetchBuffer.scala:32:27] wire [2:0] _io_enq_ready_T_9 = _io_enq_ready_T_8; // @[FetchBuffer.scala:32:27] wire [3:0] _io_enq_ready_T_10 = {2'h0, _io_enq_ready_T_3} + {1'h0, _io_enq_ready_T_9}; // @[FetchBuffer.scala:32:27] wire [2:0] _io_enq_ready_T_11 = _io_enq_ready_T_10[2:0]; // @[FetchBuffer.scala:32:27] wire _io_enq_ready_T_12 = io_enq_bits_mask_0[0]; // @[FetchBuffer.scala:16:7, :32:57] wire _in_uops_0_valid_T = io_enq_bits_mask_0[0]; // @[FetchBuffer.scala:16:7, :32:57, :44:71] wire _enq_ptr_T = io_enq_bits_mask_0[0]; // @[FetchBuffer.scala:16:7, :32:57, :89:44] wire _io_enq_ready_T_13 = io_enq_bits_mask_0[1]; // @[FetchBuffer.scala:16:7, :32:57] wire _in_uops_1_valid_T = io_enq_bits_mask_0[1]; // @[FetchBuffer.scala:16:7, :32:57, :44:71] wire _enq_ptr_T_1 = io_enq_bits_mask_0[1]; // @[FetchBuffer.scala:16:7, :32:57, :89:44] wire _io_enq_ready_T_14 = io_enq_bits_mask_0[2]; // @[FetchBuffer.scala:16:7, :32:57] wire _in_uops_2_valid_T = io_enq_bits_mask_0[2]; // @[FetchBuffer.scala:16:7, :32:57, :44:71] wire _enq_ptr_T_2 = io_enq_bits_mask_0[2]; // @[FetchBuffer.scala:16:7, :32:57, :89:44] wire _io_enq_ready_T_15 = io_enq_bits_mask_0[3]; // @[FetchBuffer.scala:16:7, :32:57] wire _in_uops_3_valid_T = io_enq_bits_mask_0[3]; // @[FetchBuffer.scala:16:7, :32:57, :44:71] wire _enq_ptr_T_3 = io_enq_bits_mask_0[3]; // @[FetchBuffer.scala:16:7, :32:57, :89:44] wire [1:0] _io_enq_ready_T_16 = {1'h0, _io_enq_ready_T_12} + {1'h0, _io_enq_ready_T_13}; // @[FetchBuffer.scala:32:57] wire [1:0] _io_enq_ready_T_17 = _io_enq_ready_T_16; // @[FetchBuffer.scala:32:57] wire [1:0] _io_enq_ready_T_18 = {1'h0, _io_enq_ready_T_14} + {1'h0, _io_enq_ready_T_15}; // @[FetchBuffer.scala:32:57] wire [1:0] _io_enq_ready_T_19 = _io_enq_ready_T_18; // @[FetchBuffer.scala:32:57] wire [2:0] _io_enq_ready_T_20 = {1'h0, _io_enq_ready_T_17} + {1'h0, _io_enq_ready_T_19}; // @[FetchBuffer.scala:32:57] wire [2:0] _io_enq_ready_T_21 = _io_enq_ready_T_20; // @[FetchBuffer.scala:32:57] wire [3:0] _io_enq_ready_T_22 = {1'h0, _io_enq_ready_T_11} + {1'h0, _io_enq_ready_T_21}; // @[FetchBuffer.scala:32:{27,46,57}] assign _io_enq_ready_T_23 = ~(_io_enq_ready_T_22[3]); // @[FetchBuffer.scala:32:{46,76}] assign io_enq_ready_0 = _io_enq_ready_T_23; // @[FetchBuffer.scala:16:7, :32:76] wire _in_uops_0_valid_T_1; // @[FetchBuffer.scala:44:52] wire _in_uops_0_bits_rvc_T_1; // @[FetchBuffer.scala:51:65] wire _in_uops_0_bits_sfb_br_T_6; // @[FetchBuffer.scala:52:114] wire _in_uops_0_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:54:65] wire _in_uops_0_bits_xcpt_T; // @[FetchBuffer.scala:60:52] wire [1:0] _in_uops_0_bits_mem_size_T; // @[FetchBuffer.scala:57:63] wire _in_uops_1_valid_T_1; // @[FetchBuffer.scala:44:52] wire _in_uops_1_bits_rvc_T_1; // @[FetchBuffer.scala:51:65] wire _in_uops_1_bits_sfb_br_T_6; // @[FetchBuffer.scala:52:114] wire _in_uops_1_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:54:65] wire _in_uops_1_bits_xcpt_T; // @[FetchBuffer.scala:60:52] wire [1:0] _in_uops_1_bits_mem_size_T; // @[FetchBuffer.scala:57:63] wire _in_uops_2_valid_T_1; // @[FetchBuffer.scala:44:52] wire _in_uops_2_bits_rvc_T_1; // @[FetchBuffer.scala:51:65] wire _in_uops_2_bits_sfb_br_T_6; // @[FetchBuffer.scala:52:114] wire _in_uops_2_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:54:65] wire _in_uops_2_bits_xcpt_T; // @[FetchBuffer.scala:60:52] wire [1:0] _in_uops_2_bits_mem_size_T; // @[FetchBuffer.scala:57:63] wire _in_uops_3_valid_T_1; // @[FetchBuffer.scala:44:52] wire _in_uops_3_bits_rvc_T_1; // @[FetchBuffer.scala:51:65] wire _in_uops_3_bits_sfb_br_T_6; // @[FetchBuffer.scala:52:114] wire _in_uops_3_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:54:65] wire _in_uops_3_bits_xcpt_T; // @[FetchBuffer.scala:60:52] wire [1:0] _in_uops_3_bits_mem_size_T; // @[FetchBuffer.scala:57:63] wire in_uops_0_bits_next_pc_valid; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_edge_inst; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_rvc; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_sfb_br; // @[FetchBuffer.scala:35:21] wire in_uops_0_bits_xcpt; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_0_bits_xcpt_cause; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_0_bits_mem_size; // @[FetchBuffer.scala:35:21] wire in_uops_0_valid; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_next_pc_valid; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_rvc; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_sfb_br; // @[FetchBuffer.scala:35:21] wire in_uops_1_bits_xcpt; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_1_bits_xcpt_cause; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_1_bits_mem_size; // @[FetchBuffer.scala:35:21] wire in_uops_1_valid; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_next_pc_valid; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_rvc; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_sfb_br; // @[FetchBuffer.scala:35:21] wire in_uops_2_bits_xcpt; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_2_bits_xcpt_cause; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_2_bits_mem_size; // @[FetchBuffer.scala:35:21] wire in_uops_2_valid; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_next_pc_valid; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_rvc; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_sfb_br; // @[FetchBuffer.scala:35:21] wire in_uops_3_bits_xcpt; // @[FetchBuffer.scala:35:21] wire [63:0] in_uops_3_bits_xcpt_cause; // @[FetchBuffer.scala:35:21] wire [1:0] in_uops_3_bits_mem_size; // @[FetchBuffer.scala:35:21] wire in_uops_3_valid; // @[FetchBuffer.scala:35:21] wire [3:0] lower; // @[FetchBuffer.scala:38:19] wire [2:0] _lower_T = io_enq_bits_mask_0[3:1]; // @[FetchBuffer.scala:16:7, :39:39] wire [2:0] _lower_T_1 = _lower_T; // @[Utils.scala:17:29] wire [2:0] _lower_T_2 = {1'h0, _lower_T[2:1]}; // @[Utils.scala:17:29] wire [2:0] _lower_T_3 = {2'h0, _lower_T[2]}; // @[Utils.scala:17:29] wire [2:0] _lower_T_4 = _lower_T_1 | _lower_T_2; // @[Utils.scala:17:{29,45}] wire [2:0] _lower_T_5 = _lower_T_4 | _lower_T_3; // @[Utils.scala:17:{29,45}] assign lower = {1'h0, _lower_T_5}; // @[Utils.scala:17:45] wire [3:0] _maybe_cfi_mask_T = ~lower; // @[FetchBuffer.scala:38:19, :40:43] wire [3:0] maybe_cfi_mask = io_enq_bits_mask_0 & _maybe_cfi_mask_T; // @[FetchBuffer.scala:16:7, :40:{41,43}] wire [1:0] _rvc_T = io_enq_bits_insts_0_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35] wire [1:0] _in_uops_0_bits_rvc_T = io_enq_bits_insts_0_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35, :51:59] wire rvc = _rvc_T != 2'h3; // @[FetchBuffer.scala:42:{35,41}] wire [31:0] _GEN = {17'h0, io_enq_bits_exp_insts_0_0[14:0] & 15'h707F}; // @[FetchBuffer.scala:16:7, :43:61] wire [31:0] _cond_br_T; // @[FetchBuffer.scala:43:61] assign _cond_br_T = _GEN; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_2; // @[FetchBuffer.scala:43:61] assign _cond_br_T_2 = _GEN; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_4; // @[FetchBuffer.scala:43:61] assign _cond_br_T_4 = _GEN; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_6; // @[FetchBuffer.scala:43:61] assign _cond_br_T_6 = _GEN; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_8; // @[FetchBuffer.scala:43:61] assign _cond_br_T_8 = _GEN; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_10; // @[FetchBuffer.scala:43:61] assign _cond_br_T_10 = _GEN; // @[FetchBuffer.scala:43:61] wire _cond_br_T_1 = _cond_br_T == 32'h1063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_3 = _cond_br_T_2 == 32'h5063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_5 = _cond_br_T_4 == 32'h7063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_7 = _cond_br_T_6 == 32'h63; // @[FetchBuffer.scala:43:61] wire _cond_br_T_9 = _cond_br_T_8 == 32'h4063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_11 = _cond_br_T_10 == 32'h6063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_12 = _cond_br_T_1 | _cond_br_T_3; // @[FetchBuffer.scala:43:61] wire _cond_br_T_13 = _cond_br_T_12 | _cond_br_T_5; // @[FetchBuffer.scala:43:61] wire _cond_br_T_14 = _cond_br_T_13 | _cond_br_T_7; // @[FetchBuffer.scala:43:61] wire _cond_br_T_15 = _cond_br_T_14 | _cond_br_T_9; // @[FetchBuffer.scala:43:61] wire cond_br = _cond_br_T_15 | _cond_br_T_11; // @[FetchBuffer.scala:43:61] assign _in_uops_0_valid_T_1 = io_enq_valid_0 & _in_uops_0_valid_T; // @[FetchBuffer.scala:16:7, :44:{52,71}] assign in_uops_0_valid = _in_uops_0_valid_T_1; // @[FetchBuffer.scala:35:21, :44:52] assign _in_uops_0_bits_rvc_T_1 = _in_uops_0_bits_rvc_T != 2'h3; // @[FetchBuffer.scala:51:{59,65}] assign in_uops_0_bits_rvc = _in_uops_0_bits_rvc_T_1; // @[FetchBuffer.scala:35:21, :51:65] wire _in_uops_0_bits_sfb_br_sign_T_1 = io_enq_bits_exp_insts_0_0[31]; // @[FetchBuffer.scala:16:7] wire _in_uops_0_bits_sfb_br_sign_T_2 = _in_uops_0_bits_sfb_br_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire in_uops_0_bits_sfb_br_sign = _in_uops_0_bits_sfb_br_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire in_uops_0_bits_sfb_br_hi_hi_hi = in_uops_0_bits_sfb_br_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _in_uops_0_bits_sfb_br_b30_20_T_1 = io_enq_bits_exp_insts_0_0[30:20]; // @[FetchBuffer.scala:16:7] wire [10:0] _in_uops_0_bits_sfb_br_b30_20_T_2 = _in_uops_0_bits_sfb_br_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] in_uops_0_bits_sfb_br_b30_20 = {11{in_uops_0_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] in_uops_0_bits_sfb_br_hi_hi_lo = in_uops_0_bits_sfb_br_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _in_uops_0_bits_sfb_br_b19_12_T_3 = io_enq_bits_exp_insts_0_0[19:12]; // @[FetchBuffer.scala:16:7] wire [7:0] _in_uops_0_bits_sfb_br_b19_12_T_4 = _in_uops_0_bits_sfb_br_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] in_uops_0_bits_sfb_br_b19_12 = {8{in_uops_0_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] in_uops_0_bits_sfb_br_hi_lo_hi = in_uops_0_bits_sfb_br_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _in_uops_0_bits_sfb_br_b11_T_4 = io_enq_bits_exp_insts_0_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_0_bits_sfb_br_b0_T_3 = io_enq_bits_exp_insts_0_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_0_bits_sfb_br_b11_T_5 = _in_uops_0_bits_sfb_br_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _in_uops_0_bits_sfb_br_b11_T_7 = io_enq_bits_exp_insts_0_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_0_bits_sfb_br_b0_T_1 = io_enq_bits_exp_insts_0_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_0_bits_sfb_br_b11_T_8 = _in_uops_0_bits_sfb_br_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _in_uops_0_bits_sfb_br_b11_T_9 = _in_uops_0_bits_sfb_br_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _in_uops_0_bits_sfb_br_b11_T_10 = _in_uops_0_bits_sfb_br_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire in_uops_0_bits_sfb_br_b11 = _in_uops_0_bits_sfb_br_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire in_uops_0_bits_sfb_br_hi_lo_lo = in_uops_0_bits_sfb_br_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _in_uops_0_bits_sfb_br_b10_5_T_3 = io_enq_bits_exp_insts_0_0[30:25]; // @[FetchBuffer.scala:16:7] wire [5:0] in_uops_0_bits_sfb_br_b10_5 = _in_uops_0_bits_sfb_br_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _in_uops_0_bits_sfb_br_b4_1_T_4 = io_enq_bits_exp_insts_0_0[11:8]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_0_bits_sfb_br_b4_1_T_9 = _in_uops_0_bits_sfb_br_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _in_uops_0_bits_sfb_br_b4_1_T_6 = io_enq_bits_exp_insts_0_0[19:16]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_0_bits_sfb_br_b4_1_T_7 = io_enq_bits_exp_insts_0_0[24:21]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_0_bits_sfb_br_b4_1_T_8 = _in_uops_0_bits_sfb_br_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] in_uops_0_bits_sfb_br_b4_1 = _in_uops_0_bits_sfb_br_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _in_uops_0_bits_sfb_br_b0_T_5 = io_enq_bits_exp_insts_0_0[15]; // @[FetchBuffer.scala:16:7] wire [9:0] in_uops_0_bits_sfb_br_lo_hi = {in_uops_0_bits_sfb_br_b10_5, in_uops_0_bits_sfb_br_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] in_uops_0_bits_sfb_br_lo = {in_uops_0_bits_sfb_br_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] in_uops_0_bits_sfb_br_hi_lo = {in_uops_0_bits_sfb_br_hi_lo_hi, in_uops_0_bits_sfb_br_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] in_uops_0_bits_sfb_br_hi_hi = {in_uops_0_bits_sfb_br_hi_hi_hi, in_uops_0_bits_sfb_br_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] in_uops_0_bits_sfb_br_hi = {in_uops_0_bits_sfb_br_hi_hi, in_uops_0_bits_sfb_br_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_0_bits_sfb_br_T = {in_uops_0_bits_sfb_br_hi, in_uops_0_bits_sfb_br_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_0_bits_sfb_br_T_1 = _in_uops_0_bits_sfb_br_T; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _in_uops_0_bits_sfb_br_T_2 = {2'h1, ~rvc, 1'h0}; // @[FetchBuffer.scala:42:41, :52:98] wire _in_uops_0_bits_sfb_br_T_3 = _in_uops_0_bits_sfb_br_T_1 == {{28{_in_uops_0_bits_sfb_br_T_2[3]}}, _in_uops_0_bits_sfb_br_T_2}; // @[FetchBuffer.scala:52:{91,98}] wire _in_uops_0_bits_sfb_br_T_4 = cond_br & _in_uops_0_bits_sfb_br_T_3; // @[FetchBuffer.scala:52:{47,91}] wire _in_uops_0_bits_sfb_br_T_5 = ~io_enq_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7, :52:117] assign _in_uops_0_bits_sfb_br_T_6 = _in_uops_0_bits_sfb_br_T_4 & _in_uops_0_bits_sfb_br_T_5; // @[FetchBuffer.scala:52:{47,114,117}] assign in_uops_0_bits_sfb_br = _in_uops_0_bits_sfb_br_T_6; // @[FetchBuffer.scala:35:21, :52:114] wire _in_uops_0_bits_next_pc_valid_T = maybe_cfi_mask[0]; // @[FetchBuffer.scala:40:41, :54:82] assign _in_uops_0_bits_next_pc_valid_T_1 = io_enq_bits_next_pc_valid_0 & _in_uops_0_bits_next_pc_valid_T; // @[FetchBuffer.scala:16:7, :54:{65,82}] assign in_uops_0_bits_next_pc_valid = _in_uops_0_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:35:21, :54:65] assign _in_uops_0_bits_mem_size_T = io_enq_bits_exp_insts_0_0[13:12]; // @[FetchBuffer.scala:16:7, :57:63] assign in_uops_0_bits_mem_size = _in_uops_0_bits_mem_size_T; // @[FetchBuffer.scala:35:21, :57:63] wire _GEN_0 = io_enq_bits_xcpt_pf_if_0 | io_enq_bits_xcpt_ae_if_0; // @[FetchBuffer.scala:16:7, :60:52] assign _in_uops_0_bits_xcpt_T = _GEN_0; // @[FetchBuffer.scala:60:52] assign _in_uops_1_bits_xcpt_T = _GEN_0; // @[FetchBuffer.scala:60:52] assign _in_uops_2_bits_xcpt_T = _GEN_0; // @[FetchBuffer.scala:60:52] assign _in_uops_3_bits_xcpt_T = _GEN_0; // @[FetchBuffer.scala:60:52] assign in_uops_0_bits_xcpt = _in_uops_0_bits_xcpt_T; // @[FetchBuffer.scala:35:21, :60:52] assign in_uops_0_bits_edge_inst = _in_uops_0_bits_edge_inst_T; // @[FetchBuffer.scala:35:21, :61:45] wire [3:0] _GEN_1 = io_enq_bits_xcpt_pf_if_0 ? 4'hC : 4'h1; // @[FetchBuffer.scala:16:7, :62:38] wire [3:0] _in_uops_0_bits_xcpt_cause_T; // @[FetchBuffer.scala:62:38] assign _in_uops_0_bits_xcpt_cause_T = _GEN_1; // @[FetchBuffer.scala:62:38] wire [3:0] _in_uops_1_bits_xcpt_cause_T; // @[FetchBuffer.scala:62:38] assign _in_uops_1_bits_xcpt_cause_T = _GEN_1; // @[FetchBuffer.scala:62:38] wire [3:0] _in_uops_2_bits_xcpt_cause_T; // @[FetchBuffer.scala:62:38] assign _in_uops_2_bits_xcpt_cause_T = _GEN_1; // @[FetchBuffer.scala:62:38] wire [3:0] _in_uops_3_bits_xcpt_cause_T; // @[FetchBuffer.scala:62:38] assign _in_uops_3_bits_xcpt_cause_T = _GEN_1; // @[FetchBuffer.scala:62:38] assign in_uops_0_bits_xcpt_cause = {60'h0, _in_uops_0_bits_xcpt_cause_T}; // @[FetchBuffer.scala:35:21, :62:{32,38}] wire [1:0] _rvc_T_1 = io_enq_bits_insts_1_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35] wire [1:0] _in_uops_1_bits_rvc_T = io_enq_bits_insts_1_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35, :51:59] wire rvc_1 = _rvc_T_1 != 2'h3; // @[FetchBuffer.scala:42:{35,41}] wire [31:0] _GEN_2 = {17'h0, io_enq_bits_exp_insts_1_0[14:0] & 15'h707F}; // @[FetchBuffer.scala:16:7, :43:61] wire [31:0] _cond_br_T_16; // @[FetchBuffer.scala:43:61] assign _cond_br_T_16 = _GEN_2; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_18; // @[FetchBuffer.scala:43:61] assign _cond_br_T_18 = _GEN_2; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_20; // @[FetchBuffer.scala:43:61] assign _cond_br_T_20 = _GEN_2; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_22; // @[FetchBuffer.scala:43:61] assign _cond_br_T_22 = _GEN_2; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_24; // @[FetchBuffer.scala:43:61] assign _cond_br_T_24 = _GEN_2; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_26; // @[FetchBuffer.scala:43:61] assign _cond_br_T_26 = _GEN_2; // @[FetchBuffer.scala:43:61] wire _cond_br_T_17 = _cond_br_T_16 == 32'h1063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_19 = _cond_br_T_18 == 32'h5063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_21 = _cond_br_T_20 == 32'h7063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_23 = _cond_br_T_22 == 32'h63; // @[FetchBuffer.scala:43:61] wire _cond_br_T_25 = _cond_br_T_24 == 32'h4063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_27 = _cond_br_T_26 == 32'h6063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_28 = _cond_br_T_17 | _cond_br_T_19; // @[FetchBuffer.scala:43:61] wire _cond_br_T_29 = _cond_br_T_28 | _cond_br_T_21; // @[FetchBuffer.scala:43:61] wire _cond_br_T_30 = _cond_br_T_29 | _cond_br_T_23; // @[FetchBuffer.scala:43:61] wire _cond_br_T_31 = _cond_br_T_30 | _cond_br_T_25; // @[FetchBuffer.scala:43:61] wire cond_br_1 = _cond_br_T_31 | _cond_br_T_27; // @[FetchBuffer.scala:43:61] assign _in_uops_1_valid_T_1 = io_enq_valid_0 & _in_uops_1_valid_T; // @[FetchBuffer.scala:16:7, :44:{52,71}] assign in_uops_1_valid = _in_uops_1_valid_T_1; // @[FetchBuffer.scala:35:21, :44:52] assign _in_uops_1_bits_rvc_T_1 = _in_uops_1_bits_rvc_T != 2'h3; // @[FetchBuffer.scala:51:{59,65}] assign in_uops_1_bits_rvc = _in_uops_1_bits_rvc_T_1; // @[FetchBuffer.scala:35:21, :51:65] wire _in_uops_1_bits_sfb_br_sign_T_1 = io_enq_bits_exp_insts_1_0[31]; // @[FetchBuffer.scala:16:7] wire _in_uops_1_bits_sfb_br_sign_T_2 = _in_uops_1_bits_sfb_br_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire in_uops_1_bits_sfb_br_sign = _in_uops_1_bits_sfb_br_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire in_uops_1_bits_sfb_br_hi_hi_hi = in_uops_1_bits_sfb_br_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _in_uops_1_bits_sfb_br_b30_20_T_1 = io_enq_bits_exp_insts_1_0[30:20]; // @[FetchBuffer.scala:16:7] wire [10:0] _in_uops_1_bits_sfb_br_b30_20_T_2 = _in_uops_1_bits_sfb_br_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] in_uops_1_bits_sfb_br_b30_20 = {11{in_uops_1_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] in_uops_1_bits_sfb_br_hi_hi_lo = in_uops_1_bits_sfb_br_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _in_uops_1_bits_sfb_br_b19_12_T_3 = io_enq_bits_exp_insts_1_0[19:12]; // @[FetchBuffer.scala:16:7] wire [7:0] _in_uops_1_bits_sfb_br_b19_12_T_4 = _in_uops_1_bits_sfb_br_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] in_uops_1_bits_sfb_br_b19_12 = {8{in_uops_1_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] in_uops_1_bits_sfb_br_hi_lo_hi = in_uops_1_bits_sfb_br_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _in_uops_1_bits_sfb_br_b11_T_4 = io_enq_bits_exp_insts_1_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_1_bits_sfb_br_b0_T_3 = io_enq_bits_exp_insts_1_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_1_bits_sfb_br_b11_T_5 = _in_uops_1_bits_sfb_br_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _in_uops_1_bits_sfb_br_b11_T_7 = io_enq_bits_exp_insts_1_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_1_bits_sfb_br_b0_T_1 = io_enq_bits_exp_insts_1_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_1_bits_sfb_br_b11_T_8 = _in_uops_1_bits_sfb_br_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _in_uops_1_bits_sfb_br_b11_T_9 = _in_uops_1_bits_sfb_br_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _in_uops_1_bits_sfb_br_b11_T_10 = _in_uops_1_bits_sfb_br_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire in_uops_1_bits_sfb_br_b11 = _in_uops_1_bits_sfb_br_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire in_uops_1_bits_sfb_br_hi_lo_lo = in_uops_1_bits_sfb_br_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _in_uops_1_bits_sfb_br_b10_5_T_3 = io_enq_bits_exp_insts_1_0[30:25]; // @[FetchBuffer.scala:16:7] wire [5:0] in_uops_1_bits_sfb_br_b10_5 = _in_uops_1_bits_sfb_br_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _in_uops_1_bits_sfb_br_b4_1_T_4 = io_enq_bits_exp_insts_1_0[11:8]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_1_bits_sfb_br_b4_1_T_9 = _in_uops_1_bits_sfb_br_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _in_uops_1_bits_sfb_br_b4_1_T_6 = io_enq_bits_exp_insts_1_0[19:16]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_1_bits_sfb_br_b4_1_T_7 = io_enq_bits_exp_insts_1_0[24:21]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_1_bits_sfb_br_b4_1_T_8 = _in_uops_1_bits_sfb_br_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] in_uops_1_bits_sfb_br_b4_1 = _in_uops_1_bits_sfb_br_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _in_uops_1_bits_sfb_br_b0_T_5 = io_enq_bits_exp_insts_1_0[15]; // @[FetchBuffer.scala:16:7] wire [9:0] in_uops_1_bits_sfb_br_lo_hi = {in_uops_1_bits_sfb_br_b10_5, in_uops_1_bits_sfb_br_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] in_uops_1_bits_sfb_br_lo = {in_uops_1_bits_sfb_br_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] in_uops_1_bits_sfb_br_hi_lo = {in_uops_1_bits_sfb_br_hi_lo_hi, in_uops_1_bits_sfb_br_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] in_uops_1_bits_sfb_br_hi_hi = {in_uops_1_bits_sfb_br_hi_hi_hi, in_uops_1_bits_sfb_br_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] in_uops_1_bits_sfb_br_hi = {in_uops_1_bits_sfb_br_hi_hi, in_uops_1_bits_sfb_br_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_1_bits_sfb_br_T = {in_uops_1_bits_sfb_br_hi, in_uops_1_bits_sfb_br_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_1_bits_sfb_br_T_1 = _in_uops_1_bits_sfb_br_T; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _in_uops_1_bits_sfb_br_T_2 = {2'h1, ~rvc_1, 1'h0}; // @[FetchBuffer.scala:42:41, :52:98] wire _in_uops_1_bits_sfb_br_T_3 = _in_uops_1_bits_sfb_br_T_1 == {{28{_in_uops_1_bits_sfb_br_T_2[3]}}, _in_uops_1_bits_sfb_br_T_2}; // @[FetchBuffer.scala:52:{91,98}] wire _in_uops_1_bits_sfb_br_T_4 = cond_br_1 & _in_uops_1_bits_sfb_br_T_3; // @[FetchBuffer.scala:52:{47,91}] wire _in_uops_1_bits_sfb_br_T_5 = ~io_enq_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7, :52:117] assign _in_uops_1_bits_sfb_br_T_6 = _in_uops_1_bits_sfb_br_T_4 & _in_uops_1_bits_sfb_br_T_5; // @[FetchBuffer.scala:52:{47,114,117}] assign in_uops_1_bits_sfb_br = _in_uops_1_bits_sfb_br_T_6; // @[FetchBuffer.scala:35:21, :52:114] wire _in_uops_1_bits_next_pc_valid_T = maybe_cfi_mask[1]; // @[FetchBuffer.scala:40:41, :54:82] assign _in_uops_1_bits_next_pc_valid_T_1 = io_enq_bits_next_pc_valid_0 & _in_uops_1_bits_next_pc_valid_T; // @[FetchBuffer.scala:16:7, :54:{65,82}] assign in_uops_1_bits_next_pc_valid = _in_uops_1_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:35:21, :54:65] assign _in_uops_1_bits_mem_size_T = io_enq_bits_exp_insts_1_0[13:12]; // @[FetchBuffer.scala:16:7, :57:63] assign in_uops_1_bits_mem_size = _in_uops_1_bits_mem_size_T; // @[FetchBuffer.scala:35:21, :57:63] assign in_uops_1_bits_xcpt = _in_uops_1_bits_xcpt_T; // @[FetchBuffer.scala:35:21, :60:52] assign in_uops_1_bits_xcpt_cause = {60'h0, _in_uops_1_bits_xcpt_cause_T}; // @[FetchBuffer.scala:35:21, :62:{32,38}] wire [1:0] _rvc_T_2 = io_enq_bits_insts_2_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35] wire [1:0] _in_uops_2_bits_rvc_T = io_enq_bits_insts_2_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35, :51:59] wire rvc_2 = _rvc_T_2 != 2'h3; // @[FetchBuffer.scala:42:{35,41}] wire [31:0] _GEN_3 = {17'h0, io_enq_bits_exp_insts_2_0[14:0] & 15'h707F}; // @[FetchBuffer.scala:16:7, :43:61] wire [31:0] _cond_br_T_32; // @[FetchBuffer.scala:43:61] assign _cond_br_T_32 = _GEN_3; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_34; // @[FetchBuffer.scala:43:61] assign _cond_br_T_34 = _GEN_3; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_36; // @[FetchBuffer.scala:43:61] assign _cond_br_T_36 = _GEN_3; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_38; // @[FetchBuffer.scala:43:61] assign _cond_br_T_38 = _GEN_3; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_40; // @[FetchBuffer.scala:43:61] assign _cond_br_T_40 = _GEN_3; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_42; // @[FetchBuffer.scala:43:61] assign _cond_br_T_42 = _GEN_3; // @[FetchBuffer.scala:43:61] wire _cond_br_T_33 = _cond_br_T_32 == 32'h1063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_35 = _cond_br_T_34 == 32'h5063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_37 = _cond_br_T_36 == 32'h7063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_39 = _cond_br_T_38 == 32'h63; // @[FetchBuffer.scala:43:61] wire _cond_br_T_41 = _cond_br_T_40 == 32'h4063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_43 = _cond_br_T_42 == 32'h6063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_44 = _cond_br_T_33 | _cond_br_T_35; // @[FetchBuffer.scala:43:61] wire _cond_br_T_45 = _cond_br_T_44 | _cond_br_T_37; // @[FetchBuffer.scala:43:61] wire _cond_br_T_46 = _cond_br_T_45 | _cond_br_T_39; // @[FetchBuffer.scala:43:61] wire _cond_br_T_47 = _cond_br_T_46 | _cond_br_T_41; // @[FetchBuffer.scala:43:61] wire cond_br_2 = _cond_br_T_47 | _cond_br_T_43; // @[FetchBuffer.scala:43:61] assign _in_uops_2_valid_T_1 = io_enq_valid_0 & _in_uops_2_valid_T; // @[FetchBuffer.scala:16:7, :44:{52,71}] assign in_uops_2_valid = _in_uops_2_valid_T_1; // @[FetchBuffer.scala:35:21, :44:52] assign _in_uops_2_bits_rvc_T_1 = _in_uops_2_bits_rvc_T != 2'h3; // @[FetchBuffer.scala:51:{59,65}] assign in_uops_2_bits_rvc = _in_uops_2_bits_rvc_T_1; // @[FetchBuffer.scala:35:21, :51:65] wire _in_uops_2_bits_sfb_br_sign_T_1 = io_enq_bits_exp_insts_2_0[31]; // @[FetchBuffer.scala:16:7] wire _in_uops_2_bits_sfb_br_sign_T_2 = _in_uops_2_bits_sfb_br_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire in_uops_2_bits_sfb_br_sign = _in_uops_2_bits_sfb_br_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire in_uops_2_bits_sfb_br_hi_hi_hi = in_uops_2_bits_sfb_br_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _in_uops_2_bits_sfb_br_b30_20_T_1 = io_enq_bits_exp_insts_2_0[30:20]; // @[FetchBuffer.scala:16:7] wire [10:0] _in_uops_2_bits_sfb_br_b30_20_T_2 = _in_uops_2_bits_sfb_br_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] in_uops_2_bits_sfb_br_b30_20 = {11{in_uops_2_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] in_uops_2_bits_sfb_br_hi_hi_lo = in_uops_2_bits_sfb_br_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _in_uops_2_bits_sfb_br_b19_12_T_3 = io_enq_bits_exp_insts_2_0[19:12]; // @[FetchBuffer.scala:16:7] wire [7:0] _in_uops_2_bits_sfb_br_b19_12_T_4 = _in_uops_2_bits_sfb_br_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] in_uops_2_bits_sfb_br_b19_12 = {8{in_uops_2_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] in_uops_2_bits_sfb_br_hi_lo_hi = in_uops_2_bits_sfb_br_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _in_uops_2_bits_sfb_br_b11_T_4 = io_enq_bits_exp_insts_2_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_2_bits_sfb_br_b0_T_3 = io_enq_bits_exp_insts_2_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_2_bits_sfb_br_b11_T_5 = _in_uops_2_bits_sfb_br_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _in_uops_2_bits_sfb_br_b11_T_7 = io_enq_bits_exp_insts_2_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_2_bits_sfb_br_b0_T_1 = io_enq_bits_exp_insts_2_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_2_bits_sfb_br_b11_T_8 = _in_uops_2_bits_sfb_br_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _in_uops_2_bits_sfb_br_b11_T_9 = _in_uops_2_bits_sfb_br_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _in_uops_2_bits_sfb_br_b11_T_10 = _in_uops_2_bits_sfb_br_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire in_uops_2_bits_sfb_br_b11 = _in_uops_2_bits_sfb_br_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire in_uops_2_bits_sfb_br_hi_lo_lo = in_uops_2_bits_sfb_br_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _in_uops_2_bits_sfb_br_b10_5_T_3 = io_enq_bits_exp_insts_2_0[30:25]; // @[FetchBuffer.scala:16:7] wire [5:0] in_uops_2_bits_sfb_br_b10_5 = _in_uops_2_bits_sfb_br_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _in_uops_2_bits_sfb_br_b4_1_T_4 = io_enq_bits_exp_insts_2_0[11:8]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_2_bits_sfb_br_b4_1_T_9 = _in_uops_2_bits_sfb_br_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _in_uops_2_bits_sfb_br_b4_1_T_6 = io_enq_bits_exp_insts_2_0[19:16]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_2_bits_sfb_br_b4_1_T_7 = io_enq_bits_exp_insts_2_0[24:21]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_2_bits_sfb_br_b4_1_T_8 = _in_uops_2_bits_sfb_br_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] in_uops_2_bits_sfb_br_b4_1 = _in_uops_2_bits_sfb_br_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _in_uops_2_bits_sfb_br_b0_T_5 = io_enq_bits_exp_insts_2_0[15]; // @[FetchBuffer.scala:16:7] wire [9:0] in_uops_2_bits_sfb_br_lo_hi = {in_uops_2_bits_sfb_br_b10_5, in_uops_2_bits_sfb_br_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] in_uops_2_bits_sfb_br_lo = {in_uops_2_bits_sfb_br_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] in_uops_2_bits_sfb_br_hi_lo = {in_uops_2_bits_sfb_br_hi_lo_hi, in_uops_2_bits_sfb_br_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] in_uops_2_bits_sfb_br_hi_hi = {in_uops_2_bits_sfb_br_hi_hi_hi, in_uops_2_bits_sfb_br_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] in_uops_2_bits_sfb_br_hi = {in_uops_2_bits_sfb_br_hi_hi, in_uops_2_bits_sfb_br_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_2_bits_sfb_br_T = {in_uops_2_bits_sfb_br_hi, in_uops_2_bits_sfb_br_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_2_bits_sfb_br_T_1 = _in_uops_2_bits_sfb_br_T; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _in_uops_2_bits_sfb_br_T_2 = {2'h1, ~rvc_2, 1'h0}; // @[FetchBuffer.scala:42:41, :52:98] wire _in_uops_2_bits_sfb_br_T_3 = _in_uops_2_bits_sfb_br_T_1 == {{28{_in_uops_2_bits_sfb_br_T_2[3]}}, _in_uops_2_bits_sfb_br_T_2}; // @[FetchBuffer.scala:52:{91,98}] wire _in_uops_2_bits_sfb_br_T_4 = cond_br_2 & _in_uops_2_bits_sfb_br_T_3; // @[FetchBuffer.scala:52:{47,91}] wire _in_uops_2_bits_sfb_br_T_5 = ~io_enq_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7, :52:117] assign _in_uops_2_bits_sfb_br_T_6 = _in_uops_2_bits_sfb_br_T_4 & _in_uops_2_bits_sfb_br_T_5; // @[FetchBuffer.scala:52:{47,114,117}] assign in_uops_2_bits_sfb_br = _in_uops_2_bits_sfb_br_T_6; // @[FetchBuffer.scala:35:21, :52:114] wire _in_uops_2_bits_next_pc_valid_T = maybe_cfi_mask[2]; // @[FetchBuffer.scala:40:41, :54:82] assign _in_uops_2_bits_next_pc_valid_T_1 = io_enq_bits_next_pc_valid_0 & _in_uops_2_bits_next_pc_valid_T; // @[FetchBuffer.scala:16:7, :54:{65,82}] assign in_uops_2_bits_next_pc_valid = _in_uops_2_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:35:21, :54:65] assign _in_uops_2_bits_mem_size_T = io_enq_bits_exp_insts_2_0[13:12]; // @[FetchBuffer.scala:16:7, :57:63] assign in_uops_2_bits_mem_size = _in_uops_2_bits_mem_size_T; // @[FetchBuffer.scala:35:21, :57:63] assign in_uops_2_bits_xcpt = _in_uops_2_bits_xcpt_T; // @[FetchBuffer.scala:35:21, :60:52] assign in_uops_2_bits_xcpt_cause = {60'h0, _in_uops_2_bits_xcpt_cause_T}; // @[FetchBuffer.scala:35:21, :62:{32,38}] wire [1:0] _rvc_T_3 = io_enq_bits_insts_3_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35] wire [1:0] _in_uops_3_bits_rvc_T = io_enq_bits_insts_3_0[1:0]; // @[FetchBuffer.scala:16:7, :42:35, :51:59] wire rvc_3 = _rvc_T_3 != 2'h3; // @[FetchBuffer.scala:42:{35,41}] wire [31:0] _GEN_4 = {17'h0, io_enq_bits_exp_insts_3_0[14:0] & 15'h707F}; // @[FetchBuffer.scala:16:7, :43:61] wire [31:0] _cond_br_T_48; // @[FetchBuffer.scala:43:61] assign _cond_br_T_48 = _GEN_4; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_50; // @[FetchBuffer.scala:43:61] assign _cond_br_T_50 = _GEN_4; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_52; // @[FetchBuffer.scala:43:61] assign _cond_br_T_52 = _GEN_4; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_54; // @[FetchBuffer.scala:43:61] assign _cond_br_T_54 = _GEN_4; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_56; // @[FetchBuffer.scala:43:61] assign _cond_br_T_56 = _GEN_4; // @[FetchBuffer.scala:43:61] wire [31:0] _cond_br_T_58; // @[FetchBuffer.scala:43:61] assign _cond_br_T_58 = _GEN_4; // @[FetchBuffer.scala:43:61] wire _cond_br_T_49 = _cond_br_T_48 == 32'h1063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_51 = _cond_br_T_50 == 32'h5063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_53 = _cond_br_T_52 == 32'h7063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_55 = _cond_br_T_54 == 32'h63; // @[FetchBuffer.scala:43:61] wire _cond_br_T_57 = _cond_br_T_56 == 32'h4063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_59 = _cond_br_T_58 == 32'h6063; // @[FetchBuffer.scala:43:61] wire _cond_br_T_60 = _cond_br_T_49 | _cond_br_T_51; // @[FetchBuffer.scala:43:61] wire _cond_br_T_61 = _cond_br_T_60 | _cond_br_T_53; // @[FetchBuffer.scala:43:61] wire _cond_br_T_62 = _cond_br_T_61 | _cond_br_T_55; // @[FetchBuffer.scala:43:61] wire _cond_br_T_63 = _cond_br_T_62 | _cond_br_T_57; // @[FetchBuffer.scala:43:61] wire cond_br_3 = _cond_br_T_63 | _cond_br_T_59; // @[FetchBuffer.scala:43:61] assign _in_uops_3_valid_T_1 = io_enq_valid_0 & _in_uops_3_valid_T; // @[FetchBuffer.scala:16:7, :44:{52,71}] assign in_uops_3_valid = _in_uops_3_valid_T_1; // @[FetchBuffer.scala:35:21, :44:52] assign _in_uops_3_bits_rvc_T_1 = _in_uops_3_bits_rvc_T != 2'h3; // @[FetchBuffer.scala:51:{59,65}] assign in_uops_3_bits_rvc = _in_uops_3_bits_rvc_T_1; // @[FetchBuffer.scala:35:21, :51:65] wire _in_uops_3_bits_sfb_br_sign_T_1 = io_enq_bits_exp_insts_3_0[31]; // @[FetchBuffer.scala:16:7] wire _in_uops_3_bits_sfb_br_sign_T_2 = _in_uops_3_bits_sfb_br_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire in_uops_3_bits_sfb_br_sign = _in_uops_3_bits_sfb_br_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire in_uops_3_bits_sfb_br_hi_hi_hi = in_uops_3_bits_sfb_br_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _in_uops_3_bits_sfb_br_b30_20_T_1 = io_enq_bits_exp_insts_3_0[30:20]; // @[FetchBuffer.scala:16:7] wire [10:0] _in_uops_3_bits_sfb_br_b30_20_T_2 = _in_uops_3_bits_sfb_br_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] in_uops_3_bits_sfb_br_b30_20 = {11{in_uops_3_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] in_uops_3_bits_sfb_br_hi_hi_lo = in_uops_3_bits_sfb_br_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _in_uops_3_bits_sfb_br_b19_12_T_3 = io_enq_bits_exp_insts_3_0[19:12]; // @[FetchBuffer.scala:16:7] wire [7:0] _in_uops_3_bits_sfb_br_b19_12_T_4 = _in_uops_3_bits_sfb_br_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] in_uops_3_bits_sfb_br_b19_12 = {8{in_uops_3_bits_sfb_br_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] in_uops_3_bits_sfb_br_hi_lo_hi = in_uops_3_bits_sfb_br_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _in_uops_3_bits_sfb_br_b11_T_4 = io_enq_bits_exp_insts_3_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_3_bits_sfb_br_b0_T_3 = io_enq_bits_exp_insts_3_0[20]; // @[FetchBuffer.scala:16:7] wire _in_uops_3_bits_sfb_br_b11_T_5 = _in_uops_3_bits_sfb_br_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _in_uops_3_bits_sfb_br_b11_T_7 = io_enq_bits_exp_insts_3_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_3_bits_sfb_br_b0_T_1 = io_enq_bits_exp_insts_3_0[7]; // @[FetchBuffer.scala:16:7] wire _in_uops_3_bits_sfb_br_b11_T_8 = _in_uops_3_bits_sfb_br_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _in_uops_3_bits_sfb_br_b11_T_9 = _in_uops_3_bits_sfb_br_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _in_uops_3_bits_sfb_br_b11_T_10 = _in_uops_3_bits_sfb_br_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire in_uops_3_bits_sfb_br_b11 = _in_uops_3_bits_sfb_br_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire in_uops_3_bits_sfb_br_hi_lo_lo = in_uops_3_bits_sfb_br_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _in_uops_3_bits_sfb_br_b10_5_T_3 = io_enq_bits_exp_insts_3_0[30:25]; // @[FetchBuffer.scala:16:7] wire [5:0] in_uops_3_bits_sfb_br_b10_5 = _in_uops_3_bits_sfb_br_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _in_uops_3_bits_sfb_br_b4_1_T_4 = io_enq_bits_exp_insts_3_0[11:8]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_3_bits_sfb_br_b4_1_T_9 = _in_uops_3_bits_sfb_br_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _in_uops_3_bits_sfb_br_b4_1_T_6 = io_enq_bits_exp_insts_3_0[19:16]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_3_bits_sfb_br_b4_1_T_7 = io_enq_bits_exp_insts_3_0[24:21]; // @[FetchBuffer.scala:16:7] wire [3:0] _in_uops_3_bits_sfb_br_b4_1_T_8 = _in_uops_3_bits_sfb_br_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] in_uops_3_bits_sfb_br_b4_1 = _in_uops_3_bits_sfb_br_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _in_uops_3_bits_sfb_br_b0_T_5 = io_enq_bits_exp_insts_3_0[15]; // @[FetchBuffer.scala:16:7] wire [9:0] in_uops_3_bits_sfb_br_lo_hi = {in_uops_3_bits_sfb_br_b10_5, in_uops_3_bits_sfb_br_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] in_uops_3_bits_sfb_br_lo = {in_uops_3_bits_sfb_br_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] in_uops_3_bits_sfb_br_hi_lo = {in_uops_3_bits_sfb_br_hi_lo_hi, in_uops_3_bits_sfb_br_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] in_uops_3_bits_sfb_br_hi_hi = {in_uops_3_bits_sfb_br_hi_hi_hi, in_uops_3_bits_sfb_br_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] in_uops_3_bits_sfb_br_hi = {in_uops_3_bits_sfb_br_hi_hi, in_uops_3_bits_sfb_br_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_3_bits_sfb_br_T = {in_uops_3_bits_sfb_br_hi, in_uops_3_bits_sfb_br_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _in_uops_3_bits_sfb_br_T_1 = _in_uops_3_bits_sfb_br_T; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _in_uops_3_bits_sfb_br_T_2 = {2'h1, ~rvc_3, 1'h0}; // @[FetchBuffer.scala:42:41, :52:98] wire _in_uops_3_bits_sfb_br_T_3 = _in_uops_3_bits_sfb_br_T_1 == {{28{_in_uops_3_bits_sfb_br_T_2[3]}}, _in_uops_3_bits_sfb_br_T_2}; // @[FetchBuffer.scala:52:{91,98}] wire _in_uops_3_bits_sfb_br_T_4 = cond_br_3 & _in_uops_3_bits_sfb_br_T_3; // @[FetchBuffer.scala:52:{47,91}] wire _in_uops_3_bits_sfb_br_T_5 = ~io_enq_bits_next_pc_valid_0; // @[FetchBuffer.scala:16:7, :52:117] assign _in_uops_3_bits_sfb_br_T_6 = _in_uops_3_bits_sfb_br_T_4 & _in_uops_3_bits_sfb_br_T_5; // @[FetchBuffer.scala:52:{47,114,117}] assign in_uops_3_bits_sfb_br = _in_uops_3_bits_sfb_br_T_6; // @[FetchBuffer.scala:35:21, :52:114] wire _in_uops_3_bits_next_pc_valid_T = maybe_cfi_mask[3]; // @[FetchBuffer.scala:40:41, :54:82] assign _in_uops_3_bits_next_pc_valid_T_1 = io_enq_bits_next_pc_valid_0 & _in_uops_3_bits_next_pc_valid_T; // @[FetchBuffer.scala:16:7, :54:{65,82}] assign in_uops_3_bits_next_pc_valid = _in_uops_3_bits_next_pc_valid_T_1; // @[FetchBuffer.scala:35:21, :54:65] assign _in_uops_3_bits_mem_size_T = io_enq_bits_exp_insts_3_0[13:12]; // @[FetchBuffer.scala:16:7, :57:63] assign in_uops_3_bits_mem_size = _in_uops_3_bits_mem_size_T; // @[FetchBuffer.scala:35:21, :57:63] assign in_uops_3_bits_xcpt = _in_uops_3_bits_xcpt_T; // @[FetchBuffer.scala:35:21, :60:52] assign in_uops_3_bits_xcpt_cause = {60'h0, _in_uops_3_bits_xcpt_cause_T}; // @[FetchBuffer.scala:35:21, :62:{32,38}] wire _write_mask_0_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_0_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_0_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_0_3_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_1_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_1_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_1_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_1_3_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_2_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_2_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_2_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_2_3_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_3_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_3_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_3_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_3_3_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_4_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_4_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_4_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_4_3_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_5_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_5_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_5_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_5_3_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_6_0_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_6_1_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_6_2_T_1; // @[FetchBuffer.scala:84:37] wire _write_mask_6_3_T_1; // @[FetchBuffer.scala:84:37] wire write_mask_0_0; // @[FetchBuffer.scala:78:24] wire write_mask_0_1; // @[FetchBuffer.scala:78:24] wire write_mask_0_2; // @[FetchBuffer.scala:78:24] wire write_mask_0_3; // @[FetchBuffer.scala:78:24] wire write_mask_1_0; // @[FetchBuffer.scala:78:24] wire write_mask_1_1; // @[FetchBuffer.scala:78:24] wire write_mask_1_2; // @[FetchBuffer.scala:78:24] wire write_mask_1_3; // @[FetchBuffer.scala:78:24] wire write_mask_2_0; // @[FetchBuffer.scala:78:24] wire write_mask_2_1; // @[FetchBuffer.scala:78:24] wire write_mask_2_2; // @[FetchBuffer.scala:78:24] wire write_mask_2_3; // @[FetchBuffer.scala:78:24] wire write_mask_3_0; // @[FetchBuffer.scala:78:24] wire write_mask_3_1; // @[FetchBuffer.scala:78:24] wire write_mask_3_2; // @[FetchBuffer.scala:78:24] wire write_mask_3_3; // @[FetchBuffer.scala:78:24] wire write_mask_4_0; // @[FetchBuffer.scala:78:24] wire write_mask_4_1; // @[FetchBuffer.scala:78:24] wire write_mask_4_2; // @[FetchBuffer.scala:78:24] wire write_mask_4_3; // @[FetchBuffer.scala:78:24] wire write_mask_5_0; // @[FetchBuffer.scala:78:24] wire write_mask_5_1; // @[FetchBuffer.scala:78:24] wire write_mask_5_2; // @[FetchBuffer.scala:78:24] wire write_mask_5_3; // @[FetchBuffer.scala:78:24] wire write_mask_6_0; // @[FetchBuffer.scala:78:24] wire write_mask_6_1; // @[FetchBuffer.scala:78:24] wire write_mask_6_2; // @[FetchBuffer.scala:78:24] wire write_mask_6_3; // @[FetchBuffer.scala:78:24] wire _write_mask_0_0_T = enq_ptr[0]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_0_0_T_1 = _write_mask_0_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_0_0 = _write_mask_0_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_1_0_T = enq_ptr[1]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_1_0_T_1 = _write_mask_1_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_1_0 = _write_mask_1_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_2_0_T = enq_ptr[2]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_2_0_T_1 = _write_mask_2_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_2_0 = _write_mask_2_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_3_0_T = enq_ptr[3]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_3_0_T_1 = _write_mask_3_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_3_0 = _write_mask_3_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_4_0_T = enq_ptr[4]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_4_0_T_1 = _write_mask_4_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_4_0 = _write_mask_4_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_5_0_T = enq_ptr[5]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_5_0_T_1 = _write_mask_5_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_5_0 = _write_mask_5_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_6_0_T = enq_ptr[6]; // @[FetchBuffer.scala:29:24, :84:33] assign _write_mask_6_0_T_1 = _write_mask_6_0_T & in_uops_0_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_6_0 = _write_mask_6_0_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire [6:0] _T_4 = in_uops_0_valid ? {enq_ptr[5:0], _write_mask_6_0_T} : enq_ptr; // @[FetchBuffer.scala:29:24, :35:21, :69:26, :84:33, :86:17] wire _write_mask_0_1_T = _T_4[0]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_0_1_T_1 = _write_mask_0_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_0_1 = _write_mask_0_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_1_1_T = _T_4[1]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_1_1_T_1 = _write_mask_1_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_1_1 = _write_mask_1_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_2_1_T = _T_4[2]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_2_1_T_1 = _write_mask_2_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_2_1 = _write_mask_2_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_3_1_T = _T_4[3]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_3_1_T_1 = _write_mask_3_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_3_1 = _write_mask_3_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_4_1_T = _T_4[4]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_4_1_T_1 = _write_mask_4_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_4_1 = _write_mask_4_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_5_1_T = _T_4[5]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_5_1_T_1 = _write_mask_5_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_5_1 = _write_mask_5_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_6_1_T = _T_4[6]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_6_1_T_1 = _write_mask_6_1_T & in_uops_1_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_6_1 = _write_mask_6_1_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire [6:0] _T_9 = in_uops_1_valid ? {_T_4[5:0], _write_mask_6_1_T} : _T_4; // @[FetchBuffer.scala:35:21, :69:26, :84:33, :86:17] wire _write_mask_0_2_T = _T_9[0]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_0_2_T_1 = _write_mask_0_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_0_2 = _write_mask_0_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_1_2_T = _T_9[1]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_1_2_T_1 = _write_mask_1_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_1_2 = _write_mask_1_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_2_2_T = _T_9[2]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_2_2_T_1 = _write_mask_2_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_2_2 = _write_mask_2_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_3_2_T = _T_9[3]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_3_2_T_1 = _write_mask_3_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_3_2 = _write_mask_3_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_4_2_T = _T_9[4]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_4_2_T_1 = _write_mask_4_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_4_2 = _write_mask_4_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_5_2_T = _T_9[5]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_5_2_T_1 = _write_mask_5_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_5_2 = _write_mask_5_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_6_2_T = _T_9[6]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_6_2_T_1 = _write_mask_6_2_T & in_uops_2_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_6_2 = _write_mask_6_2_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire [6:0] _T_14 = in_uops_2_valid ? {_T_9[5:0], _write_mask_6_2_T} : _T_9; // @[FetchBuffer.scala:35:21, :69:26, :84:33, :86:17] wire _write_mask_0_3_T = _T_14[0]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_0_3_T_1 = _write_mask_0_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_0_3 = _write_mask_0_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_1_3_T = _T_14[1]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_1_3_T_1 = _write_mask_1_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_1_3 = _write_mask_1_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_2_3_T = _T_14[2]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_2_3_T_1 = _write_mask_2_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_2_3 = _write_mask_2_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_3_3_T = _T_14[3]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_3_3_T_1 = _write_mask_3_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_3_3 = _write_mask_3_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_4_3_T = _T_14[4]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_4_3_T_1 = _write_mask_4_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_4_3 = _write_mask_4_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_5_3_T = _T_14[5]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_5_3_T_1 = _write_mask_5_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_5_3 = _write_mask_5_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire _write_mask_6_3_T = _T_14[6]; // @[FetchBuffer.scala:84:33, :86:17] assign _write_mask_6_3_T_1 = _write_mask_6_3_T & in_uops_3_valid; // @[FetchBuffer.scala:35:21, :84:{33,37}] assign write_mask_6_3 = _write_mask_6_3_T_1; // @[FetchBuffer.scala:78:24, :84:37] wire [1:0] _enq_ptr_T_4 = {1'h0, _enq_ptr_T} + {1'h0, _enq_ptr_T_1}; // @[FetchBuffer.scala:89:44] wire [1:0] _enq_ptr_T_5 = _enq_ptr_T_4; // @[FetchBuffer.scala:89:44] wire [1:0] _enq_ptr_T_6 = {1'h0, _enq_ptr_T_2} + {1'h0, _enq_ptr_T_3}; // @[FetchBuffer.scala:89:44] wire [1:0] _enq_ptr_T_7 = _enq_ptr_T_6; // @[FetchBuffer.scala:89:44] wire [2:0] _enq_ptr_T_8 = {1'h0, _enq_ptr_T_5} + {1'h0, _enq_ptr_T_7}; // @[FetchBuffer.scala:89:44] wire [2:0] _enq_ptr_T_9 = _enq_ptr_T_8; // @[FetchBuffer.scala:89:44] wire [13:0] _enq_ptr_full_T; // @[FetchBuffer.scala:75:16] wire [13:0] enq_ptr_full; // @[FetchBuffer.scala:74:20] assign _enq_ptr_full_T = {7'h0, enq_ptr} << _enq_ptr_T_9; // @[FetchBuffer.scala:29:24, :75:16, :89:44] assign enq_ptr_full = _enq_ptr_full_T; // @[FetchBuffer.scala:74:20, :75:16] wire [6:0] _enq_ptr_T_10 = enq_ptr_full[6:0]; // @[FetchBuffer.scala:74:20, :76:10] wire [6:0] _enq_ptr_T_11 = enq_ptr_full[13:7]; // @[FetchBuffer.scala:74:20, :76:26] wire [6:0] _enq_ptr_T_12 = _enq_ptr_T_10 | _enq_ptr_T_11; // @[FetchBuffer.scala:76:{10,18,26}] wire [6:0] _enq_ptr_T_13 = _enq_ptr_T_12; // @[FetchBuffer.scala:76:{18,32}] wire _ram_0_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_0_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_0_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_0_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_0_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_0_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_0_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_0_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_0_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_0_WIRE_bits_inst = _ram_0_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_0_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_0_WIRE_bits_raw_inst = _ram_0_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_bits_pc = _ram_0_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_0_WIRE_112; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_edge_inst = _ram_0_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_0_WIRE_64; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_rvc = _ram_0_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_0_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_btb_resp_valid = _ram_0_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_btb_resp_bits_cfiType = _ram_0_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_0_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_btb_resp_bits_taken = _ram_0_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_0_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_0_WIRE_bits_btb_resp_bits_mask = _ram_0_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_btb_resp_bits_bridx = _ram_0_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_0_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_0_WIRE_bits_btb_resp_bits_target = _ram_0_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_0_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_0_WIRE_bits_btb_resp_bits_entry = _ram_0_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_0_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_0_WIRE_bits_btb_resp_bits_bht_history = _ram_0_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_btb_resp_bits_bht_value = _ram_0_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_0_WIRE_50; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_sfb_br = _ram_0_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_0_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_next_pc_valid = _ram_0_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_bits_next_pc_bits = _ram_0_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_0_WIRE_bits_ras_head = _ram_0_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_0_WIRE_43; // @[Mux.scala:30:73] wire _ram_0_WIRE_bits_xcpt = _ram_0_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_0_WIRE_bits_xcpt_cause = _ram_0_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_bits_mem_size = _ram_0_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_7 = write_mask_0_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_8 = write_mask_0_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_9 = write_mask_0_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_10 = write_mask_0_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_11 = _ram_0_T_7 | _ram_0_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_12 = _ram_0_T_11 | _ram_0_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_13 = _ram_0_T_12 | _ram_0_T_10; // @[Mux.scala:30:73] assign _ram_0_WIRE_3 = _ram_0_T_13; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_mem_size = _ram_0_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_266 = write_mask_0_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_267 = write_mask_0_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_268 = write_mask_0_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_269 = write_mask_0_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_270 = _ram_0_T_266 | _ram_0_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_271 = _ram_0_T_270 | _ram_0_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_0_T_272 = _ram_0_T_271 | _ram_0_T_269; // @[Mux.scala:30:73] assign _ram_0_WIRE_42 = _ram_0_T_272; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_xcpt_cause = _ram_0_WIRE_42; // @[Mux.scala:30:73] wire _ram_0_T_273 = write_mask_0_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_0_T_274 = write_mask_0_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_0_T_275 = write_mask_0_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_0_T_276 = write_mask_0_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_0_T_277 = _ram_0_T_273 | _ram_0_T_274; // @[Mux.scala:30:73] wire _ram_0_T_278 = _ram_0_T_277 | _ram_0_T_275; // @[Mux.scala:30:73] wire _ram_0_T_279 = _ram_0_T_278 | _ram_0_T_276; // @[Mux.scala:30:73] assign _ram_0_WIRE_43 = _ram_0_T_279; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_xcpt = _ram_0_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_287 = write_mask_0_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_288 = write_mask_0_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_289 = write_mask_0_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_290 = write_mask_0_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_291 = _ram_0_T_287 | _ram_0_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_292 = _ram_0_T_291 | _ram_0_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_0_T_293 = _ram_0_T_292 | _ram_0_T_290; // @[Mux.scala:30:73] assign _ram_0_WIRE_45 = _ram_0_T_293; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_ras_head = _ram_0_WIRE_45; // @[Mux.scala:30:73] wire _ram_0_WIRE_48; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_next_pc_valid = _ram_0_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_0_WIRE_47; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_next_pc_bits = _ram_0_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_294 = write_mask_0_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_295 = write_mask_0_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_296 = write_mask_0_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_297 = write_mask_0_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_298 = _ram_0_T_294 | _ram_0_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_299 = _ram_0_T_298 | _ram_0_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_300 = _ram_0_T_299 | _ram_0_T_297; // @[Mux.scala:30:73] assign _ram_0_WIRE_47 = _ram_0_T_300; // @[Mux.scala:30:73] assign _ram_0_WIRE_46_bits = _ram_0_WIRE_47; // @[Mux.scala:30:73] wire _ram_0_T_301 = write_mask_0_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_0_T_302 = write_mask_0_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_0_T_303 = write_mask_0_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_0_T_304 = write_mask_0_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_0_T_305 = _ram_0_T_301 | _ram_0_T_302; // @[Mux.scala:30:73] wire _ram_0_T_306 = _ram_0_T_305 | _ram_0_T_303; // @[Mux.scala:30:73] wire _ram_0_T_307 = _ram_0_T_306 | _ram_0_T_304; // @[Mux.scala:30:73] assign _ram_0_WIRE_48 = _ram_0_T_307; // @[Mux.scala:30:73] assign _ram_0_WIRE_46_valid = _ram_0_WIRE_48; // @[Mux.scala:30:73] wire _ram_0_T_315 = write_mask_0_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_0_T_316 = write_mask_0_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_0_T_317 = write_mask_0_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_0_T_318 = write_mask_0_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_0_T_319 = _ram_0_T_315 | _ram_0_T_316; // @[Mux.scala:30:73] wire _ram_0_T_320 = _ram_0_T_319 | _ram_0_T_317; // @[Mux.scala:30:73] wire _ram_0_T_321 = _ram_0_T_320 | _ram_0_T_318; // @[Mux.scala:30:73] assign _ram_0_WIRE_50 = _ram_0_T_321; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_sfb_br = _ram_0_WIRE_50; // @[Mux.scala:30:73] wire _ram_0_WIRE_62; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_valid = _ram_0_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_cfiType = _ram_0_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_0_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_taken = _ram_0_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_0_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_mask = _ram_0_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_bridx = _ram_0_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_0_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_target = _ram_0_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_0_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_entry = _ram_0_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_0_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_bht_history = _ram_0_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_btb_resp_bits_bht_value = _ram_0_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_61; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_cfiType = _ram_0_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_0_WIRE_60; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_taken = _ram_0_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_0_WIRE_59; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_mask = _ram_0_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_58; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_bridx = _ram_0_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_0_WIRE_57; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_target = _ram_0_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_0_WIRE_56; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_entry = _ram_0_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_0_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_bht_history = _ram_0_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_bits_bht_value = _ram_0_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_0_WIRE_55; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_bht_history = _ram_0_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_0_WIRE_54; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_bht_value = _ram_0_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_322 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_323 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_324 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_325 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_326 = _ram_0_T_322 | _ram_0_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_327 = _ram_0_T_326 | _ram_0_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_328 = _ram_0_T_327 | _ram_0_T_325; // @[Mux.scala:30:73] assign _ram_0_WIRE_54 = _ram_0_T_328; // @[Mux.scala:30:73] assign _ram_0_WIRE_53_value = _ram_0_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_329 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_330 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_331 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_332 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_333 = _ram_0_T_329 | _ram_0_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_334 = _ram_0_T_333 | _ram_0_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_0_T_335 = _ram_0_T_334 | _ram_0_T_332; // @[Mux.scala:30:73] assign _ram_0_WIRE_55 = _ram_0_T_335; // @[Mux.scala:30:73] assign _ram_0_WIRE_53_history = _ram_0_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_336 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_337 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_338 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_339 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_340 = _ram_0_T_336 | _ram_0_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_341 = _ram_0_T_340 | _ram_0_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_0_T_342 = _ram_0_T_341 | _ram_0_T_339; // @[Mux.scala:30:73] assign _ram_0_WIRE_56 = _ram_0_T_342; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_entry = _ram_0_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_343 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_344 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_345 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_346 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_347 = _ram_0_T_343 | _ram_0_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_348 = _ram_0_T_347 | _ram_0_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_0_T_349 = _ram_0_T_348 | _ram_0_T_346; // @[Mux.scala:30:73] assign _ram_0_WIRE_57 = _ram_0_T_349; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_target = _ram_0_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_350 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_351 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_352 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_353 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_354 = _ram_0_T_350 | _ram_0_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_355 = _ram_0_T_354 | _ram_0_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_356 = _ram_0_T_355 | _ram_0_T_353; // @[Mux.scala:30:73] assign _ram_0_WIRE_58 = _ram_0_T_356; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_bridx = _ram_0_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_357 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_358 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_359 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_360 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_361 = _ram_0_T_357 | _ram_0_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_362 = _ram_0_T_361 | _ram_0_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_0_T_363 = _ram_0_T_362 | _ram_0_T_360; // @[Mux.scala:30:73] assign _ram_0_WIRE_59 = _ram_0_T_363; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_mask = _ram_0_WIRE_59; // @[Mux.scala:30:73] wire _ram_0_T_364 = write_mask_0_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_0_T_365 = write_mask_0_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_0_T_366 = write_mask_0_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_0_T_367 = write_mask_0_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_0_T_368 = _ram_0_T_364 | _ram_0_T_365; // @[Mux.scala:30:73] wire _ram_0_T_369 = _ram_0_T_368 | _ram_0_T_366; // @[Mux.scala:30:73] wire _ram_0_T_370 = _ram_0_T_369 | _ram_0_T_367; // @[Mux.scala:30:73] assign _ram_0_WIRE_60 = _ram_0_T_370; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_taken = _ram_0_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_371 = write_mask_0_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_372 = write_mask_0_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_373 = write_mask_0_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_374 = write_mask_0_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_375 = _ram_0_T_371 | _ram_0_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_376 = _ram_0_T_375 | _ram_0_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_0_T_377 = _ram_0_T_376 | _ram_0_T_374; // @[Mux.scala:30:73] assign _ram_0_WIRE_61 = _ram_0_T_377; // @[Mux.scala:30:73] assign _ram_0_WIRE_52_cfiType = _ram_0_WIRE_61; // @[Mux.scala:30:73] wire _ram_0_T_378 = write_mask_0_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_0_T_379 = write_mask_0_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_0_T_380 = write_mask_0_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_0_T_381 = write_mask_0_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_0_T_382 = _ram_0_T_378 | _ram_0_T_379; // @[Mux.scala:30:73] wire _ram_0_T_383 = _ram_0_T_382 | _ram_0_T_380; // @[Mux.scala:30:73] wire _ram_0_T_384 = _ram_0_T_383 | _ram_0_T_381; // @[Mux.scala:30:73] assign _ram_0_WIRE_62 = _ram_0_T_384; // @[Mux.scala:30:73] assign _ram_0_WIRE_51_valid = _ram_0_WIRE_62; // @[Mux.scala:30:73] wire _ram_0_T_392 = write_mask_0_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_0_T_393 = write_mask_0_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_0_T_394 = write_mask_0_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_0_T_395 = write_mask_0_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_0_T_396 = _ram_0_T_392 | _ram_0_T_393; // @[Mux.scala:30:73] wire _ram_0_T_397 = _ram_0_T_396 | _ram_0_T_394; // @[Mux.scala:30:73] wire _ram_0_T_398 = _ram_0_T_397 | _ram_0_T_395; // @[Mux.scala:30:73] assign _ram_0_WIRE_64 = _ram_0_T_398; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_rvc = _ram_0_WIRE_64; // @[Mux.scala:30:73] wire _ram_0_T_714 = write_mask_0_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_0_T_718 = _ram_0_T_714; // @[Mux.scala:30:73] wire _ram_0_T_719 = _ram_0_T_718; // @[Mux.scala:30:73] wire _ram_0_T_720 = _ram_0_T_719; // @[Mux.scala:30:73] assign _ram_0_WIRE_112 = _ram_0_T_720; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_edge_inst = _ram_0_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_721 = write_mask_0_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_722 = write_mask_0_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_723 = write_mask_0_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_724 = write_mask_0_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_725 = _ram_0_T_721 | _ram_0_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_726 = _ram_0_T_725 | _ram_0_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_0_T_727 = _ram_0_T_726 | _ram_0_T_724; // @[Mux.scala:30:73] assign _ram_0_WIRE_113 = _ram_0_T_727; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_pc = _ram_0_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_728 = write_mask_0_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_729 = write_mask_0_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_730 = write_mask_0_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_731 = write_mask_0_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_732 = _ram_0_T_728 | _ram_0_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_733 = _ram_0_T_732 | _ram_0_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_734 = _ram_0_T_733 | _ram_0_T_731; // @[Mux.scala:30:73] assign _ram_0_WIRE_114 = _ram_0_T_734; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_raw_inst = _ram_0_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_735 = write_mask_0_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_736 = write_mask_0_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_737 = write_mask_0_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_738 = write_mask_0_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_739 = _ram_0_T_735 | _ram_0_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_740 = _ram_0_T_739 | _ram_0_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_0_T_741 = _ram_0_T_740 | _ram_0_T_738; // @[Mux.scala:30:73] assign _ram_0_WIRE_115 = _ram_0_T_741; // @[Mux.scala:30:73] assign _ram_0_WIRE_1_inst = _ram_0_WIRE_115; // @[Mux.scala:30:73] wire _ram_0_T_742 = write_mask_0_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_0_T_743 = write_mask_0_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_0_T_744 = write_mask_0_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_0_T_745 = write_mask_0_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_0_T_746 = _ram_0_T_742 | _ram_0_T_743; // @[Mux.scala:30:73] wire _ram_0_T_747 = _ram_0_T_746 | _ram_0_T_744; // @[Mux.scala:30:73] wire _ram_0_T_748 = _ram_0_T_747 | _ram_0_T_745; // @[Mux.scala:30:73] assign _ram_0_WIRE_116 = _ram_0_T_748; // @[Mux.scala:30:73] wire _ram_0_WIRE_valid = _ram_0_WIRE_116; // @[Mux.scala:30:73] wire _ram_1_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_1_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_1_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_1_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_1_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_1_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_1_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_1_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_1_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_1_WIRE_bits_inst = _ram_1_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_1_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_1_WIRE_bits_raw_inst = _ram_1_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_bits_pc = _ram_1_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_1_WIRE_112; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_edge_inst = _ram_1_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_1_WIRE_64; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_rvc = _ram_1_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_1_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_btb_resp_valid = _ram_1_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_btb_resp_bits_cfiType = _ram_1_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_1_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_btb_resp_bits_taken = _ram_1_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_1_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_1_WIRE_bits_btb_resp_bits_mask = _ram_1_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_btb_resp_bits_bridx = _ram_1_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_1_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_1_WIRE_bits_btb_resp_bits_target = _ram_1_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_1_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_1_WIRE_bits_btb_resp_bits_entry = _ram_1_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_1_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_1_WIRE_bits_btb_resp_bits_bht_history = _ram_1_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_btb_resp_bits_bht_value = _ram_1_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_1_WIRE_50; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_sfb_br = _ram_1_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_1_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_next_pc_valid = _ram_1_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_bits_next_pc_bits = _ram_1_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_1_WIRE_bits_ras_head = _ram_1_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_1_WIRE_43; // @[Mux.scala:30:73] wire _ram_1_WIRE_bits_xcpt = _ram_1_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_1_WIRE_bits_xcpt_cause = _ram_1_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_bits_mem_size = _ram_1_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_7 = write_mask_1_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_8 = write_mask_1_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_9 = write_mask_1_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_10 = write_mask_1_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_11 = _ram_1_T_7 | _ram_1_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_12 = _ram_1_T_11 | _ram_1_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_13 = _ram_1_T_12 | _ram_1_T_10; // @[Mux.scala:30:73] assign _ram_1_WIRE_3 = _ram_1_T_13; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_mem_size = _ram_1_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_266 = write_mask_1_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_267 = write_mask_1_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_268 = write_mask_1_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_269 = write_mask_1_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_270 = _ram_1_T_266 | _ram_1_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_271 = _ram_1_T_270 | _ram_1_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_1_T_272 = _ram_1_T_271 | _ram_1_T_269; // @[Mux.scala:30:73] assign _ram_1_WIRE_42 = _ram_1_T_272; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_xcpt_cause = _ram_1_WIRE_42; // @[Mux.scala:30:73] wire _ram_1_T_273 = write_mask_1_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_1_T_274 = write_mask_1_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_1_T_275 = write_mask_1_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_1_T_276 = write_mask_1_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_1_T_277 = _ram_1_T_273 | _ram_1_T_274; // @[Mux.scala:30:73] wire _ram_1_T_278 = _ram_1_T_277 | _ram_1_T_275; // @[Mux.scala:30:73] wire _ram_1_T_279 = _ram_1_T_278 | _ram_1_T_276; // @[Mux.scala:30:73] assign _ram_1_WIRE_43 = _ram_1_T_279; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_xcpt = _ram_1_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_287 = write_mask_1_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_288 = write_mask_1_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_289 = write_mask_1_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_290 = write_mask_1_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_291 = _ram_1_T_287 | _ram_1_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_292 = _ram_1_T_291 | _ram_1_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_1_T_293 = _ram_1_T_292 | _ram_1_T_290; // @[Mux.scala:30:73] assign _ram_1_WIRE_45 = _ram_1_T_293; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_ras_head = _ram_1_WIRE_45; // @[Mux.scala:30:73] wire _ram_1_WIRE_48; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_next_pc_valid = _ram_1_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_1_WIRE_47; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_next_pc_bits = _ram_1_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_294 = write_mask_1_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_295 = write_mask_1_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_296 = write_mask_1_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_297 = write_mask_1_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_298 = _ram_1_T_294 | _ram_1_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_299 = _ram_1_T_298 | _ram_1_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_300 = _ram_1_T_299 | _ram_1_T_297; // @[Mux.scala:30:73] assign _ram_1_WIRE_47 = _ram_1_T_300; // @[Mux.scala:30:73] assign _ram_1_WIRE_46_bits = _ram_1_WIRE_47; // @[Mux.scala:30:73] wire _ram_1_T_301 = write_mask_1_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_1_T_302 = write_mask_1_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_1_T_303 = write_mask_1_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_1_T_304 = write_mask_1_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_1_T_305 = _ram_1_T_301 | _ram_1_T_302; // @[Mux.scala:30:73] wire _ram_1_T_306 = _ram_1_T_305 | _ram_1_T_303; // @[Mux.scala:30:73] wire _ram_1_T_307 = _ram_1_T_306 | _ram_1_T_304; // @[Mux.scala:30:73] assign _ram_1_WIRE_48 = _ram_1_T_307; // @[Mux.scala:30:73] assign _ram_1_WIRE_46_valid = _ram_1_WIRE_48; // @[Mux.scala:30:73] wire _ram_1_T_315 = write_mask_1_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_1_T_316 = write_mask_1_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_1_T_317 = write_mask_1_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_1_T_318 = write_mask_1_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_1_T_319 = _ram_1_T_315 | _ram_1_T_316; // @[Mux.scala:30:73] wire _ram_1_T_320 = _ram_1_T_319 | _ram_1_T_317; // @[Mux.scala:30:73] wire _ram_1_T_321 = _ram_1_T_320 | _ram_1_T_318; // @[Mux.scala:30:73] assign _ram_1_WIRE_50 = _ram_1_T_321; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_sfb_br = _ram_1_WIRE_50; // @[Mux.scala:30:73] wire _ram_1_WIRE_62; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_valid = _ram_1_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_cfiType = _ram_1_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_1_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_taken = _ram_1_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_1_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_mask = _ram_1_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_bridx = _ram_1_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_1_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_target = _ram_1_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_1_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_entry = _ram_1_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_1_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_bht_history = _ram_1_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_btb_resp_bits_bht_value = _ram_1_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_61; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_cfiType = _ram_1_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_1_WIRE_60; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_taken = _ram_1_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_1_WIRE_59; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_mask = _ram_1_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_58; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_bridx = _ram_1_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_1_WIRE_57; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_target = _ram_1_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_1_WIRE_56; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_entry = _ram_1_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_1_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_bht_history = _ram_1_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_bits_bht_value = _ram_1_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_1_WIRE_55; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_bht_history = _ram_1_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_1_WIRE_54; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_bht_value = _ram_1_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_322 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_323 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_324 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_325 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_326 = _ram_1_T_322 | _ram_1_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_327 = _ram_1_T_326 | _ram_1_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_328 = _ram_1_T_327 | _ram_1_T_325; // @[Mux.scala:30:73] assign _ram_1_WIRE_54 = _ram_1_T_328; // @[Mux.scala:30:73] assign _ram_1_WIRE_53_value = _ram_1_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_329 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_330 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_331 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_332 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_333 = _ram_1_T_329 | _ram_1_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_334 = _ram_1_T_333 | _ram_1_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_1_T_335 = _ram_1_T_334 | _ram_1_T_332; // @[Mux.scala:30:73] assign _ram_1_WIRE_55 = _ram_1_T_335; // @[Mux.scala:30:73] assign _ram_1_WIRE_53_history = _ram_1_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_336 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_337 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_338 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_339 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_340 = _ram_1_T_336 | _ram_1_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_341 = _ram_1_T_340 | _ram_1_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_1_T_342 = _ram_1_T_341 | _ram_1_T_339; // @[Mux.scala:30:73] assign _ram_1_WIRE_56 = _ram_1_T_342; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_entry = _ram_1_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_343 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_344 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_345 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_346 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_347 = _ram_1_T_343 | _ram_1_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_348 = _ram_1_T_347 | _ram_1_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_1_T_349 = _ram_1_T_348 | _ram_1_T_346; // @[Mux.scala:30:73] assign _ram_1_WIRE_57 = _ram_1_T_349; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_target = _ram_1_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_350 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_351 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_352 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_353 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_354 = _ram_1_T_350 | _ram_1_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_355 = _ram_1_T_354 | _ram_1_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_356 = _ram_1_T_355 | _ram_1_T_353; // @[Mux.scala:30:73] assign _ram_1_WIRE_58 = _ram_1_T_356; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_bridx = _ram_1_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_357 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_358 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_359 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_360 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_361 = _ram_1_T_357 | _ram_1_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_362 = _ram_1_T_361 | _ram_1_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_1_T_363 = _ram_1_T_362 | _ram_1_T_360; // @[Mux.scala:30:73] assign _ram_1_WIRE_59 = _ram_1_T_363; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_mask = _ram_1_WIRE_59; // @[Mux.scala:30:73] wire _ram_1_T_364 = write_mask_1_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_1_T_365 = write_mask_1_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_1_T_366 = write_mask_1_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_1_T_367 = write_mask_1_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_1_T_368 = _ram_1_T_364 | _ram_1_T_365; // @[Mux.scala:30:73] wire _ram_1_T_369 = _ram_1_T_368 | _ram_1_T_366; // @[Mux.scala:30:73] wire _ram_1_T_370 = _ram_1_T_369 | _ram_1_T_367; // @[Mux.scala:30:73] assign _ram_1_WIRE_60 = _ram_1_T_370; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_taken = _ram_1_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_371 = write_mask_1_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_372 = write_mask_1_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_373 = write_mask_1_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_374 = write_mask_1_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_375 = _ram_1_T_371 | _ram_1_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_376 = _ram_1_T_375 | _ram_1_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_1_T_377 = _ram_1_T_376 | _ram_1_T_374; // @[Mux.scala:30:73] assign _ram_1_WIRE_61 = _ram_1_T_377; // @[Mux.scala:30:73] assign _ram_1_WIRE_52_cfiType = _ram_1_WIRE_61; // @[Mux.scala:30:73] wire _ram_1_T_378 = write_mask_1_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_1_T_379 = write_mask_1_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_1_T_380 = write_mask_1_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_1_T_381 = write_mask_1_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_1_T_382 = _ram_1_T_378 | _ram_1_T_379; // @[Mux.scala:30:73] wire _ram_1_T_383 = _ram_1_T_382 | _ram_1_T_380; // @[Mux.scala:30:73] wire _ram_1_T_384 = _ram_1_T_383 | _ram_1_T_381; // @[Mux.scala:30:73] assign _ram_1_WIRE_62 = _ram_1_T_384; // @[Mux.scala:30:73] assign _ram_1_WIRE_51_valid = _ram_1_WIRE_62; // @[Mux.scala:30:73] wire _ram_1_T_392 = write_mask_1_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_1_T_393 = write_mask_1_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_1_T_394 = write_mask_1_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_1_T_395 = write_mask_1_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_1_T_396 = _ram_1_T_392 | _ram_1_T_393; // @[Mux.scala:30:73] wire _ram_1_T_397 = _ram_1_T_396 | _ram_1_T_394; // @[Mux.scala:30:73] wire _ram_1_T_398 = _ram_1_T_397 | _ram_1_T_395; // @[Mux.scala:30:73] assign _ram_1_WIRE_64 = _ram_1_T_398; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_rvc = _ram_1_WIRE_64; // @[Mux.scala:30:73] wire _ram_1_T_714 = write_mask_1_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_1_T_718 = _ram_1_T_714; // @[Mux.scala:30:73] wire _ram_1_T_719 = _ram_1_T_718; // @[Mux.scala:30:73] wire _ram_1_T_720 = _ram_1_T_719; // @[Mux.scala:30:73] assign _ram_1_WIRE_112 = _ram_1_T_720; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_edge_inst = _ram_1_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_721 = write_mask_1_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_722 = write_mask_1_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_723 = write_mask_1_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_724 = write_mask_1_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_725 = _ram_1_T_721 | _ram_1_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_726 = _ram_1_T_725 | _ram_1_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_1_T_727 = _ram_1_T_726 | _ram_1_T_724; // @[Mux.scala:30:73] assign _ram_1_WIRE_113 = _ram_1_T_727; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_pc = _ram_1_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_728 = write_mask_1_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_729 = write_mask_1_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_730 = write_mask_1_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_731 = write_mask_1_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_732 = _ram_1_T_728 | _ram_1_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_733 = _ram_1_T_732 | _ram_1_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_734 = _ram_1_T_733 | _ram_1_T_731; // @[Mux.scala:30:73] assign _ram_1_WIRE_114 = _ram_1_T_734; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_raw_inst = _ram_1_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_735 = write_mask_1_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_736 = write_mask_1_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_737 = write_mask_1_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_738 = write_mask_1_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_739 = _ram_1_T_735 | _ram_1_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_740 = _ram_1_T_739 | _ram_1_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_1_T_741 = _ram_1_T_740 | _ram_1_T_738; // @[Mux.scala:30:73] assign _ram_1_WIRE_115 = _ram_1_T_741; // @[Mux.scala:30:73] assign _ram_1_WIRE_1_inst = _ram_1_WIRE_115; // @[Mux.scala:30:73] wire _ram_1_T_742 = write_mask_1_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_1_T_743 = write_mask_1_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_1_T_744 = write_mask_1_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_1_T_745 = write_mask_1_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_1_T_746 = _ram_1_T_742 | _ram_1_T_743; // @[Mux.scala:30:73] wire _ram_1_T_747 = _ram_1_T_746 | _ram_1_T_744; // @[Mux.scala:30:73] wire _ram_1_T_748 = _ram_1_T_747 | _ram_1_T_745; // @[Mux.scala:30:73] assign _ram_1_WIRE_116 = _ram_1_T_748; // @[Mux.scala:30:73] wire _ram_1_WIRE_valid = _ram_1_WIRE_116; // @[Mux.scala:30:73] wire _ram_2_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_2_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_2_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_2_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_2_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_2_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_2_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_2_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_2_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_2_WIRE_bits_inst = _ram_2_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_2_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_2_WIRE_bits_raw_inst = _ram_2_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_bits_pc = _ram_2_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_2_WIRE_112; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_edge_inst = _ram_2_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_2_WIRE_64; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_rvc = _ram_2_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_2_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_btb_resp_valid = _ram_2_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_btb_resp_bits_cfiType = _ram_2_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_2_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_btb_resp_bits_taken = _ram_2_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_2_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_2_WIRE_bits_btb_resp_bits_mask = _ram_2_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_btb_resp_bits_bridx = _ram_2_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_2_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_2_WIRE_bits_btb_resp_bits_target = _ram_2_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_2_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_2_WIRE_bits_btb_resp_bits_entry = _ram_2_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_2_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_2_WIRE_bits_btb_resp_bits_bht_history = _ram_2_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_btb_resp_bits_bht_value = _ram_2_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_2_WIRE_50; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_sfb_br = _ram_2_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_2_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_next_pc_valid = _ram_2_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_bits_next_pc_bits = _ram_2_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_2_WIRE_bits_ras_head = _ram_2_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_2_WIRE_43; // @[Mux.scala:30:73] wire _ram_2_WIRE_bits_xcpt = _ram_2_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_2_WIRE_bits_xcpt_cause = _ram_2_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_bits_mem_size = _ram_2_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_7 = write_mask_2_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_8 = write_mask_2_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_9 = write_mask_2_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_10 = write_mask_2_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_11 = _ram_2_T_7 | _ram_2_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_12 = _ram_2_T_11 | _ram_2_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_13 = _ram_2_T_12 | _ram_2_T_10; // @[Mux.scala:30:73] assign _ram_2_WIRE_3 = _ram_2_T_13; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_mem_size = _ram_2_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_266 = write_mask_2_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_267 = write_mask_2_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_268 = write_mask_2_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_269 = write_mask_2_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_270 = _ram_2_T_266 | _ram_2_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_271 = _ram_2_T_270 | _ram_2_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_2_T_272 = _ram_2_T_271 | _ram_2_T_269; // @[Mux.scala:30:73] assign _ram_2_WIRE_42 = _ram_2_T_272; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_xcpt_cause = _ram_2_WIRE_42; // @[Mux.scala:30:73] wire _ram_2_T_273 = write_mask_2_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_2_T_274 = write_mask_2_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_2_T_275 = write_mask_2_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_2_T_276 = write_mask_2_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_2_T_277 = _ram_2_T_273 | _ram_2_T_274; // @[Mux.scala:30:73] wire _ram_2_T_278 = _ram_2_T_277 | _ram_2_T_275; // @[Mux.scala:30:73] wire _ram_2_T_279 = _ram_2_T_278 | _ram_2_T_276; // @[Mux.scala:30:73] assign _ram_2_WIRE_43 = _ram_2_T_279; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_xcpt = _ram_2_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_287 = write_mask_2_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_288 = write_mask_2_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_289 = write_mask_2_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_290 = write_mask_2_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_291 = _ram_2_T_287 | _ram_2_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_292 = _ram_2_T_291 | _ram_2_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_2_T_293 = _ram_2_T_292 | _ram_2_T_290; // @[Mux.scala:30:73] assign _ram_2_WIRE_45 = _ram_2_T_293; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_ras_head = _ram_2_WIRE_45; // @[Mux.scala:30:73] wire _ram_2_WIRE_48; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_next_pc_valid = _ram_2_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_2_WIRE_47; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_next_pc_bits = _ram_2_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_294 = write_mask_2_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_295 = write_mask_2_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_296 = write_mask_2_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_297 = write_mask_2_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_298 = _ram_2_T_294 | _ram_2_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_299 = _ram_2_T_298 | _ram_2_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_300 = _ram_2_T_299 | _ram_2_T_297; // @[Mux.scala:30:73] assign _ram_2_WIRE_47 = _ram_2_T_300; // @[Mux.scala:30:73] assign _ram_2_WIRE_46_bits = _ram_2_WIRE_47; // @[Mux.scala:30:73] wire _ram_2_T_301 = write_mask_2_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_2_T_302 = write_mask_2_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_2_T_303 = write_mask_2_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_2_T_304 = write_mask_2_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_2_T_305 = _ram_2_T_301 | _ram_2_T_302; // @[Mux.scala:30:73] wire _ram_2_T_306 = _ram_2_T_305 | _ram_2_T_303; // @[Mux.scala:30:73] wire _ram_2_T_307 = _ram_2_T_306 | _ram_2_T_304; // @[Mux.scala:30:73] assign _ram_2_WIRE_48 = _ram_2_T_307; // @[Mux.scala:30:73] assign _ram_2_WIRE_46_valid = _ram_2_WIRE_48; // @[Mux.scala:30:73] wire _ram_2_T_315 = write_mask_2_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_2_T_316 = write_mask_2_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_2_T_317 = write_mask_2_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_2_T_318 = write_mask_2_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_2_T_319 = _ram_2_T_315 | _ram_2_T_316; // @[Mux.scala:30:73] wire _ram_2_T_320 = _ram_2_T_319 | _ram_2_T_317; // @[Mux.scala:30:73] wire _ram_2_T_321 = _ram_2_T_320 | _ram_2_T_318; // @[Mux.scala:30:73] assign _ram_2_WIRE_50 = _ram_2_T_321; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_sfb_br = _ram_2_WIRE_50; // @[Mux.scala:30:73] wire _ram_2_WIRE_62; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_valid = _ram_2_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_cfiType = _ram_2_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_2_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_taken = _ram_2_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_2_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_mask = _ram_2_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_bridx = _ram_2_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_2_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_target = _ram_2_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_2_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_entry = _ram_2_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_2_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_bht_history = _ram_2_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_btb_resp_bits_bht_value = _ram_2_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_61; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_cfiType = _ram_2_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_2_WIRE_60; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_taken = _ram_2_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_2_WIRE_59; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_mask = _ram_2_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_58; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_bridx = _ram_2_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_2_WIRE_57; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_target = _ram_2_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_2_WIRE_56; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_entry = _ram_2_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_2_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_bht_history = _ram_2_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_bits_bht_value = _ram_2_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_2_WIRE_55; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_bht_history = _ram_2_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_2_WIRE_54; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_bht_value = _ram_2_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_322 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_323 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_324 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_325 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_326 = _ram_2_T_322 | _ram_2_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_327 = _ram_2_T_326 | _ram_2_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_328 = _ram_2_T_327 | _ram_2_T_325; // @[Mux.scala:30:73] assign _ram_2_WIRE_54 = _ram_2_T_328; // @[Mux.scala:30:73] assign _ram_2_WIRE_53_value = _ram_2_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_329 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_330 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_331 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_332 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_333 = _ram_2_T_329 | _ram_2_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_334 = _ram_2_T_333 | _ram_2_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_2_T_335 = _ram_2_T_334 | _ram_2_T_332; // @[Mux.scala:30:73] assign _ram_2_WIRE_55 = _ram_2_T_335; // @[Mux.scala:30:73] assign _ram_2_WIRE_53_history = _ram_2_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_336 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_337 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_338 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_339 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_340 = _ram_2_T_336 | _ram_2_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_341 = _ram_2_T_340 | _ram_2_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_2_T_342 = _ram_2_T_341 | _ram_2_T_339; // @[Mux.scala:30:73] assign _ram_2_WIRE_56 = _ram_2_T_342; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_entry = _ram_2_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_343 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_344 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_345 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_346 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_347 = _ram_2_T_343 | _ram_2_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_348 = _ram_2_T_347 | _ram_2_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_2_T_349 = _ram_2_T_348 | _ram_2_T_346; // @[Mux.scala:30:73] assign _ram_2_WIRE_57 = _ram_2_T_349; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_target = _ram_2_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_350 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_351 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_352 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_353 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_354 = _ram_2_T_350 | _ram_2_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_355 = _ram_2_T_354 | _ram_2_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_356 = _ram_2_T_355 | _ram_2_T_353; // @[Mux.scala:30:73] assign _ram_2_WIRE_58 = _ram_2_T_356; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_bridx = _ram_2_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_357 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_358 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_359 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_360 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_361 = _ram_2_T_357 | _ram_2_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_362 = _ram_2_T_361 | _ram_2_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_2_T_363 = _ram_2_T_362 | _ram_2_T_360; // @[Mux.scala:30:73] assign _ram_2_WIRE_59 = _ram_2_T_363; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_mask = _ram_2_WIRE_59; // @[Mux.scala:30:73] wire _ram_2_T_364 = write_mask_2_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_2_T_365 = write_mask_2_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_2_T_366 = write_mask_2_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_2_T_367 = write_mask_2_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_2_T_368 = _ram_2_T_364 | _ram_2_T_365; // @[Mux.scala:30:73] wire _ram_2_T_369 = _ram_2_T_368 | _ram_2_T_366; // @[Mux.scala:30:73] wire _ram_2_T_370 = _ram_2_T_369 | _ram_2_T_367; // @[Mux.scala:30:73] assign _ram_2_WIRE_60 = _ram_2_T_370; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_taken = _ram_2_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_371 = write_mask_2_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_372 = write_mask_2_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_373 = write_mask_2_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_374 = write_mask_2_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_375 = _ram_2_T_371 | _ram_2_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_376 = _ram_2_T_375 | _ram_2_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_2_T_377 = _ram_2_T_376 | _ram_2_T_374; // @[Mux.scala:30:73] assign _ram_2_WIRE_61 = _ram_2_T_377; // @[Mux.scala:30:73] assign _ram_2_WIRE_52_cfiType = _ram_2_WIRE_61; // @[Mux.scala:30:73] wire _ram_2_T_378 = write_mask_2_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_2_T_379 = write_mask_2_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_2_T_380 = write_mask_2_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_2_T_381 = write_mask_2_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_2_T_382 = _ram_2_T_378 | _ram_2_T_379; // @[Mux.scala:30:73] wire _ram_2_T_383 = _ram_2_T_382 | _ram_2_T_380; // @[Mux.scala:30:73] wire _ram_2_T_384 = _ram_2_T_383 | _ram_2_T_381; // @[Mux.scala:30:73] assign _ram_2_WIRE_62 = _ram_2_T_384; // @[Mux.scala:30:73] assign _ram_2_WIRE_51_valid = _ram_2_WIRE_62; // @[Mux.scala:30:73] wire _ram_2_T_392 = write_mask_2_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_2_T_393 = write_mask_2_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_2_T_394 = write_mask_2_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_2_T_395 = write_mask_2_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_2_T_396 = _ram_2_T_392 | _ram_2_T_393; // @[Mux.scala:30:73] wire _ram_2_T_397 = _ram_2_T_396 | _ram_2_T_394; // @[Mux.scala:30:73] wire _ram_2_T_398 = _ram_2_T_397 | _ram_2_T_395; // @[Mux.scala:30:73] assign _ram_2_WIRE_64 = _ram_2_T_398; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_rvc = _ram_2_WIRE_64; // @[Mux.scala:30:73] wire _ram_2_T_714 = write_mask_2_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_2_T_718 = _ram_2_T_714; // @[Mux.scala:30:73] wire _ram_2_T_719 = _ram_2_T_718; // @[Mux.scala:30:73] wire _ram_2_T_720 = _ram_2_T_719; // @[Mux.scala:30:73] assign _ram_2_WIRE_112 = _ram_2_T_720; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_edge_inst = _ram_2_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_721 = write_mask_2_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_722 = write_mask_2_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_723 = write_mask_2_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_724 = write_mask_2_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_725 = _ram_2_T_721 | _ram_2_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_726 = _ram_2_T_725 | _ram_2_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_2_T_727 = _ram_2_T_726 | _ram_2_T_724; // @[Mux.scala:30:73] assign _ram_2_WIRE_113 = _ram_2_T_727; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_pc = _ram_2_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_728 = write_mask_2_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_729 = write_mask_2_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_730 = write_mask_2_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_731 = write_mask_2_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_732 = _ram_2_T_728 | _ram_2_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_733 = _ram_2_T_732 | _ram_2_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_734 = _ram_2_T_733 | _ram_2_T_731; // @[Mux.scala:30:73] assign _ram_2_WIRE_114 = _ram_2_T_734; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_raw_inst = _ram_2_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_735 = write_mask_2_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_736 = write_mask_2_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_737 = write_mask_2_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_738 = write_mask_2_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_739 = _ram_2_T_735 | _ram_2_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_740 = _ram_2_T_739 | _ram_2_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_2_T_741 = _ram_2_T_740 | _ram_2_T_738; // @[Mux.scala:30:73] assign _ram_2_WIRE_115 = _ram_2_T_741; // @[Mux.scala:30:73] assign _ram_2_WIRE_1_inst = _ram_2_WIRE_115; // @[Mux.scala:30:73] wire _ram_2_T_742 = write_mask_2_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_2_T_743 = write_mask_2_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_2_T_744 = write_mask_2_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_2_T_745 = write_mask_2_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_2_T_746 = _ram_2_T_742 | _ram_2_T_743; // @[Mux.scala:30:73] wire _ram_2_T_747 = _ram_2_T_746 | _ram_2_T_744; // @[Mux.scala:30:73] wire _ram_2_T_748 = _ram_2_T_747 | _ram_2_T_745; // @[Mux.scala:30:73] assign _ram_2_WIRE_116 = _ram_2_T_748; // @[Mux.scala:30:73] wire _ram_2_WIRE_valid = _ram_2_WIRE_116; // @[Mux.scala:30:73] wire _ram_3_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_3_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_3_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_3_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_3_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_3_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_3_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_3_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_3_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_3_WIRE_bits_inst = _ram_3_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_3_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_3_WIRE_bits_raw_inst = _ram_3_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_bits_pc = _ram_3_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_3_WIRE_112; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_edge_inst = _ram_3_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_3_WIRE_64; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_rvc = _ram_3_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_3_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_btb_resp_valid = _ram_3_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_btb_resp_bits_cfiType = _ram_3_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_3_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_btb_resp_bits_taken = _ram_3_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_3_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_3_WIRE_bits_btb_resp_bits_mask = _ram_3_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_btb_resp_bits_bridx = _ram_3_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_3_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_3_WIRE_bits_btb_resp_bits_target = _ram_3_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_3_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_3_WIRE_bits_btb_resp_bits_entry = _ram_3_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_3_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_3_WIRE_bits_btb_resp_bits_bht_history = _ram_3_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_btb_resp_bits_bht_value = _ram_3_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_3_WIRE_50; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_sfb_br = _ram_3_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_3_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_next_pc_valid = _ram_3_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_bits_next_pc_bits = _ram_3_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_3_WIRE_bits_ras_head = _ram_3_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_3_WIRE_43; // @[Mux.scala:30:73] wire _ram_3_WIRE_bits_xcpt = _ram_3_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_3_WIRE_bits_xcpt_cause = _ram_3_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_bits_mem_size = _ram_3_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_7 = write_mask_3_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_8 = write_mask_3_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_9 = write_mask_3_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_10 = write_mask_3_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_11 = _ram_3_T_7 | _ram_3_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_12 = _ram_3_T_11 | _ram_3_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_13 = _ram_3_T_12 | _ram_3_T_10; // @[Mux.scala:30:73] assign _ram_3_WIRE_3 = _ram_3_T_13; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_mem_size = _ram_3_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_266 = write_mask_3_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_267 = write_mask_3_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_268 = write_mask_3_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_269 = write_mask_3_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_270 = _ram_3_T_266 | _ram_3_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_271 = _ram_3_T_270 | _ram_3_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_3_T_272 = _ram_3_T_271 | _ram_3_T_269; // @[Mux.scala:30:73] assign _ram_3_WIRE_42 = _ram_3_T_272; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_xcpt_cause = _ram_3_WIRE_42; // @[Mux.scala:30:73] wire _ram_3_T_273 = write_mask_3_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_3_T_274 = write_mask_3_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_3_T_275 = write_mask_3_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_3_T_276 = write_mask_3_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_3_T_277 = _ram_3_T_273 | _ram_3_T_274; // @[Mux.scala:30:73] wire _ram_3_T_278 = _ram_3_T_277 | _ram_3_T_275; // @[Mux.scala:30:73] wire _ram_3_T_279 = _ram_3_T_278 | _ram_3_T_276; // @[Mux.scala:30:73] assign _ram_3_WIRE_43 = _ram_3_T_279; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_xcpt = _ram_3_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_287 = write_mask_3_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_288 = write_mask_3_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_289 = write_mask_3_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_290 = write_mask_3_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_291 = _ram_3_T_287 | _ram_3_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_292 = _ram_3_T_291 | _ram_3_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_3_T_293 = _ram_3_T_292 | _ram_3_T_290; // @[Mux.scala:30:73] assign _ram_3_WIRE_45 = _ram_3_T_293; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_ras_head = _ram_3_WIRE_45; // @[Mux.scala:30:73] wire _ram_3_WIRE_48; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_next_pc_valid = _ram_3_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_3_WIRE_47; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_next_pc_bits = _ram_3_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_294 = write_mask_3_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_295 = write_mask_3_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_296 = write_mask_3_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_297 = write_mask_3_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_298 = _ram_3_T_294 | _ram_3_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_299 = _ram_3_T_298 | _ram_3_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_300 = _ram_3_T_299 | _ram_3_T_297; // @[Mux.scala:30:73] assign _ram_3_WIRE_47 = _ram_3_T_300; // @[Mux.scala:30:73] assign _ram_3_WIRE_46_bits = _ram_3_WIRE_47; // @[Mux.scala:30:73] wire _ram_3_T_301 = write_mask_3_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_3_T_302 = write_mask_3_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_3_T_303 = write_mask_3_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_3_T_304 = write_mask_3_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_3_T_305 = _ram_3_T_301 | _ram_3_T_302; // @[Mux.scala:30:73] wire _ram_3_T_306 = _ram_3_T_305 | _ram_3_T_303; // @[Mux.scala:30:73] wire _ram_3_T_307 = _ram_3_T_306 | _ram_3_T_304; // @[Mux.scala:30:73] assign _ram_3_WIRE_48 = _ram_3_T_307; // @[Mux.scala:30:73] assign _ram_3_WIRE_46_valid = _ram_3_WIRE_48; // @[Mux.scala:30:73] wire _ram_3_T_315 = write_mask_3_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_3_T_316 = write_mask_3_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_3_T_317 = write_mask_3_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_3_T_318 = write_mask_3_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_3_T_319 = _ram_3_T_315 | _ram_3_T_316; // @[Mux.scala:30:73] wire _ram_3_T_320 = _ram_3_T_319 | _ram_3_T_317; // @[Mux.scala:30:73] wire _ram_3_T_321 = _ram_3_T_320 | _ram_3_T_318; // @[Mux.scala:30:73] assign _ram_3_WIRE_50 = _ram_3_T_321; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_sfb_br = _ram_3_WIRE_50; // @[Mux.scala:30:73] wire _ram_3_WIRE_62; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_valid = _ram_3_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_cfiType = _ram_3_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_3_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_taken = _ram_3_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_3_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_mask = _ram_3_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_bridx = _ram_3_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_3_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_target = _ram_3_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_3_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_entry = _ram_3_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_3_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_bht_history = _ram_3_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_btb_resp_bits_bht_value = _ram_3_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_61; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_cfiType = _ram_3_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_3_WIRE_60; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_taken = _ram_3_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_3_WIRE_59; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_mask = _ram_3_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_58; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_bridx = _ram_3_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_3_WIRE_57; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_target = _ram_3_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_3_WIRE_56; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_entry = _ram_3_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_3_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_bht_history = _ram_3_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_bits_bht_value = _ram_3_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_3_WIRE_55; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_bht_history = _ram_3_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_3_WIRE_54; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_bht_value = _ram_3_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_322 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_323 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_324 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_325 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_326 = _ram_3_T_322 | _ram_3_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_327 = _ram_3_T_326 | _ram_3_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_328 = _ram_3_T_327 | _ram_3_T_325; // @[Mux.scala:30:73] assign _ram_3_WIRE_54 = _ram_3_T_328; // @[Mux.scala:30:73] assign _ram_3_WIRE_53_value = _ram_3_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_329 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_330 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_331 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_332 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_333 = _ram_3_T_329 | _ram_3_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_334 = _ram_3_T_333 | _ram_3_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_3_T_335 = _ram_3_T_334 | _ram_3_T_332; // @[Mux.scala:30:73] assign _ram_3_WIRE_55 = _ram_3_T_335; // @[Mux.scala:30:73] assign _ram_3_WIRE_53_history = _ram_3_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_336 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_337 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_338 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_339 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_340 = _ram_3_T_336 | _ram_3_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_341 = _ram_3_T_340 | _ram_3_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_3_T_342 = _ram_3_T_341 | _ram_3_T_339; // @[Mux.scala:30:73] assign _ram_3_WIRE_56 = _ram_3_T_342; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_entry = _ram_3_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_343 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_344 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_345 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_346 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_347 = _ram_3_T_343 | _ram_3_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_348 = _ram_3_T_347 | _ram_3_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_3_T_349 = _ram_3_T_348 | _ram_3_T_346; // @[Mux.scala:30:73] assign _ram_3_WIRE_57 = _ram_3_T_349; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_target = _ram_3_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_350 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_351 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_352 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_353 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_354 = _ram_3_T_350 | _ram_3_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_355 = _ram_3_T_354 | _ram_3_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_356 = _ram_3_T_355 | _ram_3_T_353; // @[Mux.scala:30:73] assign _ram_3_WIRE_58 = _ram_3_T_356; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_bridx = _ram_3_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_357 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_358 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_359 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_360 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_361 = _ram_3_T_357 | _ram_3_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_362 = _ram_3_T_361 | _ram_3_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_3_T_363 = _ram_3_T_362 | _ram_3_T_360; // @[Mux.scala:30:73] assign _ram_3_WIRE_59 = _ram_3_T_363; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_mask = _ram_3_WIRE_59; // @[Mux.scala:30:73] wire _ram_3_T_364 = write_mask_3_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_3_T_365 = write_mask_3_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_3_T_366 = write_mask_3_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_3_T_367 = write_mask_3_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_3_T_368 = _ram_3_T_364 | _ram_3_T_365; // @[Mux.scala:30:73] wire _ram_3_T_369 = _ram_3_T_368 | _ram_3_T_366; // @[Mux.scala:30:73] wire _ram_3_T_370 = _ram_3_T_369 | _ram_3_T_367; // @[Mux.scala:30:73] assign _ram_3_WIRE_60 = _ram_3_T_370; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_taken = _ram_3_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_371 = write_mask_3_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_372 = write_mask_3_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_373 = write_mask_3_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_374 = write_mask_3_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_375 = _ram_3_T_371 | _ram_3_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_376 = _ram_3_T_375 | _ram_3_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_3_T_377 = _ram_3_T_376 | _ram_3_T_374; // @[Mux.scala:30:73] assign _ram_3_WIRE_61 = _ram_3_T_377; // @[Mux.scala:30:73] assign _ram_3_WIRE_52_cfiType = _ram_3_WIRE_61; // @[Mux.scala:30:73] wire _ram_3_T_378 = write_mask_3_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_3_T_379 = write_mask_3_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_3_T_380 = write_mask_3_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_3_T_381 = write_mask_3_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_3_T_382 = _ram_3_T_378 | _ram_3_T_379; // @[Mux.scala:30:73] wire _ram_3_T_383 = _ram_3_T_382 | _ram_3_T_380; // @[Mux.scala:30:73] wire _ram_3_T_384 = _ram_3_T_383 | _ram_3_T_381; // @[Mux.scala:30:73] assign _ram_3_WIRE_62 = _ram_3_T_384; // @[Mux.scala:30:73] assign _ram_3_WIRE_51_valid = _ram_3_WIRE_62; // @[Mux.scala:30:73] wire _ram_3_T_392 = write_mask_3_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_3_T_393 = write_mask_3_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_3_T_394 = write_mask_3_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_3_T_395 = write_mask_3_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_3_T_396 = _ram_3_T_392 | _ram_3_T_393; // @[Mux.scala:30:73] wire _ram_3_T_397 = _ram_3_T_396 | _ram_3_T_394; // @[Mux.scala:30:73] wire _ram_3_T_398 = _ram_3_T_397 | _ram_3_T_395; // @[Mux.scala:30:73] assign _ram_3_WIRE_64 = _ram_3_T_398; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_rvc = _ram_3_WIRE_64; // @[Mux.scala:30:73] wire _ram_3_T_714 = write_mask_3_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_3_T_718 = _ram_3_T_714; // @[Mux.scala:30:73] wire _ram_3_T_719 = _ram_3_T_718; // @[Mux.scala:30:73] wire _ram_3_T_720 = _ram_3_T_719; // @[Mux.scala:30:73] assign _ram_3_WIRE_112 = _ram_3_T_720; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_edge_inst = _ram_3_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_721 = write_mask_3_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_722 = write_mask_3_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_723 = write_mask_3_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_724 = write_mask_3_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_725 = _ram_3_T_721 | _ram_3_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_726 = _ram_3_T_725 | _ram_3_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_3_T_727 = _ram_3_T_726 | _ram_3_T_724; // @[Mux.scala:30:73] assign _ram_3_WIRE_113 = _ram_3_T_727; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_pc = _ram_3_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_728 = write_mask_3_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_729 = write_mask_3_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_730 = write_mask_3_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_731 = write_mask_3_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_732 = _ram_3_T_728 | _ram_3_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_733 = _ram_3_T_732 | _ram_3_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_734 = _ram_3_T_733 | _ram_3_T_731; // @[Mux.scala:30:73] assign _ram_3_WIRE_114 = _ram_3_T_734; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_raw_inst = _ram_3_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_735 = write_mask_3_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_736 = write_mask_3_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_737 = write_mask_3_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_738 = write_mask_3_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_739 = _ram_3_T_735 | _ram_3_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_740 = _ram_3_T_739 | _ram_3_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_3_T_741 = _ram_3_T_740 | _ram_3_T_738; // @[Mux.scala:30:73] assign _ram_3_WIRE_115 = _ram_3_T_741; // @[Mux.scala:30:73] assign _ram_3_WIRE_1_inst = _ram_3_WIRE_115; // @[Mux.scala:30:73] wire _ram_3_T_742 = write_mask_3_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_3_T_743 = write_mask_3_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_3_T_744 = write_mask_3_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_3_T_745 = write_mask_3_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_3_T_746 = _ram_3_T_742 | _ram_3_T_743; // @[Mux.scala:30:73] wire _ram_3_T_747 = _ram_3_T_746 | _ram_3_T_744; // @[Mux.scala:30:73] wire _ram_3_T_748 = _ram_3_T_747 | _ram_3_T_745; // @[Mux.scala:30:73] assign _ram_3_WIRE_116 = _ram_3_T_748; // @[Mux.scala:30:73] wire _ram_3_WIRE_valid = _ram_3_WIRE_116; // @[Mux.scala:30:73] wire _ram_4_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_4_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_4_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_4_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_4_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_4_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_4_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_4_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_4_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_4_WIRE_bits_inst = _ram_4_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_4_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_4_WIRE_bits_raw_inst = _ram_4_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_bits_pc = _ram_4_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_4_WIRE_112; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_edge_inst = _ram_4_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_4_WIRE_64; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_rvc = _ram_4_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_4_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_btb_resp_valid = _ram_4_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_btb_resp_bits_cfiType = _ram_4_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_4_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_btb_resp_bits_taken = _ram_4_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_4_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_4_WIRE_bits_btb_resp_bits_mask = _ram_4_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_btb_resp_bits_bridx = _ram_4_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_4_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_4_WIRE_bits_btb_resp_bits_target = _ram_4_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_4_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_4_WIRE_bits_btb_resp_bits_entry = _ram_4_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_4_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_4_WIRE_bits_btb_resp_bits_bht_history = _ram_4_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_btb_resp_bits_bht_value = _ram_4_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_4_WIRE_50; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_sfb_br = _ram_4_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_4_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_next_pc_valid = _ram_4_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_bits_next_pc_bits = _ram_4_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_4_WIRE_bits_ras_head = _ram_4_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_4_WIRE_43; // @[Mux.scala:30:73] wire _ram_4_WIRE_bits_xcpt = _ram_4_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_4_WIRE_bits_xcpt_cause = _ram_4_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_bits_mem_size = _ram_4_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_7 = write_mask_4_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_8 = write_mask_4_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_9 = write_mask_4_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_10 = write_mask_4_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_11 = _ram_4_T_7 | _ram_4_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_12 = _ram_4_T_11 | _ram_4_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_13 = _ram_4_T_12 | _ram_4_T_10; // @[Mux.scala:30:73] assign _ram_4_WIRE_3 = _ram_4_T_13; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_mem_size = _ram_4_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_266 = write_mask_4_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_267 = write_mask_4_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_268 = write_mask_4_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_269 = write_mask_4_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_270 = _ram_4_T_266 | _ram_4_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_271 = _ram_4_T_270 | _ram_4_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_4_T_272 = _ram_4_T_271 | _ram_4_T_269; // @[Mux.scala:30:73] assign _ram_4_WIRE_42 = _ram_4_T_272; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_xcpt_cause = _ram_4_WIRE_42; // @[Mux.scala:30:73] wire _ram_4_T_273 = write_mask_4_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_4_T_274 = write_mask_4_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_4_T_275 = write_mask_4_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_4_T_276 = write_mask_4_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_4_T_277 = _ram_4_T_273 | _ram_4_T_274; // @[Mux.scala:30:73] wire _ram_4_T_278 = _ram_4_T_277 | _ram_4_T_275; // @[Mux.scala:30:73] wire _ram_4_T_279 = _ram_4_T_278 | _ram_4_T_276; // @[Mux.scala:30:73] assign _ram_4_WIRE_43 = _ram_4_T_279; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_xcpt = _ram_4_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_287 = write_mask_4_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_288 = write_mask_4_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_289 = write_mask_4_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_290 = write_mask_4_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_291 = _ram_4_T_287 | _ram_4_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_292 = _ram_4_T_291 | _ram_4_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_4_T_293 = _ram_4_T_292 | _ram_4_T_290; // @[Mux.scala:30:73] assign _ram_4_WIRE_45 = _ram_4_T_293; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_ras_head = _ram_4_WIRE_45; // @[Mux.scala:30:73] wire _ram_4_WIRE_48; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_next_pc_valid = _ram_4_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_4_WIRE_47; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_next_pc_bits = _ram_4_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_294 = write_mask_4_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_295 = write_mask_4_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_296 = write_mask_4_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_297 = write_mask_4_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_298 = _ram_4_T_294 | _ram_4_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_299 = _ram_4_T_298 | _ram_4_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_300 = _ram_4_T_299 | _ram_4_T_297; // @[Mux.scala:30:73] assign _ram_4_WIRE_47 = _ram_4_T_300; // @[Mux.scala:30:73] assign _ram_4_WIRE_46_bits = _ram_4_WIRE_47; // @[Mux.scala:30:73] wire _ram_4_T_301 = write_mask_4_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_4_T_302 = write_mask_4_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_4_T_303 = write_mask_4_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_4_T_304 = write_mask_4_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_4_T_305 = _ram_4_T_301 | _ram_4_T_302; // @[Mux.scala:30:73] wire _ram_4_T_306 = _ram_4_T_305 | _ram_4_T_303; // @[Mux.scala:30:73] wire _ram_4_T_307 = _ram_4_T_306 | _ram_4_T_304; // @[Mux.scala:30:73] assign _ram_4_WIRE_48 = _ram_4_T_307; // @[Mux.scala:30:73] assign _ram_4_WIRE_46_valid = _ram_4_WIRE_48; // @[Mux.scala:30:73] wire _ram_4_T_315 = write_mask_4_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_4_T_316 = write_mask_4_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_4_T_317 = write_mask_4_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_4_T_318 = write_mask_4_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_4_T_319 = _ram_4_T_315 | _ram_4_T_316; // @[Mux.scala:30:73] wire _ram_4_T_320 = _ram_4_T_319 | _ram_4_T_317; // @[Mux.scala:30:73] wire _ram_4_T_321 = _ram_4_T_320 | _ram_4_T_318; // @[Mux.scala:30:73] assign _ram_4_WIRE_50 = _ram_4_T_321; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_sfb_br = _ram_4_WIRE_50; // @[Mux.scala:30:73] wire _ram_4_WIRE_62; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_valid = _ram_4_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_cfiType = _ram_4_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_4_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_taken = _ram_4_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_4_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_mask = _ram_4_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_bridx = _ram_4_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_4_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_target = _ram_4_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_4_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_entry = _ram_4_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_4_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_bht_history = _ram_4_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_btb_resp_bits_bht_value = _ram_4_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_61; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_cfiType = _ram_4_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_4_WIRE_60; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_taken = _ram_4_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_4_WIRE_59; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_mask = _ram_4_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_58; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_bridx = _ram_4_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_4_WIRE_57; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_target = _ram_4_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_4_WIRE_56; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_entry = _ram_4_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_4_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_bht_history = _ram_4_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_bits_bht_value = _ram_4_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_4_WIRE_55; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_bht_history = _ram_4_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_4_WIRE_54; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_bht_value = _ram_4_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_322 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_323 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_324 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_325 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_326 = _ram_4_T_322 | _ram_4_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_327 = _ram_4_T_326 | _ram_4_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_328 = _ram_4_T_327 | _ram_4_T_325; // @[Mux.scala:30:73] assign _ram_4_WIRE_54 = _ram_4_T_328; // @[Mux.scala:30:73] assign _ram_4_WIRE_53_value = _ram_4_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_329 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_330 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_331 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_332 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_333 = _ram_4_T_329 | _ram_4_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_334 = _ram_4_T_333 | _ram_4_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_4_T_335 = _ram_4_T_334 | _ram_4_T_332; // @[Mux.scala:30:73] assign _ram_4_WIRE_55 = _ram_4_T_335; // @[Mux.scala:30:73] assign _ram_4_WIRE_53_history = _ram_4_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_336 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_337 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_338 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_339 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_340 = _ram_4_T_336 | _ram_4_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_341 = _ram_4_T_340 | _ram_4_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_4_T_342 = _ram_4_T_341 | _ram_4_T_339; // @[Mux.scala:30:73] assign _ram_4_WIRE_56 = _ram_4_T_342; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_entry = _ram_4_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_343 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_344 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_345 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_346 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_347 = _ram_4_T_343 | _ram_4_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_348 = _ram_4_T_347 | _ram_4_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_4_T_349 = _ram_4_T_348 | _ram_4_T_346; // @[Mux.scala:30:73] assign _ram_4_WIRE_57 = _ram_4_T_349; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_target = _ram_4_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_350 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_351 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_352 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_353 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_354 = _ram_4_T_350 | _ram_4_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_355 = _ram_4_T_354 | _ram_4_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_356 = _ram_4_T_355 | _ram_4_T_353; // @[Mux.scala:30:73] assign _ram_4_WIRE_58 = _ram_4_T_356; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_bridx = _ram_4_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_357 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_358 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_359 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_360 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_361 = _ram_4_T_357 | _ram_4_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_362 = _ram_4_T_361 | _ram_4_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_4_T_363 = _ram_4_T_362 | _ram_4_T_360; // @[Mux.scala:30:73] assign _ram_4_WIRE_59 = _ram_4_T_363; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_mask = _ram_4_WIRE_59; // @[Mux.scala:30:73] wire _ram_4_T_364 = write_mask_4_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_4_T_365 = write_mask_4_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_4_T_366 = write_mask_4_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_4_T_367 = write_mask_4_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_4_T_368 = _ram_4_T_364 | _ram_4_T_365; // @[Mux.scala:30:73] wire _ram_4_T_369 = _ram_4_T_368 | _ram_4_T_366; // @[Mux.scala:30:73] wire _ram_4_T_370 = _ram_4_T_369 | _ram_4_T_367; // @[Mux.scala:30:73] assign _ram_4_WIRE_60 = _ram_4_T_370; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_taken = _ram_4_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_371 = write_mask_4_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_372 = write_mask_4_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_373 = write_mask_4_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_374 = write_mask_4_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_375 = _ram_4_T_371 | _ram_4_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_376 = _ram_4_T_375 | _ram_4_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_4_T_377 = _ram_4_T_376 | _ram_4_T_374; // @[Mux.scala:30:73] assign _ram_4_WIRE_61 = _ram_4_T_377; // @[Mux.scala:30:73] assign _ram_4_WIRE_52_cfiType = _ram_4_WIRE_61; // @[Mux.scala:30:73] wire _ram_4_T_378 = write_mask_4_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_4_T_379 = write_mask_4_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_4_T_380 = write_mask_4_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_4_T_381 = write_mask_4_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_4_T_382 = _ram_4_T_378 | _ram_4_T_379; // @[Mux.scala:30:73] wire _ram_4_T_383 = _ram_4_T_382 | _ram_4_T_380; // @[Mux.scala:30:73] wire _ram_4_T_384 = _ram_4_T_383 | _ram_4_T_381; // @[Mux.scala:30:73] assign _ram_4_WIRE_62 = _ram_4_T_384; // @[Mux.scala:30:73] assign _ram_4_WIRE_51_valid = _ram_4_WIRE_62; // @[Mux.scala:30:73] wire _ram_4_T_392 = write_mask_4_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_4_T_393 = write_mask_4_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_4_T_394 = write_mask_4_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_4_T_395 = write_mask_4_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_4_T_396 = _ram_4_T_392 | _ram_4_T_393; // @[Mux.scala:30:73] wire _ram_4_T_397 = _ram_4_T_396 | _ram_4_T_394; // @[Mux.scala:30:73] wire _ram_4_T_398 = _ram_4_T_397 | _ram_4_T_395; // @[Mux.scala:30:73] assign _ram_4_WIRE_64 = _ram_4_T_398; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_rvc = _ram_4_WIRE_64; // @[Mux.scala:30:73] wire _ram_4_T_714 = write_mask_4_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_4_T_718 = _ram_4_T_714; // @[Mux.scala:30:73] wire _ram_4_T_719 = _ram_4_T_718; // @[Mux.scala:30:73] wire _ram_4_T_720 = _ram_4_T_719; // @[Mux.scala:30:73] assign _ram_4_WIRE_112 = _ram_4_T_720; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_edge_inst = _ram_4_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_721 = write_mask_4_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_722 = write_mask_4_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_723 = write_mask_4_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_724 = write_mask_4_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_725 = _ram_4_T_721 | _ram_4_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_726 = _ram_4_T_725 | _ram_4_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_4_T_727 = _ram_4_T_726 | _ram_4_T_724; // @[Mux.scala:30:73] assign _ram_4_WIRE_113 = _ram_4_T_727; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_pc = _ram_4_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_728 = write_mask_4_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_729 = write_mask_4_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_730 = write_mask_4_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_731 = write_mask_4_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_732 = _ram_4_T_728 | _ram_4_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_733 = _ram_4_T_732 | _ram_4_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_734 = _ram_4_T_733 | _ram_4_T_731; // @[Mux.scala:30:73] assign _ram_4_WIRE_114 = _ram_4_T_734; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_raw_inst = _ram_4_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_735 = write_mask_4_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_736 = write_mask_4_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_737 = write_mask_4_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_738 = write_mask_4_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_739 = _ram_4_T_735 | _ram_4_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_740 = _ram_4_T_739 | _ram_4_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_4_T_741 = _ram_4_T_740 | _ram_4_T_738; // @[Mux.scala:30:73] assign _ram_4_WIRE_115 = _ram_4_T_741; // @[Mux.scala:30:73] assign _ram_4_WIRE_1_inst = _ram_4_WIRE_115; // @[Mux.scala:30:73] wire _ram_4_T_742 = write_mask_4_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_4_T_743 = write_mask_4_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_4_T_744 = write_mask_4_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_4_T_745 = write_mask_4_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_4_T_746 = _ram_4_T_742 | _ram_4_T_743; // @[Mux.scala:30:73] wire _ram_4_T_747 = _ram_4_T_746 | _ram_4_T_744; // @[Mux.scala:30:73] wire _ram_4_T_748 = _ram_4_T_747 | _ram_4_T_745; // @[Mux.scala:30:73] assign _ram_4_WIRE_116 = _ram_4_T_748; // @[Mux.scala:30:73] wire _ram_4_WIRE_valid = _ram_4_WIRE_116; // @[Mux.scala:30:73] wire _ram_5_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_5_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_5_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_5_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_5_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_5_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_5_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_5_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_5_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_5_WIRE_bits_inst = _ram_5_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_5_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_5_WIRE_bits_raw_inst = _ram_5_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_bits_pc = _ram_5_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_5_WIRE_112; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_edge_inst = _ram_5_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_5_WIRE_64; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_rvc = _ram_5_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_5_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_btb_resp_valid = _ram_5_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_btb_resp_bits_cfiType = _ram_5_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_5_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_btb_resp_bits_taken = _ram_5_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_5_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_5_WIRE_bits_btb_resp_bits_mask = _ram_5_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_btb_resp_bits_bridx = _ram_5_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_5_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_5_WIRE_bits_btb_resp_bits_target = _ram_5_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_5_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_5_WIRE_bits_btb_resp_bits_entry = _ram_5_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_5_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_5_WIRE_bits_btb_resp_bits_bht_history = _ram_5_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_btb_resp_bits_bht_value = _ram_5_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_5_WIRE_50; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_sfb_br = _ram_5_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_5_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_next_pc_valid = _ram_5_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_bits_next_pc_bits = _ram_5_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_5_WIRE_bits_ras_head = _ram_5_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_5_WIRE_43; // @[Mux.scala:30:73] wire _ram_5_WIRE_bits_xcpt = _ram_5_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_5_WIRE_bits_xcpt_cause = _ram_5_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_bits_mem_size = _ram_5_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_7 = write_mask_5_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_8 = write_mask_5_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_9 = write_mask_5_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_10 = write_mask_5_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_11 = _ram_5_T_7 | _ram_5_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_12 = _ram_5_T_11 | _ram_5_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_13 = _ram_5_T_12 | _ram_5_T_10; // @[Mux.scala:30:73] assign _ram_5_WIRE_3 = _ram_5_T_13; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_mem_size = _ram_5_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_266 = write_mask_5_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_267 = write_mask_5_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_268 = write_mask_5_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_269 = write_mask_5_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_270 = _ram_5_T_266 | _ram_5_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_271 = _ram_5_T_270 | _ram_5_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_5_T_272 = _ram_5_T_271 | _ram_5_T_269; // @[Mux.scala:30:73] assign _ram_5_WIRE_42 = _ram_5_T_272; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_xcpt_cause = _ram_5_WIRE_42; // @[Mux.scala:30:73] wire _ram_5_T_273 = write_mask_5_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_5_T_274 = write_mask_5_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_5_T_275 = write_mask_5_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_5_T_276 = write_mask_5_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_5_T_277 = _ram_5_T_273 | _ram_5_T_274; // @[Mux.scala:30:73] wire _ram_5_T_278 = _ram_5_T_277 | _ram_5_T_275; // @[Mux.scala:30:73] wire _ram_5_T_279 = _ram_5_T_278 | _ram_5_T_276; // @[Mux.scala:30:73] assign _ram_5_WIRE_43 = _ram_5_T_279; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_xcpt = _ram_5_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_287 = write_mask_5_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_288 = write_mask_5_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_289 = write_mask_5_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_290 = write_mask_5_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_291 = _ram_5_T_287 | _ram_5_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_292 = _ram_5_T_291 | _ram_5_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_5_T_293 = _ram_5_T_292 | _ram_5_T_290; // @[Mux.scala:30:73] assign _ram_5_WIRE_45 = _ram_5_T_293; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_ras_head = _ram_5_WIRE_45; // @[Mux.scala:30:73] wire _ram_5_WIRE_48; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_next_pc_valid = _ram_5_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_5_WIRE_47; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_next_pc_bits = _ram_5_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_294 = write_mask_5_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_295 = write_mask_5_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_296 = write_mask_5_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_297 = write_mask_5_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_298 = _ram_5_T_294 | _ram_5_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_299 = _ram_5_T_298 | _ram_5_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_300 = _ram_5_T_299 | _ram_5_T_297; // @[Mux.scala:30:73] assign _ram_5_WIRE_47 = _ram_5_T_300; // @[Mux.scala:30:73] assign _ram_5_WIRE_46_bits = _ram_5_WIRE_47; // @[Mux.scala:30:73] wire _ram_5_T_301 = write_mask_5_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_5_T_302 = write_mask_5_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_5_T_303 = write_mask_5_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_5_T_304 = write_mask_5_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_5_T_305 = _ram_5_T_301 | _ram_5_T_302; // @[Mux.scala:30:73] wire _ram_5_T_306 = _ram_5_T_305 | _ram_5_T_303; // @[Mux.scala:30:73] wire _ram_5_T_307 = _ram_5_T_306 | _ram_5_T_304; // @[Mux.scala:30:73] assign _ram_5_WIRE_48 = _ram_5_T_307; // @[Mux.scala:30:73] assign _ram_5_WIRE_46_valid = _ram_5_WIRE_48; // @[Mux.scala:30:73] wire _ram_5_T_315 = write_mask_5_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_5_T_316 = write_mask_5_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_5_T_317 = write_mask_5_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_5_T_318 = write_mask_5_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_5_T_319 = _ram_5_T_315 | _ram_5_T_316; // @[Mux.scala:30:73] wire _ram_5_T_320 = _ram_5_T_319 | _ram_5_T_317; // @[Mux.scala:30:73] wire _ram_5_T_321 = _ram_5_T_320 | _ram_5_T_318; // @[Mux.scala:30:73] assign _ram_5_WIRE_50 = _ram_5_T_321; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_sfb_br = _ram_5_WIRE_50; // @[Mux.scala:30:73] wire _ram_5_WIRE_62; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_valid = _ram_5_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_cfiType = _ram_5_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_5_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_taken = _ram_5_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_5_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_mask = _ram_5_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_bridx = _ram_5_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_5_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_target = _ram_5_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_5_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_entry = _ram_5_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_5_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_bht_history = _ram_5_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_btb_resp_bits_bht_value = _ram_5_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_61; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_cfiType = _ram_5_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_5_WIRE_60; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_taken = _ram_5_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_5_WIRE_59; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_mask = _ram_5_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_58; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_bridx = _ram_5_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_5_WIRE_57; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_target = _ram_5_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_5_WIRE_56; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_entry = _ram_5_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_5_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_bht_history = _ram_5_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_bits_bht_value = _ram_5_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_5_WIRE_55; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_bht_history = _ram_5_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_5_WIRE_54; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_bht_value = _ram_5_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_322 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_323 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_324 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_325 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_326 = _ram_5_T_322 | _ram_5_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_327 = _ram_5_T_326 | _ram_5_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_328 = _ram_5_T_327 | _ram_5_T_325; // @[Mux.scala:30:73] assign _ram_5_WIRE_54 = _ram_5_T_328; // @[Mux.scala:30:73] assign _ram_5_WIRE_53_value = _ram_5_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_329 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_330 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_331 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_332 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_333 = _ram_5_T_329 | _ram_5_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_334 = _ram_5_T_333 | _ram_5_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_5_T_335 = _ram_5_T_334 | _ram_5_T_332; // @[Mux.scala:30:73] assign _ram_5_WIRE_55 = _ram_5_T_335; // @[Mux.scala:30:73] assign _ram_5_WIRE_53_history = _ram_5_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_336 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_337 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_338 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_339 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_340 = _ram_5_T_336 | _ram_5_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_341 = _ram_5_T_340 | _ram_5_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_5_T_342 = _ram_5_T_341 | _ram_5_T_339; // @[Mux.scala:30:73] assign _ram_5_WIRE_56 = _ram_5_T_342; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_entry = _ram_5_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_343 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_344 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_345 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_346 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_347 = _ram_5_T_343 | _ram_5_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_348 = _ram_5_T_347 | _ram_5_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_5_T_349 = _ram_5_T_348 | _ram_5_T_346; // @[Mux.scala:30:73] assign _ram_5_WIRE_57 = _ram_5_T_349; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_target = _ram_5_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_350 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_351 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_352 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_353 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_354 = _ram_5_T_350 | _ram_5_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_355 = _ram_5_T_354 | _ram_5_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_356 = _ram_5_T_355 | _ram_5_T_353; // @[Mux.scala:30:73] assign _ram_5_WIRE_58 = _ram_5_T_356; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_bridx = _ram_5_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_357 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_358 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_359 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_360 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_361 = _ram_5_T_357 | _ram_5_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_362 = _ram_5_T_361 | _ram_5_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_5_T_363 = _ram_5_T_362 | _ram_5_T_360; // @[Mux.scala:30:73] assign _ram_5_WIRE_59 = _ram_5_T_363; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_mask = _ram_5_WIRE_59; // @[Mux.scala:30:73] wire _ram_5_T_364 = write_mask_5_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_5_T_365 = write_mask_5_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_5_T_366 = write_mask_5_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_5_T_367 = write_mask_5_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_5_T_368 = _ram_5_T_364 | _ram_5_T_365; // @[Mux.scala:30:73] wire _ram_5_T_369 = _ram_5_T_368 | _ram_5_T_366; // @[Mux.scala:30:73] wire _ram_5_T_370 = _ram_5_T_369 | _ram_5_T_367; // @[Mux.scala:30:73] assign _ram_5_WIRE_60 = _ram_5_T_370; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_taken = _ram_5_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_371 = write_mask_5_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_372 = write_mask_5_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_373 = write_mask_5_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_374 = write_mask_5_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_375 = _ram_5_T_371 | _ram_5_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_376 = _ram_5_T_375 | _ram_5_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_5_T_377 = _ram_5_T_376 | _ram_5_T_374; // @[Mux.scala:30:73] assign _ram_5_WIRE_61 = _ram_5_T_377; // @[Mux.scala:30:73] assign _ram_5_WIRE_52_cfiType = _ram_5_WIRE_61; // @[Mux.scala:30:73] wire _ram_5_T_378 = write_mask_5_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_5_T_379 = write_mask_5_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_5_T_380 = write_mask_5_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_5_T_381 = write_mask_5_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_5_T_382 = _ram_5_T_378 | _ram_5_T_379; // @[Mux.scala:30:73] wire _ram_5_T_383 = _ram_5_T_382 | _ram_5_T_380; // @[Mux.scala:30:73] wire _ram_5_T_384 = _ram_5_T_383 | _ram_5_T_381; // @[Mux.scala:30:73] assign _ram_5_WIRE_62 = _ram_5_T_384; // @[Mux.scala:30:73] assign _ram_5_WIRE_51_valid = _ram_5_WIRE_62; // @[Mux.scala:30:73] wire _ram_5_T_392 = write_mask_5_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_5_T_393 = write_mask_5_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_5_T_394 = write_mask_5_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_5_T_395 = write_mask_5_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_5_T_396 = _ram_5_T_392 | _ram_5_T_393; // @[Mux.scala:30:73] wire _ram_5_T_397 = _ram_5_T_396 | _ram_5_T_394; // @[Mux.scala:30:73] wire _ram_5_T_398 = _ram_5_T_397 | _ram_5_T_395; // @[Mux.scala:30:73] assign _ram_5_WIRE_64 = _ram_5_T_398; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_rvc = _ram_5_WIRE_64; // @[Mux.scala:30:73] wire _ram_5_T_714 = write_mask_5_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_5_T_718 = _ram_5_T_714; // @[Mux.scala:30:73] wire _ram_5_T_719 = _ram_5_T_718; // @[Mux.scala:30:73] wire _ram_5_T_720 = _ram_5_T_719; // @[Mux.scala:30:73] assign _ram_5_WIRE_112 = _ram_5_T_720; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_edge_inst = _ram_5_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_721 = write_mask_5_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_722 = write_mask_5_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_723 = write_mask_5_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_724 = write_mask_5_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_725 = _ram_5_T_721 | _ram_5_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_726 = _ram_5_T_725 | _ram_5_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_5_T_727 = _ram_5_T_726 | _ram_5_T_724; // @[Mux.scala:30:73] assign _ram_5_WIRE_113 = _ram_5_T_727; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_pc = _ram_5_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_728 = write_mask_5_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_729 = write_mask_5_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_730 = write_mask_5_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_731 = write_mask_5_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_732 = _ram_5_T_728 | _ram_5_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_733 = _ram_5_T_732 | _ram_5_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_734 = _ram_5_T_733 | _ram_5_T_731; // @[Mux.scala:30:73] assign _ram_5_WIRE_114 = _ram_5_T_734; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_raw_inst = _ram_5_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_735 = write_mask_5_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_736 = write_mask_5_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_737 = write_mask_5_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_738 = write_mask_5_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_739 = _ram_5_T_735 | _ram_5_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_740 = _ram_5_T_739 | _ram_5_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_5_T_741 = _ram_5_T_740 | _ram_5_T_738; // @[Mux.scala:30:73] assign _ram_5_WIRE_115 = _ram_5_T_741; // @[Mux.scala:30:73] assign _ram_5_WIRE_1_inst = _ram_5_WIRE_115; // @[Mux.scala:30:73] wire _ram_5_T_742 = write_mask_5_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_5_T_743 = write_mask_5_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_5_T_744 = write_mask_5_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_5_T_745 = write_mask_5_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_5_T_746 = _ram_5_T_742 | _ram_5_T_743; // @[Mux.scala:30:73] wire _ram_5_T_747 = _ram_5_T_746 | _ram_5_T_744; // @[Mux.scala:30:73] wire _ram_5_T_748 = _ram_5_T_747 | _ram_5_T_745; // @[Mux.scala:30:73] assign _ram_5_WIRE_116 = _ram_5_T_748; // @[Mux.scala:30:73] wire _ram_5_WIRE_valid = _ram_5_WIRE_116; // @[Mux.scala:30:73] wire _ram_6_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _ram_6_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_6_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_6_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_6_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_6_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_6_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_6_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [31:0] _ram_6_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ram_6_WIRE_bits_inst = _ram_6_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _ram_6_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_6_WIRE_bits_raw_inst = _ram_6_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_113; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_bits_pc = _ram_6_WIRE_1_pc; // @[Mux.scala:30:73] wire _ram_6_WIRE_112; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_edge_inst = _ram_6_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _ram_6_WIRE_64; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_rvc = _ram_6_WIRE_1_rvc; // @[Mux.scala:30:73] wire _ram_6_WIRE_51_valid; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_btb_resp_valid = _ram_6_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_btb_resp_bits_cfiType = _ram_6_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ram_6_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_btb_resp_bits_taken = _ram_6_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_6_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [3:0] _ram_6_WIRE_bits_btb_resp_bits_mask = _ram_6_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_btb_resp_bits_bridx = _ram_6_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_6_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [38:0] _ram_6_WIRE_bits_btb_resp_bits_target = _ram_6_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_6_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _ram_6_WIRE_bits_btb_resp_bits_entry = _ram_6_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_6_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [7:0] _ram_6_WIRE_bits_btb_resp_bits_bht_history = _ram_6_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_btb_resp_bits_bht_value = _ram_6_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ram_6_WIRE_50; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_sfb_br = _ram_6_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _ram_6_WIRE_46_valid; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_next_pc_valid = _ram_6_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_bits_next_pc_bits = _ram_6_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _ram_6_WIRE_bits_ras_head = _ram_6_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _ram_6_WIRE_43; // @[Mux.scala:30:73] wire _ram_6_WIRE_bits_xcpt = _ram_6_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _ram_6_WIRE_bits_xcpt_cause = _ram_6_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_bits_mem_size = _ram_6_WIRE_1_mem_size; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_7 = write_mask_6_0 ? in_uops_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_8 = write_mask_6_1 ? in_uops_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_9 = write_mask_6_2 ? in_uops_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_10 = write_mask_6_3 ? in_uops_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_11 = _ram_6_T_7 | _ram_6_T_8; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_12 = _ram_6_T_11 | _ram_6_T_9; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_13 = _ram_6_T_12 | _ram_6_T_10; // @[Mux.scala:30:73] assign _ram_6_WIRE_3 = _ram_6_T_13; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_mem_size = _ram_6_WIRE_3; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_266 = write_mask_6_0 ? in_uops_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_267 = write_mask_6_1 ? in_uops_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_268 = write_mask_6_2 ? in_uops_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_269 = write_mask_6_3 ? in_uops_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_270 = _ram_6_T_266 | _ram_6_T_267; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_271 = _ram_6_T_270 | _ram_6_T_268; // @[Mux.scala:30:73] wire [63:0] _ram_6_T_272 = _ram_6_T_271 | _ram_6_T_269; // @[Mux.scala:30:73] assign _ram_6_WIRE_42 = _ram_6_T_272; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_xcpt_cause = _ram_6_WIRE_42; // @[Mux.scala:30:73] wire _ram_6_T_273 = write_mask_6_0 & in_uops_0_bits_xcpt; // @[Mux.scala:30:73] wire _ram_6_T_274 = write_mask_6_1 & in_uops_1_bits_xcpt; // @[Mux.scala:30:73] wire _ram_6_T_275 = write_mask_6_2 & in_uops_2_bits_xcpt; // @[Mux.scala:30:73] wire _ram_6_T_276 = write_mask_6_3 & in_uops_3_bits_xcpt; // @[Mux.scala:30:73] wire _ram_6_T_277 = _ram_6_T_273 | _ram_6_T_274; // @[Mux.scala:30:73] wire _ram_6_T_278 = _ram_6_T_277 | _ram_6_T_275; // @[Mux.scala:30:73] wire _ram_6_T_279 = _ram_6_T_278 | _ram_6_T_276; // @[Mux.scala:30:73] assign _ram_6_WIRE_43 = _ram_6_T_279; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_xcpt = _ram_6_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_287 = write_mask_6_0 ? in_uops_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_288 = write_mask_6_1 ? in_uops_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_289 = write_mask_6_2 ? in_uops_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_290 = write_mask_6_3 ? in_uops_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_291 = _ram_6_T_287 | _ram_6_T_288; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_292 = _ram_6_T_291 | _ram_6_T_289; // @[Mux.scala:30:73] wire [2:0] _ram_6_T_293 = _ram_6_T_292 | _ram_6_T_290; // @[Mux.scala:30:73] assign _ram_6_WIRE_45 = _ram_6_T_293; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_ras_head = _ram_6_WIRE_45; // @[Mux.scala:30:73] wire _ram_6_WIRE_48; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_next_pc_valid = _ram_6_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _ram_6_WIRE_47; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_next_pc_bits = _ram_6_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_294 = write_mask_6_0 ? in_uops_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_295 = write_mask_6_1 ? in_uops_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_296 = write_mask_6_2 ? in_uops_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_297 = write_mask_6_3 ? in_uops_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_298 = _ram_6_T_294 | _ram_6_T_295; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_299 = _ram_6_T_298 | _ram_6_T_296; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_300 = _ram_6_T_299 | _ram_6_T_297; // @[Mux.scala:30:73] assign _ram_6_WIRE_47 = _ram_6_T_300; // @[Mux.scala:30:73] assign _ram_6_WIRE_46_bits = _ram_6_WIRE_47; // @[Mux.scala:30:73] wire _ram_6_T_301 = write_mask_6_0 & in_uops_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_6_T_302 = write_mask_6_1 & in_uops_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_6_T_303 = write_mask_6_2 & in_uops_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_6_T_304 = write_mask_6_3 & in_uops_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ram_6_T_305 = _ram_6_T_301 | _ram_6_T_302; // @[Mux.scala:30:73] wire _ram_6_T_306 = _ram_6_T_305 | _ram_6_T_303; // @[Mux.scala:30:73] wire _ram_6_T_307 = _ram_6_T_306 | _ram_6_T_304; // @[Mux.scala:30:73] assign _ram_6_WIRE_48 = _ram_6_T_307; // @[Mux.scala:30:73] assign _ram_6_WIRE_46_valid = _ram_6_WIRE_48; // @[Mux.scala:30:73] wire _ram_6_T_315 = write_mask_6_0 & in_uops_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_6_T_316 = write_mask_6_1 & in_uops_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_6_T_317 = write_mask_6_2 & in_uops_2_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_6_T_318 = write_mask_6_3 & in_uops_3_bits_sfb_br; // @[Mux.scala:30:73] wire _ram_6_T_319 = _ram_6_T_315 | _ram_6_T_316; // @[Mux.scala:30:73] wire _ram_6_T_320 = _ram_6_T_319 | _ram_6_T_317; // @[Mux.scala:30:73] wire _ram_6_T_321 = _ram_6_T_320 | _ram_6_T_318; // @[Mux.scala:30:73] assign _ram_6_WIRE_50 = _ram_6_T_321; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_sfb_br = _ram_6_WIRE_50; // @[Mux.scala:30:73] wire _ram_6_WIRE_62; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_valid = _ram_6_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_cfiType = _ram_6_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _ram_6_WIRE_52_taken; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_taken = _ram_6_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ram_6_WIRE_52_mask; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_mask = _ram_6_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_52_bridx; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_bridx = _ram_6_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_6_WIRE_52_target; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_target = _ram_6_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _ram_6_WIRE_52_entry; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_entry = _ram_6_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ram_6_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_bht_history = _ram_6_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_btb_resp_bits_bht_value = _ram_6_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_61; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_cfiType = _ram_6_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _ram_6_WIRE_60; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_taken = _ram_6_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _ram_6_WIRE_59; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_mask = _ram_6_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_58; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_bridx = _ram_6_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _ram_6_WIRE_57; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_target = _ram_6_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _ram_6_WIRE_56; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_entry = _ram_6_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _ram_6_WIRE_53_history; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_bht_history = _ram_6_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_53_value; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_bits_bht_value = _ram_6_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _ram_6_WIRE_55; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_bht_history = _ram_6_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _ram_6_WIRE_54; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_bht_value = _ram_6_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_322 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_323 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_324 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_325 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_326 = _ram_6_T_322 | _ram_6_T_323; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_327 = _ram_6_T_326 | _ram_6_T_324; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_328 = _ram_6_T_327 | _ram_6_T_325; // @[Mux.scala:30:73] assign _ram_6_WIRE_54 = _ram_6_T_328; // @[Mux.scala:30:73] assign _ram_6_WIRE_53_value = _ram_6_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_329 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_330 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_331 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_332 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_333 = _ram_6_T_329 | _ram_6_T_330; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_334 = _ram_6_T_333 | _ram_6_T_331; // @[Mux.scala:30:73] wire [7:0] _ram_6_T_335 = _ram_6_T_334 | _ram_6_T_332; // @[Mux.scala:30:73] assign _ram_6_WIRE_55 = _ram_6_T_335; // @[Mux.scala:30:73] assign _ram_6_WIRE_53_history = _ram_6_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_336 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_337 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_338 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_339 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_340 = _ram_6_T_336 | _ram_6_T_337; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_341 = _ram_6_T_340 | _ram_6_T_338; // @[Mux.scala:30:73] wire [5:0] _ram_6_T_342 = _ram_6_T_341 | _ram_6_T_339; // @[Mux.scala:30:73] assign _ram_6_WIRE_56 = _ram_6_T_342; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_entry = _ram_6_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_343 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_344 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_345 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_346 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_347 = _ram_6_T_343 | _ram_6_T_344; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_348 = _ram_6_T_347 | _ram_6_T_345; // @[Mux.scala:30:73] wire [38:0] _ram_6_T_349 = _ram_6_T_348 | _ram_6_T_346; // @[Mux.scala:30:73] assign _ram_6_WIRE_57 = _ram_6_T_349; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_target = _ram_6_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_350 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_351 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_352 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_353 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_354 = _ram_6_T_350 | _ram_6_T_351; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_355 = _ram_6_T_354 | _ram_6_T_352; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_356 = _ram_6_T_355 | _ram_6_T_353; // @[Mux.scala:30:73] assign _ram_6_WIRE_58 = _ram_6_T_356; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_bridx = _ram_6_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_357 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_358 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_359 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_360 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_361 = _ram_6_T_357 | _ram_6_T_358; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_362 = _ram_6_T_361 | _ram_6_T_359; // @[Mux.scala:30:73] wire [3:0] _ram_6_T_363 = _ram_6_T_362 | _ram_6_T_360; // @[Mux.scala:30:73] assign _ram_6_WIRE_59 = _ram_6_T_363; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_mask = _ram_6_WIRE_59; // @[Mux.scala:30:73] wire _ram_6_T_364 = write_mask_6_0 & in_uops_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_6_T_365 = write_mask_6_1 & in_uops_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_6_T_366 = write_mask_6_2 & in_uops_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_6_T_367 = write_mask_6_3 & in_uops_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ram_6_T_368 = _ram_6_T_364 | _ram_6_T_365; // @[Mux.scala:30:73] wire _ram_6_T_369 = _ram_6_T_368 | _ram_6_T_366; // @[Mux.scala:30:73] wire _ram_6_T_370 = _ram_6_T_369 | _ram_6_T_367; // @[Mux.scala:30:73] assign _ram_6_WIRE_60 = _ram_6_T_370; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_taken = _ram_6_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_371 = write_mask_6_0 ? in_uops_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_372 = write_mask_6_1 ? in_uops_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_373 = write_mask_6_2 ? in_uops_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_374 = write_mask_6_3 ? in_uops_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_375 = _ram_6_T_371 | _ram_6_T_372; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_376 = _ram_6_T_375 | _ram_6_T_373; // @[Mux.scala:30:73] wire [1:0] _ram_6_T_377 = _ram_6_T_376 | _ram_6_T_374; // @[Mux.scala:30:73] assign _ram_6_WIRE_61 = _ram_6_T_377; // @[Mux.scala:30:73] assign _ram_6_WIRE_52_cfiType = _ram_6_WIRE_61; // @[Mux.scala:30:73] wire _ram_6_T_378 = write_mask_6_0 & in_uops_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_6_T_379 = write_mask_6_1 & in_uops_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_6_T_380 = write_mask_6_2 & in_uops_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_6_T_381 = write_mask_6_3 & in_uops_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ram_6_T_382 = _ram_6_T_378 | _ram_6_T_379; // @[Mux.scala:30:73] wire _ram_6_T_383 = _ram_6_T_382 | _ram_6_T_380; // @[Mux.scala:30:73] wire _ram_6_T_384 = _ram_6_T_383 | _ram_6_T_381; // @[Mux.scala:30:73] assign _ram_6_WIRE_62 = _ram_6_T_384; // @[Mux.scala:30:73] assign _ram_6_WIRE_51_valid = _ram_6_WIRE_62; // @[Mux.scala:30:73] wire _ram_6_T_392 = write_mask_6_0 & in_uops_0_bits_rvc; // @[Mux.scala:30:73] wire _ram_6_T_393 = write_mask_6_1 & in_uops_1_bits_rvc; // @[Mux.scala:30:73] wire _ram_6_T_394 = write_mask_6_2 & in_uops_2_bits_rvc; // @[Mux.scala:30:73] wire _ram_6_T_395 = write_mask_6_3 & in_uops_3_bits_rvc; // @[Mux.scala:30:73] wire _ram_6_T_396 = _ram_6_T_392 | _ram_6_T_393; // @[Mux.scala:30:73] wire _ram_6_T_397 = _ram_6_T_396 | _ram_6_T_394; // @[Mux.scala:30:73] wire _ram_6_T_398 = _ram_6_T_397 | _ram_6_T_395; // @[Mux.scala:30:73] assign _ram_6_WIRE_64 = _ram_6_T_398; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_rvc = _ram_6_WIRE_64; // @[Mux.scala:30:73] wire _ram_6_T_714 = write_mask_6_0 & in_uops_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ram_6_T_718 = _ram_6_T_714; // @[Mux.scala:30:73] wire _ram_6_T_719 = _ram_6_T_718; // @[Mux.scala:30:73] wire _ram_6_T_720 = _ram_6_T_719; // @[Mux.scala:30:73] assign _ram_6_WIRE_112 = _ram_6_T_720; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_edge_inst = _ram_6_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_721 = write_mask_6_0 ? in_uops_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_722 = write_mask_6_1 ? in_uops_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_723 = write_mask_6_2 ? in_uops_2_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_724 = write_mask_6_3 ? in_uops_3_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_725 = _ram_6_T_721 | _ram_6_T_722; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_726 = _ram_6_T_725 | _ram_6_T_723; // @[Mux.scala:30:73] wire [39:0] _ram_6_T_727 = _ram_6_T_726 | _ram_6_T_724; // @[Mux.scala:30:73] assign _ram_6_WIRE_113 = _ram_6_T_727; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_pc = _ram_6_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_728 = write_mask_6_0 ? in_uops_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_729 = write_mask_6_1 ? in_uops_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_730 = write_mask_6_2 ? in_uops_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_731 = write_mask_6_3 ? in_uops_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_732 = _ram_6_T_728 | _ram_6_T_729; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_733 = _ram_6_T_732 | _ram_6_T_730; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_734 = _ram_6_T_733 | _ram_6_T_731; // @[Mux.scala:30:73] assign _ram_6_WIRE_114 = _ram_6_T_734; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_raw_inst = _ram_6_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_735 = write_mask_6_0 ? in_uops_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_736 = write_mask_6_1 ? in_uops_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_737 = write_mask_6_2 ? in_uops_2_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_738 = write_mask_6_3 ? in_uops_3_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_739 = _ram_6_T_735 | _ram_6_T_736; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_740 = _ram_6_T_739 | _ram_6_T_737; // @[Mux.scala:30:73] wire [31:0] _ram_6_T_741 = _ram_6_T_740 | _ram_6_T_738; // @[Mux.scala:30:73] assign _ram_6_WIRE_115 = _ram_6_T_741; // @[Mux.scala:30:73] assign _ram_6_WIRE_1_inst = _ram_6_WIRE_115; // @[Mux.scala:30:73] wire _ram_6_T_742 = write_mask_6_0 & in_uops_0_valid; // @[Mux.scala:30:73] wire _ram_6_T_743 = write_mask_6_1 & in_uops_1_valid; // @[Mux.scala:30:73] wire _ram_6_T_744 = write_mask_6_2 & in_uops_2_valid; // @[Mux.scala:30:73] wire _ram_6_T_745 = write_mask_6_3 & in_uops_3_valid; // @[Mux.scala:30:73] wire _ram_6_T_746 = _ram_6_T_742 | _ram_6_T_743; // @[Mux.scala:30:73] wire _ram_6_T_747 = _ram_6_T_746 | _ram_6_T_744; // @[Mux.scala:30:73] wire _ram_6_T_748 = _ram_6_T_747 | _ram_6_T_745; // @[Mux.scala:30:73] assign _ram_6_WIRE_116 = _ram_6_T_748; // @[Mux.scala:30:73] wire _ram_6_WIRE_valid = _ram_6_WIRE_116; // @[Mux.scala:30:73] wire _out_uop_T = deq_ptr[0]; // @[Mux.scala:32:36] wire _out_uop_T_1399 = deq_ptr[0]; // @[Mux.scala:32:36] wire _out_uop_T_2798 = deq_ptr[0]; // @[Mux.scala:32:36] wire _out_uop_T_4197 = deq_ptr[0]; // @[Mux.scala:32:36] wire _out_uop_T_1 = deq_ptr[1]; // @[Mux.scala:32:36] wire _out_uop_T_1400 = deq_ptr[1]; // @[Mux.scala:32:36] wire _out_uop_T_2799 = deq_ptr[1]; // @[Mux.scala:32:36] wire _out_uop_T_4198 = deq_ptr[1]; // @[Mux.scala:32:36] wire _out_uop_T_2 = deq_ptr[2]; // @[Mux.scala:32:36] wire _out_uop_T_1401 = deq_ptr[2]; // @[Mux.scala:32:36] wire _out_uop_T_2800 = deq_ptr[2]; // @[Mux.scala:32:36] wire _out_uop_T_4199 = deq_ptr[2]; // @[Mux.scala:32:36] wire _out_uop_T_3 = deq_ptr[3]; // @[Mux.scala:32:36] wire _out_uop_T_1402 = deq_ptr[3]; // @[Mux.scala:32:36] wire _out_uop_T_2801 = deq_ptr[3]; // @[Mux.scala:32:36] wire _out_uop_T_4 = deq_ptr[4]; // @[Mux.scala:32:36] wire _out_uop_T_1403 = deq_ptr[4]; // @[Mux.scala:32:36] wire _out_uop_T_4194 = deq_ptr[4]; // @[Mux.scala:32:36] wire _out_uop_T_5 = deq_ptr[5]; // @[Mux.scala:32:36] wire _out_uop_T_2796 = deq_ptr[5]; // @[Mux.scala:32:36] wire _out_uop_T_4195 = deq_ptr[5]; // @[Mux.scala:32:36] wire _out_uop_T_6 = deq_ptr[6]; // @[Mux.scala:32:36] wire _out_uop_T_1398 = deq_ptr[6]; // @[Mux.scala:32:36] wire _out_uop_WIRE_115; // @[Mux.scala:30:73] assign io_deq_0_valid_0 = out_uop_valid; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_inst; // @[Mux.scala:30:73] assign io_deq_0_bits_inst_0 = out_uop_bits_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_raw_inst; // @[Mux.scala:30:73] assign io_deq_0_bits_raw_inst_0 = out_uop_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_pc; // @[Mux.scala:30:73] assign io_deq_0_bits_pc_0 = out_uop_bits_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_edge_inst; // @[Mux.scala:30:73] assign io_deq_0_bits_edge_inst_0 = out_uop_bits_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_rvc; // @[Mux.scala:30:73] assign io_deq_0_bits_rvc_0 = out_uop_bits_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_btb_resp_valid; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_valid_0 = out_uop_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_btb_resp_bits_cfiType; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_cfiType_0 = out_uop_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_btb_resp_bits_taken; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_taken_0 = out_uop_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_btb_resp_bits_mask; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_mask_0 = out_uop_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_btb_resp_bits_bridx; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_bridx_0 = out_uop_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_btb_resp_bits_target; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_target_0 = out_uop_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_btb_resp_bits_entry; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_entry_0 = out_uop_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_btb_resp_bits_bht_history; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_bht_history_0 = out_uop_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_btb_resp_bits_bht_value; // @[Mux.scala:30:73] assign io_deq_0_bits_btb_resp_bits_bht_value_0 = out_uop_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_sfb_br; // @[Mux.scala:30:73] assign io_deq_0_bits_sfb_br_0 = out_uop_bits_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_next_pc_valid; // @[Mux.scala:30:73] assign io_deq_0_bits_next_pc_valid_0 = out_uop_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_next_pc_bits; // @[Mux.scala:30:73] assign io_deq_0_bits_next_pc_bits_0 = out_uop_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_ras_head; // @[Mux.scala:30:73] assign io_deq_0_bits_ras_head_0 = out_uop_bits_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_xcpt; // @[Mux.scala:30:73] assign io_deq_0_bits_xcpt_0 = out_uop_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_xcpt_cause; // @[Mux.scala:30:73] assign io_deq_0_bits_xcpt_cause_0 = out_uop_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_mem_size; // @[Mux.scala:30:73] assign io_deq_0_bits_mem_size_0 = out_uop_bits_mem_size; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_114; // @[Mux.scala:30:73] assign out_uop_bits_inst = _out_uop_WIRE_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_113; // @[Mux.scala:30:73] assign out_uop_bits_raw_inst = _out_uop_WIRE_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_112; // @[Mux.scala:30:73] assign out_uop_bits_pc = _out_uop_WIRE_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_111; // @[Mux.scala:30:73] assign out_uop_bits_edge_inst = _out_uop_WIRE_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_63; // @[Mux.scala:30:73] assign out_uop_bits_rvc = _out_uop_WIRE_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_50_valid; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_valid = _out_uop_WIRE_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_50_bits_cfiType; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_cfiType = _out_uop_WIRE_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_50_bits_taken; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_taken = _out_uop_WIRE_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_50_bits_mask; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_mask = _out_uop_WIRE_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_50_bits_bridx; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_bridx = _out_uop_WIRE_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_50_bits_target; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_target = _out_uop_WIRE_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_50_bits_entry; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_entry = _out_uop_WIRE_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_50_bits_bht_history; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_bht_history = _out_uop_WIRE_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_50_bits_bht_value; // @[Mux.scala:30:73] assign out_uop_bits_btb_resp_bits_bht_value = _out_uop_WIRE_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_49; // @[Mux.scala:30:73] assign out_uop_bits_sfb_br = _out_uop_WIRE_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_45_valid; // @[Mux.scala:30:73] assign out_uop_bits_next_pc_valid = _out_uop_WIRE_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_45_bits; // @[Mux.scala:30:73] assign out_uop_bits_next_pc_bits = _out_uop_WIRE_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_44; // @[Mux.scala:30:73] assign out_uop_bits_ras_head = _out_uop_WIRE_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_42; // @[Mux.scala:30:73] assign out_uop_bits_xcpt = _out_uop_WIRE_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_41; // @[Mux.scala:30:73] assign out_uop_bits_xcpt_cause = _out_uop_WIRE_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_2; // @[Mux.scala:30:73] assign out_uop_bits_mem_size = _out_uop_WIRE_mem_size; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_20 = _out_uop_T ? ram_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_21 = _out_uop_T_1 ? ram_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_22 = _out_uop_T_2 ? ram_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_23 = _out_uop_T_3 ? ram_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_24 = _out_uop_T_4 ? ram_4_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_25 = _out_uop_T_5 ? ram_5_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_26 = _out_uop_T_6 ? ram_6_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_27 = _out_uop_T_20 | _out_uop_T_21; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_28 = _out_uop_T_27 | _out_uop_T_22; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_29 = _out_uop_T_28 | _out_uop_T_23; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_30 = _out_uop_T_29 | _out_uop_T_24; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_31 = _out_uop_T_30 | _out_uop_T_25; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_32 = _out_uop_T_31 | _out_uop_T_26; // @[Mux.scala:30:73] assign _out_uop_WIRE_2 = _out_uop_T_32; // @[Mux.scala:30:73] assign _out_uop_WIRE_mem_size = _out_uop_WIRE_2; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_501 = _out_uop_T ? ram_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_502 = _out_uop_T_1 ? ram_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_503 = _out_uop_T_2 ? ram_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_504 = _out_uop_T_3 ? ram_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_505 = _out_uop_T_4 ? ram_4_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_506 = _out_uop_T_5 ? ram_5_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_507 = _out_uop_T_6 ? ram_6_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_508 = _out_uop_T_501 | _out_uop_T_502; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_509 = _out_uop_T_508 | _out_uop_T_503; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_510 = _out_uop_T_509 | _out_uop_T_504; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_511 = _out_uop_T_510 | _out_uop_T_505; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_512 = _out_uop_T_511 | _out_uop_T_506; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_513 = _out_uop_T_512 | _out_uop_T_507; // @[Mux.scala:30:73] assign _out_uop_WIRE_41 = _out_uop_T_513; // @[Mux.scala:30:73] assign _out_uop_WIRE_xcpt_cause = _out_uop_WIRE_41; // @[Mux.scala:30:73] wire _out_uop_T_514 = _out_uop_T & ram_0_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_515 = _out_uop_T_1 & ram_1_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_516 = _out_uop_T_2 & ram_2_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_517 = _out_uop_T_3 & ram_3_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_518 = _out_uop_T_4 & ram_4_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_519 = _out_uop_T_5 & ram_5_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_520 = _out_uop_T_6 & ram_6_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_521 = _out_uop_T_514 | _out_uop_T_515; // @[Mux.scala:30:73] wire _out_uop_T_522 = _out_uop_T_521 | _out_uop_T_516; // @[Mux.scala:30:73] wire _out_uop_T_523 = _out_uop_T_522 | _out_uop_T_517; // @[Mux.scala:30:73] wire _out_uop_T_524 = _out_uop_T_523 | _out_uop_T_518; // @[Mux.scala:30:73] wire _out_uop_T_525 = _out_uop_T_524 | _out_uop_T_519; // @[Mux.scala:30:73] wire _out_uop_T_526 = _out_uop_T_525 | _out_uop_T_520; // @[Mux.scala:30:73] assign _out_uop_WIRE_42 = _out_uop_T_526; // @[Mux.scala:30:73] assign _out_uop_WIRE_xcpt = _out_uop_WIRE_42; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_540 = _out_uop_T ? ram_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_541 = _out_uop_T_1 ? ram_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_542 = _out_uop_T_2 ? ram_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_543 = _out_uop_T_3 ? ram_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_544 = _out_uop_T_4 ? ram_4_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_545 = _out_uop_T_5 ? ram_5_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_546 = _out_uop_T_6 ? ram_6_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_547 = _out_uop_T_540 | _out_uop_T_541; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_548 = _out_uop_T_547 | _out_uop_T_542; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_549 = _out_uop_T_548 | _out_uop_T_543; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_550 = _out_uop_T_549 | _out_uop_T_544; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_551 = _out_uop_T_550 | _out_uop_T_545; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_552 = _out_uop_T_551 | _out_uop_T_546; // @[Mux.scala:30:73] assign _out_uop_WIRE_44 = _out_uop_T_552; // @[Mux.scala:30:73] assign _out_uop_WIRE_ras_head = _out_uop_WIRE_44; // @[Mux.scala:30:73] wire _out_uop_WIRE_47; // @[Mux.scala:30:73] assign _out_uop_WIRE_next_pc_valid = _out_uop_WIRE_45_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_46; // @[Mux.scala:30:73] assign _out_uop_WIRE_next_pc_bits = _out_uop_WIRE_45_bits; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_553 = _out_uop_T ? ram_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_554 = _out_uop_T_1 ? ram_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_555 = _out_uop_T_2 ? ram_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_556 = _out_uop_T_3 ? ram_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_557 = _out_uop_T_4 ? ram_4_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_558 = _out_uop_T_5 ? ram_5_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_559 = _out_uop_T_6 ? ram_6_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_560 = _out_uop_T_553 | _out_uop_T_554; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_561 = _out_uop_T_560 | _out_uop_T_555; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_562 = _out_uop_T_561 | _out_uop_T_556; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_563 = _out_uop_T_562 | _out_uop_T_557; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_564 = _out_uop_T_563 | _out_uop_T_558; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_565 = _out_uop_T_564 | _out_uop_T_559; // @[Mux.scala:30:73] assign _out_uop_WIRE_46 = _out_uop_T_565; // @[Mux.scala:30:73] assign _out_uop_WIRE_45_bits = _out_uop_WIRE_46; // @[Mux.scala:30:73] wire _out_uop_T_566 = _out_uop_T & ram_0_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_567 = _out_uop_T_1 & ram_1_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_568 = _out_uop_T_2 & ram_2_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_569 = _out_uop_T_3 & ram_3_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_570 = _out_uop_T_4 & ram_4_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_571 = _out_uop_T_5 & ram_5_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_572 = _out_uop_T_6 & ram_6_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_573 = _out_uop_T_566 | _out_uop_T_567; // @[Mux.scala:30:73] wire _out_uop_T_574 = _out_uop_T_573 | _out_uop_T_568; // @[Mux.scala:30:73] wire _out_uop_T_575 = _out_uop_T_574 | _out_uop_T_569; // @[Mux.scala:30:73] wire _out_uop_T_576 = _out_uop_T_575 | _out_uop_T_570; // @[Mux.scala:30:73] wire _out_uop_T_577 = _out_uop_T_576 | _out_uop_T_571; // @[Mux.scala:30:73] wire _out_uop_T_578 = _out_uop_T_577 | _out_uop_T_572; // @[Mux.scala:30:73] assign _out_uop_WIRE_47 = _out_uop_T_578; // @[Mux.scala:30:73] assign _out_uop_WIRE_45_valid = _out_uop_WIRE_47; // @[Mux.scala:30:73] wire _out_uop_T_592 = _out_uop_T & ram_0_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_593 = _out_uop_T_1 & ram_1_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_594 = _out_uop_T_2 & ram_2_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_595 = _out_uop_T_3 & ram_3_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_596 = _out_uop_T_4 & ram_4_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_597 = _out_uop_T_5 & ram_5_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_598 = _out_uop_T_6 & ram_6_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_599 = _out_uop_T_592 | _out_uop_T_593; // @[Mux.scala:30:73] wire _out_uop_T_600 = _out_uop_T_599 | _out_uop_T_594; // @[Mux.scala:30:73] wire _out_uop_T_601 = _out_uop_T_600 | _out_uop_T_595; // @[Mux.scala:30:73] wire _out_uop_T_602 = _out_uop_T_601 | _out_uop_T_596; // @[Mux.scala:30:73] wire _out_uop_T_603 = _out_uop_T_602 | _out_uop_T_597; // @[Mux.scala:30:73] wire _out_uop_T_604 = _out_uop_T_603 | _out_uop_T_598; // @[Mux.scala:30:73] assign _out_uop_WIRE_49 = _out_uop_T_604; // @[Mux.scala:30:73] assign _out_uop_WIRE_sfb_br = _out_uop_WIRE_49; // @[Mux.scala:30:73] wire _out_uop_WIRE_61; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_valid = _out_uop_WIRE_50_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_51_cfiType; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_cfiType = _out_uop_WIRE_50_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_51_taken; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_taken = _out_uop_WIRE_50_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_51_mask; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_mask = _out_uop_WIRE_50_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_51_bridx; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_bridx = _out_uop_WIRE_50_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_51_target; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_target = _out_uop_WIRE_50_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_51_entry; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_entry = _out_uop_WIRE_50_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_51_bht_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_bht_history = _out_uop_WIRE_50_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_51_bht_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_btb_resp_bits_bht_value = _out_uop_WIRE_50_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_60; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_cfiType = _out_uop_WIRE_51_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_59; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_taken = _out_uop_WIRE_51_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_58; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_mask = _out_uop_WIRE_51_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_57; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_bridx = _out_uop_WIRE_51_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_56; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_target = _out_uop_WIRE_51_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_55; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_entry = _out_uop_WIRE_51_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_52_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_bht_history = _out_uop_WIRE_51_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_52_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_bits_bht_value = _out_uop_WIRE_51_bht_value; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_54; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_bht_history = _out_uop_WIRE_52_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_53; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_bht_value = _out_uop_WIRE_52_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_605 = _out_uop_T ? ram_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_606 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_607 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_608 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_609 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_610 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_611 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_612 = _out_uop_T_605 | _out_uop_T_606; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_613 = _out_uop_T_612 | _out_uop_T_607; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_614 = _out_uop_T_613 | _out_uop_T_608; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_615 = _out_uop_T_614 | _out_uop_T_609; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_616 = _out_uop_T_615 | _out_uop_T_610; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_617 = _out_uop_T_616 | _out_uop_T_611; // @[Mux.scala:30:73] assign _out_uop_WIRE_53 = _out_uop_T_617; // @[Mux.scala:30:73] assign _out_uop_WIRE_52_value = _out_uop_WIRE_53; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_618 = _out_uop_T ? ram_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_619 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_620 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_621 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_622 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_623 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_624 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_625 = _out_uop_T_618 | _out_uop_T_619; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_626 = _out_uop_T_625 | _out_uop_T_620; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_627 = _out_uop_T_626 | _out_uop_T_621; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_628 = _out_uop_T_627 | _out_uop_T_622; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_629 = _out_uop_T_628 | _out_uop_T_623; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_630 = _out_uop_T_629 | _out_uop_T_624; // @[Mux.scala:30:73] assign _out_uop_WIRE_54 = _out_uop_T_630; // @[Mux.scala:30:73] assign _out_uop_WIRE_52_history = _out_uop_WIRE_54; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_631 = _out_uop_T ? ram_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_632 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_633 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_634 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_635 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_636 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_637 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_638 = _out_uop_T_631 | _out_uop_T_632; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_639 = _out_uop_T_638 | _out_uop_T_633; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_640 = _out_uop_T_639 | _out_uop_T_634; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_641 = _out_uop_T_640 | _out_uop_T_635; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_642 = _out_uop_T_641 | _out_uop_T_636; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_643 = _out_uop_T_642 | _out_uop_T_637; // @[Mux.scala:30:73] assign _out_uop_WIRE_55 = _out_uop_T_643; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_entry = _out_uop_WIRE_55; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_644 = _out_uop_T ? ram_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_645 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_646 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_647 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_648 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_649 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_650 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_651 = _out_uop_T_644 | _out_uop_T_645; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_652 = _out_uop_T_651 | _out_uop_T_646; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_653 = _out_uop_T_652 | _out_uop_T_647; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_654 = _out_uop_T_653 | _out_uop_T_648; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_655 = _out_uop_T_654 | _out_uop_T_649; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_656 = _out_uop_T_655 | _out_uop_T_650; // @[Mux.scala:30:73] assign _out_uop_WIRE_56 = _out_uop_T_656; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_target = _out_uop_WIRE_56; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_657 = _out_uop_T ? ram_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_658 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_659 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_660 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_661 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_662 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_663 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_664 = _out_uop_T_657 | _out_uop_T_658; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_665 = _out_uop_T_664 | _out_uop_T_659; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_666 = _out_uop_T_665 | _out_uop_T_660; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_667 = _out_uop_T_666 | _out_uop_T_661; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_668 = _out_uop_T_667 | _out_uop_T_662; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_669 = _out_uop_T_668 | _out_uop_T_663; // @[Mux.scala:30:73] assign _out_uop_WIRE_57 = _out_uop_T_669; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_bridx = _out_uop_WIRE_57; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_670 = _out_uop_T ? ram_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_671 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_672 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_673 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_674 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_675 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_676 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_677 = _out_uop_T_670 | _out_uop_T_671; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_678 = _out_uop_T_677 | _out_uop_T_672; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_679 = _out_uop_T_678 | _out_uop_T_673; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_680 = _out_uop_T_679 | _out_uop_T_674; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_681 = _out_uop_T_680 | _out_uop_T_675; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_682 = _out_uop_T_681 | _out_uop_T_676; // @[Mux.scala:30:73] assign _out_uop_WIRE_58 = _out_uop_T_682; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_mask = _out_uop_WIRE_58; // @[Mux.scala:30:73] wire _out_uop_T_683 = _out_uop_T & ram_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_684 = _out_uop_T_1 & ram_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_685 = _out_uop_T_2 & ram_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_686 = _out_uop_T_3 & ram_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_687 = _out_uop_T_4 & ram_4_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_688 = _out_uop_T_5 & ram_5_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_689 = _out_uop_T_6 & ram_6_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_690 = _out_uop_T_683 | _out_uop_T_684; // @[Mux.scala:30:73] wire _out_uop_T_691 = _out_uop_T_690 | _out_uop_T_685; // @[Mux.scala:30:73] wire _out_uop_T_692 = _out_uop_T_691 | _out_uop_T_686; // @[Mux.scala:30:73] wire _out_uop_T_693 = _out_uop_T_692 | _out_uop_T_687; // @[Mux.scala:30:73] wire _out_uop_T_694 = _out_uop_T_693 | _out_uop_T_688; // @[Mux.scala:30:73] wire _out_uop_T_695 = _out_uop_T_694 | _out_uop_T_689; // @[Mux.scala:30:73] assign _out_uop_WIRE_59 = _out_uop_T_695; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_taken = _out_uop_WIRE_59; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_696 = _out_uop_T ? ram_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_697 = _out_uop_T_1 ? ram_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_698 = _out_uop_T_2 ? ram_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_699 = _out_uop_T_3 ? ram_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_700 = _out_uop_T_4 ? ram_4_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_701 = _out_uop_T_5 ? ram_5_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_702 = _out_uop_T_6 ? ram_6_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_703 = _out_uop_T_696 | _out_uop_T_697; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_704 = _out_uop_T_703 | _out_uop_T_698; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_705 = _out_uop_T_704 | _out_uop_T_699; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_706 = _out_uop_T_705 | _out_uop_T_700; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_707 = _out_uop_T_706 | _out_uop_T_701; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_708 = _out_uop_T_707 | _out_uop_T_702; // @[Mux.scala:30:73] assign _out_uop_WIRE_60 = _out_uop_T_708; // @[Mux.scala:30:73] assign _out_uop_WIRE_51_cfiType = _out_uop_WIRE_60; // @[Mux.scala:30:73] wire _out_uop_T_709 = _out_uop_T & ram_0_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_710 = _out_uop_T_1 & ram_1_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_711 = _out_uop_T_2 & ram_2_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_712 = _out_uop_T_3 & ram_3_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_713 = _out_uop_T_4 & ram_4_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_714 = _out_uop_T_5 & ram_5_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_715 = _out_uop_T_6 & ram_6_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_716 = _out_uop_T_709 | _out_uop_T_710; // @[Mux.scala:30:73] wire _out_uop_T_717 = _out_uop_T_716 | _out_uop_T_711; // @[Mux.scala:30:73] wire _out_uop_T_718 = _out_uop_T_717 | _out_uop_T_712; // @[Mux.scala:30:73] wire _out_uop_T_719 = _out_uop_T_718 | _out_uop_T_713; // @[Mux.scala:30:73] wire _out_uop_T_720 = _out_uop_T_719 | _out_uop_T_714; // @[Mux.scala:30:73] wire _out_uop_T_721 = _out_uop_T_720 | _out_uop_T_715; // @[Mux.scala:30:73] assign _out_uop_WIRE_61 = _out_uop_T_721; // @[Mux.scala:30:73] assign _out_uop_WIRE_50_valid = _out_uop_WIRE_61; // @[Mux.scala:30:73] wire _out_uop_T_735 = _out_uop_T & ram_0_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_736 = _out_uop_T_1 & ram_1_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_737 = _out_uop_T_2 & ram_2_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_738 = _out_uop_T_3 & ram_3_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_739 = _out_uop_T_4 & ram_4_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_740 = _out_uop_T_5 & ram_5_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_741 = _out_uop_T_6 & ram_6_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_742 = _out_uop_T_735 | _out_uop_T_736; // @[Mux.scala:30:73] wire _out_uop_T_743 = _out_uop_T_742 | _out_uop_T_737; // @[Mux.scala:30:73] wire _out_uop_T_744 = _out_uop_T_743 | _out_uop_T_738; // @[Mux.scala:30:73] wire _out_uop_T_745 = _out_uop_T_744 | _out_uop_T_739; // @[Mux.scala:30:73] wire _out_uop_T_746 = _out_uop_T_745 | _out_uop_T_740; // @[Mux.scala:30:73] wire _out_uop_T_747 = _out_uop_T_746 | _out_uop_T_741; // @[Mux.scala:30:73] assign _out_uop_WIRE_63 = _out_uop_T_747; // @[Mux.scala:30:73] assign _out_uop_WIRE_rvc = _out_uop_WIRE_63; // @[Mux.scala:30:73] wire _out_uop_T_1333 = _out_uop_T & ram_0_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1334 = _out_uop_T_1 & ram_1_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1335 = _out_uop_T_2 & ram_2_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1336 = _out_uop_T_3 & ram_3_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1337 = _out_uop_T_4 & ram_4_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1338 = _out_uop_T_5 & ram_5_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1339 = _out_uop_T_6 & ram_6_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1340 = _out_uop_T_1333 | _out_uop_T_1334; // @[Mux.scala:30:73] wire _out_uop_T_1341 = _out_uop_T_1340 | _out_uop_T_1335; // @[Mux.scala:30:73] wire _out_uop_T_1342 = _out_uop_T_1341 | _out_uop_T_1336; // @[Mux.scala:30:73] wire _out_uop_T_1343 = _out_uop_T_1342 | _out_uop_T_1337; // @[Mux.scala:30:73] wire _out_uop_T_1344 = _out_uop_T_1343 | _out_uop_T_1338; // @[Mux.scala:30:73] wire _out_uop_T_1345 = _out_uop_T_1344 | _out_uop_T_1339; // @[Mux.scala:30:73] assign _out_uop_WIRE_111 = _out_uop_T_1345; // @[Mux.scala:30:73] assign _out_uop_WIRE_edge_inst = _out_uop_WIRE_111; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1346 = _out_uop_T ? ram_0_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1347 = _out_uop_T_1 ? ram_1_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1348 = _out_uop_T_2 ? ram_2_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1349 = _out_uop_T_3 ? ram_3_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1350 = _out_uop_T_4 ? ram_4_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1351 = _out_uop_T_5 ? ram_5_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1352 = _out_uop_T_6 ? ram_6_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1353 = _out_uop_T_1346 | _out_uop_T_1347; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1354 = _out_uop_T_1353 | _out_uop_T_1348; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1355 = _out_uop_T_1354 | _out_uop_T_1349; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1356 = _out_uop_T_1355 | _out_uop_T_1350; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1357 = _out_uop_T_1356 | _out_uop_T_1351; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1358 = _out_uop_T_1357 | _out_uop_T_1352; // @[Mux.scala:30:73] assign _out_uop_WIRE_112 = _out_uop_T_1358; // @[Mux.scala:30:73] assign _out_uop_WIRE_pc = _out_uop_WIRE_112; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1359 = _out_uop_T ? ram_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1360 = _out_uop_T_1 ? ram_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1361 = _out_uop_T_2 ? ram_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1362 = _out_uop_T_3 ? ram_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1363 = _out_uop_T_4 ? ram_4_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1364 = _out_uop_T_5 ? ram_5_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1365 = _out_uop_T_6 ? ram_6_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1366 = _out_uop_T_1359 | _out_uop_T_1360; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1367 = _out_uop_T_1366 | _out_uop_T_1361; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1368 = _out_uop_T_1367 | _out_uop_T_1362; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1369 = _out_uop_T_1368 | _out_uop_T_1363; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1370 = _out_uop_T_1369 | _out_uop_T_1364; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1371 = _out_uop_T_1370 | _out_uop_T_1365; // @[Mux.scala:30:73] assign _out_uop_WIRE_113 = _out_uop_T_1371; // @[Mux.scala:30:73] assign _out_uop_WIRE_raw_inst = _out_uop_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1372 = _out_uop_T ? ram_0_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1373 = _out_uop_T_1 ? ram_1_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1374 = _out_uop_T_2 ? ram_2_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1375 = _out_uop_T_3 ? ram_3_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1376 = _out_uop_T_4 ? ram_4_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1377 = _out_uop_T_5 ? ram_5_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1378 = _out_uop_T_6 ? ram_6_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_1379 = _out_uop_T_1372 | _out_uop_T_1373; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1380 = _out_uop_T_1379 | _out_uop_T_1374; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1381 = _out_uop_T_1380 | _out_uop_T_1375; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1382 = _out_uop_T_1381 | _out_uop_T_1376; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1383 = _out_uop_T_1382 | _out_uop_T_1377; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_1384 = _out_uop_T_1383 | _out_uop_T_1378; // @[Mux.scala:30:73] assign _out_uop_WIRE_114 = _out_uop_T_1384; // @[Mux.scala:30:73] assign _out_uop_WIRE_inst = _out_uop_WIRE_114; // @[Mux.scala:30:73] wire _out_uop_T_1385 = _out_uop_T & ram_0_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1386 = _out_uop_T_1 & ram_1_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1387 = _out_uop_T_2 & ram_2_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1388 = _out_uop_T_3 & ram_3_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1389 = _out_uop_T_4 & ram_4_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1390 = _out_uop_T_5 & ram_5_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1391 = _out_uop_T_6 & ram_6_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1392 = _out_uop_T_1385 | _out_uop_T_1386; // @[Mux.scala:30:73] wire _out_uop_T_1393 = _out_uop_T_1392 | _out_uop_T_1387; // @[Mux.scala:30:73] wire _out_uop_T_1394 = _out_uop_T_1393 | _out_uop_T_1388; // @[Mux.scala:30:73] wire _out_uop_T_1395 = _out_uop_T_1394 | _out_uop_T_1389; // @[Mux.scala:30:73] wire _out_uop_T_1396 = _out_uop_T_1395 | _out_uop_T_1390; // @[Mux.scala:30:73] wire _out_uop_T_1397 = _out_uop_T_1396 | _out_uop_T_1391; // @[Mux.scala:30:73] assign _out_uop_WIRE_115 = _out_uop_T_1397; // @[Mux.scala:30:73] assign out_uop_valid = _out_uop_WIRE_115; // @[Mux.scala:30:73] wire _deq_ptr_T = io_deq_0_ready_0 & io_deq_0_valid_0; // @[Decoupled.scala:51:35] wire _out_uop_T_1404 = deq_ptr[5]; // @[Mux.scala:32:36] wire _out_uop_WIRE_231; // @[Mux.scala:30:73] assign io_deq_1_valid_0 = out_uop_1_valid; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_116_inst; // @[Mux.scala:30:73] assign io_deq_1_bits_inst_0 = out_uop_1_bits_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_116_raw_inst; // @[Mux.scala:30:73] assign io_deq_1_bits_raw_inst_0 = out_uop_1_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_116_pc; // @[Mux.scala:30:73] assign io_deq_1_bits_pc_0 = out_uop_1_bits_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_edge_inst; // @[Mux.scala:30:73] assign io_deq_1_bits_edge_inst_0 = out_uop_1_bits_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_rvc; // @[Mux.scala:30:73] assign io_deq_1_bits_rvc_0 = out_uop_1_bits_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_btb_resp_valid; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_valid_0 = out_uop_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_btb_resp_bits_cfiType; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_cfiType_0 = out_uop_1_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_btb_resp_bits_taken; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_taken_0 = out_uop_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_116_btb_resp_bits_mask; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_mask_0 = out_uop_1_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_btb_resp_bits_bridx; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_bridx_0 = out_uop_1_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_116_btb_resp_bits_target; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_target_0 = out_uop_1_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_116_btb_resp_bits_entry; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_entry_0 = out_uop_1_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_116_btb_resp_bits_bht_history; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_bht_history_0 = out_uop_1_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_btb_resp_bits_bht_value; // @[Mux.scala:30:73] assign io_deq_1_bits_btb_resp_bits_bht_value_0 = out_uop_1_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_sfb_br; // @[Mux.scala:30:73] assign io_deq_1_bits_sfb_br_0 = out_uop_1_bits_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_next_pc_valid; // @[Mux.scala:30:73] assign io_deq_1_bits_next_pc_valid_0 = out_uop_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_116_next_pc_bits; // @[Mux.scala:30:73] assign io_deq_1_bits_next_pc_bits_0 = out_uop_1_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_116_ras_head; // @[Mux.scala:30:73] assign io_deq_1_bits_ras_head_0 = out_uop_1_bits_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_116_xcpt; // @[Mux.scala:30:73] assign io_deq_1_bits_xcpt_0 = out_uop_1_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_116_xcpt_cause; // @[Mux.scala:30:73] assign io_deq_1_bits_xcpt_cause_0 = out_uop_1_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_116_mem_size; // @[Mux.scala:30:73] assign io_deq_1_bits_mem_size_0 = out_uop_1_bits_mem_size; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_230; // @[Mux.scala:30:73] assign out_uop_1_bits_inst = _out_uop_WIRE_116_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_229; // @[Mux.scala:30:73] assign out_uop_1_bits_raw_inst = _out_uop_WIRE_116_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_228; // @[Mux.scala:30:73] assign out_uop_1_bits_pc = _out_uop_WIRE_116_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_227; // @[Mux.scala:30:73] assign out_uop_1_bits_edge_inst = _out_uop_WIRE_116_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_179; // @[Mux.scala:30:73] assign out_uop_1_bits_rvc = _out_uop_WIRE_116_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_166_valid; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_valid = _out_uop_WIRE_116_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_166_bits_cfiType; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_cfiType = _out_uop_WIRE_116_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_166_bits_taken; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_taken = _out_uop_WIRE_116_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_166_bits_mask; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_mask = _out_uop_WIRE_116_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_166_bits_bridx; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_bridx = _out_uop_WIRE_116_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_166_bits_target; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_target = _out_uop_WIRE_116_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_166_bits_entry; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_entry = _out_uop_WIRE_116_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_166_bits_bht_history; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_bht_history = _out_uop_WIRE_116_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_166_bits_bht_value; // @[Mux.scala:30:73] assign out_uop_1_bits_btb_resp_bits_bht_value = _out_uop_WIRE_116_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_165; // @[Mux.scala:30:73] assign out_uop_1_bits_sfb_br = _out_uop_WIRE_116_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_161_valid; // @[Mux.scala:30:73] assign out_uop_1_bits_next_pc_valid = _out_uop_WIRE_116_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_161_bits; // @[Mux.scala:30:73] assign out_uop_1_bits_next_pc_bits = _out_uop_WIRE_116_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_160; // @[Mux.scala:30:73] assign out_uop_1_bits_ras_head = _out_uop_WIRE_116_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_158; // @[Mux.scala:30:73] assign out_uop_1_bits_xcpt = _out_uop_WIRE_116_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_157; // @[Mux.scala:30:73] assign out_uop_1_bits_xcpt_cause = _out_uop_WIRE_116_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_118; // @[Mux.scala:30:73] assign out_uop_1_bits_mem_size = _out_uop_WIRE_116_mem_size; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1418 = _out_uop_T_1398 ? ram_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1419 = _out_uop_T_1399 ? ram_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1420 = _out_uop_T_1400 ? ram_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1421 = _out_uop_T_1401 ? ram_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1422 = _out_uop_T_1402 ? ram_4_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1423 = _out_uop_T_1403 ? ram_5_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1424 = _out_uop_T_1404 ? ram_6_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_1425 = _out_uop_T_1418 | _out_uop_T_1419; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1426 = _out_uop_T_1425 | _out_uop_T_1420; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1427 = _out_uop_T_1426 | _out_uop_T_1421; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1428 = _out_uop_T_1427 | _out_uop_T_1422; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1429 = _out_uop_T_1428 | _out_uop_T_1423; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_1430 = _out_uop_T_1429 | _out_uop_T_1424; // @[Mux.scala:30:73] assign _out_uop_WIRE_118 = _out_uop_T_1430; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_mem_size = _out_uop_WIRE_118; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1899 = _out_uop_T_1398 ? ram_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1900 = _out_uop_T_1399 ? ram_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1901 = _out_uop_T_1400 ? ram_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1902 = _out_uop_T_1401 ? ram_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1903 = _out_uop_T_1402 ? ram_4_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1904 = _out_uop_T_1403 ? ram_5_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1905 = _out_uop_T_1404 ? ram_6_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_1906 = _out_uop_T_1899 | _out_uop_T_1900; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1907 = _out_uop_T_1906 | _out_uop_T_1901; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1908 = _out_uop_T_1907 | _out_uop_T_1902; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1909 = _out_uop_T_1908 | _out_uop_T_1903; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1910 = _out_uop_T_1909 | _out_uop_T_1904; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_1911 = _out_uop_T_1910 | _out_uop_T_1905; // @[Mux.scala:30:73] assign _out_uop_WIRE_157 = _out_uop_T_1911; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_xcpt_cause = _out_uop_WIRE_157; // @[Mux.scala:30:73] wire _out_uop_T_1912 = _out_uop_T_1398 & ram_0_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1913 = _out_uop_T_1399 & ram_1_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1914 = _out_uop_T_1400 & ram_2_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1915 = _out_uop_T_1401 & ram_3_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1916 = _out_uop_T_1402 & ram_4_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1917 = _out_uop_T_1403 & ram_5_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1918 = _out_uop_T_1404 & ram_6_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1919 = _out_uop_T_1912 | _out_uop_T_1913; // @[Mux.scala:30:73] wire _out_uop_T_1920 = _out_uop_T_1919 | _out_uop_T_1914; // @[Mux.scala:30:73] wire _out_uop_T_1921 = _out_uop_T_1920 | _out_uop_T_1915; // @[Mux.scala:30:73] wire _out_uop_T_1922 = _out_uop_T_1921 | _out_uop_T_1916; // @[Mux.scala:30:73] wire _out_uop_T_1923 = _out_uop_T_1922 | _out_uop_T_1917; // @[Mux.scala:30:73] wire _out_uop_T_1924 = _out_uop_T_1923 | _out_uop_T_1918; // @[Mux.scala:30:73] assign _out_uop_WIRE_158 = _out_uop_T_1924; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_xcpt = _out_uop_WIRE_158; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1938 = _out_uop_T_1398 ? ram_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1939 = _out_uop_T_1399 ? ram_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1940 = _out_uop_T_1400 ? ram_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1941 = _out_uop_T_1401 ? ram_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1942 = _out_uop_T_1402 ? ram_4_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1943 = _out_uop_T_1403 ? ram_5_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1944 = _out_uop_T_1404 ? ram_6_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_1945 = _out_uop_T_1938 | _out_uop_T_1939; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1946 = _out_uop_T_1945 | _out_uop_T_1940; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1947 = _out_uop_T_1946 | _out_uop_T_1941; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1948 = _out_uop_T_1947 | _out_uop_T_1942; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1949 = _out_uop_T_1948 | _out_uop_T_1943; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_1950 = _out_uop_T_1949 | _out_uop_T_1944; // @[Mux.scala:30:73] assign _out_uop_WIRE_160 = _out_uop_T_1950; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_ras_head = _out_uop_WIRE_160; // @[Mux.scala:30:73] wire _out_uop_WIRE_163; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_next_pc_valid = _out_uop_WIRE_161_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_162; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_next_pc_bits = _out_uop_WIRE_161_bits; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1951 = _out_uop_T_1398 ? ram_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1952 = _out_uop_T_1399 ? ram_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1953 = _out_uop_T_1400 ? ram_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1954 = _out_uop_T_1401 ? ram_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1955 = _out_uop_T_1402 ? ram_4_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1956 = _out_uop_T_1403 ? ram_5_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1957 = _out_uop_T_1404 ? ram_6_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_1958 = _out_uop_T_1951 | _out_uop_T_1952; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1959 = _out_uop_T_1958 | _out_uop_T_1953; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1960 = _out_uop_T_1959 | _out_uop_T_1954; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1961 = _out_uop_T_1960 | _out_uop_T_1955; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1962 = _out_uop_T_1961 | _out_uop_T_1956; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_1963 = _out_uop_T_1962 | _out_uop_T_1957; // @[Mux.scala:30:73] assign _out_uop_WIRE_162 = _out_uop_T_1963; // @[Mux.scala:30:73] assign _out_uop_WIRE_161_bits = _out_uop_WIRE_162; // @[Mux.scala:30:73] wire _out_uop_T_1964 = _out_uop_T_1398 & ram_0_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1965 = _out_uop_T_1399 & ram_1_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1966 = _out_uop_T_1400 & ram_2_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1967 = _out_uop_T_1401 & ram_3_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1968 = _out_uop_T_1402 & ram_4_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1969 = _out_uop_T_1403 & ram_5_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1970 = _out_uop_T_1404 & ram_6_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1971 = _out_uop_T_1964 | _out_uop_T_1965; // @[Mux.scala:30:73] wire _out_uop_T_1972 = _out_uop_T_1971 | _out_uop_T_1966; // @[Mux.scala:30:73] wire _out_uop_T_1973 = _out_uop_T_1972 | _out_uop_T_1967; // @[Mux.scala:30:73] wire _out_uop_T_1974 = _out_uop_T_1973 | _out_uop_T_1968; // @[Mux.scala:30:73] wire _out_uop_T_1975 = _out_uop_T_1974 | _out_uop_T_1969; // @[Mux.scala:30:73] wire _out_uop_T_1976 = _out_uop_T_1975 | _out_uop_T_1970; // @[Mux.scala:30:73] assign _out_uop_WIRE_163 = _out_uop_T_1976; // @[Mux.scala:30:73] assign _out_uop_WIRE_161_valid = _out_uop_WIRE_163; // @[Mux.scala:30:73] wire _out_uop_T_1990 = _out_uop_T_1398 & ram_0_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1991 = _out_uop_T_1399 & ram_1_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1992 = _out_uop_T_1400 & ram_2_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1993 = _out_uop_T_1401 & ram_3_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1994 = _out_uop_T_1402 & ram_4_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1995 = _out_uop_T_1403 & ram_5_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1996 = _out_uop_T_1404 & ram_6_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_1997 = _out_uop_T_1990 | _out_uop_T_1991; // @[Mux.scala:30:73] wire _out_uop_T_1998 = _out_uop_T_1997 | _out_uop_T_1992; // @[Mux.scala:30:73] wire _out_uop_T_1999 = _out_uop_T_1998 | _out_uop_T_1993; // @[Mux.scala:30:73] wire _out_uop_T_2000 = _out_uop_T_1999 | _out_uop_T_1994; // @[Mux.scala:30:73] wire _out_uop_T_2001 = _out_uop_T_2000 | _out_uop_T_1995; // @[Mux.scala:30:73] wire _out_uop_T_2002 = _out_uop_T_2001 | _out_uop_T_1996; // @[Mux.scala:30:73] assign _out_uop_WIRE_165 = _out_uop_T_2002; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_sfb_br = _out_uop_WIRE_165; // @[Mux.scala:30:73] wire _out_uop_WIRE_177; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_valid = _out_uop_WIRE_166_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_167_cfiType; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_cfiType = _out_uop_WIRE_166_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_167_taken; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_taken = _out_uop_WIRE_166_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_167_mask; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_mask = _out_uop_WIRE_166_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_167_bridx; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_bridx = _out_uop_WIRE_166_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_167_target; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_target = _out_uop_WIRE_166_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_167_entry; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_entry = _out_uop_WIRE_166_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_167_bht_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_bht_history = _out_uop_WIRE_166_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_167_bht_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_btb_resp_bits_bht_value = _out_uop_WIRE_166_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_176; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_cfiType = _out_uop_WIRE_167_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_175; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_taken = _out_uop_WIRE_167_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_174; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_mask = _out_uop_WIRE_167_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_173; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_bridx = _out_uop_WIRE_167_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_172; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_target = _out_uop_WIRE_167_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_171; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_entry = _out_uop_WIRE_167_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_168_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_bht_history = _out_uop_WIRE_167_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_168_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_bits_bht_value = _out_uop_WIRE_167_bht_value; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_170; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_bht_history = _out_uop_WIRE_168_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_169; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_bht_value = _out_uop_WIRE_168_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2003 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2004 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2005 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2006 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2007 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2008 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2009 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2010 = _out_uop_T_2003 | _out_uop_T_2004; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2011 = _out_uop_T_2010 | _out_uop_T_2005; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2012 = _out_uop_T_2011 | _out_uop_T_2006; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2013 = _out_uop_T_2012 | _out_uop_T_2007; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2014 = _out_uop_T_2013 | _out_uop_T_2008; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2015 = _out_uop_T_2014 | _out_uop_T_2009; // @[Mux.scala:30:73] assign _out_uop_WIRE_169 = _out_uop_T_2015; // @[Mux.scala:30:73] assign _out_uop_WIRE_168_value = _out_uop_WIRE_169; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_2016 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2017 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2018 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2019 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2020 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2021 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2022 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_2023 = _out_uop_T_2016 | _out_uop_T_2017; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_2024 = _out_uop_T_2023 | _out_uop_T_2018; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_2025 = _out_uop_T_2024 | _out_uop_T_2019; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_2026 = _out_uop_T_2025 | _out_uop_T_2020; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_2027 = _out_uop_T_2026 | _out_uop_T_2021; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_2028 = _out_uop_T_2027 | _out_uop_T_2022; // @[Mux.scala:30:73] assign _out_uop_WIRE_170 = _out_uop_T_2028; // @[Mux.scala:30:73] assign _out_uop_WIRE_168_history = _out_uop_WIRE_170; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_2029 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2030 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2031 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2032 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2033 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2034 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2035 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_2036 = _out_uop_T_2029 | _out_uop_T_2030; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_2037 = _out_uop_T_2036 | _out_uop_T_2031; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_2038 = _out_uop_T_2037 | _out_uop_T_2032; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_2039 = _out_uop_T_2038 | _out_uop_T_2033; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_2040 = _out_uop_T_2039 | _out_uop_T_2034; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_2041 = _out_uop_T_2040 | _out_uop_T_2035; // @[Mux.scala:30:73] assign _out_uop_WIRE_171 = _out_uop_T_2041; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_entry = _out_uop_WIRE_171; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_2042 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2043 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2044 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2045 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2046 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2047 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2048 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_2049 = _out_uop_T_2042 | _out_uop_T_2043; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_2050 = _out_uop_T_2049 | _out_uop_T_2044; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_2051 = _out_uop_T_2050 | _out_uop_T_2045; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_2052 = _out_uop_T_2051 | _out_uop_T_2046; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_2053 = _out_uop_T_2052 | _out_uop_T_2047; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_2054 = _out_uop_T_2053 | _out_uop_T_2048; // @[Mux.scala:30:73] assign _out_uop_WIRE_172 = _out_uop_T_2054; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_target = _out_uop_WIRE_172; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2055 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2056 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2057 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2058 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2059 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2060 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2061 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2062 = _out_uop_T_2055 | _out_uop_T_2056; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2063 = _out_uop_T_2062 | _out_uop_T_2057; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2064 = _out_uop_T_2063 | _out_uop_T_2058; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2065 = _out_uop_T_2064 | _out_uop_T_2059; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2066 = _out_uop_T_2065 | _out_uop_T_2060; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2067 = _out_uop_T_2066 | _out_uop_T_2061; // @[Mux.scala:30:73] assign _out_uop_WIRE_173 = _out_uop_T_2067; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_bridx = _out_uop_WIRE_173; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_2068 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2069 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2070 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2071 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2072 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2073 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2074 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_2075 = _out_uop_T_2068 | _out_uop_T_2069; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_2076 = _out_uop_T_2075 | _out_uop_T_2070; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_2077 = _out_uop_T_2076 | _out_uop_T_2071; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_2078 = _out_uop_T_2077 | _out_uop_T_2072; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_2079 = _out_uop_T_2078 | _out_uop_T_2073; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_2080 = _out_uop_T_2079 | _out_uop_T_2074; // @[Mux.scala:30:73] assign _out_uop_WIRE_174 = _out_uop_T_2080; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_mask = _out_uop_WIRE_174; // @[Mux.scala:30:73] wire _out_uop_T_2081 = _out_uop_T_1398 & ram_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2082 = _out_uop_T_1399 & ram_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2083 = _out_uop_T_1400 & ram_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2084 = _out_uop_T_1401 & ram_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2085 = _out_uop_T_1402 & ram_4_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2086 = _out_uop_T_1403 & ram_5_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2087 = _out_uop_T_1404 & ram_6_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2088 = _out_uop_T_2081 | _out_uop_T_2082; // @[Mux.scala:30:73] wire _out_uop_T_2089 = _out_uop_T_2088 | _out_uop_T_2083; // @[Mux.scala:30:73] wire _out_uop_T_2090 = _out_uop_T_2089 | _out_uop_T_2084; // @[Mux.scala:30:73] wire _out_uop_T_2091 = _out_uop_T_2090 | _out_uop_T_2085; // @[Mux.scala:30:73] wire _out_uop_T_2092 = _out_uop_T_2091 | _out_uop_T_2086; // @[Mux.scala:30:73] wire _out_uop_T_2093 = _out_uop_T_2092 | _out_uop_T_2087; // @[Mux.scala:30:73] assign _out_uop_WIRE_175 = _out_uop_T_2093; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_taken = _out_uop_WIRE_175; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2094 = _out_uop_T_1398 ? ram_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2095 = _out_uop_T_1399 ? ram_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2096 = _out_uop_T_1400 ? ram_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2097 = _out_uop_T_1401 ? ram_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2098 = _out_uop_T_1402 ? ram_4_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2099 = _out_uop_T_1403 ? ram_5_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2100 = _out_uop_T_1404 ? ram_6_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2101 = _out_uop_T_2094 | _out_uop_T_2095; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2102 = _out_uop_T_2101 | _out_uop_T_2096; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2103 = _out_uop_T_2102 | _out_uop_T_2097; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2104 = _out_uop_T_2103 | _out_uop_T_2098; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2105 = _out_uop_T_2104 | _out_uop_T_2099; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2106 = _out_uop_T_2105 | _out_uop_T_2100; // @[Mux.scala:30:73] assign _out_uop_WIRE_176 = _out_uop_T_2106; // @[Mux.scala:30:73] assign _out_uop_WIRE_167_cfiType = _out_uop_WIRE_176; // @[Mux.scala:30:73] wire _out_uop_T_2107 = _out_uop_T_1398 & ram_0_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2108 = _out_uop_T_1399 & ram_1_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2109 = _out_uop_T_1400 & ram_2_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2110 = _out_uop_T_1401 & ram_3_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2111 = _out_uop_T_1402 & ram_4_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2112 = _out_uop_T_1403 & ram_5_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2113 = _out_uop_T_1404 & ram_6_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2114 = _out_uop_T_2107 | _out_uop_T_2108; // @[Mux.scala:30:73] wire _out_uop_T_2115 = _out_uop_T_2114 | _out_uop_T_2109; // @[Mux.scala:30:73] wire _out_uop_T_2116 = _out_uop_T_2115 | _out_uop_T_2110; // @[Mux.scala:30:73] wire _out_uop_T_2117 = _out_uop_T_2116 | _out_uop_T_2111; // @[Mux.scala:30:73] wire _out_uop_T_2118 = _out_uop_T_2117 | _out_uop_T_2112; // @[Mux.scala:30:73] wire _out_uop_T_2119 = _out_uop_T_2118 | _out_uop_T_2113; // @[Mux.scala:30:73] assign _out_uop_WIRE_177 = _out_uop_T_2119; // @[Mux.scala:30:73] assign _out_uop_WIRE_166_valid = _out_uop_WIRE_177; // @[Mux.scala:30:73] wire _out_uop_T_2133 = _out_uop_T_1398 & ram_0_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2134 = _out_uop_T_1399 & ram_1_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2135 = _out_uop_T_1400 & ram_2_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2136 = _out_uop_T_1401 & ram_3_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2137 = _out_uop_T_1402 & ram_4_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2138 = _out_uop_T_1403 & ram_5_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2139 = _out_uop_T_1404 & ram_6_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2140 = _out_uop_T_2133 | _out_uop_T_2134; // @[Mux.scala:30:73] wire _out_uop_T_2141 = _out_uop_T_2140 | _out_uop_T_2135; // @[Mux.scala:30:73] wire _out_uop_T_2142 = _out_uop_T_2141 | _out_uop_T_2136; // @[Mux.scala:30:73] wire _out_uop_T_2143 = _out_uop_T_2142 | _out_uop_T_2137; // @[Mux.scala:30:73] wire _out_uop_T_2144 = _out_uop_T_2143 | _out_uop_T_2138; // @[Mux.scala:30:73] wire _out_uop_T_2145 = _out_uop_T_2144 | _out_uop_T_2139; // @[Mux.scala:30:73] assign _out_uop_WIRE_179 = _out_uop_T_2145; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_rvc = _out_uop_WIRE_179; // @[Mux.scala:30:73] wire _out_uop_T_2731 = _out_uop_T_1398 & ram_0_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2732 = _out_uop_T_1399 & ram_1_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2733 = _out_uop_T_1400 & ram_2_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2734 = _out_uop_T_1401 & ram_3_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2735 = _out_uop_T_1402 & ram_4_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2736 = _out_uop_T_1403 & ram_5_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2737 = _out_uop_T_1404 & ram_6_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2738 = _out_uop_T_2731 | _out_uop_T_2732; // @[Mux.scala:30:73] wire _out_uop_T_2739 = _out_uop_T_2738 | _out_uop_T_2733; // @[Mux.scala:30:73] wire _out_uop_T_2740 = _out_uop_T_2739 | _out_uop_T_2734; // @[Mux.scala:30:73] wire _out_uop_T_2741 = _out_uop_T_2740 | _out_uop_T_2735; // @[Mux.scala:30:73] wire _out_uop_T_2742 = _out_uop_T_2741 | _out_uop_T_2736; // @[Mux.scala:30:73] wire _out_uop_T_2743 = _out_uop_T_2742 | _out_uop_T_2737; // @[Mux.scala:30:73] assign _out_uop_WIRE_227 = _out_uop_T_2743; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_edge_inst = _out_uop_WIRE_227; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_2744 = _out_uop_T_1398 ? ram_0_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2745 = _out_uop_T_1399 ? ram_1_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2746 = _out_uop_T_1400 ? ram_2_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2747 = _out_uop_T_1401 ? ram_3_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2748 = _out_uop_T_1402 ? ram_4_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2749 = _out_uop_T_1403 ? ram_5_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2750 = _out_uop_T_1404 ? ram_6_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_2751 = _out_uop_T_2744 | _out_uop_T_2745; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_2752 = _out_uop_T_2751 | _out_uop_T_2746; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_2753 = _out_uop_T_2752 | _out_uop_T_2747; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_2754 = _out_uop_T_2753 | _out_uop_T_2748; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_2755 = _out_uop_T_2754 | _out_uop_T_2749; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_2756 = _out_uop_T_2755 | _out_uop_T_2750; // @[Mux.scala:30:73] assign _out_uop_WIRE_228 = _out_uop_T_2756; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_pc = _out_uop_WIRE_228; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2757 = _out_uop_T_1398 ? ram_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2758 = _out_uop_T_1399 ? ram_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2759 = _out_uop_T_1400 ? ram_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2760 = _out_uop_T_1401 ? ram_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2761 = _out_uop_T_1402 ? ram_4_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2762 = _out_uop_T_1403 ? ram_5_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2763 = _out_uop_T_1404 ? ram_6_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2764 = _out_uop_T_2757 | _out_uop_T_2758; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2765 = _out_uop_T_2764 | _out_uop_T_2759; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2766 = _out_uop_T_2765 | _out_uop_T_2760; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2767 = _out_uop_T_2766 | _out_uop_T_2761; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2768 = _out_uop_T_2767 | _out_uop_T_2762; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2769 = _out_uop_T_2768 | _out_uop_T_2763; // @[Mux.scala:30:73] assign _out_uop_WIRE_229 = _out_uop_T_2769; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_raw_inst = _out_uop_WIRE_229; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2770 = _out_uop_T_1398 ? ram_0_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2771 = _out_uop_T_1399 ? ram_1_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2772 = _out_uop_T_1400 ? ram_2_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2773 = _out_uop_T_1401 ? ram_3_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2774 = _out_uop_T_1402 ? ram_4_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2775 = _out_uop_T_1403 ? ram_5_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2776 = _out_uop_T_1404 ? ram_6_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_2777 = _out_uop_T_2770 | _out_uop_T_2771; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2778 = _out_uop_T_2777 | _out_uop_T_2772; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2779 = _out_uop_T_2778 | _out_uop_T_2773; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2780 = _out_uop_T_2779 | _out_uop_T_2774; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2781 = _out_uop_T_2780 | _out_uop_T_2775; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_2782 = _out_uop_T_2781 | _out_uop_T_2776; // @[Mux.scala:30:73] assign _out_uop_WIRE_230 = _out_uop_T_2782; // @[Mux.scala:30:73] assign _out_uop_WIRE_116_inst = _out_uop_WIRE_230; // @[Mux.scala:30:73] wire _out_uop_T_2783 = _out_uop_T_1398 & ram_0_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2784 = _out_uop_T_1399 & ram_1_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2785 = _out_uop_T_1400 & ram_2_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2786 = _out_uop_T_1401 & ram_3_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2787 = _out_uop_T_1402 & ram_4_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2788 = _out_uop_T_1403 & ram_5_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2789 = _out_uop_T_1404 & ram_6_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_2790 = _out_uop_T_2783 | _out_uop_T_2784; // @[Mux.scala:30:73] wire _out_uop_T_2791 = _out_uop_T_2790 | _out_uop_T_2785; // @[Mux.scala:30:73] wire _out_uop_T_2792 = _out_uop_T_2791 | _out_uop_T_2786; // @[Mux.scala:30:73] wire _out_uop_T_2793 = _out_uop_T_2792 | _out_uop_T_2787; // @[Mux.scala:30:73] wire _out_uop_T_2794 = _out_uop_T_2793 | _out_uop_T_2788; // @[Mux.scala:30:73] wire _out_uop_T_2795 = _out_uop_T_2794 | _out_uop_T_2789; // @[Mux.scala:30:73] assign _out_uop_WIRE_231 = _out_uop_T_2795; // @[Mux.scala:30:73] assign out_uop_1_valid = _out_uop_WIRE_231; // @[Mux.scala:30:73] wire _deq_ptr_T_1 = io_deq_1_ready_0 & io_deq_1_valid_0; // @[Decoupled.scala:51:35] wire _out_uop_T_2797 = deq_ptr[6]; // @[Mux.scala:32:36] wire _out_uop_T_4196 = deq_ptr[6]; // @[Mux.scala:32:36] wire _out_uop_T_2802 = deq_ptr[4]; // @[Mux.scala:32:36] wire _out_uop_WIRE_347; // @[Mux.scala:30:73] assign io_peek_0_valid_0 = out_uop_2_valid; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_232_inst; // @[Mux.scala:30:73] assign io_peek_0_bits_inst_0 = out_uop_2_bits_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_232_raw_inst; // @[Mux.scala:30:73] assign io_peek_0_bits_raw_inst_0 = out_uop_2_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_232_pc; // @[Mux.scala:30:73] assign io_peek_0_bits_pc_0 = out_uop_2_bits_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_edge_inst; // @[Mux.scala:30:73] assign io_peek_0_bits_edge_inst_0 = out_uop_2_bits_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_rvc; // @[Mux.scala:30:73] assign io_peek_0_bits_rvc_0 = out_uop_2_bits_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_btb_resp_valid; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_valid_0 = out_uop_2_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_btb_resp_bits_cfiType; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_cfiType_0 = out_uop_2_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_btb_resp_bits_taken; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_taken_0 = out_uop_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_232_btb_resp_bits_mask; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_mask_0 = out_uop_2_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_btb_resp_bits_bridx; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_bridx_0 = out_uop_2_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_232_btb_resp_bits_target; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_target_0 = out_uop_2_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_232_btb_resp_bits_entry; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_entry_0 = out_uop_2_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_232_btb_resp_bits_bht_history; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_bht_history_0 = out_uop_2_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_btb_resp_bits_bht_value; // @[Mux.scala:30:73] assign io_peek_0_bits_btb_resp_bits_bht_value_0 = out_uop_2_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_sfb_br; // @[Mux.scala:30:73] assign io_peek_0_bits_sfb_br_0 = out_uop_2_bits_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_next_pc_valid; // @[Mux.scala:30:73] assign io_peek_0_bits_next_pc_valid_0 = out_uop_2_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_232_next_pc_bits; // @[Mux.scala:30:73] assign io_peek_0_bits_next_pc_bits_0 = out_uop_2_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_232_ras_head; // @[Mux.scala:30:73] assign io_peek_0_bits_ras_head_0 = out_uop_2_bits_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_232_xcpt; // @[Mux.scala:30:73] assign io_peek_0_bits_xcpt_0 = out_uop_2_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_232_xcpt_cause; // @[Mux.scala:30:73] assign io_peek_0_bits_xcpt_cause_0 = out_uop_2_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_232_mem_size; // @[Mux.scala:30:73] assign io_peek_0_bits_mem_size_0 = out_uop_2_bits_mem_size; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_346; // @[Mux.scala:30:73] assign out_uop_2_bits_inst = _out_uop_WIRE_232_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_345; // @[Mux.scala:30:73] assign out_uop_2_bits_raw_inst = _out_uop_WIRE_232_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_344; // @[Mux.scala:30:73] assign out_uop_2_bits_pc = _out_uop_WIRE_232_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_343; // @[Mux.scala:30:73] assign out_uop_2_bits_edge_inst = _out_uop_WIRE_232_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_295; // @[Mux.scala:30:73] assign out_uop_2_bits_rvc = _out_uop_WIRE_232_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_282_valid; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_valid = _out_uop_WIRE_232_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_282_bits_cfiType; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_cfiType = _out_uop_WIRE_232_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_282_bits_taken; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_taken = _out_uop_WIRE_232_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_282_bits_mask; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_mask = _out_uop_WIRE_232_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_282_bits_bridx; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_bridx = _out_uop_WIRE_232_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_282_bits_target; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_target = _out_uop_WIRE_232_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_282_bits_entry; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_entry = _out_uop_WIRE_232_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_282_bits_bht_history; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_bht_history = _out_uop_WIRE_232_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_282_bits_bht_value; // @[Mux.scala:30:73] assign out_uop_2_bits_btb_resp_bits_bht_value = _out_uop_WIRE_232_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_281; // @[Mux.scala:30:73] assign out_uop_2_bits_sfb_br = _out_uop_WIRE_232_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_277_valid; // @[Mux.scala:30:73] assign out_uop_2_bits_next_pc_valid = _out_uop_WIRE_232_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_277_bits; // @[Mux.scala:30:73] assign out_uop_2_bits_next_pc_bits = _out_uop_WIRE_232_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_276; // @[Mux.scala:30:73] assign out_uop_2_bits_ras_head = _out_uop_WIRE_232_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_274; // @[Mux.scala:30:73] assign out_uop_2_bits_xcpt = _out_uop_WIRE_232_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_273; // @[Mux.scala:30:73] assign out_uop_2_bits_xcpt_cause = _out_uop_WIRE_232_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_234; // @[Mux.scala:30:73] assign out_uop_2_bits_mem_size = _out_uop_WIRE_232_mem_size; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2816 = _out_uop_T_2796 ? ram_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2817 = _out_uop_T_2797 ? ram_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2818 = _out_uop_T_2798 ? ram_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2819 = _out_uop_T_2799 ? ram_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2820 = _out_uop_T_2800 ? ram_4_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2821 = _out_uop_T_2801 ? ram_5_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2822 = _out_uop_T_2802 ? ram_6_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_2823 = _out_uop_T_2816 | _out_uop_T_2817; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2824 = _out_uop_T_2823 | _out_uop_T_2818; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2825 = _out_uop_T_2824 | _out_uop_T_2819; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2826 = _out_uop_T_2825 | _out_uop_T_2820; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2827 = _out_uop_T_2826 | _out_uop_T_2821; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_2828 = _out_uop_T_2827 | _out_uop_T_2822; // @[Mux.scala:30:73] assign _out_uop_WIRE_234 = _out_uop_T_2828; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_mem_size = _out_uop_WIRE_234; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3297 = _out_uop_T_2796 ? ram_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3298 = _out_uop_T_2797 ? ram_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3299 = _out_uop_T_2798 ? ram_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3300 = _out_uop_T_2799 ? ram_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3301 = _out_uop_T_2800 ? ram_4_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3302 = _out_uop_T_2801 ? ram_5_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3303 = _out_uop_T_2802 ? ram_6_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_3304 = _out_uop_T_3297 | _out_uop_T_3298; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3305 = _out_uop_T_3304 | _out_uop_T_3299; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3306 = _out_uop_T_3305 | _out_uop_T_3300; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3307 = _out_uop_T_3306 | _out_uop_T_3301; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3308 = _out_uop_T_3307 | _out_uop_T_3302; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_3309 = _out_uop_T_3308 | _out_uop_T_3303; // @[Mux.scala:30:73] assign _out_uop_WIRE_273 = _out_uop_T_3309; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_xcpt_cause = _out_uop_WIRE_273; // @[Mux.scala:30:73] wire _out_uop_T_3310 = _out_uop_T_2796 & ram_0_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3311 = _out_uop_T_2797 & ram_1_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3312 = _out_uop_T_2798 & ram_2_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3313 = _out_uop_T_2799 & ram_3_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3314 = _out_uop_T_2800 & ram_4_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3315 = _out_uop_T_2801 & ram_5_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3316 = _out_uop_T_2802 & ram_6_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3317 = _out_uop_T_3310 | _out_uop_T_3311; // @[Mux.scala:30:73] wire _out_uop_T_3318 = _out_uop_T_3317 | _out_uop_T_3312; // @[Mux.scala:30:73] wire _out_uop_T_3319 = _out_uop_T_3318 | _out_uop_T_3313; // @[Mux.scala:30:73] wire _out_uop_T_3320 = _out_uop_T_3319 | _out_uop_T_3314; // @[Mux.scala:30:73] wire _out_uop_T_3321 = _out_uop_T_3320 | _out_uop_T_3315; // @[Mux.scala:30:73] wire _out_uop_T_3322 = _out_uop_T_3321 | _out_uop_T_3316; // @[Mux.scala:30:73] assign _out_uop_WIRE_274 = _out_uop_T_3322; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_xcpt = _out_uop_WIRE_274; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3336 = _out_uop_T_2796 ? ram_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3337 = _out_uop_T_2797 ? ram_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3338 = _out_uop_T_2798 ? ram_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3339 = _out_uop_T_2799 ? ram_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3340 = _out_uop_T_2800 ? ram_4_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3341 = _out_uop_T_2801 ? ram_5_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3342 = _out_uop_T_2802 ? ram_6_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_3343 = _out_uop_T_3336 | _out_uop_T_3337; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3344 = _out_uop_T_3343 | _out_uop_T_3338; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3345 = _out_uop_T_3344 | _out_uop_T_3339; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3346 = _out_uop_T_3345 | _out_uop_T_3340; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3347 = _out_uop_T_3346 | _out_uop_T_3341; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_3348 = _out_uop_T_3347 | _out_uop_T_3342; // @[Mux.scala:30:73] assign _out_uop_WIRE_276 = _out_uop_T_3348; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_ras_head = _out_uop_WIRE_276; // @[Mux.scala:30:73] wire _out_uop_WIRE_279; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_next_pc_valid = _out_uop_WIRE_277_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_278; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_next_pc_bits = _out_uop_WIRE_277_bits; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_3349 = _out_uop_T_2796 ? ram_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3350 = _out_uop_T_2797 ? ram_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3351 = _out_uop_T_2798 ? ram_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3352 = _out_uop_T_2799 ? ram_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3353 = _out_uop_T_2800 ? ram_4_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3354 = _out_uop_T_2801 ? ram_5_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3355 = _out_uop_T_2802 ? ram_6_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_3356 = _out_uop_T_3349 | _out_uop_T_3350; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_3357 = _out_uop_T_3356 | _out_uop_T_3351; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_3358 = _out_uop_T_3357 | _out_uop_T_3352; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_3359 = _out_uop_T_3358 | _out_uop_T_3353; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_3360 = _out_uop_T_3359 | _out_uop_T_3354; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_3361 = _out_uop_T_3360 | _out_uop_T_3355; // @[Mux.scala:30:73] assign _out_uop_WIRE_278 = _out_uop_T_3361; // @[Mux.scala:30:73] assign _out_uop_WIRE_277_bits = _out_uop_WIRE_278; // @[Mux.scala:30:73] wire _out_uop_T_3362 = _out_uop_T_2796 & ram_0_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3363 = _out_uop_T_2797 & ram_1_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3364 = _out_uop_T_2798 & ram_2_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3365 = _out_uop_T_2799 & ram_3_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3366 = _out_uop_T_2800 & ram_4_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3367 = _out_uop_T_2801 & ram_5_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3368 = _out_uop_T_2802 & ram_6_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3369 = _out_uop_T_3362 | _out_uop_T_3363; // @[Mux.scala:30:73] wire _out_uop_T_3370 = _out_uop_T_3369 | _out_uop_T_3364; // @[Mux.scala:30:73] wire _out_uop_T_3371 = _out_uop_T_3370 | _out_uop_T_3365; // @[Mux.scala:30:73] wire _out_uop_T_3372 = _out_uop_T_3371 | _out_uop_T_3366; // @[Mux.scala:30:73] wire _out_uop_T_3373 = _out_uop_T_3372 | _out_uop_T_3367; // @[Mux.scala:30:73] wire _out_uop_T_3374 = _out_uop_T_3373 | _out_uop_T_3368; // @[Mux.scala:30:73] assign _out_uop_WIRE_279 = _out_uop_T_3374; // @[Mux.scala:30:73] assign _out_uop_WIRE_277_valid = _out_uop_WIRE_279; // @[Mux.scala:30:73] wire _out_uop_T_3388 = _out_uop_T_2796 & ram_0_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3389 = _out_uop_T_2797 & ram_1_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3390 = _out_uop_T_2798 & ram_2_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3391 = _out_uop_T_2799 & ram_3_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3392 = _out_uop_T_2800 & ram_4_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3393 = _out_uop_T_2801 & ram_5_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3394 = _out_uop_T_2802 & ram_6_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3395 = _out_uop_T_3388 | _out_uop_T_3389; // @[Mux.scala:30:73] wire _out_uop_T_3396 = _out_uop_T_3395 | _out_uop_T_3390; // @[Mux.scala:30:73] wire _out_uop_T_3397 = _out_uop_T_3396 | _out_uop_T_3391; // @[Mux.scala:30:73] wire _out_uop_T_3398 = _out_uop_T_3397 | _out_uop_T_3392; // @[Mux.scala:30:73] wire _out_uop_T_3399 = _out_uop_T_3398 | _out_uop_T_3393; // @[Mux.scala:30:73] wire _out_uop_T_3400 = _out_uop_T_3399 | _out_uop_T_3394; // @[Mux.scala:30:73] assign _out_uop_WIRE_281 = _out_uop_T_3400; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_sfb_br = _out_uop_WIRE_281; // @[Mux.scala:30:73] wire _out_uop_WIRE_293; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_valid = _out_uop_WIRE_282_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_283_cfiType; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_cfiType = _out_uop_WIRE_282_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_283_taken; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_taken = _out_uop_WIRE_282_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_283_mask; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_mask = _out_uop_WIRE_282_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_283_bridx; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_bridx = _out_uop_WIRE_282_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_283_target; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_target = _out_uop_WIRE_282_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_283_entry; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_entry = _out_uop_WIRE_282_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_283_bht_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_bht_history = _out_uop_WIRE_282_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_283_bht_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_btb_resp_bits_bht_value = _out_uop_WIRE_282_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_292; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_cfiType = _out_uop_WIRE_283_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_291; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_taken = _out_uop_WIRE_283_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_290; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_mask = _out_uop_WIRE_283_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_289; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_bridx = _out_uop_WIRE_283_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_288; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_target = _out_uop_WIRE_283_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_287; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_entry = _out_uop_WIRE_283_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_284_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_bht_history = _out_uop_WIRE_283_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_284_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_bits_bht_value = _out_uop_WIRE_283_bht_value; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_286; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_bht_history = _out_uop_WIRE_284_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_285; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_bht_value = _out_uop_WIRE_284_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3401 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3402 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3403 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3404 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3405 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3406 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3407 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3408 = _out_uop_T_3401 | _out_uop_T_3402; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3409 = _out_uop_T_3408 | _out_uop_T_3403; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3410 = _out_uop_T_3409 | _out_uop_T_3404; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3411 = _out_uop_T_3410 | _out_uop_T_3405; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3412 = _out_uop_T_3411 | _out_uop_T_3406; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3413 = _out_uop_T_3412 | _out_uop_T_3407; // @[Mux.scala:30:73] assign _out_uop_WIRE_285 = _out_uop_T_3413; // @[Mux.scala:30:73] assign _out_uop_WIRE_284_value = _out_uop_WIRE_285; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_3414 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3415 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3416 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3417 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3418 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3419 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3420 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_3421 = _out_uop_T_3414 | _out_uop_T_3415; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_3422 = _out_uop_T_3421 | _out_uop_T_3416; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_3423 = _out_uop_T_3422 | _out_uop_T_3417; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_3424 = _out_uop_T_3423 | _out_uop_T_3418; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_3425 = _out_uop_T_3424 | _out_uop_T_3419; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_3426 = _out_uop_T_3425 | _out_uop_T_3420; // @[Mux.scala:30:73] assign _out_uop_WIRE_286 = _out_uop_T_3426; // @[Mux.scala:30:73] assign _out_uop_WIRE_284_history = _out_uop_WIRE_286; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_3427 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3428 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3429 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3430 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3431 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3432 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3433 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_3434 = _out_uop_T_3427 | _out_uop_T_3428; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_3435 = _out_uop_T_3434 | _out_uop_T_3429; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_3436 = _out_uop_T_3435 | _out_uop_T_3430; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_3437 = _out_uop_T_3436 | _out_uop_T_3431; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_3438 = _out_uop_T_3437 | _out_uop_T_3432; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_3439 = _out_uop_T_3438 | _out_uop_T_3433; // @[Mux.scala:30:73] assign _out_uop_WIRE_287 = _out_uop_T_3439; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_entry = _out_uop_WIRE_287; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_3440 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3441 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3442 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3443 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3444 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3445 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3446 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_3447 = _out_uop_T_3440 | _out_uop_T_3441; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_3448 = _out_uop_T_3447 | _out_uop_T_3442; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_3449 = _out_uop_T_3448 | _out_uop_T_3443; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_3450 = _out_uop_T_3449 | _out_uop_T_3444; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_3451 = _out_uop_T_3450 | _out_uop_T_3445; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_3452 = _out_uop_T_3451 | _out_uop_T_3446; // @[Mux.scala:30:73] assign _out_uop_WIRE_288 = _out_uop_T_3452; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_target = _out_uop_WIRE_288; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3453 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3454 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3455 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3456 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3457 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3458 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3459 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3460 = _out_uop_T_3453 | _out_uop_T_3454; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3461 = _out_uop_T_3460 | _out_uop_T_3455; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3462 = _out_uop_T_3461 | _out_uop_T_3456; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3463 = _out_uop_T_3462 | _out_uop_T_3457; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3464 = _out_uop_T_3463 | _out_uop_T_3458; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3465 = _out_uop_T_3464 | _out_uop_T_3459; // @[Mux.scala:30:73] assign _out_uop_WIRE_289 = _out_uop_T_3465; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_bridx = _out_uop_WIRE_289; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_3466 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3467 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3468 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3469 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3470 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3471 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3472 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_3473 = _out_uop_T_3466 | _out_uop_T_3467; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_3474 = _out_uop_T_3473 | _out_uop_T_3468; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_3475 = _out_uop_T_3474 | _out_uop_T_3469; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_3476 = _out_uop_T_3475 | _out_uop_T_3470; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_3477 = _out_uop_T_3476 | _out_uop_T_3471; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_3478 = _out_uop_T_3477 | _out_uop_T_3472; // @[Mux.scala:30:73] assign _out_uop_WIRE_290 = _out_uop_T_3478; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_mask = _out_uop_WIRE_290; // @[Mux.scala:30:73] wire _out_uop_T_3479 = _out_uop_T_2796 & ram_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3480 = _out_uop_T_2797 & ram_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3481 = _out_uop_T_2798 & ram_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3482 = _out_uop_T_2799 & ram_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3483 = _out_uop_T_2800 & ram_4_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3484 = _out_uop_T_2801 & ram_5_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3485 = _out_uop_T_2802 & ram_6_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3486 = _out_uop_T_3479 | _out_uop_T_3480; // @[Mux.scala:30:73] wire _out_uop_T_3487 = _out_uop_T_3486 | _out_uop_T_3481; // @[Mux.scala:30:73] wire _out_uop_T_3488 = _out_uop_T_3487 | _out_uop_T_3482; // @[Mux.scala:30:73] wire _out_uop_T_3489 = _out_uop_T_3488 | _out_uop_T_3483; // @[Mux.scala:30:73] wire _out_uop_T_3490 = _out_uop_T_3489 | _out_uop_T_3484; // @[Mux.scala:30:73] wire _out_uop_T_3491 = _out_uop_T_3490 | _out_uop_T_3485; // @[Mux.scala:30:73] assign _out_uop_WIRE_291 = _out_uop_T_3491; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_taken = _out_uop_WIRE_291; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3492 = _out_uop_T_2796 ? ram_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3493 = _out_uop_T_2797 ? ram_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3494 = _out_uop_T_2798 ? ram_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3495 = _out_uop_T_2799 ? ram_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3496 = _out_uop_T_2800 ? ram_4_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3497 = _out_uop_T_2801 ? ram_5_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3498 = _out_uop_T_2802 ? ram_6_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_3499 = _out_uop_T_3492 | _out_uop_T_3493; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3500 = _out_uop_T_3499 | _out_uop_T_3494; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3501 = _out_uop_T_3500 | _out_uop_T_3495; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3502 = _out_uop_T_3501 | _out_uop_T_3496; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3503 = _out_uop_T_3502 | _out_uop_T_3497; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_3504 = _out_uop_T_3503 | _out_uop_T_3498; // @[Mux.scala:30:73] assign _out_uop_WIRE_292 = _out_uop_T_3504; // @[Mux.scala:30:73] assign _out_uop_WIRE_283_cfiType = _out_uop_WIRE_292; // @[Mux.scala:30:73] wire _out_uop_T_3505 = _out_uop_T_2796 & ram_0_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3506 = _out_uop_T_2797 & ram_1_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3507 = _out_uop_T_2798 & ram_2_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3508 = _out_uop_T_2799 & ram_3_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3509 = _out_uop_T_2800 & ram_4_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3510 = _out_uop_T_2801 & ram_5_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3511 = _out_uop_T_2802 & ram_6_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3512 = _out_uop_T_3505 | _out_uop_T_3506; // @[Mux.scala:30:73] wire _out_uop_T_3513 = _out_uop_T_3512 | _out_uop_T_3507; // @[Mux.scala:30:73] wire _out_uop_T_3514 = _out_uop_T_3513 | _out_uop_T_3508; // @[Mux.scala:30:73] wire _out_uop_T_3515 = _out_uop_T_3514 | _out_uop_T_3509; // @[Mux.scala:30:73] wire _out_uop_T_3516 = _out_uop_T_3515 | _out_uop_T_3510; // @[Mux.scala:30:73] wire _out_uop_T_3517 = _out_uop_T_3516 | _out_uop_T_3511; // @[Mux.scala:30:73] assign _out_uop_WIRE_293 = _out_uop_T_3517; // @[Mux.scala:30:73] assign _out_uop_WIRE_282_valid = _out_uop_WIRE_293; // @[Mux.scala:30:73] wire _out_uop_T_3531 = _out_uop_T_2796 & ram_0_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3532 = _out_uop_T_2797 & ram_1_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3533 = _out_uop_T_2798 & ram_2_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3534 = _out_uop_T_2799 & ram_3_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3535 = _out_uop_T_2800 & ram_4_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3536 = _out_uop_T_2801 & ram_5_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3537 = _out_uop_T_2802 & ram_6_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_3538 = _out_uop_T_3531 | _out_uop_T_3532; // @[Mux.scala:30:73] wire _out_uop_T_3539 = _out_uop_T_3538 | _out_uop_T_3533; // @[Mux.scala:30:73] wire _out_uop_T_3540 = _out_uop_T_3539 | _out_uop_T_3534; // @[Mux.scala:30:73] wire _out_uop_T_3541 = _out_uop_T_3540 | _out_uop_T_3535; // @[Mux.scala:30:73] wire _out_uop_T_3542 = _out_uop_T_3541 | _out_uop_T_3536; // @[Mux.scala:30:73] wire _out_uop_T_3543 = _out_uop_T_3542 | _out_uop_T_3537; // @[Mux.scala:30:73] assign _out_uop_WIRE_295 = _out_uop_T_3543; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_rvc = _out_uop_WIRE_295; // @[Mux.scala:30:73] wire _out_uop_T_4129 = _out_uop_T_2796 & ram_0_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4130 = _out_uop_T_2797 & ram_1_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4131 = _out_uop_T_2798 & ram_2_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4132 = _out_uop_T_2799 & ram_3_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4133 = _out_uop_T_2800 & ram_4_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4134 = _out_uop_T_2801 & ram_5_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4135 = _out_uop_T_2802 & ram_6_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4136 = _out_uop_T_4129 | _out_uop_T_4130; // @[Mux.scala:30:73] wire _out_uop_T_4137 = _out_uop_T_4136 | _out_uop_T_4131; // @[Mux.scala:30:73] wire _out_uop_T_4138 = _out_uop_T_4137 | _out_uop_T_4132; // @[Mux.scala:30:73] wire _out_uop_T_4139 = _out_uop_T_4138 | _out_uop_T_4133; // @[Mux.scala:30:73] wire _out_uop_T_4140 = _out_uop_T_4139 | _out_uop_T_4134; // @[Mux.scala:30:73] wire _out_uop_T_4141 = _out_uop_T_4140 | _out_uop_T_4135; // @[Mux.scala:30:73] assign _out_uop_WIRE_343 = _out_uop_T_4141; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_edge_inst = _out_uop_WIRE_343; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4142 = _out_uop_T_2796 ? ram_0_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4143 = _out_uop_T_2797 ? ram_1_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4144 = _out_uop_T_2798 ? ram_2_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4145 = _out_uop_T_2799 ? ram_3_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4146 = _out_uop_T_2800 ? ram_4_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4147 = _out_uop_T_2801 ? ram_5_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4148 = _out_uop_T_2802 ? ram_6_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4149 = _out_uop_T_4142 | _out_uop_T_4143; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4150 = _out_uop_T_4149 | _out_uop_T_4144; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4151 = _out_uop_T_4150 | _out_uop_T_4145; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4152 = _out_uop_T_4151 | _out_uop_T_4146; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4153 = _out_uop_T_4152 | _out_uop_T_4147; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4154 = _out_uop_T_4153 | _out_uop_T_4148; // @[Mux.scala:30:73] assign _out_uop_WIRE_344 = _out_uop_T_4154; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_pc = _out_uop_WIRE_344; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4155 = _out_uop_T_2796 ? ram_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4156 = _out_uop_T_2797 ? ram_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4157 = _out_uop_T_2798 ? ram_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4158 = _out_uop_T_2799 ? ram_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4159 = _out_uop_T_2800 ? ram_4_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4160 = _out_uop_T_2801 ? ram_5_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4161 = _out_uop_T_2802 ? ram_6_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4162 = _out_uop_T_4155 | _out_uop_T_4156; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4163 = _out_uop_T_4162 | _out_uop_T_4157; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4164 = _out_uop_T_4163 | _out_uop_T_4158; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4165 = _out_uop_T_4164 | _out_uop_T_4159; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4166 = _out_uop_T_4165 | _out_uop_T_4160; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4167 = _out_uop_T_4166 | _out_uop_T_4161; // @[Mux.scala:30:73] assign _out_uop_WIRE_345 = _out_uop_T_4167; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_raw_inst = _out_uop_WIRE_345; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4168 = _out_uop_T_2796 ? ram_0_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4169 = _out_uop_T_2797 ? ram_1_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4170 = _out_uop_T_2798 ? ram_2_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4171 = _out_uop_T_2799 ? ram_3_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4172 = _out_uop_T_2800 ? ram_4_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4173 = _out_uop_T_2801 ? ram_5_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4174 = _out_uop_T_2802 ? ram_6_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_4175 = _out_uop_T_4168 | _out_uop_T_4169; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4176 = _out_uop_T_4175 | _out_uop_T_4170; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4177 = _out_uop_T_4176 | _out_uop_T_4171; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4178 = _out_uop_T_4177 | _out_uop_T_4172; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4179 = _out_uop_T_4178 | _out_uop_T_4173; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_4180 = _out_uop_T_4179 | _out_uop_T_4174; // @[Mux.scala:30:73] assign _out_uop_WIRE_346 = _out_uop_T_4180; // @[Mux.scala:30:73] assign _out_uop_WIRE_232_inst = _out_uop_WIRE_346; // @[Mux.scala:30:73] wire _out_uop_T_4181 = _out_uop_T_2796 & ram_0_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4182 = _out_uop_T_2797 & ram_1_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4183 = _out_uop_T_2798 & ram_2_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4184 = _out_uop_T_2799 & ram_3_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4185 = _out_uop_T_2800 & ram_4_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4186 = _out_uop_T_2801 & ram_5_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4187 = _out_uop_T_2802 & ram_6_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4188 = _out_uop_T_4181 | _out_uop_T_4182; // @[Mux.scala:30:73] wire _out_uop_T_4189 = _out_uop_T_4188 | _out_uop_T_4183; // @[Mux.scala:30:73] wire _out_uop_T_4190 = _out_uop_T_4189 | _out_uop_T_4184; // @[Mux.scala:30:73] wire _out_uop_T_4191 = _out_uop_T_4190 | _out_uop_T_4185; // @[Mux.scala:30:73] wire _out_uop_T_4192 = _out_uop_T_4191 | _out_uop_T_4186; // @[Mux.scala:30:73] wire _out_uop_T_4193 = _out_uop_T_4192 | _out_uop_T_4187; // @[Mux.scala:30:73] assign _out_uop_WIRE_347 = _out_uop_T_4193; // @[Mux.scala:30:73] assign out_uop_2_valid = _out_uop_WIRE_347; // @[Mux.scala:30:73] wire _out_uop_T_4200 = deq_ptr[3]; // @[Mux.scala:32:36] wire _out_uop_WIRE_463; // @[Mux.scala:30:73] assign io_peek_1_valid_0 = out_uop_3_valid; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_348_inst; // @[Mux.scala:30:73] assign io_peek_1_bits_inst_0 = out_uop_3_bits_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_348_raw_inst; // @[Mux.scala:30:73] assign io_peek_1_bits_raw_inst_0 = out_uop_3_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_348_pc; // @[Mux.scala:30:73] assign io_peek_1_bits_pc_0 = out_uop_3_bits_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_edge_inst; // @[Mux.scala:30:73] assign io_peek_1_bits_edge_inst_0 = out_uop_3_bits_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_rvc; // @[Mux.scala:30:73] assign io_peek_1_bits_rvc_0 = out_uop_3_bits_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_btb_resp_valid; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_valid_0 = out_uop_3_bits_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_btb_resp_bits_cfiType; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_cfiType_0 = out_uop_3_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_btb_resp_bits_taken; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_taken_0 = out_uop_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_348_btb_resp_bits_mask; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_mask_0 = out_uop_3_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_btb_resp_bits_bridx; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_bridx_0 = out_uop_3_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_348_btb_resp_bits_target; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_target_0 = out_uop_3_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_348_btb_resp_bits_entry; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_entry_0 = out_uop_3_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_348_btb_resp_bits_bht_history; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_bht_history_0 = out_uop_3_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_btb_resp_bits_bht_value; // @[Mux.scala:30:73] assign io_peek_1_bits_btb_resp_bits_bht_value_0 = out_uop_3_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_sfb_br; // @[Mux.scala:30:73] assign io_peek_1_bits_sfb_br_0 = out_uop_3_bits_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_next_pc_valid; // @[Mux.scala:30:73] assign io_peek_1_bits_next_pc_valid_0 = out_uop_3_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_348_next_pc_bits; // @[Mux.scala:30:73] assign io_peek_1_bits_next_pc_bits_0 = out_uop_3_bits_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_348_ras_head; // @[Mux.scala:30:73] assign io_peek_1_bits_ras_head_0 = out_uop_3_bits_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_348_xcpt; // @[Mux.scala:30:73] assign io_peek_1_bits_xcpt_0 = out_uop_3_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_348_xcpt_cause; // @[Mux.scala:30:73] assign io_peek_1_bits_xcpt_cause_0 = out_uop_3_bits_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_348_mem_size; // @[Mux.scala:30:73] assign io_peek_1_bits_mem_size_0 = out_uop_3_bits_mem_size; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_462; // @[Mux.scala:30:73] assign out_uop_3_bits_inst = _out_uop_WIRE_348_inst; // @[Mux.scala:30:73] wire [31:0] _out_uop_WIRE_461; // @[Mux.scala:30:73] assign out_uop_3_bits_raw_inst = _out_uop_WIRE_348_raw_inst; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_460; // @[Mux.scala:30:73] assign out_uop_3_bits_pc = _out_uop_WIRE_348_pc; // @[Mux.scala:30:73] wire _out_uop_WIRE_459; // @[Mux.scala:30:73] assign out_uop_3_bits_edge_inst = _out_uop_WIRE_348_edge_inst; // @[Mux.scala:30:73] wire _out_uop_WIRE_411; // @[Mux.scala:30:73] assign out_uop_3_bits_rvc = _out_uop_WIRE_348_rvc; // @[Mux.scala:30:73] wire _out_uop_WIRE_398_valid; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_valid = _out_uop_WIRE_348_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_398_bits_cfiType; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_cfiType = _out_uop_WIRE_348_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_398_bits_taken; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_taken = _out_uop_WIRE_348_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_398_bits_mask; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_mask = _out_uop_WIRE_348_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_398_bits_bridx; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_bridx = _out_uop_WIRE_348_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_398_bits_target; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_target = _out_uop_WIRE_348_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_398_bits_entry; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_entry = _out_uop_WIRE_348_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_398_bits_bht_history; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_bht_history = _out_uop_WIRE_348_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_398_bits_bht_value; // @[Mux.scala:30:73] assign out_uop_3_bits_btb_resp_bits_bht_value = _out_uop_WIRE_348_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _out_uop_WIRE_397; // @[Mux.scala:30:73] assign out_uop_3_bits_sfb_br = _out_uop_WIRE_348_sfb_br; // @[Mux.scala:30:73] wire _out_uop_WIRE_393_valid; // @[Mux.scala:30:73] assign out_uop_3_bits_next_pc_valid = _out_uop_WIRE_348_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_393_bits; // @[Mux.scala:30:73] assign out_uop_3_bits_next_pc_bits = _out_uop_WIRE_348_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _out_uop_WIRE_392; // @[Mux.scala:30:73] assign out_uop_3_bits_ras_head = _out_uop_WIRE_348_ras_head; // @[Mux.scala:30:73] wire _out_uop_WIRE_390; // @[Mux.scala:30:73] assign out_uop_3_bits_xcpt = _out_uop_WIRE_348_xcpt; // @[Mux.scala:30:73] wire [63:0] _out_uop_WIRE_389; // @[Mux.scala:30:73] assign out_uop_3_bits_xcpt_cause = _out_uop_WIRE_348_xcpt_cause; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_350; // @[Mux.scala:30:73] assign out_uop_3_bits_mem_size = _out_uop_WIRE_348_mem_size; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4214 = _out_uop_T_4194 ? ram_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4215 = _out_uop_T_4195 ? ram_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4216 = _out_uop_T_4196 ? ram_2_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4217 = _out_uop_T_4197 ? ram_3_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4218 = _out_uop_T_4198 ? ram_4_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4219 = _out_uop_T_4199 ? ram_5_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4220 = _out_uop_T_4200 ? ram_6_bits_mem_size : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4221 = _out_uop_T_4214 | _out_uop_T_4215; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4222 = _out_uop_T_4221 | _out_uop_T_4216; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4223 = _out_uop_T_4222 | _out_uop_T_4217; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4224 = _out_uop_T_4223 | _out_uop_T_4218; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4225 = _out_uop_T_4224 | _out_uop_T_4219; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4226 = _out_uop_T_4225 | _out_uop_T_4220; // @[Mux.scala:30:73] assign _out_uop_WIRE_350 = _out_uop_T_4226; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_mem_size = _out_uop_WIRE_350; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4695 = _out_uop_T_4194 ? ram_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4696 = _out_uop_T_4195 ? ram_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4697 = _out_uop_T_4196 ? ram_2_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4698 = _out_uop_T_4197 ? ram_3_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4699 = _out_uop_T_4198 ? ram_4_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4700 = _out_uop_T_4199 ? ram_5_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4701 = _out_uop_T_4200 ? ram_6_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _out_uop_T_4702 = _out_uop_T_4695 | _out_uop_T_4696; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4703 = _out_uop_T_4702 | _out_uop_T_4697; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4704 = _out_uop_T_4703 | _out_uop_T_4698; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4705 = _out_uop_T_4704 | _out_uop_T_4699; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4706 = _out_uop_T_4705 | _out_uop_T_4700; // @[Mux.scala:30:73] wire [63:0] _out_uop_T_4707 = _out_uop_T_4706 | _out_uop_T_4701; // @[Mux.scala:30:73] assign _out_uop_WIRE_389 = _out_uop_T_4707; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_xcpt_cause = _out_uop_WIRE_389; // @[Mux.scala:30:73] wire _out_uop_T_4708 = _out_uop_T_4194 & ram_0_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4709 = _out_uop_T_4195 & ram_1_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4710 = _out_uop_T_4196 & ram_2_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4711 = _out_uop_T_4197 & ram_3_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4712 = _out_uop_T_4198 & ram_4_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4713 = _out_uop_T_4199 & ram_5_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4714 = _out_uop_T_4200 & ram_6_bits_xcpt; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4715 = _out_uop_T_4708 | _out_uop_T_4709; // @[Mux.scala:30:73] wire _out_uop_T_4716 = _out_uop_T_4715 | _out_uop_T_4710; // @[Mux.scala:30:73] wire _out_uop_T_4717 = _out_uop_T_4716 | _out_uop_T_4711; // @[Mux.scala:30:73] wire _out_uop_T_4718 = _out_uop_T_4717 | _out_uop_T_4712; // @[Mux.scala:30:73] wire _out_uop_T_4719 = _out_uop_T_4718 | _out_uop_T_4713; // @[Mux.scala:30:73] wire _out_uop_T_4720 = _out_uop_T_4719 | _out_uop_T_4714; // @[Mux.scala:30:73] assign _out_uop_WIRE_390 = _out_uop_T_4720; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_xcpt = _out_uop_WIRE_390; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4734 = _out_uop_T_4194 ? ram_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4735 = _out_uop_T_4195 ? ram_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4736 = _out_uop_T_4196 ? ram_2_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4737 = _out_uop_T_4197 ? ram_3_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4738 = _out_uop_T_4198 ? ram_4_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4739 = _out_uop_T_4199 ? ram_5_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4740 = _out_uop_T_4200 ? ram_6_bits_ras_head : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _out_uop_T_4741 = _out_uop_T_4734 | _out_uop_T_4735; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4742 = _out_uop_T_4741 | _out_uop_T_4736; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4743 = _out_uop_T_4742 | _out_uop_T_4737; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4744 = _out_uop_T_4743 | _out_uop_T_4738; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4745 = _out_uop_T_4744 | _out_uop_T_4739; // @[Mux.scala:30:73] wire [2:0] _out_uop_T_4746 = _out_uop_T_4745 | _out_uop_T_4740; // @[Mux.scala:30:73] assign _out_uop_WIRE_392 = _out_uop_T_4746; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_ras_head = _out_uop_WIRE_392; // @[Mux.scala:30:73] wire _out_uop_WIRE_395; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_next_pc_valid = _out_uop_WIRE_393_valid; // @[Mux.scala:30:73] wire [39:0] _out_uop_WIRE_394; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_next_pc_bits = _out_uop_WIRE_393_bits; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4747 = _out_uop_T_4194 ? ram_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4748 = _out_uop_T_4195 ? ram_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4749 = _out_uop_T_4196 ? ram_2_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4750 = _out_uop_T_4197 ? ram_3_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4751 = _out_uop_T_4198 ? ram_4_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4752 = _out_uop_T_4199 ? ram_5_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4753 = _out_uop_T_4200 ? ram_6_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_4754 = _out_uop_T_4747 | _out_uop_T_4748; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4755 = _out_uop_T_4754 | _out_uop_T_4749; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4756 = _out_uop_T_4755 | _out_uop_T_4750; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4757 = _out_uop_T_4756 | _out_uop_T_4751; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4758 = _out_uop_T_4757 | _out_uop_T_4752; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_4759 = _out_uop_T_4758 | _out_uop_T_4753; // @[Mux.scala:30:73] assign _out_uop_WIRE_394 = _out_uop_T_4759; // @[Mux.scala:30:73] assign _out_uop_WIRE_393_bits = _out_uop_WIRE_394; // @[Mux.scala:30:73] wire _out_uop_T_4760 = _out_uop_T_4194 & ram_0_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4761 = _out_uop_T_4195 & ram_1_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4762 = _out_uop_T_4196 & ram_2_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4763 = _out_uop_T_4197 & ram_3_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4764 = _out_uop_T_4198 & ram_4_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4765 = _out_uop_T_4199 & ram_5_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4766 = _out_uop_T_4200 & ram_6_bits_next_pc_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4767 = _out_uop_T_4760 | _out_uop_T_4761; // @[Mux.scala:30:73] wire _out_uop_T_4768 = _out_uop_T_4767 | _out_uop_T_4762; // @[Mux.scala:30:73] wire _out_uop_T_4769 = _out_uop_T_4768 | _out_uop_T_4763; // @[Mux.scala:30:73] wire _out_uop_T_4770 = _out_uop_T_4769 | _out_uop_T_4764; // @[Mux.scala:30:73] wire _out_uop_T_4771 = _out_uop_T_4770 | _out_uop_T_4765; // @[Mux.scala:30:73] wire _out_uop_T_4772 = _out_uop_T_4771 | _out_uop_T_4766; // @[Mux.scala:30:73] assign _out_uop_WIRE_395 = _out_uop_T_4772; // @[Mux.scala:30:73] assign _out_uop_WIRE_393_valid = _out_uop_WIRE_395; // @[Mux.scala:30:73] wire _out_uop_T_4786 = _out_uop_T_4194 & ram_0_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4787 = _out_uop_T_4195 & ram_1_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4788 = _out_uop_T_4196 & ram_2_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4789 = _out_uop_T_4197 & ram_3_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4790 = _out_uop_T_4198 & ram_4_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4791 = _out_uop_T_4199 & ram_5_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4792 = _out_uop_T_4200 & ram_6_bits_sfb_br; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4793 = _out_uop_T_4786 | _out_uop_T_4787; // @[Mux.scala:30:73] wire _out_uop_T_4794 = _out_uop_T_4793 | _out_uop_T_4788; // @[Mux.scala:30:73] wire _out_uop_T_4795 = _out_uop_T_4794 | _out_uop_T_4789; // @[Mux.scala:30:73] wire _out_uop_T_4796 = _out_uop_T_4795 | _out_uop_T_4790; // @[Mux.scala:30:73] wire _out_uop_T_4797 = _out_uop_T_4796 | _out_uop_T_4791; // @[Mux.scala:30:73] wire _out_uop_T_4798 = _out_uop_T_4797 | _out_uop_T_4792; // @[Mux.scala:30:73] assign _out_uop_WIRE_397 = _out_uop_T_4798; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_sfb_br = _out_uop_WIRE_397; // @[Mux.scala:30:73] wire _out_uop_WIRE_409; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_valid = _out_uop_WIRE_398_valid; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_399_cfiType; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_cfiType = _out_uop_WIRE_398_bits_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_399_taken; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_taken = _out_uop_WIRE_398_bits_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_399_mask; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_mask = _out_uop_WIRE_398_bits_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_399_bridx; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_bridx = _out_uop_WIRE_398_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_399_target; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_target = _out_uop_WIRE_398_bits_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_399_entry; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_entry = _out_uop_WIRE_398_bits_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_399_bht_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_bht_history = _out_uop_WIRE_398_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_399_bht_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_btb_resp_bits_bht_value = _out_uop_WIRE_398_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_408; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_cfiType = _out_uop_WIRE_399_cfiType; // @[Mux.scala:30:73] wire _out_uop_WIRE_407; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_taken = _out_uop_WIRE_399_taken; // @[Mux.scala:30:73] wire [3:0] _out_uop_WIRE_406; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_mask = _out_uop_WIRE_399_mask; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_405; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_bridx = _out_uop_WIRE_399_bridx; // @[Mux.scala:30:73] wire [38:0] _out_uop_WIRE_404; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_target = _out_uop_WIRE_399_target; // @[Mux.scala:30:73] wire [5:0] _out_uop_WIRE_403; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_entry = _out_uop_WIRE_399_entry; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_400_history; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_bht_history = _out_uop_WIRE_399_bht_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_400_value; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_bits_bht_value = _out_uop_WIRE_399_bht_value; // @[Mux.scala:30:73] wire [7:0] _out_uop_WIRE_402; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_bht_history = _out_uop_WIRE_400_history; // @[Mux.scala:30:73] wire [1:0] _out_uop_WIRE_401; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_bht_value = _out_uop_WIRE_400_value; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4799 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4800 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4801 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4802 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4803 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4804 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4805 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4806 = _out_uop_T_4799 | _out_uop_T_4800; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4807 = _out_uop_T_4806 | _out_uop_T_4801; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4808 = _out_uop_T_4807 | _out_uop_T_4802; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4809 = _out_uop_T_4808 | _out_uop_T_4803; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4810 = _out_uop_T_4809 | _out_uop_T_4804; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4811 = _out_uop_T_4810 | _out_uop_T_4805; // @[Mux.scala:30:73] assign _out_uop_WIRE_401 = _out_uop_T_4811; // @[Mux.scala:30:73] assign _out_uop_WIRE_400_value = _out_uop_WIRE_401; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_4812 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4813 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4814 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4815 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4816 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4817 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4818 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73, :32:36] wire [7:0] _out_uop_T_4819 = _out_uop_T_4812 | _out_uop_T_4813; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_4820 = _out_uop_T_4819 | _out_uop_T_4814; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_4821 = _out_uop_T_4820 | _out_uop_T_4815; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_4822 = _out_uop_T_4821 | _out_uop_T_4816; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_4823 = _out_uop_T_4822 | _out_uop_T_4817; // @[Mux.scala:30:73] wire [7:0] _out_uop_T_4824 = _out_uop_T_4823 | _out_uop_T_4818; // @[Mux.scala:30:73] assign _out_uop_WIRE_402 = _out_uop_T_4824; // @[Mux.scala:30:73] assign _out_uop_WIRE_400_history = _out_uop_WIRE_402; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_4825 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4826 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4827 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4828 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4829 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4830 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4831 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _out_uop_T_4832 = _out_uop_T_4825 | _out_uop_T_4826; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_4833 = _out_uop_T_4832 | _out_uop_T_4827; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_4834 = _out_uop_T_4833 | _out_uop_T_4828; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_4835 = _out_uop_T_4834 | _out_uop_T_4829; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_4836 = _out_uop_T_4835 | _out_uop_T_4830; // @[Mux.scala:30:73] wire [5:0] _out_uop_T_4837 = _out_uop_T_4836 | _out_uop_T_4831; // @[Mux.scala:30:73] assign _out_uop_WIRE_403 = _out_uop_T_4837; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_entry = _out_uop_WIRE_403; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_4838 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4839 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4840 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4841 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4842 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4843 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4844 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73, :32:36] wire [38:0] _out_uop_T_4845 = _out_uop_T_4838 | _out_uop_T_4839; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_4846 = _out_uop_T_4845 | _out_uop_T_4840; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_4847 = _out_uop_T_4846 | _out_uop_T_4841; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_4848 = _out_uop_T_4847 | _out_uop_T_4842; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_4849 = _out_uop_T_4848 | _out_uop_T_4843; // @[Mux.scala:30:73] wire [38:0] _out_uop_T_4850 = _out_uop_T_4849 | _out_uop_T_4844; // @[Mux.scala:30:73] assign _out_uop_WIRE_404 = _out_uop_T_4850; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_target = _out_uop_WIRE_404; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4851 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4852 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4853 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4854 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4855 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4856 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4857 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4858 = _out_uop_T_4851 | _out_uop_T_4852; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4859 = _out_uop_T_4858 | _out_uop_T_4853; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4860 = _out_uop_T_4859 | _out_uop_T_4854; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4861 = _out_uop_T_4860 | _out_uop_T_4855; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4862 = _out_uop_T_4861 | _out_uop_T_4856; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4863 = _out_uop_T_4862 | _out_uop_T_4857; // @[Mux.scala:30:73] assign _out_uop_WIRE_405 = _out_uop_T_4863; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_bridx = _out_uop_WIRE_405; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_4864 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4865 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4866 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4867 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4868 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4869 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4870 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _out_uop_T_4871 = _out_uop_T_4864 | _out_uop_T_4865; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_4872 = _out_uop_T_4871 | _out_uop_T_4866; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_4873 = _out_uop_T_4872 | _out_uop_T_4867; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_4874 = _out_uop_T_4873 | _out_uop_T_4868; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_4875 = _out_uop_T_4874 | _out_uop_T_4869; // @[Mux.scala:30:73] wire [3:0] _out_uop_T_4876 = _out_uop_T_4875 | _out_uop_T_4870; // @[Mux.scala:30:73] assign _out_uop_WIRE_406 = _out_uop_T_4876; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_mask = _out_uop_WIRE_406; // @[Mux.scala:30:73] wire _out_uop_T_4877 = _out_uop_T_4194 & ram_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4878 = _out_uop_T_4195 & ram_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4879 = _out_uop_T_4196 & ram_2_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4880 = _out_uop_T_4197 & ram_3_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4881 = _out_uop_T_4198 & ram_4_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4882 = _out_uop_T_4199 & ram_5_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4883 = _out_uop_T_4200 & ram_6_bits_btb_resp_bits_taken; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4884 = _out_uop_T_4877 | _out_uop_T_4878; // @[Mux.scala:30:73] wire _out_uop_T_4885 = _out_uop_T_4884 | _out_uop_T_4879; // @[Mux.scala:30:73] wire _out_uop_T_4886 = _out_uop_T_4885 | _out_uop_T_4880; // @[Mux.scala:30:73] wire _out_uop_T_4887 = _out_uop_T_4886 | _out_uop_T_4881; // @[Mux.scala:30:73] wire _out_uop_T_4888 = _out_uop_T_4887 | _out_uop_T_4882; // @[Mux.scala:30:73] wire _out_uop_T_4889 = _out_uop_T_4888 | _out_uop_T_4883; // @[Mux.scala:30:73] assign _out_uop_WIRE_407 = _out_uop_T_4889; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_taken = _out_uop_WIRE_407; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4890 = _out_uop_T_4194 ? ram_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4891 = _out_uop_T_4195 ? ram_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4892 = _out_uop_T_4196 ? ram_2_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4893 = _out_uop_T_4197 ? ram_3_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4894 = _out_uop_T_4198 ? ram_4_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4895 = _out_uop_T_4199 ? ram_5_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4896 = _out_uop_T_4200 ? ram_6_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _out_uop_T_4897 = _out_uop_T_4890 | _out_uop_T_4891; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4898 = _out_uop_T_4897 | _out_uop_T_4892; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4899 = _out_uop_T_4898 | _out_uop_T_4893; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4900 = _out_uop_T_4899 | _out_uop_T_4894; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4901 = _out_uop_T_4900 | _out_uop_T_4895; // @[Mux.scala:30:73] wire [1:0] _out_uop_T_4902 = _out_uop_T_4901 | _out_uop_T_4896; // @[Mux.scala:30:73] assign _out_uop_WIRE_408 = _out_uop_T_4902; // @[Mux.scala:30:73] assign _out_uop_WIRE_399_cfiType = _out_uop_WIRE_408; // @[Mux.scala:30:73] wire _out_uop_T_4903 = _out_uop_T_4194 & ram_0_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4904 = _out_uop_T_4195 & ram_1_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4905 = _out_uop_T_4196 & ram_2_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4906 = _out_uop_T_4197 & ram_3_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4907 = _out_uop_T_4198 & ram_4_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4908 = _out_uop_T_4199 & ram_5_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4909 = _out_uop_T_4200 & ram_6_bits_btb_resp_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4910 = _out_uop_T_4903 | _out_uop_T_4904; // @[Mux.scala:30:73] wire _out_uop_T_4911 = _out_uop_T_4910 | _out_uop_T_4905; // @[Mux.scala:30:73] wire _out_uop_T_4912 = _out_uop_T_4911 | _out_uop_T_4906; // @[Mux.scala:30:73] wire _out_uop_T_4913 = _out_uop_T_4912 | _out_uop_T_4907; // @[Mux.scala:30:73] wire _out_uop_T_4914 = _out_uop_T_4913 | _out_uop_T_4908; // @[Mux.scala:30:73] wire _out_uop_T_4915 = _out_uop_T_4914 | _out_uop_T_4909; // @[Mux.scala:30:73] assign _out_uop_WIRE_409 = _out_uop_T_4915; // @[Mux.scala:30:73] assign _out_uop_WIRE_398_valid = _out_uop_WIRE_409; // @[Mux.scala:30:73] wire _out_uop_T_4929 = _out_uop_T_4194 & ram_0_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4930 = _out_uop_T_4195 & ram_1_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4931 = _out_uop_T_4196 & ram_2_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4932 = _out_uop_T_4197 & ram_3_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4933 = _out_uop_T_4198 & ram_4_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4934 = _out_uop_T_4199 & ram_5_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4935 = _out_uop_T_4200 & ram_6_bits_rvc; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_4936 = _out_uop_T_4929 | _out_uop_T_4930; // @[Mux.scala:30:73] wire _out_uop_T_4937 = _out_uop_T_4936 | _out_uop_T_4931; // @[Mux.scala:30:73] wire _out_uop_T_4938 = _out_uop_T_4937 | _out_uop_T_4932; // @[Mux.scala:30:73] wire _out_uop_T_4939 = _out_uop_T_4938 | _out_uop_T_4933; // @[Mux.scala:30:73] wire _out_uop_T_4940 = _out_uop_T_4939 | _out_uop_T_4934; // @[Mux.scala:30:73] wire _out_uop_T_4941 = _out_uop_T_4940 | _out_uop_T_4935; // @[Mux.scala:30:73] assign _out_uop_WIRE_411 = _out_uop_T_4941; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_rvc = _out_uop_WIRE_411; // @[Mux.scala:30:73] wire _out_uop_T_5527 = _out_uop_T_4194 & ram_0_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5528 = _out_uop_T_4195 & ram_1_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5529 = _out_uop_T_4196 & ram_2_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5530 = _out_uop_T_4197 & ram_3_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5531 = _out_uop_T_4198 & ram_4_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5532 = _out_uop_T_4199 & ram_5_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5533 = _out_uop_T_4200 & ram_6_bits_edge_inst; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5534 = _out_uop_T_5527 | _out_uop_T_5528; // @[Mux.scala:30:73] wire _out_uop_T_5535 = _out_uop_T_5534 | _out_uop_T_5529; // @[Mux.scala:30:73] wire _out_uop_T_5536 = _out_uop_T_5535 | _out_uop_T_5530; // @[Mux.scala:30:73] wire _out_uop_T_5537 = _out_uop_T_5536 | _out_uop_T_5531; // @[Mux.scala:30:73] wire _out_uop_T_5538 = _out_uop_T_5537 | _out_uop_T_5532; // @[Mux.scala:30:73] wire _out_uop_T_5539 = _out_uop_T_5538 | _out_uop_T_5533; // @[Mux.scala:30:73] assign _out_uop_WIRE_459 = _out_uop_T_5539; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_edge_inst = _out_uop_WIRE_459; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_5540 = _out_uop_T_4194 ? ram_0_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5541 = _out_uop_T_4195 ? ram_1_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5542 = _out_uop_T_4196 ? ram_2_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5543 = _out_uop_T_4197 ? ram_3_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5544 = _out_uop_T_4198 ? ram_4_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5545 = _out_uop_T_4199 ? ram_5_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5546 = _out_uop_T_4200 ? ram_6_bits_pc : 40'h0; // @[Mux.scala:30:73, :32:36] wire [39:0] _out_uop_T_5547 = _out_uop_T_5540 | _out_uop_T_5541; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_5548 = _out_uop_T_5547 | _out_uop_T_5542; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_5549 = _out_uop_T_5548 | _out_uop_T_5543; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_5550 = _out_uop_T_5549 | _out_uop_T_5544; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_5551 = _out_uop_T_5550 | _out_uop_T_5545; // @[Mux.scala:30:73] wire [39:0] _out_uop_T_5552 = _out_uop_T_5551 | _out_uop_T_5546; // @[Mux.scala:30:73] assign _out_uop_WIRE_460 = _out_uop_T_5552; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_pc = _out_uop_WIRE_460; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5553 = _out_uop_T_4194 ? ram_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5554 = _out_uop_T_4195 ? ram_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5555 = _out_uop_T_4196 ? ram_2_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5556 = _out_uop_T_4197 ? ram_3_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5557 = _out_uop_T_4198 ? ram_4_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5558 = _out_uop_T_4199 ? ram_5_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5559 = _out_uop_T_4200 ? ram_6_bits_raw_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5560 = _out_uop_T_5553 | _out_uop_T_5554; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5561 = _out_uop_T_5560 | _out_uop_T_5555; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5562 = _out_uop_T_5561 | _out_uop_T_5556; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5563 = _out_uop_T_5562 | _out_uop_T_5557; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5564 = _out_uop_T_5563 | _out_uop_T_5558; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5565 = _out_uop_T_5564 | _out_uop_T_5559; // @[Mux.scala:30:73] assign _out_uop_WIRE_461 = _out_uop_T_5565; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_raw_inst = _out_uop_WIRE_461; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5566 = _out_uop_T_4194 ? ram_0_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5567 = _out_uop_T_4195 ? ram_1_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5568 = _out_uop_T_4196 ? ram_2_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5569 = _out_uop_T_4197 ? ram_3_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5570 = _out_uop_T_4198 ? ram_4_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5571 = _out_uop_T_4199 ? ram_5_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5572 = _out_uop_T_4200 ? ram_6_bits_inst : 32'h0; // @[Mux.scala:30:73, :32:36] wire [31:0] _out_uop_T_5573 = _out_uop_T_5566 | _out_uop_T_5567; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5574 = _out_uop_T_5573 | _out_uop_T_5568; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5575 = _out_uop_T_5574 | _out_uop_T_5569; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5576 = _out_uop_T_5575 | _out_uop_T_5570; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5577 = _out_uop_T_5576 | _out_uop_T_5571; // @[Mux.scala:30:73] wire [31:0] _out_uop_T_5578 = _out_uop_T_5577 | _out_uop_T_5572; // @[Mux.scala:30:73] assign _out_uop_WIRE_462 = _out_uop_T_5578; // @[Mux.scala:30:73] assign _out_uop_WIRE_348_inst = _out_uop_WIRE_462; // @[Mux.scala:30:73] wire _out_uop_T_5579 = _out_uop_T_4194 & ram_0_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5580 = _out_uop_T_4195 & ram_1_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5581 = _out_uop_T_4196 & ram_2_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5582 = _out_uop_T_4197 & ram_3_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5583 = _out_uop_T_4198 & ram_4_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5584 = _out_uop_T_4199 & ram_5_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5585 = _out_uop_T_4200 & ram_6_valid; // @[Mux.scala:30:73, :32:36] wire _out_uop_T_5586 = _out_uop_T_5579 | _out_uop_T_5580; // @[Mux.scala:30:73] wire _out_uop_T_5587 = _out_uop_T_5586 | _out_uop_T_5581; // @[Mux.scala:30:73] wire _out_uop_T_5588 = _out_uop_T_5587 | _out_uop_T_5582; // @[Mux.scala:30:73] wire _out_uop_T_5589 = _out_uop_T_5588 | _out_uop_T_5583; // @[Mux.scala:30:73] wire _out_uop_T_5590 = _out_uop_T_5589 | _out_uop_T_5584; // @[Mux.scala:30:73] wire _out_uop_T_5591 = _out_uop_T_5590 | _out_uop_T_5585; // @[Mux.scala:30:73] assign _out_uop_WIRE_463 = _out_uop_T_5591; // @[Mux.scala:30:73] assign out_uop_3_valid = _out_uop_WIRE_463; // @[Mux.scala:30:73] wire [1:0] _deq_ptr_T_2 = {1'h0, _deq_ptr_T} + {1'h0, _deq_ptr_T_1}; // @[Decoupled.scala:51:35] wire [1:0] _deq_ptr_T_3 = _deq_ptr_T_2; // @[FetchBuffer.scala:117:42] wire [13:0] deq_ptr_full; // @[FetchBuffer.scala:74:20] wire [9:0] _deq_ptr_full_T = {3'h0, deq_ptr} << _deq_ptr_T_3; // @[FetchBuffer.scala:30:24, :75:16, :117:42] assign deq_ptr_full = {4'h0, _deq_ptr_full_T}; // @[FetchBuffer.scala:74:20, :75:{10,16}] wire [6:0] _deq_ptr_T_4 = deq_ptr_full[6:0]; // @[FetchBuffer.scala:74:20, :76:10] wire [6:0] _deq_ptr_T_5 = deq_ptr_full[13:7]; // @[FetchBuffer.scala:74:20, :76:26] wire [6:0] _deq_ptr_T_6 = _deq_ptr_T_4 | _deq_ptr_T_5; // @[FetchBuffer.scala:76:{10,18,26}] wire [6:0] _deq_ptr_T_7 = _deq_ptr_T_6; // @[FetchBuffer.scala:76:{18,32}]
Generate the Verilog code corresponding to this FIRRTL code module TLMasterBEToNoC : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst b of TLBFromNoC connect b.clock, clock connect b.reset, reset inst e of TLEToNoC connect e.clock, clock connect e.reset, reset connect io.tilelink.b.bits, b.io.protocol.bits connect io.tilelink.b.valid, b.io.protocol.valid connect b.io.protocol.ready, io.tilelink.b.ready connect e.io.protocol, io.tilelink.e connect b.io.flit, io.flits.b connect io.flits.e.bits, e.io.flit.bits connect io.flits.e.valid, e.io.flit.valid connect e.io.flit.ready, io.flits.e.ready
module TLMasterBEToNoC( // @[Tilelink.scala:100:7] input clock, // @[Tilelink.scala:100:7] input reset, // @[Tilelink.scala:100:7] output io_flits_b_ready, // @[Tilelink.scala:107:14] input io_flits_b_valid, // @[Tilelink.scala:107:14] input io_flits_b_bits_head, // @[Tilelink.scala:107:14] input io_flits_b_bits_tail, // @[Tilelink.scala:107:14] input io_flits_e_ready, // @[Tilelink.scala:107:14] output io_flits_e_valid, // @[Tilelink.scala:107:14] output io_flits_e_bits_head, // @[Tilelink.scala:107:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:107:14] output [3:0] io_flits_e_bits_egress_id // @[Tilelink.scala:107:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:116:17] TLBFromNoC b ( // @[Tilelink.scala:115:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail) ); // @[Tilelink.scala:115:17] TLEToNoC e ( // @[Tilelink.scala:116:17] .clock (clock), .reset (reset), .io_protocol_ready (/* unused */), .io_protocol_valid (1'h0), // @[Tilelink.scala:107:14, :115:17, :116:17] .io_protocol_bits_sink (5'h0), // @[Tilelink.scala:107:14, :116:17] .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:116:17] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:100:7, :116:17, :121:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_90 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_346 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_90( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_346 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_24 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_24( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_clear = 1'h0; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_TileResetSetter : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_70 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a21d64s7k1z3u_1 connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ChecksumCalc : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { check : UInt<1>, start : UInt<16>, init : UInt<16>}}, stream : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}}, result : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}} reg csum : UInt<80>, clock reg check : UInt<1>, clock reg start : UInt<16>, clock reg startPos : UInt<16>, clock node _nextStartPos_T = add(startPos, UInt<4>(0h8)) node nextStartPos = tail(_nextStartPos_T, 1) node _sumMask_T = bits(io.stream.in.bits.keep, 0, 0) node _sumMask_T_1 = add(startPos, UInt<1>(0h0)) node _sumMask_T_2 = tail(_sumMask_T_1, 1) node _sumMask_T_3 = geq(_sumMask_T_2, start) node sumMask_0 = and(_sumMask_T, _sumMask_T_3) node _sumMask_T_4 = bits(io.stream.in.bits.keep, 1, 1) node _sumMask_T_5 = add(startPos, UInt<1>(0h1)) node _sumMask_T_6 = tail(_sumMask_T_5, 1) node _sumMask_T_7 = geq(_sumMask_T_6, start) node sumMask_1 = and(_sumMask_T_4, _sumMask_T_7) node _sumMask_T_8 = bits(io.stream.in.bits.keep, 2, 2) node _sumMask_T_9 = add(startPos, UInt<2>(0h2)) node _sumMask_T_10 = tail(_sumMask_T_9, 1) node _sumMask_T_11 = geq(_sumMask_T_10, start) node sumMask_2 = and(_sumMask_T_8, _sumMask_T_11) node _sumMask_T_12 = bits(io.stream.in.bits.keep, 3, 3) node _sumMask_T_13 = add(startPos, UInt<2>(0h3)) node _sumMask_T_14 = tail(_sumMask_T_13, 1) node _sumMask_T_15 = geq(_sumMask_T_14, start) node sumMask_3 = and(_sumMask_T_12, _sumMask_T_15) node _sumMask_T_16 = bits(io.stream.in.bits.keep, 4, 4) node _sumMask_T_17 = add(startPos, UInt<3>(0h4)) node _sumMask_T_18 = tail(_sumMask_T_17, 1) node _sumMask_T_19 = geq(_sumMask_T_18, start) node sumMask_4 = and(_sumMask_T_16, _sumMask_T_19) node _sumMask_T_20 = bits(io.stream.in.bits.keep, 5, 5) node _sumMask_T_21 = add(startPos, UInt<3>(0h5)) node _sumMask_T_22 = tail(_sumMask_T_21, 1) node _sumMask_T_23 = geq(_sumMask_T_22, start) node sumMask_5 = and(_sumMask_T_20, _sumMask_T_23) node _sumMask_T_24 = bits(io.stream.in.bits.keep, 6, 6) node _sumMask_T_25 = add(startPos, UInt<3>(0h6)) node _sumMask_T_26 = tail(_sumMask_T_25, 1) node _sumMask_T_27 = geq(_sumMask_T_26, start) node sumMask_6 = and(_sumMask_T_24, _sumMask_T_27) node _sumMask_T_28 = bits(io.stream.in.bits.keep, 7, 7) node _sumMask_T_29 = add(startPos, UInt<3>(0h7)) node _sumMask_T_30 = tail(_sumMask_T_29, 1) node _sumMask_T_31 = geq(_sumMask_T_30, start) node sumMask_7 = and(_sumMask_T_28, _sumMask_T_31) node _sumData_T = mux(sumMask_0, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_1 = mux(sumMask_1, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_2 = mux(sumMask_2, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_3 = mux(sumMask_3, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_4 = mux(sumMask_4, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_5 = mux(sumMask_5, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_6 = mux(sumMask_6, UInt<8>(0hff), UInt<8>(0h0)) node _sumData_T_7 = mux(sumMask_7, UInt<8>(0hff), UInt<8>(0h0)) node sumData_lo_lo = cat(_sumData_T_1, _sumData_T) node sumData_lo_hi = cat(_sumData_T_3, _sumData_T_2) node sumData_lo = cat(sumData_lo_hi, sumData_lo_lo) node sumData_hi_lo = cat(_sumData_T_5, _sumData_T_4) node sumData_hi_hi = cat(_sumData_T_7, _sumData_T_6) node sumData_hi = cat(sumData_hi_hi, sumData_hi_lo) node _sumData_T_8 = cat(sumData_hi, sumData_lo) node sumData = and(io.stream.in.bits.data, _sumData_T_8) regreset state : UInt<2>, clock, reset, UInt<2>(0h0) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_stream_out_valid_T = eq(state, UInt<2>(0h1)) node _io_stream_out_valid_T_1 = and(_io_stream_out_valid_T, io.stream.in.valid) connect io.stream.out.valid, _io_stream_out_valid_T_1 node _io_stream_in_ready_T = eq(state, UInt<2>(0h1)) node _io_stream_in_ready_T_1 = and(_io_stream_in_ready_T, io.stream.out.ready) connect io.stream.in.ready, _io_stream_in_ready_T_1 connect io.stream.out.bits, io.stream.in.bits node _io_result_valid_T = eq(state, UInt<2>(0h3)) connect io.result.valid, _io_result_valid_T node _io_result_bits_T = bits(csum, 15, 0) connect io.result.bits, _io_result_bits_T node _T = and(io.req.ready, io.req.valid) when _T : connect check, io.req.bits.check connect start, io.req.bits.start connect csum, io.req.bits.init connect startPos, UInt<1>(0h0) connect state, UInt<2>(0h1) node _T_1 = and(io.stream.in.ready, io.stream.in.valid) when _T_1 : when check : node _csum_T = add(csum, sumData) node _csum_T_1 = tail(_csum_T, 1) connect csum, _csum_T_1 connect startPos, nextStartPos when io.stream.in.bits.last : node _state_T = mux(check, UInt<2>(0h2), UInt<2>(0h0)) connect state, _state_T node _T_2 = eq(state, UInt<2>(0h2)) when _T_2 : node upper = bits(csum, 79, 16) node lower = bits(csum, 15, 0) node _T_3 = eq(upper, UInt<1>(0h0)) when _T_3 : node _csum_T_2 = not(lower) connect csum, _csum_T_2 connect state, UInt<2>(0h3) else : node _csum_T_3 = add(upper, lower) node _csum_T_4 = tail(_csum_T_3, 1) connect csum, _csum_T_4 node _T_4 = and(io.result.ready, io.result.valid) when _T_4 : connect state, UInt<2>(0h0)
module ChecksumCalc( // @[Checksum.scala:23:7] input clock, // @[Checksum.scala:23:7] input reset, // @[Checksum.scala:23:7] output io_req_ready, // @[Checksum.scala:26:14] input io_req_valid, // @[Checksum.scala:26:14] input io_req_bits_check, // @[Checksum.scala:26:14] input [15:0] io_req_bits_start, // @[Checksum.scala:26:14] input [15:0] io_req_bits_init, // @[Checksum.scala:26:14] output io_stream_in_ready, // @[Checksum.scala:26:14] input io_stream_in_valid, // @[Checksum.scala:26:14] input [63:0] io_stream_in_bits_data, // @[Checksum.scala:26:14] input [7:0] io_stream_in_bits_keep, // @[Checksum.scala:26:14] input io_stream_in_bits_last, // @[Checksum.scala:26:14] input io_stream_out_ready, // @[Checksum.scala:26:14] output io_stream_out_valid, // @[Checksum.scala:26:14] output [63:0] io_stream_out_bits_data, // @[Checksum.scala:26:14] output [7:0] io_stream_out_bits_keep, // @[Checksum.scala:26:14] output io_stream_out_bits_last, // @[Checksum.scala:26:14] input io_result_ready, // @[Checksum.scala:26:14] output io_result_valid, // @[Checksum.scala:26:14] output [15:0] io_result_bits // @[Checksum.scala:26:14] ); wire io_req_valid_0 = io_req_valid; // @[Checksum.scala:23:7] wire io_req_bits_check_0 = io_req_bits_check; // @[Checksum.scala:23:7] wire [15:0] io_req_bits_start_0 = io_req_bits_start; // @[Checksum.scala:23:7] wire [15:0] io_req_bits_init_0 = io_req_bits_init; // @[Checksum.scala:23:7] wire io_stream_in_valid_0 = io_stream_in_valid; // @[Checksum.scala:23:7] wire [63:0] io_stream_in_bits_data_0 = io_stream_in_bits_data; // @[Checksum.scala:23:7] wire [7:0] io_stream_in_bits_keep_0 = io_stream_in_bits_keep; // @[Checksum.scala:23:7] wire io_stream_in_bits_last_0 = io_stream_in_bits_last; // @[Checksum.scala:23:7] wire io_stream_out_ready_0 = io_stream_out_ready; // @[Checksum.scala:23:7] wire io_result_ready_0 = io_result_ready; // @[Checksum.scala:23:7] wire _io_req_ready_T; // @[Checksum.scala:45:25] wire _io_stream_in_ready_T_1; // @[Checksum.scala:47:44] wire [63:0] io_stream_out_bits_data_0 = io_stream_in_bits_data_0; // @[Checksum.scala:23:7] wire [7:0] io_stream_out_bits_keep_0 = io_stream_in_bits_keep_0; // @[Checksum.scala:23:7] wire io_stream_out_bits_last_0 = io_stream_in_bits_last_0; // @[Checksum.scala:23:7] wire _io_stream_out_valid_T_1; // @[Checksum.scala:46:45] wire _io_result_valid_T; // @[Checksum.scala:49:28] wire [15:0] _io_result_bits_T; // @[Checksum.scala:50:25] wire io_req_ready_0; // @[Checksum.scala:23:7] wire io_stream_in_ready_0; // @[Checksum.scala:23:7] wire io_stream_out_valid_0; // @[Checksum.scala:23:7] wire io_result_valid_0; // @[Checksum.scala:23:7] wire [15:0] io_result_bits_0; // @[Checksum.scala:23:7] reg [79:0] csum; // @[Checksum.scala:32:17] reg check; // @[Checksum.scala:33:18] reg [15:0] start; // @[Checksum.scala:34:19] reg [15:0] startPos; // @[Checksum.scala:35:21] wire [16:0] _sumMask_T_1 = {1'h0, startPos}; // @[Checksum.scala:35:21, :36:31, :38:44] wire [16:0] _nextStartPos_T = _sumMask_T_1 + 17'h8; // @[Checksum.scala:36:31, :38:44] wire [15:0] nextStartPos = _nextStartPos_T[15:0]; // @[Checksum.scala:36:31] wire _sumMask_T = io_stream_in_bits_keep_0[0]; // @[Checksum.scala:23:7, :38:27] wire [15:0] _sumMask_T_2 = _sumMask_T_1[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_3 = _sumMask_T_2 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_0 = _sumMask_T & _sumMask_T_3; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_4 = io_stream_in_bits_keep_0[1]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_5 = _sumMask_T_1 + 17'h1; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_6 = _sumMask_T_5[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_7 = _sumMask_T_6 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_1 = _sumMask_T_4 & _sumMask_T_7; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_8 = io_stream_in_bits_keep_0[2]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_9 = _sumMask_T_1 + 17'h2; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_10 = _sumMask_T_9[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_11 = _sumMask_T_10 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_2 = _sumMask_T_8 & _sumMask_T_11; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_12 = io_stream_in_bits_keep_0[3]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_13 = _sumMask_T_1 + 17'h3; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_14 = _sumMask_T_13[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_15 = _sumMask_T_14 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_3 = _sumMask_T_12 & _sumMask_T_15; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_16 = io_stream_in_bits_keep_0[4]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_17 = _sumMask_T_1 + 17'h4; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_18 = _sumMask_T_17[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_19 = _sumMask_T_18 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_4 = _sumMask_T_16 & _sumMask_T_19; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_20 = io_stream_in_bits_keep_0[5]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_21 = _sumMask_T_1 + 17'h5; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_22 = _sumMask_T_21[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_23 = _sumMask_T_22 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_5 = _sumMask_T_20 & _sumMask_T_23; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_24 = io_stream_in_bits_keep_0[6]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_25 = _sumMask_T_1 + 17'h6; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_26 = _sumMask_T_25[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_27 = _sumMask_T_26 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_6 = _sumMask_T_24 & _sumMask_T_27; // @[Checksum.scala:38:{27,31,51}] wire _sumMask_T_28 = io_stream_in_bits_keep_0[7]; // @[Checksum.scala:23:7, :38:27] wire [16:0] _sumMask_T_29 = _sumMask_T_1 + 17'h7; // @[Checksum.scala:38:44] wire [15:0] _sumMask_T_30 = _sumMask_T_29[15:0]; // @[Checksum.scala:38:44] wire _sumMask_T_31 = _sumMask_T_30 >= start; // @[Checksum.scala:34:19, :38:{44,51}] wire sumMask_7 = _sumMask_T_28 & _sumMask_T_31; // @[Checksum.scala:38:{27,31,51}] wire [7:0] _sumData_T = {8{sumMask_0}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_1 = {8{sumMask_1}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_2 = {8{sumMask_2}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_3 = {8{sumMask_3}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_4 = {8{sumMask_4}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_5 = {8{sumMask_5}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_6 = {8{sumMask_6}}; // @[Checksum.scala:38:31, :40:57] wire [7:0] _sumData_T_7 = {8{sumMask_7}}; // @[Checksum.scala:38:31, :40:57] wire [15:0] sumData_lo_lo = {_sumData_T_1, _sumData_T}; // @[Checksum.scala:40:57] wire [15:0] sumData_lo_hi = {_sumData_T_3, _sumData_T_2}; // @[Checksum.scala:40:57] wire [31:0] sumData_lo = {sumData_lo_hi, sumData_lo_lo}; // @[Checksum.scala:40:57] wire [15:0] sumData_hi_lo = {_sumData_T_5, _sumData_T_4}; // @[Checksum.scala:40:57] wire [15:0] sumData_hi_hi = {_sumData_T_7, _sumData_T_6}; // @[Checksum.scala:40:57] wire [31:0] sumData_hi = {sumData_hi_hi, sumData_hi_lo}; // @[Checksum.scala:40:57] wire [63:0] _sumData_T_8 = {sumData_hi, sumData_lo}; // @[Checksum.scala:40:57] wire [63:0] sumData = io_stream_in_bits_data_0 & _sumData_T_8; // @[Checksum.scala:23:7, :40:{40,57}] reg [1:0] state; // @[Checksum.scala:43:22] assign _io_req_ready_T = state == 2'h0; // @[Checksum.scala:43:22, :45:25] assign io_req_ready_0 = _io_req_ready_T; // @[Checksum.scala:23:7, :45:25] wire _GEN = state == 2'h1; // @[Checksum.scala:43:22, :46:32] wire _io_stream_out_valid_T; // @[Checksum.scala:46:32] assign _io_stream_out_valid_T = _GEN; // @[Checksum.scala:46:32] wire _io_stream_in_ready_T; // @[Checksum.scala:47:31] assign _io_stream_in_ready_T = _GEN; // @[Checksum.scala:46:32, :47:31] assign _io_stream_out_valid_T_1 = _io_stream_out_valid_T & io_stream_in_valid_0; // @[Checksum.scala:23:7, :46:{32,45}] assign io_stream_out_valid_0 = _io_stream_out_valid_T_1; // @[Checksum.scala:23:7, :46:45] assign _io_stream_in_ready_T_1 = _io_stream_in_ready_T & io_stream_out_ready_0; // @[Checksum.scala:23:7, :47:{31,44}] assign io_stream_in_ready_0 = _io_stream_in_ready_T_1; // @[Checksum.scala:23:7, :47:44] assign _io_result_valid_T = &state; // @[Checksum.scala:43:22, :49:28] assign io_result_valid_0 = _io_result_valid_T; // @[Checksum.scala:23:7, :49:28] assign _io_result_bits_T = csum[15:0]; // @[Checksum.scala:32:17, :50:25] wire [15:0] lower = csum[15:0]; // @[Checksum.scala:32:17, :50:25, :73:21] assign io_result_bits_0 = _io_result_bits_T; // @[Checksum.scala:23:7, :50:25] wire [80:0] _csum_T = {1'h0, csum} + {17'h0, sumData}; // @[Checksum.scala:32:17, :40:40, :62:20] wire [79:0] _csum_T_1 = _csum_T[79:0]; // @[Checksum.scala:62:20] wire [1:0] _state_T = {check, 1'h0}; // @[Checksum.scala:33:18, :67:19] wire [63:0] upper = csum[79:16]; // @[Checksum.scala:32:17, :72:21] wire [15:0] _csum_T_2 = ~lower; // @[Checksum.scala:73:21, :76:15] wire [64:0] _csum_T_3 = {1'h0, upper} + {49'h0, lower}; // @[Checksum.scala:72:21, :73:21, :79:21] wire [63:0] _csum_T_4 = _csum_T_3[63:0]; // @[Checksum.scala:79:21] wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _T_1 = io_stream_in_ready_0 & io_stream_in_valid_0; // @[Decoupled.scala:51:35] wire _GEN_0 = _T_1 & check; // @[Decoupled.scala:51:35] wire _T_2 = state == 2'h2; // @[Checksum.scala:43:22, :71:15] wire _T_3 = upper == 64'h0; // @[Checksum.scala:55:10, :72:21, :75:17] always @(posedge clock) begin // @[Checksum.scala:23:7] if (_T_2) // @[Checksum.scala:71:15] csum <= _T_3 ? {64'h0, _csum_T_2} : {16'h0, _csum_T_4}; // @[Checksum.scala:32:17, :55:10, :75:{17,26}, :76:{12,15}, :79:{12,21}] else if (_GEN_0) // @[Checksum.scala:52:22, :60:28, :61:18, :62:12] csum <= _csum_T_1; // @[Checksum.scala:32:17, :62:20] else if (_T) // @[Decoupled.scala:51:35] csum <= {64'h0, io_req_bits_init_0}; // @[Checksum.scala:23:7, :32:17, :55:10] if (_T) begin // @[Decoupled.scala:51:35] check <= io_req_bits_check_0; // @[Checksum.scala:23:7, :33:18] start <= io_req_bits_start_0; // @[Checksum.scala:23:7, :34:19] end if (_GEN_0) // @[Checksum.scala:52:22, :60:28, :61:18, :62:12] startPos <= nextStartPos; // @[Checksum.scala:35:21, :36:31] else if (_T) // @[Decoupled.scala:51:35] startPos <= 16'h0; // @[Checksum.scala:35:21] if (reset) // @[Checksum.scala:23:7] state <= 2'h0; // @[Checksum.scala:43:22] else if (io_result_ready_0 & io_result_valid_0) // @[Decoupled.scala:51:35] state <= 2'h0; // @[Checksum.scala:43:22] else if (_T_2 & _T_3) // @[Checksum.scala:60:28, :71:{15,27}, :75:{17,26}, :77:13] state <= 2'h3; // @[Checksum.scala:43:22] else if (_T_1 & io_stream_in_bits_last_0) // @[Decoupled.scala:51:35] state <= _state_T; // @[Checksum.scala:43:22, :67:19] else if (_T) // @[Decoupled.scala:51:35] state <= 2'h1; // @[Checksum.scala:43:22] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Checksum.scala:23:7] assign io_stream_in_ready = io_stream_in_ready_0; // @[Checksum.scala:23:7] assign io_stream_out_valid = io_stream_out_valid_0; // @[Checksum.scala:23:7] assign io_stream_out_bits_data = io_stream_out_bits_data_0; // @[Checksum.scala:23:7] assign io_stream_out_bits_keep = io_stream_out_bits_keep_0; // @[Checksum.scala:23:7] assign io_stream_out_bits_last = io_stream_out_bits_last_0; // @[Checksum.scala:23:7] assign io_result_valid = io_result_valid_0; // @[Checksum.scala:23:7] assign io_result_bits = io_result_bits_0; // @[Checksum.scala:23:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_250 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_250( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_34 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_317 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_320 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_34( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_317 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_320 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_10 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_10( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_148 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_404 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_148( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_404 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_1 : input clock : Clock input reset : Reset output auto : { } skip
module TLBuffer_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset // @[Buffer.scala:40:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_32 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_32( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_2 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_2 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_2( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_2 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_1 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_1( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_3 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, busy : UInt<1>} reg stages : { data : UInt<128>, fromDMA : UInt<1>}[1], clock wire _valids_WIRE : UInt<1>[1] connect _valids_WIRE[0], UInt<1>(0h0) regreset valids : UInt<1>[1], clock, reset, _valids_WIRE wire stalling : UInt<1>[1] connect stalling[0], UInt<1>(0h0) node _io_busy_T = or(io.in.valid, valids[0]) connect io.busy, _io_busy_T node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_0_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_0_T_1 = and(valids[0], _stalling_0_T) connect stalling[0], _stalling_0_T_1 connect io.out.valid, valids[0] when io.out.ready : connect valids[0], UInt<1>(0h0) node _T = and(io.in.ready, io.in.valid) when _T : connect valids[0], UInt<1>(0h1) node _T_1 = and(io.in.ready, io.in.valid) when _T_1 : connect stages[0], io.in.bits connect io.out.bits, stages[0]
module Pipeline_3( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14] input io_in_bits_fromDMA, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_data, // @[Pipeline.scala:7:14] output io_out_bits_fromDMA // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7] wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7] wire io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [127:0] stages_0_data; // @[Pipeline.scala:21:21] assign io_out_bits_data_0 = stages_0_data; // @[Pipeline.scala:6:7, :21:21] reg stages_0_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_fromDMA_0 = stages_0_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_0; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] assign _io_busy_T = io_in_valid_0 | valids_0; // @[Pipeline.scala:6:7, :22:25, :24:28] assign io_busy = _io_busy_T; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_0_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_0_T_1 = valids_0 & _stalling_0_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_0 = _stalling_0_T_1; // @[Pipeline.scala:23:27, :28:34] wire _T_1 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_1) begin // @[Decoupled.scala:51:35] stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] end if (reset) // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] else // @[Pipeline.scala:6:7] valids_0 <= _T_1 | ~io_out_ready_0 & valids_0; // @[Decoupled.scala:51:35] always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7] assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<17>(0h10000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = and(_T_139, _T_144) node _T_146 = or(UInt<1>(0h0), _T_145) node _T_147 = and(_T_138, _T_146) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_147, UInt<1>(0h1), "") : assert_2 node _T_151 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_152 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_153 = and(_T_151, _T_152) node _T_154 = or(UInt<1>(0h0), _T_153) node _T_155 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<17>(0h10000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = and(_T_154, _T_159) node _T_161 = or(UInt<1>(0h0), _T_160) node _T_162 = and(UInt<1>(0h0), _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_162, UInt<1>(0h1), "") : assert_3 node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(source_ok, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_169 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_169, UInt<1>(0h1), "") : assert_5 node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(is_aligned, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_176 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_176, UInt<1>(0h1), "") : assert_7 node _T_180 = not(io.in.a.bits.mask) node _T_181 = eq(_T_180, UInt<1>(0h0)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_181, UInt<1>(0h1), "") : assert_8 node _T_185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_185, UInt<1>(0h1), "") : assert_9 node _T_189 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_189 : node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_194 = shr(io.in.a.bits.source, 2) node _T_195 = eq(_T_194, UInt<1>(0h0)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_8) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_199 = and(_T_197, _T_198) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_200 = shr(io.in.a.bits.source, 2) node _T_201 = eq(_T_200, UInt<1>(0h1)) node _T_202 = leq(UInt<1>(0h0), uncommonBits_9) node _T_203 = and(_T_201, _T_202) node _T_204 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_205 = and(_T_203, _T_204) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<2>(0h2)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_10) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<2>(0h3)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_11) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_220 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_221 = or(_T_193, _T_199) node _T_222 = or(_T_221, _T_205) node _T_223 = or(_T_222, _T_211) node _T_224 = or(_T_223, _T_217) node _T_225 = or(_T_224, _T_218) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_220) node _T_228 = and(_T_192, _T_227) node _T_229 = or(UInt<1>(0h0), _T_228) node _T_230 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = and(_T_230, _T_235) node _T_237 = or(UInt<1>(0h0), _T_236) node _T_238 = and(_T_229, _T_237) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_238, UInt<1>(0h1), "") : assert_10 node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(UInt<1>(0h0), _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_253, UInt<1>(0h1), "") : assert_11 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(source_ok, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_260, UInt<1>(0h1), "") : assert_13 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(is_aligned, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_267, UInt<1>(0h1), "") : assert_15 node _T_271 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : node _T_274 = eq(_T_271, UInt<1>(0h0)) when _T_274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_271, UInt<1>(0h1), "") : assert_16 node _T_275 = not(io.in.a.bits.mask) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_276, UInt<1>(0h1), "") : assert_17 node _T_280 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(_T_280, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_280, UInt<1>(0h1), "") : assert_18 node _T_284 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_284 : node _T_285 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_286 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_287 = and(_T_285, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_289 = shr(io.in.a.bits.source, 2) node _T_290 = eq(_T_289, UInt<1>(0h0)) node _T_291 = leq(UInt<1>(0h0), uncommonBits_12) node _T_292 = and(_T_290, _T_291) node _T_293 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_294 = and(_T_292, _T_293) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h1)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_13) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<2>(0h2)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_14) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h3)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_15) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_315 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_316 = or(_T_288, _T_294) node _T_317 = or(_T_316, _T_300) node _T_318 = or(_T_317, _T_306) node _T_319 = or(_T_318, _T_312) node _T_320 = or(_T_319, _T_313) node _T_321 = or(_T_320, _T_314) node _T_322 = or(_T_321, _T_315) node _T_323 = and(_T_287, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_324, UInt<1>(0h1), "") : assert_19 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<17>(0h10000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = and(_T_331, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_338, UInt<1>(0h1), "") : assert_20 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(source_ok, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(is_aligned, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_348 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_348, UInt<1>(0h1), "") : assert_23 node _T_352 = eq(io.in.a.bits.mask, mask) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_352, UInt<1>(0h1), "") : assert_24 node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_356, UInt<1>(0h1), "") : assert_25 node _T_360 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_360 : node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_365 = shr(io.in.a.bits.source, 2) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = leq(UInt<1>(0h0), uncommonBits_16) node _T_368 = and(_T_366, _T_367) node _T_369 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_370 = and(_T_368, _T_369) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_371 = shr(io.in.a.bits.source, 2) node _T_372 = eq(_T_371, UInt<1>(0h1)) node _T_373 = leq(UInt<1>(0h0), uncommonBits_17) node _T_374 = and(_T_372, _T_373) node _T_375 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_377 = shr(io.in.a.bits.source, 2) node _T_378 = eq(_T_377, UInt<2>(0h2)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_18) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_382 = and(_T_380, _T_381) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_383 = shr(io.in.a.bits.source, 2) node _T_384 = eq(_T_383, UInt<2>(0h3)) node _T_385 = leq(UInt<1>(0h0), uncommonBits_19) node _T_386 = and(_T_384, _T_385) node _T_387 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_390 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_392 = or(_T_364, _T_370) node _T_393 = or(_T_392, _T_376) node _T_394 = or(_T_393, _T_382) node _T_395 = or(_T_394, _T_388) node _T_396 = or(_T_395, _T_389) node _T_397 = or(_T_396, _T_390) node _T_398 = or(_T_397, _T_391) node _T_399 = and(_T_363, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_402 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<17>(0h10000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = and(_T_401, _T_406) node _T_408 = or(UInt<1>(0h0), _T_407) node _T_409 = and(_T_400, _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_409, UInt<1>(0h1), "") : assert_26 node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(source_ok, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(is_aligned, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_419 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_419, UInt<1>(0h1), "") : assert_29 node _T_423 = eq(io.in.a.bits.mask, mask) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_423, UInt<1>(0h1), "") : assert_30 node _T_427 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_427 : node _T_428 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_429 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_430 = and(_T_428, _T_429) node _T_431 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_432 = shr(io.in.a.bits.source, 2) node _T_433 = eq(_T_432, UInt<1>(0h0)) node _T_434 = leq(UInt<1>(0h0), uncommonBits_20) node _T_435 = and(_T_433, _T_434) node _T_436 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_437 = and(_T_435, _T_436) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_438 = shr(io.in.a.bits.source, 2) node _T_439 = eq(_T_438, UInt<1>(0h1)) node _T_440 = leq(UInt<1>(0h0), uncommonBits_21) node _T_441 = and(_T_439, _T_440) node _T_442 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_443 = and(_T_441, _T_442) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_444 = shr(io.in.a.bits.source, 2) node _T_445 = eq(_T_444, UInt<2>(0h2)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_22) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_449 = and(_T_447, _T_448) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_450 = shr(io.in.a.bits.source, 2) node _T_451 = eq(_T_450, UInt<2>(0h3)) node _T_452 = leq(UInt<1>(0h0), uncommonBits_23) node _T_453 = and(_T_451, _T_452) node _T_454 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_458 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_459 = or(_T_431, _T_437) node _T_460 = or(_T_459, _T_443) node _T_461 = or(_T_460, _T_449) node _T_462 = or(_T_461, _T_455) node _T_463 = or(_T_462, _T_456) node _T_464 = or(_T_463, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = and(_T_430, _T_465) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = and(_T_468, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = and(_T_467, _T_475) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_476, UInt<1>(0h1), "") : assert_31 node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(source_ok, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(is_aligned, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_486 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_486, UInt<1>(0h1), "") : assert_34 node _T_490 = not(mask) node _T_491 = and(io.in.a.bits.mask, _T_490) node _T_492 = eq(_T_491, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_492, UInt<1>(0h1), "") : assert_35 node _T_496 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_496 : node _T_497 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_498 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_499 = and(_T_497, _T_498) node _T_500 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_24) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<1>(0h1)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_25) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<2>(0h2)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_26) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<2>(0h3)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_27) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_526 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_527 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_528 = or(_T_500, _T_506) node _T_529 = or(_T_528, _T_512) node _T_530 = or(_T_529, _T_518) node _T_531 = or(_T_530, _T_524) node _T_532 = or(_T_531, _T_525) node _T_533 = or(_T_532, _T_526) node _T_534 = or(_T_533, _T_527) node _T_535 = and(_T_499, _T_534) node _T_536 = or(UInt<1>(0h0), _T_535) node _T_537 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_538 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_539 = cvt(_T_538) node _T_540 = and(_T_539, asSInt(UInt<17>(0h10000))) node _T_541 = asSInt(_T_540) node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0))) node _T_543 = and(_T_537, _T_542) node _T_544 = or(UInt<1>(0h0), _T_543) node _T_545 = and(_T_536, _T_544) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_545, UInt<1>(0h1), "") : assert_36 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(source_ok, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(is_aligned, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_555 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_555, UInt<1>(0h1), "") : assert_39 node _T_559 = eq(io.in.a.bits.mask, mask) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_559, UInt<1>(0h1), "") : assert_40 node _T_563 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_563 : node _T_564 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_565 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_566 = and(_T_564, _T_565) node _T_567 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_568 = shr(io.in.a.bits.source, 2) node _T_569 = eq(_T_568, UInt<1>(0h0)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_28) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_573 = and(_T_571, _T_572) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_574 = shr(io.in.a.bits.source, 2) node _T_575 = eq(_T_574, UInt<1>(0h1)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_29) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<2>(0h2)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_30) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<2>(0h3)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_31) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_594 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_595 = or(_T_567, _T_573) node _T_596 = or(_T_595, _T_579) node _T_597 = or(_T_596, _T_585) node _T_598 = or(_T_597, _T_591) node _T_599 = or(_T_598, _T_592) node _T_600 = or(_T_599, _T_593) node _T_601 = or(_T_600, _T_594) node _T_602 = and(_T_566, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_605 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_606 = cvt(_T_605) node _T_607 = and(_T_606, asSInt(UInt<17>(0h10000))) node _T_608 = asSInt(_T_607) node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0))) node _T_610 = and(_T_604, _T_609) node _T_611 = or(UInt<1>(0h0), _T_610) node _T_612 = and(_T_603, _T_611) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_612, UInt<1>(0h1), "") : assert_41 node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(source_ok, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(is_aligned, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_622 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_622, UInt<1>(0h1), "") : assert_44 node _T_626 = eq(io.in.a.bits.mask, mask) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_626, UInt<1>(0h1), "") : assert_45 node _T_630 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_630 : node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<1>(0h0)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_32) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_641 = shr(io.in.a.bits.source, 2) node _T_642 = eq(_T_641, UInt<1>(0h1)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_33) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_646 = and(_T_644, _T_645) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_647 = shr(io.in.a.bits.source, 2) node _T_648 = eq(_T_647, UInt<2>(0h2)) node _T_649 = leq(UInt<1>(0h0), uncommonBits_34) node _T_650 = and(_T_648, _T_649) node _T_651 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_652 = and(_T_650, _T_651) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_653 = shr(io.in.a.bits.source, 2) node _T_654 = eq(_T_653, UInt<2>(0h3)) node _T_655 = leq(UInt<1>(0h0), uncommonBits_35) node _T_656 = and(_T_654, _T_655) node _T_657 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_661 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_662 = or(_T_634, _T_640) node _T_663 = or(_T_662, _T_646) node _T_664 = or(_T_663, _T_652) node _T_665 = or(_T_664, _T_658) node _T_666 = or(_T_665, _T_659) node _T_667 = or(_T_666, _T_660) node _T_668 = or(_T_667, _T_661) node _T_669 = and(_T_633, _T_668) node _T_670 = or(UInt<1>(0h0), _T_669) node _T_671 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<17>(0h10000))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = and(_T_671, _T_676) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = and(_T_670, _T_678) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_679, UInt<1>(0h1), "") : assert_46 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(source_ok, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(is_aligned, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_689 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_689, UInt<1>(0h1), "") : assert_49 node _T_693 = eq(io.in.a.bits.mask, mask) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_693, UInt<1>(0h1), "") : assert_50 node _T_697 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_697, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_701 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_701, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_705 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_705 : node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(source_ok_1, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_709 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_709, UInt<1>(0h1), "") : assert_54 node _T_713 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_713, UInt<1>(0h1), "") : assert_55 node _T_717 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_717, UInt<1>(0h1), "") : assert_56 node _T_721 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_721, UInt<1>(0h1), "") : assert_57 node _T_725 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_725 : node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(source_ok_1, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(sink_ok, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_732 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_732, UInt<1>(0h1), "") : assert_60 node _T_736 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_736, UInt<1>(0h1), "") : assert_61 node _T_740 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_740, UInt<1>(0h1), "") : assert_62 node _T_744 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_744, UInt<1>(0h1), "") : assert_63 node _T_748 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_749 = or(UInt<1>(0h0), _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_749, UInt<1>(0h1), "") : assert_64 node _T_753 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(source_ok_1, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(sink_ok, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_760 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_761 = asUInt(reset) node _T_762 = eq(_T_761, UInt<1>(0h0)) when _T_762 : node _T_763 = eq(_T_760, UInt<1>(0h0)) when _T_763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_760, UInt<1>(0h1), "") : assert_67 node _T_764 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_764, UInt<1>(0h1), "") : assert_68 node _T_768 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_768, UInt<1>(0h1), "") : assert_69 node _T_772 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_773 = or(_T_772, io.in.d.bits.corrupt) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_773, UInt<1>(0h1), "") : assert_70 node _T_777 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_778, UInt<1>(0h1), "") : assert_71 node _T_782 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_782 : node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(source_ok_1, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_786 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_786, UInt<1>(0h1), "") : assert_73 node _T_790 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_790, UInt<1>(0h1), "") : assert_74 node _T_794 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_795, UInt<1>(0h1), "") : assert_75 node _T_799 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_799 : node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(source_ok_1, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_803 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_803, UInt<1>(0h1), "") : assert_77 node _T_807 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_808 = or(_T_807, io.in.d.bits.corrupt) node _T_809 = asUInt(reset) node _T_810 = eq(_T_809, UInt<1>(0h0)) when _T_810 : node _T_811 = eq(_T_808, UInt<1>(0h0)) when _T_811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_808, UInt<1>(0h1), "") : assert_78 node _T_812 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_813 = or(UInt<1>(0h0), _T_812) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_813, UInt<1>(0h1), "") : assert_79 node _T_817 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_817 : node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(source_ok_1, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_821 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_821, UInt<1>(0h1), "") : assert_81 node _T_825 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_825, UInt<1>(0h1), "") : assert_82 node _T_829 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_830 = or(UInt<1>(0h0), _T_829) node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_T_830, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_830, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_834 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_834, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_838 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_838, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_842 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_842, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_846 = eq(a_first, UInt<1>(0h0)) node _T_847 = and(io.in.a.valid, _T_846) when _T_847 : node _T_848 = eq(io.in.a.bits.opcode, opcode) node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(_T_848, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_848, UInt<1>(0h1), "") : assert_87 node _T_852 = eq(io.in.a.bits.param, param) node _T_853 = asUInt(reset) node _T_854 = eq(_T_853, UInt<1>(0h0)) when _T_854 : node _T_855 = eq(_T_852, UInt<1>(0h0)) when _T_855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_852, UInt<1>(0h1), "") : assert_88 node _T_856 = eq(io.in.a.bits.size, size) node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(_T_856, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_856, UInt<1>(0h1), "") : assert_89 node _T_860 = eq(io.in.a.bits.source, source) node _T_861 = asUInt(reset) node _T_862 = eq(_T_861, UInt<1>(0h0)) when _T_862 : node _T_863 = eq(_T_860, UInt<1>(0h0)) when _T_863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_860, UInt<1>(0h1), "") : assert_90 node _T_864 = eq(io.in.a.bits.address, address) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_864, UInt<1>(0h1), "") : assert_91 node _T_868 = and(io.in.a.ready, io.in.a.valid) node _T_869 = and(_T_868, a_first) when _T_869 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_870 = eq(d_first, UInt<1>(0h0)) node _T_871 = and(io.in.d.valid, _T_870) when _T_871 : node _T_872 = eq(io.in.d.bits.opcode, opcode_1) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_872, UInt<1>(0h1), "") : assert_92 node _T_876 = eq(io.in.d.bits.param, param_1) node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(_T_876, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_876, UInt<1>(0h1), "") : assert_93 node _T_880 = eq(io.in.d.bits.size, size_1) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_880, UInt<1>(0h1), "") : assert_94 node _T_884 = eq(io.in.d.bits.source, source_1) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_884, UInt<1>(0h1), "") : assert_95 node _T_888 = eq(io.in.d.bits.sink, sink) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_888, UInt<1>(0h1), "") : assert_96 node _T_892 = eq(io.in.d.bits.denied, denied) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_892, UInt<1>(0h1), "") : assert_97 node _T_896 = and(io.in.d.ready, io.in.d.valid) node _T_897 = and(_T_896, d_first) when _T_897 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_898 = and(io.in.a.valid, a_first_1) node _T_899 = and(_T_898, UInt<1>(0h1)) when _T_899 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_900 = and(io.in.a.ready, io.in.a.valid) node _T_901 = and(_T_900, a_first_1) node _T_902 = and(_T_901, UInt<1>(0h1)) when _T_902 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_903 = dshr(inflight, io.in.a.bits.source) node _T_904 = bits(_T_903, 0, 0) node _T_905 = eq(_T_904, UInt<1>(0h0)) node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(_T_905, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_905, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_909 = and(io.in.d.valid, d_first_1) node _T_910 = and(_T_909, UInt<1>(0h1)) node _T_911 = eq(d_release_ack, UInt<1>(0h0)) node _T_912 = and(_T_910, _T_911) when _T_912 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_913 = and(io.in.d.ready, io.in.d.valid) node _T_914 = and(_T_913, d_first_1) node _T_915 = and(_T_914, UInt<1>(0h1)) node _T_916 = eq(d_release_ack, UInt<1>(0h0)) node _T_917 = and(_T_915, _T_916) when _T_917 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_918 = and(io.in.d.valid, d_first_1) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = eq(d_release_ack, UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) when _T_921 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_922 = dshr(inflight, io.in.d.bits.source) node _T_923 = bits(_T_922, 0, 0) node _T_924 = or(_T_923, same_cycle_resp) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_924, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_928 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_929 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_930 = or(_T_928, _T_929) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_930, UInt<1>(0h1), "") : assert_100 node _T_934 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_934, UInt<1>(0h1), "") : assert_101 else : node _T_938 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_939 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_940 = or(_T_938, _T_939) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_940, UInt<1>(0h1), "") : assert_102 node _T_944 = eq(io.in.d.bits.size, a_size_lookup) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_944, UInt<1>(0h1), "") : assert_103 node _T_948 = and(io.in.d.valid, d_first_1) node _T_949 = and(_T_948, a_first_1) node _T_950 = and(_T_949, io.in.a.valid) node _T_951 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_952 = and(_T_950, _T_951) node _T_953 = eq(d_release_ack, UInt<1>(0h0)) node _T_954 = and(_T_952, _T_953) when _T_954 : node _T_955 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_956 = or(_T_955, io.in.a.ready) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_956, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_960 = orr(inflight) node _T_961 = eq(_T_960, UInt<1>(0h0)) node _T_962 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_963 = or(_T_961, _T_962) node _T_964 = lt(watchdog, plusarg_reader.out) node _T_965 = or(_T_963, _T_964) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_965, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_969 = and(io.in.a.ready, io.in.a.valid) node _T_970 = and(io.in.d.ready, io.in.d.valid) node _T_971 = or(_T_969, _T_970) when _T_971 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_972 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_973 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_974 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_975 = and(_T_973, _T_974) node _T_976 = and(_T_972, _T_975) when _T_976 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_977 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_978 = and(_T_977, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_979 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_980 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_981 = and(_T_979, _T_980) node _T_982 = and(_T_978, _T_981) when _T_982 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_983 = dshr(inflight_1, _WIRE_15.bits.source) node _T_984 = bits(_T_983, 0, 0) node _T_985 = eq(_T_984, UInt<1>(0h0)) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_985, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_989 = and(io.in.d.valid, d_first_2) node _T_990 = and(_T_989, UInt<1>(0h1)) node _T_991 = and(_T_990, d_release_ack_1) when _T_991 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_992 = and(io.in.d.ready, io.in.d.valid) node _T_993 = and(_T_992, d_first_2) node _T_994 = and(_T_993, UInt<1>(0h1)) node _T_995 = and(_T_994, d_release_ack_1) when _T_995 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_996 = and(io.in.d.valid, d_first_2) node _T_997 = and(_T_996, UInt<1>(0h1)) node _T_998 = and(_T_997, d_release_ack_1) when _T_998 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_999 = dshr(inflight_1, io.in.d.bits.source) node _T_1000 = bits(_T_999, 0, 0) node _T_1001 = or(_T_1000, same_cycle_resp_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1005 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_108 else : node _T_1009 = eq(io.in.d.bits.size, c_size_lookup) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_109 node _T_1013 = and(io.in.d.valid, d_first_2) node _T_1014 = and(_T_1013, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1015 = and(_T_1014, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1016 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1017 = and(_T_1015, _T_1016) node _T_1018 = and(_T_1017, d_release_ack_1) node _T_1019 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1020 = and(_T_1018, _T_1019) when _T_1020 : node _T_1021 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1022 = or(_T_1021, _WIRE_23.ready) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_1026 = orr(inflight_1) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) node _T_1028 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1029 = or(_T_1027, _T_1028) node _T_1030 = lt(watchdog_1, plusarg_reader_1.out) node _T_1031 = or(_T_1029, _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1035 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1036 = and(io.in.d.ready, io.in.d.valid) node _T_1037 = or(_T_1035, _T_1036) when _T_1037 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [259:0] _inflight_opcodes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [259:0] _inflight_sizes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [64:0] _inflight_T_4 = 65'h1FFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [259:0] d_opcodes_clr_1 = 260'h0; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1 = 260'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [64:0] d_clr_1 = 65'h0; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1 = 65'h0; // @[Monitor.scala:775:34] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_969 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_969; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_969; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1037 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1037; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1037; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1037; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_902 = _T_969 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_902 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_902 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_902 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_902 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_902 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_948 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_4 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_948 ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_915 = _T_1037 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_915 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_915 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_915 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_161 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_161( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_0ClockSinkDomain : output auto : { egress_width_widget_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, egress_width_widget_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, egress_width_widget_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, flip ingress_width_widget_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, flip ingress_width_widget_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, flip ingress_width_widget_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_16 connect routers.clock, childClock connect routers.reset, childReset inst ingress_width_widget of IngressWidthWidget connect ingress_width_widget.clock, childClock connect ingress_width_widget.reset, childReset inst ingress_width_widget_1 of IngressWidthWidget_1 connect ingress_width_widget_1.clock, childClock connect ingress_width_widget_1.reset, childReset inst ingress_width_widget_2 of IngressWidthWidget_2 connect ingress_width_widget_2.clock, childClock connect ingress_width_widget_2.reset, childReset inst egress_width_widget of EgressWidthWidget connect egress_width_widget.clock, childClock connect egress_width_widget.reset, childReset inst egress_width_widget_1 of EgressWidthWidget_1 connect egress_width_widget_1.clock, childClock connect egress_width_widget_1.reset, childReset inst egress_width_widget_2 of EgressWidthWidget_2 connect egress_width_widget_2.clock, childClock connect egress_width_widget_2.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect egress_width_widget.auto.in, routers.auto.egress_nodes_out_0 connect egress_width_widget_1.auto.in, routers.auto.egress_nodes_out_1 connect egress_width_widget_2.auto.in, routers.auto.egress_nodes_out_2 connect routers.auto.ingress_nodes_in_0, ingress_width_widget.auto.out connect routers.auto.ingress_nodes_in_1, ingress_width_widget_1.auto.out connect routers.auto.ingress_nodes_in_2, ingress_width_widget_2.auto.out connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect auto.routers_debug_out, routers.auto.debug_out connect ingress_width_widget.auto.in, auto.ingress_width_widget_in_0 connect ingress_width_widget_1.auto.in, auto.ingress_width_widget_in_1 connect ingress_width_widget_2.auto.in, auto.ingress_width_widget_in_2 connect auto.egress_width_widget_out_0.flit.bits, egress_width_widget.auto.out.flit.bits connect auto.egress_width_widget_out_0.flit.valid, egress_width_widget.auto.out.flit.valid connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out_0.flit.ready connect auto.egress_width_widget_out_1.flit.bits, egress_width_widget_1.auto.out.flit.bits connect auto.egress_width_widget_out_1.flit.valid, egress_width_widget_1.auto.out.flit.valid connect egress_width_widget_1.auto.out.flit.ready, auto.egress_width_widget_out_1.flit.ready connect auto.egress_width_widget_out_2.flit.bits, egress_width_widget_2.auto.out.flit.bits connect auto.egress_width_widget_out_2.flit.valid, egress_width_widget_2.auto.out.flit.valid connect egress_width_widget_2.auto.out.flit.ready, auto.egress_width_widget_out_2.flit.ready connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLSplitACDxBENoC_be_router_0ClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_egress_width_widget_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_egress_width_widget_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_width_widget_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_width_widget_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_width_widget_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_width_widget_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_2_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _egress_width_widget_1_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_2_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_1_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_1_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_1_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_1_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [4:0] _ingress_width_widget_1_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_2_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_2_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_2_flit_bits_tail; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_1_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_0_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_1_flit_ready; // @[NoC.scala:67:22] Router_16 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_2_flit_ready (_egress_width_widget_2_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_2_flit_valid (_routers_auto_egress_nodes_out_2_flit_valid), .auto_egress_nodes_out_2_flit_bits_head (_routers_auto_egress_nodes_out_2_flit_bits_head), .auto_egress_nodes_out_2_flit_bits_tail (_routers_auto_egress_nodes_out_2_flit_bits_tail), .auto_egress_nodes_out_1_flit_ready (_egress_width_widget_1_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_1_flit_valid (_routers_auto_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (_routers_auto_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (_routers_auto_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (_routers_auto_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_0_flit_valid (_routers_auto_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (_routers_auto_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (_routers_auto_egress_nodes_out_0_flit_bits_tail), .auto_ingress_nodes_in_2_flit_valid (_ingress_width_widget_2_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_1_flit_ready (_routers_auto_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (_ingress_width_widget_1_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_1_flit_bits_head (_ingress_width_widget_1_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_1_flit_bits_tail (_ingress_width_widget_1_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_1_flit_bits_payload (_ingress_width_widget_1_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_1_flit_bits_egress_id (_ingress_width_widget_1_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_0_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_0_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_0_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_0_flit_bits_head), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_0_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_0_flit_bits_egress_id), .auto_out_flit_ready (1'h0), // @[ClockDomain.scala:14:9] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (/* unused */), .auto_out_flit_bits_tail (/* unused */), .auto_out_flit_bits_payload (/* unused */), .auto_out_flit_bits_egress_id (/* unused */) ); // @[WidthWidget.scala:88:44] IngressWidthWidget ingress_width_widget_1 ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_1_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_1_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_1_flit_bits_head), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_1_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_1_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_1_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_1_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_1_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_1_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_1_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_1_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] IngressWidthWidget_2 ingress_width_widget_2 ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_2_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_2_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_2_flit_bits_head), .auto_in_flit_bits_tail (auto_ingress_width_widget_in_2_flit_bits_tail), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_2_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_2_flit_bits_egress_id), .auto_out_flit_ready (1'h0), // @[ClockDomain.scala:14:9] .auto_out_flit_valid (_ingress_width_widget_2_auto_out_flit_valid), .auto_out_flit_bits_head (/* unused */), .auto_out_flit_bits_tail (/* unused */), .auto_out_flit_bits_payload (/* unused */), .auto_out_flit_bits_egress_id (/* unused */) ); // @[WidthWidget.scala:88:44] EgressWidthWidget egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_0_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_0_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_0_flit_bits_tail), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_0_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_0_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_0_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_0_flit_bits_tail) ); // @[WidthWidget.scala:111:43] EgressWidthWidget_1 egress_width_widget_1 ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_1_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_1_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_1_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_1_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_1_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_1_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_1_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_1_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_1_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_1_flit_bits_payload) ); // @[WidthWidget.scala:111:43] EgressWidthWidget egress_width_widget_2 ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_2_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_2_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_2_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_2_flit_bits_tail), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_2_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_2_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_2_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_2_flit_bits_tail) ); // @[WidthWidget.scala:111:43] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = or(_T_38, _T_43) node _T_75 = or(_T_74, _T_48) node _T_76 = or(_T_75, _T_53) node _T_77 = or(_T_76, _T_58) node _T_78 = or(_T_77, _T_63) node _T_79 = or(_T_78, _T_68) node _T_80 = or(_T_79, _T_73) node _T_81 = and(_T_33, _T_80) node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_83 = or(UInt<1>(0h0), _T_82) node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _T_95 = and(_T_83, _T_94) node _T_96 = or(UInt<1>(0h0), _T_81) node _T_97 = or(_T_96, _T_95) node _T_98 = and(_T_32, _T_97) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_98, UInt<1>(0h1), "") : assert_2 node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_102 connect _WIRE[1], _T_103 node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0)) node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = or(_T_105, _T_106) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_107 node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = or(UInt<1>(0h0), _T_110) node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = or(_T_116, _T_121) node _T_163 = or(_T_162, _T_126) node _T_164 = or(_T_163, _T_131) node _T_165 = or(_T_164, _T_136) node _T_166 = or(_T_165, _T_141) node _T_167 = or(_T_166, _T_146) node _T_168 = or(_T_167, _T_151) node _T_169 = or(_T_168, _T_156) node _T_170 = or(_T_169, _T_161) node _T_171 = and(_T_111, _T_170) node _T_172 = or(UInt<1>(0h0), _T_171) node _T_173 = and(_WIRE_1, _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(source_ok, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_180, UInt<1>(0h1), "") : assert_5 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(is_aligned, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_187, UInt<1>(0h1), "") : assert_7 node _T_191 = not(io.in.a.bits.mask) node _T_192 = eq(_T_191, UInt<1>(0h0)) node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_T_192, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_192, UInt<1>(0h1), "") : assert_8 node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_197 = asUInt(reset) node _T_198 = eq(_T_197, UInt<1>(0h0)) when _T_198 : node _T_199 = eq(_T_196, UInt<1>(0h0)) when _T_199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_196, UInt<1>(0h1), "") : assert_9 node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_200 : node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_206 = or(_T_204, _T_205) node _T_207 = and(_T_203, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_226 = cvt(_T_225) node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000))) node _T_228 = asSInt(_T_227) node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = or(_T_214, _T_219) node _T_251 = or(_T_250, _T_224) node _T_252 = or(_T_251, _T_229) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_239) node _T_255 = or(_T_254, _T_244) node _T_256 = or(_T_255, _T_249) node _T_257 = and(_T_209, _T_256) node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_259 = or(UInt<1>(0h0), _T_258) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_264, _T_269) node _T_271 = and(_T_259, _T_270) node _T_272 = or(UInt<1>(0h0), _T_257) node _T_273 = or(_T_272, _T_271) node _T_274 = and(_T_208, _T_273) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_274, UInt<1>(0h1), "") : assert_10 node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_278 connect _WIRE_2[1], _T_279 node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0)) node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = or(_T_281, _T_282) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_283 node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = or(_T_292, _T_297) node _T_339 = or(_T_338, _T_302) node _T_340 = or(_T_339, _T_307) node _T_341 = or(_T_340, _T_312) node _T_342 = or(_T_341, _T_317) node _T_343 = or(_T_342, _T_322) node _T_344 = or(_T_343, _T_327) node _T_345 = or(_T_344, _T_332) node _T_346 = or(_T_345, _T_337) node _T_347 = and(_T_287, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = and(_WIRE_3, _T_348) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_349, UInt<1>(0h1), "") : assert_11 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(source_ok, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_356, UInt<1>(0h1), "") : assert_13 node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(is_aligned, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_363, UInt<1>(0h1), "") : assert_15 node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_367, UInt<1>(0h1), "") : assert_16 node _T_371 = not(io.in.a.bits.mask) node _T_372 = eq(_T_371, UInt<1>(0h0)) node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_T_372, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_372, UInt<1>(0h1), "") : assert_17 node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_376, UInt<1>(0h1), "") : assert_18 node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_380 : node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_386 = or(_T_384, _T_385) node _T_387 = and(_T_383, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_388, UInt<1>(0h1), "") : assert_19 node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = or(UInt<1>(0h0), _T_394) node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = and(_T_395, _T_400) node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_404 = and(_T_402, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_407 = cvt(_T_406) node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000))) node _T_409 = asSInt(_T_408) node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0))) node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = or(_T_410, _T_415) node _T_452 = or(_T_451, _T_420) node _T_453 = or(_T_452, _T_425) node _T_454 = or(_T_453, _T_430) node _T_455 = or(_T_454, _T_435) node _T_456 = or(_T_455, _T_440) node _T_457 = or(_T_456, _T_445) node _T_458 = or(_T_457, _T_450) node _T_459 = and(_T_405, _T_458) node _T_460 = or(UInt<1>(0h0), _T_401) node _T_461 = or(_T_460, _T_459) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_461, UInt<1>(0h1), "") : assert_20 node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(source_ok, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(is_aligned, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_471, UInt<1>(0h1), "") : assert_23 node _T_475 = eq(io.in.a.bits.mask, mask) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_475, UInt<1>(0h1), "") : assert_24 node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_479, UInt<1>(0h1), "") : assert_25 node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_483 : node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_489 = or(_T_487, _T_488) node _T_490 = and(_T_486, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = and(_T_495, _T_500) node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = or(_T_510, _T_515) node _T_547 = or(_T_546, _T_520) node _T_548 = or(_T_547, _T_525) node _T_549 = or(_T_548, _T_530) node _T_550 = or(_T_549, _T_535) node _T_551 = or(_T_550, _T_540) node _T_552 = or(_T_551, _T_545) node _T_553 = and(_T_505, _T_552) node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = and(_T_554, _T_559) node _T_561 = or(UInt<1>(0h0), _T_501) node _T_562 = or(_T_561, _T_553) node _T_563 = or(_T_562, _T_560) node _T_564 = and(_T_491, _T_563) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_564, UInt<1>(0h1), "") : assert_26 node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(source_ok, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(is_aligned, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_574, UInt<1>(0h1), "") : assert_29 node _T_578 = eq(io.in.a.bits.mask, mask) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_578, UInt<1>(0h1), "") : assert_30 node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_582 : node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_585 = and(_T_583, _T_584) node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(_T_585, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_596 = cvt(_T_595) node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000))) node _T_598 = asSInt(_T_597) node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0))) node _T_600 = and(_T_594, _T_599) node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_603 = and(_T_601, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_606 = cvt(_T_605) node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000))) node _T_608 = asSInt(_T_607) node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0))) node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = or(_T_609, _T_614) node _T_646 = or(_T_645, _T_619) node _T_647 = or(_T_646, _T_624) node _T_648 = or(_T_647, _T_629) node _T_649 = or(_T_648, _T_634) node _T_650 = or(_T_649, _T_639) node _T_651 = or(_T_650, _T_644) node _T_652 = and(_T_604, _T_651) node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_655 = cvt(_T_654) node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000))) node _T_657 = asSInt(_T_656) node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0))) node _T_659 = and(_T_653, _T_658) node _T_660 = or(UInt<1>(0h0), _T_600) node _T_661 = or(_T_660, _T_652) node _T_662 = or(_T_661, _T_659) node _T_663 = and(_T_590, _T_662) node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(_T_663, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_663, UInt<1>(0h1), "") : assert_31 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(source_ok, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(is_aligned, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_673, UInt<1>(0h1), "") : assert_34 node _T_677 = not(mask) node _T_678 = and(io.in.a.bits.mask, _T_677) node _T_679 = eq(_T_678, UInt<1>(0h0)) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_679, UInt<1>(0h1), "") : assert_35 node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_683 : node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_686 = and(_T_684, _T_685) node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_689 = or(_T_687, _T_688) node _T_690 = and(_T_686, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_702 = cvt(_T_701) node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) node _T_704 = asSInt(_T_703) node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = or(_T_700, _T_705) node _T_742 = or(_T_741, _T_710) node _T_743 = or(_T_742, _T_715) node _T_744 = or(_T_743, _T_720) node _T_745 = or(_T_744, _T_725) node _T_746 = or(_T_745, _T_730) node _T_747 = or(_T_746, _T_735) node _T_748 = or(_T_747, _T_740) node _T_749 = and(_T_695, _T_748) node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = and(_T_750, _T_755) node _T_757 = or(UInt<1>(0h0), _T_749) node _T_758 = or(_T_757, _T_756) node _T_759 = and(_T_691, _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_759, UInt<1>(0h1), "") : assert_36 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(source_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_769, UInt<1>(0h1), "") : assert_39 node _T_773 = eq(io.in.a.bits.mask, mask) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_773, UInt<1>(0h1), "") : assert_40 node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_777 : node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_780 = and(_T_778, _T_779) node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_783 = or(_T_781, _T_782) node _T_784 = and(_T_780, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = or(_T_794, _T_799) node _T_836 = or(_T_835, _T_804) node _T_837 = or(_T_836, _T_809) node _T_838 = or(_T_837, _T_814) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_829) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_789, _T_842) node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = and(_T_844, _T_849) node _T_851 = or(UInt<1>(0h0), _T_843) node _T_852 = or(_T_851, _T_850) node _T_853 = and(_T_785, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_853, UInt<1>(0h1), "") : assert_41 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_863, UInt<1>(0h1), "") : assert_44 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_867, UInt<1>(0h1), "") : assert_45 node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_871 : node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_874 = and(_T_872, _T_873) node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_877 = or(_T_875, _T_876) node _T_878 = and(_T_874, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_882 = and(_T_880, _T_881) node _T_883 = or(UInt<1>(0h0), _T_882) node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = and(_T_883, _T_888) node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = or(_T_895, _T_900) node _T_927 = or(_T_926, _T_905) node _T_928 = or(_T_927, _T_910) node _T_929 = or(_T_928, _T_915) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_925) node _T_932 = and(_T_890, _T_931) node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_935 = and(_T_933, _T_934) node _T_936 = or(UInt<1>(0h0), _T_935) node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = or(_T_941, _T_946) node _T_948 = and(_T_936, _T_947) node _T_949 = or(UInt<1>(0h0), _T_889) node _T_950 = or(_T_949, _T_932) node _T_951 = or(_T_950, _T_948) node _T_952 = and(_T_879, _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_952, UInt<1>(0h1), "") : assert_46 node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(source_ok, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(is_aligned, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_962, UInt<1>(0h1), "") : assert_49 node _T_966 = eq(io.in.a.bits.mask, mask) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_966, UInt<1>(0h1), "") : assert_50 node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_970, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_974, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_978 : node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(source_ok_1, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_982, UInt<1>(0h1), "") : assert_54 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_986, UInt<1>(0h1), "") : assert_55 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_990, UInt<1>(0h1), "") : assert_56 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_994, UInt<1>(0h1), "") : assert_57 node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_998 : node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(source_ok_1, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(sink_ok, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60 node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61 node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62 node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63 node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1022 = or(UInt<1>(0h1), _T_1021) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64 node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1026 : node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(source_ok_1, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(sink_ok, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67 node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68 node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69 node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1046 = or(_T_1045, io.in.d.bits.corrupt) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70 node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1051 = or(UInt<1>(0h1), _T_1050) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71 node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1055 : node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(source_ok_1, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73 node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74 node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1068 = or(UInt<1>(0h1), _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75 node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1072 : node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(source_ok_1, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.d.bits.corrupt) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h1), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79 node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81 node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(UInt<1>(0h1), _T_1102) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84 node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1114 = cvt(_T_1113) node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = asSInt(_T_1115) node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0))) node _T_1118 = or(_T_1112, _T_1117) node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = or(_T_1120, _T_1125) node _T_1127 = and(_T_1118, _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1131 : node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1132 connect _WIRE_4[1], _T_1133 node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0)) node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1137 node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1140 = and(_T_1138, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1183 = cvt(_T_1182) node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000))) node _T_1185 = asSInt(_T_1184) node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0))) node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1188 = cvt(_T_1187) node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000))) node _T_1190 = asSInt(_T_1189) node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0))) node _T_1192 = or(_T_1146, _T_1151) node _T_1193 = or(_T_1192, _T_1156) node _T_1194 = or(_T_1193, _T_1161) node _T_1195 = or(_T_1194, _T_1166) node _T_1196 = or(_T_1195, _T_1171) node _T_1197 = or(_T_1196, _T_1176) node _T_1198 = or(_T_1197, _T_1181) node _T_1199 = or(_T_1198, _T_1186) node _T_1200 = or(_T_1199, _T_1191) node _T_1201 = and(_T_1141, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1201) node _T_1203 = and(_WIRE_5, _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86 node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(address_ok, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(legal_source, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90 node _T_1220 = eq(io.in.b.bits.mask, mask_1) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91 node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1228 : node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1231 = and(_T_1229, _T_1230) node _T_1232 = or(UInt<1>(0h0), _T_1231) node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1234 = cvt(_T_1233) node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000))) node _T_1236 = asSInt(_T_1235) node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0))) node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1274 = cvt(_T_1273) node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000))) node _T_1276 = asSInt(_T_1275) node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0))) node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = or(_T_1237, _T_1242) node _T_1284 = or(_T_1283, _T_1247) node _T_1285 = or(_T_1284, _T_1252) node _T_1286 = or(_T_1285, _T_1257) node _T_1287 = or(_T_1286, _T_1262) node _T_1288 = or(_T_1287, _T_1267) node _T_1289 = or(_T_1288, _T_1272) node _T_1290 = or(_T_1289, _T_1277) node _T_1291 = or(_T_1290, _T_1282) node _T_1292 = and(_T_1232, _T_1291) node _T_1293 = or(UInt<1>(0h0), _T_1292) node _T_1294 = and(UInt<1>(0h0), _T_1293) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93 node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(address_ok, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(legal_source, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97 node _T_1311 = eq(io.in.b.bits.mask, mask_1) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98 node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99 node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1319 : node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = or(UInt<1>(0h0), _T_1322) node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1335 = cvt(_T_1334) node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000))) node _T_1337 = asSInt(_T_1336) node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0))) node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1340 = cvt(_T_1339) node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000))) node _T_1342 = asSInt(_T_1341) node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0))) node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1345 = cvt(_T_1344) node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000))) node _T_1347 = asSInt(_T_1346) node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0))) node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1350 = cvt(_T_1349) node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000))) node _T_1352 = asSInt(_T_1351) node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0))) node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1355 = cvt(_T_1354) node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000))) node _T_1357 = asSInt(_T_1356) node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0))) node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1365 = cvt(_T_1364) node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000))) node _T_1367 = asSInt(_T_1366) node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0))) node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1370 = cvt(_T_1369) node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000))) node _T_1372 = asSInt(_T_1371) node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0))) node _T_1374 = or(_T_1328, _T_1333) node _T_1375 = or(_T_1374, _T_1338) node _T_1376 = or(_T_1375, _T_1343) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1353) node _T_1379 = or(_T_1378, _T_1358) node _T_1380 = or(_T_1379, _T_1363) node _T_1381 = or(_T_1380, _T_1368) node _T_1382 = or(_T_1381, _T_1373) node _T_1383 = and(_T_1323, _T_1382) node _T_1384 = or(UInt<1>(0h0), _T_1383) node _T_1385 = and(UInt<1>(0h0), _T_1384) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100 node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(address_ok, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(legal_source, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104 node _T_1402 = eq(io.in.b.bits.mask, mask_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105 node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1406 : node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = or(UInt<1>(0h0), _T_1409) node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1427 = cvt(_T_1426) node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000))) node _T_1429 = asSInt(_T_1428) node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0))) node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1432 = cvt(_T_1431) node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000))) node _T_1434 = asSInt(_T_1433) node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0))) node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1447 = cvt(_T_1446) node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000))) node _T_1449 = asSInt(_T_1448) node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1452 = cvt(_T_1451) node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000))) node _T_1454 = asSInt(_T_1453) node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0))) node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = or(_T_1415, _T_1420) node _T_1462 = or(_T_1461, _T_1425) node _T_1463 = or(_T_1462, _T_1430) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = or(_T_1464, _T_1440) node _T_1466 = or(_T_1465, _T_1445) node _T_1467 = or(_T_1466, _T_1450) node _T_1468 = or(_T_1467, _T_1455) node _T_1469 = or(_T_1468, _T_1460) node _T_1470 = and(_T_1410, _T_1469) node _T_1471 = or(UInt<1>(0h0), _T_1470) node _T_1472 = and(UInt<1>(0h0), _T_1471) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(address_ok, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(legal_source, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110 node _T_1489 = not(mask_1) node _T_1490 = and(io.in.b.bits.mask, _T_1489) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111 node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1495 : node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = or(UInt<1>(0h0), _T_1498) node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1506 = cvt(_T_1505) node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000))) node _T_1508 = asSInt(_T_1507) node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0))) node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1511 = cvt(_T_1510) node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000))) node _T_1513 = asSInt(_T_1512) node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0))) node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1516 = cvt(_T_1515) node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000))) node _T_1518 = asSInt(_T_1517) node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0))) node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1521 = cvt(_T_1520) node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000))) node _T_1523 = asSInt(_T_1522) node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1526 = cvt(_T_1525) node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000))) node _T_1528 = asSInt(_T_1527) node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0))) node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1536 = cvt(_T_1535) node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000))) node _T_1538 = asSInt(_T_1537) node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0))) node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1541 = cvt(_T_1540) node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000))) node _T_1543 = asSInt(_T_1542) node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0))) node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1546 = cvt(_T_1545) node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000))) node _T_1548 = asSInt(_T_1547) node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = or(_T_1504, _T_1509) node _T_1551 = or(_T_1550, _T_1514) node _T_1552 = or(_T_1551, _T_1519) node _T_1553 = or(_T_1552, _T_1524) node _T_1554 = or(_T_1553, _T_1529) node _T_1555 = or(_T_1554, _T_1534) node _T_1556 = or(_T_1555, _T_1539) node _T_1557 = or(_T_1556, _T_1544) node _T_1558 = or(_T_1557, _T_1549) node _T_1559 = and(_T_1499, _T_1558) node _T_1560 = or(UInt<1>(0h0), _T_1559) node _T_1561 = and(UInt<1>(0h0), _T_1560) node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(_T_1561, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112 node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(address_ok, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(legal_source, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116 node _T_1578 = eq(io.in.b.bits.mask, mask_1) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117 node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1582 : node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = or(UInt<1>(0h0), _T_1585) node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = or(_T_1591, _T_1596) node _T_1638 = or(_T_1637, _T_1601) node _T_1639 = or(_T_1638, _T_1606) node _T_1640 = or(_T_1639, _T_1611) node _T_1641 = or(_T_1640, _T_1616) node _T_1642 = or(_T_1641, _T_1621) node _T_1643 = or(_T_1642, _T_1626) node _T_1644 = or(_T_1643, _T_1631) node _T_1645 = or(_T_1644, _T_1636) node _T_1646 = and(_T_1586, _T_1645) node _T_1647 = or(UInt<1>(0h0), _T_1646) node _T_1648 = and(UInt<1>(0h0), _T_1647) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118 node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(address_ok, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(legal_source, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1658 = asUInt(reset) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) when _T_1659 : node _T_1660 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122 node _T_1665 = eq(io.in.b.bits.mask, mask_1) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123 node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1669 : node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1680 = cvt(_T_1679) node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000))) node _T_1682 = asSInt(_T_1681) node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0))) node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = or(_T_1678, _T_1683) node _T_1725 = or(_T_1724, _T_1688) node _T_1726 = or(_T_1725, _T_1693) node _T_1727 = or(_T_1726, _T_1698) node _T_1728 = or(_T_1727, _T_1703) node _T_1729 = or(_T_1728, _T_1708) node _T_1730 = or(_T_1729, _T_1713) node _T_1731 = or(_T_1730, _T_1718) node _T_1732 = or(_T_1731, _T_1723) node _T_1733 = and(_T_1673, _T_1732) node _T_1734 = or(UInt<1>(0h0), _T_1733) node _T_1735 = and(UInt<1>(0h0), _T_1734) node _T_1736 = asUInt(reset) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) when _T_1737 : node _T_1738 = eq(_T_1735, UInt<1>(0h0)) when _T_1738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124 node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(address_ok, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1742 = asUInt(reset) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) when _T_1743 : node _T_1744 = eq(legal_source, UInt<1>(0h0)) when _T_1744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1748 = eq(io.in.b.bits.mask, mask_1) node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(_T_1748, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128 node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1767, _T_1775) node _T_1777 = asUInt(reset) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) when _T_1778 : node _T_1779 = eq(_T_1776, UInt<1>(0h0)) when _T_1779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131 node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1780 : node _T_1781 = asUInt(reset) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(address_ok_1, UInt<1>(0h0)) when _T_1783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(source_ok_2, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134 node _T_1791 = asUInt(reset) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) when _T_1792 : node _T_1793 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136 node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137 node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1802 : node _T_1803 = asUInt(reset) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) when _T_1804 : node _T_1805 = eq(address_ok_1, UInt<1>(0h0)) when _T_1805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(source_ok_2, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140 node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142 node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1820 : node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1826 = or(_T_1824, _T_1825) node _T_1827 = and(_T_1823, _T_1826) node _T_1828 = or(UInt<1>(0h0), _T_1827) node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1851 = cvt(_T_1850) node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000))) node _T_1853 = asSInt(_T_1852) node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0))) node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1856 = cvt(_T_1855) node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000))) node _T_1858 = asSInt(_T_1857) node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0))) node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1861 = cvt(_T_1860) node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000))) node _T_1863 = asSInt(_T_1862) node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0))) node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1866 = cvt(_T_1865) node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000))) node _T_1868 = asSInt(_T_1867) node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0))) node _T_1870 = or(_T_1834, _T_1839) node _T_1871 = or(_T_1870, _T_1844) node _T_1872 = or(_T_1871, _T_1849) node _T_1873 = or(_T_1872, _T_1854) node _T_1874 = or(_T_1873, _T_1859) node _T_1875 = or(_T_1874, _T_1864) node _T_1876 = or(_T_1875, _T_1869) node _T_1877 = and(_T_1829, _T_1876) node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1879 = or(UInt<1>(0h0), _T_1878) node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1881 = cvt(_T_1880) node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000))) node _T_1883 = asSInt(_T_1882) node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = and(_T_1879, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1877) node _T_1893 = or(_T_1892, _T_1891) node _T_1894 = and(_T_1828, _T_1893) node _T_1895 = asUInt(reset) node _T_1896 = eq(_T_1895, UInt<1>(0h0)) when _T_1896 : node _T_1897 = eq(_T_1894, UInt<1>(0h0)) when _T_1897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143 node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1898 connect _WIRE_6[1], _T_1899 node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0)) node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1903 = or(_T_1901, _T_1902) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1903 node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1906 = and(_T_1904, _T_1905) node _T_1907 = or(UInt<1>(0h0), _T_1906) node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1924 = cvt(_T_1923) node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000))) node _T_1926 = asSInt(_T_1925) node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0))) node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1929 = cvt(_T_1928) node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000))) node _T_1931 = asSInt(_T_1930) node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0))) node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1934 = cvt(_T_1933) node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000))) node _T_1936 = asSInt(_T_1935) node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0))) node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1939 = cvt(_T_1938) node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000))) node _T_1941 = asSInt(_T_1940) node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0))) node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1944 = cvt(_T_1943) node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000))) node _T_1946 = asSInt(_T_1945) node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0))) node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1949 = cvt(_T_1948) node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000))) node _T_1951 = asSInt(_T_1950) node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0))) node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1954 = cvt(_T_1953) node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000))) node _T_1956 = asSInt(_T_1955) node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0))) node _T_1958 = or(_T_1912, _T_1917) node _T_1959 = or(_T_1958, _T_1922) node _T_1960 = or(_T_1959, _T_1927) node _T_1961 = or(_T_1960, _T_1932) node _T_1962 = or(_T_1961, _T_1937) node _T_1963 = or(_T_1962, _T_1942) node _T_1964 = or(_T_1963, _T_1947) node _T_1965 = or(_T_1964, _T_1952) node _T_1966 = or(_T_1965, _T_1957) node _T_1967 = and(_T_1907, _T_1966) node _T_1968 = or(UInt<1>(0h0), _T_1967) node _T_1969 = and(_WIRE_7, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(source_ok_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146 node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148 node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149 node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1991 : node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1994 = and(_T_1992, _T_1993) node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1997 = or(_T_1995, _T_1996) node _T_1998 = and(_T_1994, _T_1997) node _T_1999 = or(UInt<1>(0h0), _T_1998) node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2002 = cvt(_T_2001) node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000))) node _T_2004 = asSInt(_T_2003) node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0))) node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2007 = cvt(_T_2006) node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000))) node _T_2009 = asSInt(_T_2008) node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0))) node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2012 = cvt(_T_2011) node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000))) node _T_2014 = asSInt(_T_2013) node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0))) node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2017 = cvt(_T_2016) node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000))) node _T_2019 = asSInt(_T_2018) node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0))) node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2022 = cvt(_T_2021) node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000))) node _T_2024 = asSInt(_T_2023) node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2027 = cvt(_T_2026) node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000))) node _T_2029 = asSInt(_T_2028) node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0))) node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2032 = cvt(_T_2031) node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000))) node _T_2034 = asSInt(_T_2033) node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0))) node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2005, _T_2010) node _T_2042 = or(_T_2041, _T_2015) node _T_2043 = or(_T_2042, _T_2020) node _T_2044 = or(_T_2043, _T_2025) node _T_2045 = or(_T_2044, _T_2030) node _T_2046 = or(_T_2045, _T_2035) node _T_2047 = or(_T_2046, _T_2040) node _T_2048 = and(_T_2000, _T_2047) node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2050 = or(UInt<1>(0h0), _T_2049) node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2052 = cvt(_T_2051) node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000))) node _T_2054 = asSInt(_T_2053) node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0))) node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2057 = cvt(_T_2056) node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000))) node _T_2059 = asSInt(_T_2058) node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0))) node _T_2061 = or(_T_2055, _T_2060) node _T_2062 = and(_T_2050, _T_2061) node _T_2063 = or(UInt<1>(0h0), _T_2048) node _T_2064 = or(_T_2063, _T_2062) node _T_2065 = and(_T_1999, _T_2064) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150 node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2069 connect _WIRE_8[1], _T_2070 node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0)) node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2074 = or(_T_2072, _T_2073) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2074 node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2077 = and(_T_2075, _T_2076) node _T_2078 = or(UInt<1>(0h0), _T_2077) node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2100 = cvt(_T_2099) node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000))) node _T_2102 = asSInt(_T_2101) node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0))) node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2105 = cvt(_T_2104) node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000))) node _T_2107 = asSInt(_T_2106) node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0))) node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2110 = cvt(_T_2109) node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000))) node _T_2112 = asSInt(_T_2111) node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0))) node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2115 = cvt(_T_2114) node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000))) node _T_2117 = asSInt(_T_2116) node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0))) node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2120 = cvt(_T_2119) node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000))) node _T_2122 = asSInt(_T_2121) node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0))) node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2125 = cvt(_T_2124) node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000))) node _T_2127 = asSInt(_T_2126) node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = or(_T_2083, _T_2088) node _T_2130 = or(_T_2129, _T_2093) node _T_2131 = or(_T_2130, _T_2098) node _T_2132 = or(_T_2131, _T_2103) node _T_2133 = or(_T_2132, _T_2108) node _T_2134 = or(_T_2133, _T_2113) node _T_2135 = or(_T_2134, _T_2118) node _T_2136 = or(_T_2135, _T_2123) node _T_2137 = or(_T_2136, _T_2128) node _T_2138 = and(_T_2078, _T_2137) node _T_2139 = or(UInt<1>(0h0), _T_2138) node _T_2140 = and(_WIRE_9, _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151 node _T_2144 = asUInt(reset) node _T_2145 = eq(_T_2144, UInt<1>(0h0)) when _T_2145 : node _T_2146 = eq(source_ok_2, UInt<1>(0h0)) when _T_2146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2148 = asUInt(reset) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) when _T_2149 : node _T_2150 = eq(_T_2147, UInt<1>(0h0)) when _T_2150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153 node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(_T_2154, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155 node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2158 : node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(address_ok_1, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(source_ok_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159 node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(_T_2172, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160 node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2176 : node _T_2177 = asUInt(reset) node _T_2178 = eq(_T_2177, UInt<1>(0h0)) when _T_2178 : node _T_2179 = eq(address_ok_1, UInt<1>(0h0)) when _T_2179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(source_ok_2, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164 node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2190 : node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(address_ok_1, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(source_ok_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2197 = asUInt(reset) node _T_2198 = eq(_T_2197, UInt<1>(0h0)) when _T_2198 : node _T_2199 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168 node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(_T_2204, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2211 = eq(a_first, UInt<1>(0h0)) node _T_2212 = and(io.in.a.valid, _T_2211) when _T_2212 : node _T_2213 = eq(io.in.a.bits.opcode, opcode) node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : node _T_2216 = eq(_T_2213, UInt<1>(0h0)) when _T_2216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171 node _T_2217 = eq(io.in.a.bits.param, param) node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : node _T_2220 = eq(_T_2217, UInt<1>(0h0)) when _T_2220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172 node _T_2221 = eq(io.in.a.bits.size, size) node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : node _T_2224 = eq(_T_2221, UInt<1>(0h0)) when _T_2224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173 node _T_2225 = eq(io.in.a.bits.source, source) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174 node _T_2229 = eq(io.in.a.bits.address, address) node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(_T_2229, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175 node _T_2233 = and(io.in.a.ready, io.in.a.valid) node _T_2234 = and(_T_2233, a_first) when _T_2234 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2235 = eq(d_first, UInt<1>(0h0)) node _T_2236 = and(io.in.d.valid, _T_2235) when _T_2236 : node _T_2237 = eq(io.in.d.bits.opcode, opcode_1) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176 node _T_2241 = eq(io.in.d.bits.param, param_1) node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(_T_2241, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177 node _T_2245 = eq(io.in.d.bits.size, size_1) node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : node _T_2248 = eq(_T_2245, UInt<1>(0h0)) when _T_2248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178 node _T_2249 = eq(io.in.d.bits.source, source_1) node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : node _T_2252 = eq(_T_2249, UInt<1>(0h0)) when _T_2252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179 node _T_2253 = eq(io.in.d.bits.sink, sink) node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : node _T_2256 = eq(_T_2253, UInt<1>(0h0)) when _T_2256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180 node _T_2257 = eq(io.in.d.bits.denied, denied) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181 node _T_2261 = and(io.in.d.ready, io.in.d.valid) node _T_2262 = and(_T_2261, d_first) when _T_2262 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2263 = eq(b_first, UInt<1>(0h0)) node _T_2264 = and(io.in.b.valid, _T_2263) when _T_2264 : node _T_2265 = eq(io.in.b.bits.opcode, opcode_2) node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : node _T_2268 = eq(_T_2265, UInt<1>(0h0)) when _T_2268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182 node _T_2269 = eq(io.in.b.bits.param, param_2) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(_T_2269, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183 node _T_2273 = eq(io.in.b.bits.size, size_2) node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : node _T_2276 = eq(_T_2273, UInt<1>(0h0)) when _T_2276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184 node _T_2277 = eq(io.in.b.bits.source, source_2) node _T_2278 = asUInt(reset) node _T_2279 = eq(_T_2278, UInt<1>(0h0)) when _T_2279 : node _T_2280 = eq(_T_2277, UInt<1>(0h0)) when _T_2280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185 node _T_2281 = eq(io.in.b.bits.address, address_1) node _T_2282 = asUInt(reset) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : node _T_2284 = eq(_T_2281, UInt<1>(0h0)) when _T_2284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186 node _T_2285 = and(io.in.b.ready, io.in.b.valid) node _T_2286 = and(_T_2285, b_first) when _T_2286 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2287 = eq(c_first, UInt<1>(0h0)) node _T_2288 = and(io.in.c.valid, _T_2287) when _T_2288 : node _T_2289 = eq(io.in.c.bits.opcode, opcode_3) node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : node _T_2292 = eq(_T_2289, UInt<1>(0h0)) when _T_2292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187 node _T_2293 = eq(io.in.c.bits.param, param_3) node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : node _T_2296 = eq(_T_2293, UInt<1>(0h0)) when _T_2296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188 node _T_2297 = eq(io.in.c.bits.size, size_3) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(_T_2297, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189 node _T_2301 = eq(io.in.c.bits.source, source_3) node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : node _T_2304 = eq(_T_2301, UInt<1>(0h0)) when _T_2304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190 node _T_2305 = eq(io.in.c.bits.address, address_2) node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(_T_2305, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191 node _T_2309 = and(io.in.c.ready, io.in.c.valid) node _T_2310 = and(_T_2309, c_first) when _T_2310 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2311 = and(io.in.a.valid, a_first_1) node _T_2312 = and(_T_2311, UInt<1>(0h1)) when _T_2312 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2313 = and(io.in.a.ready, io.in.a.valid) node _T_2314 = and(_T_2313, a_first_1) node _T_2315 = and(_T_2314, UInt<1>(0h1)) when _T_2315 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2316 = dshr(inflight, io.in.a.bits.source) node _T_2317 = bits(_T_2316, 0, 0) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(_T_2318, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2322 = and(io.in.d.valid, d_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) node _T_2324 = eq(d_release_ack, UInt<1>(0h0)) node _T_2325 = and(_T_2323, _T_2324) when _T_2325 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2326 = and(io.in.d.ready, io.in.d.valid) node _T_2327 = and(_T_2326, d_first_1) node _T_2328 = and(_T_2327, UInt<1>(0h1)) node _T_2329 = eq(d_release_ack, UInt<1>(0h0)) node _T_2330 = and(_T_2328, _T_2329) when _T_2330 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2331 = and(io.in.d.valid, d_first_1) node _T_2332 = and(_T_2331, UInt<1>(0h1)) node _T_2333 = eq(d_release_ack, UInt<1>(0h0)) node _T_2334 = and(_T_2332, _T_2333) when _T_2334 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2335 = dshr(inflight, io.in.d.bits.source) node _T_2336 = bits(_T_2335, 0, 0) node _T_2337 = or(_T_2336, same_cycle_resp) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2343 = or(_T_2341, _T_2342) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194 node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195 else : node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2353 = or(_T_2351, _T_2352) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196 node _T_2357 = eq(io.in.d.bits.size, a_size_lookup) node _T_2358 = asUInt(reset) node _T_2359 = eq(_T_2358, UInt<1>(0h0)) when _T_2359 : node _T_2360 = eq(_T_2357, UInt<1>(0h0)) when _T_2360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197 node _T_2361 = and(io.in.d.valid, d_first_1) node _T_2362 = and(_T_2361, a_first_1) node _T_2363 = and(_T_2362, io.in.a.valid) node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2365 = and(_T_2363, _T_2364) node _T_2366 = eq(d_release_ack, UInt<1>(0h0)) node _T_2367 = and(_T_2365, _T_2366) when _T_2367 : node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2369 = or(_T_2368, io.in.a.ready) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198 node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2374 = orr(a_set_wo_ready) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) node _T_2376 = or(_T_2373, _T_2375) node _T_2377 = asUInt(reset) node _T_2378 = eq(_T_2377, UInt<1>(0h0)) when _T_2378 : node _T_2379 = eq(_T_2376, UInt<1>(0h0)) when _T_2379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_107 node _T_2380 = orr(inflight) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2383 = or(_T_2381, _T_2382) node _T_2384 = lt(watchdog, plusarg_reader.out) node _T_2385 = or(_T_2383, _T_2384) node _T_2386 = asUInt(reset) node _T_2387 = eq(_T_2386, UInt<1>(0h0)) when _T_2387 : node _T_2388 = eq(_T_2385, UInt<1>(0h0)) when _T_2388 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2389 = and(io.in.a.ready, io.in.a.valid) node _T_2390 = and(io.in.d.ready, io.in.d.valid) node _T_2391 = or(_T_2389, _T_2390) when _T_2391 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2392 = and(io.in.c.valid, c_first_1) node _T_2393 = bits(io.in.c.bits.opcode, 2, 2) node _T_2394 = bits(io.in.c.bits.opcode, 1, 1) node _T_2395 = and(_T_2393, _T_2394) node _T_2396 = and(_T_2392, _T_2395) when _T_2396 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2397 = and(io.in.c.ready, io.in.c.valid) node _T_2398 = and(_T_2397, c_first_1) node _T_2399 = bits(io.in.c.bits.opcode, 2, 2) node _T_2400 = bits(io.in.c.bits.opcode, 1, 1) node _T_2401 = and(_T_2399, _T_2400) node _T_2402 = and(_T_2398, _T_2401) when _T_2402 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2403 = dshr(inflight_1, io.in.c.bits.source) node _T_2404 = bits(_T_2403, 0, 0) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2409 = and(io.in.d.valid, d_first_2) node _T_2410 = and(_T_2409, UInt<1>(0h1)) node _T_2411 = and(_T_2410, d_release_ack_1) when _T_2411 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2412 = and(io.in.d.ready, io.in.d.valid) node _T_2413 = and(_T_2412, d_first_2) node _T_2414 = and(_T_2413, UInt<1>(0h1)) node _T_2415 = and(_T_2414, d_release_ack_1) when _T_2415 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2416 = and(io.in.d.valid, d_first_2) node _T_2417 = and(_T_2416, UInt<1>(0h1)) node _T_2418 = and(_T_2417, d_release_ack_1) when _T_2418 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2419 = dshr(inflight_1, io.in.d.bits.source) node _T_2420 = bits(_T_2419, 0, 0) node _T_2421 = or(_T_2420, same_cycle_resp_1) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203 else : node _T_2429 = eq(io.in.d.bits.size, c_size_lookup) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204 node _T_2433 = and(io.in.d.valid, d_first_2) node _T_2434 = and(_T_2433, c_first_1) node _T_2435 = and(_T_2434, io.in.c.valid) node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = and(_T_2437, d_release_ack_1) node _T_2439 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2440 = and(_T_2438, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2442 = or(_T_2441, io.in.c.ready) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205 node _T_2446 = orr(c_set_wo_ready) when _T_2446 : node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_108 node _T_2451 = orr(inflight_1) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2454 = or(_T_2452, _T_2453) node _T_2455 = lt(watchdog_1, plusarg_reader_1.out) node _T_2456 = or(_T_2454, _T_2455) node _T_2457 = asUInt(reset) node _T_2458 = eq(_T_2457, UInt<1>(0h0)) when _T_2458 : node _T_2459 = eq(_T_2456, UInt<1>(0h0)) when _T_2459 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2460 = and(io.in.c.ready, io.in.c.valid) node _T_2461 = and(io.in.d.ready, io.in.d.valid) node _T_2462 = or(_T_2460, _T_2461) when _T_2462 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2463 = and(io.in.d.ready, io.in.d.valid) node _T_2464 = and(_T_2463, d_first_3) node _T_2465 = bits(io.in.d.bits.opcode, 2, 2) node _T_2466 = bits(io.in.d.bits.opcode, 1, 1) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = and(_T_2465, _T_2467) node _T_2469 = and(_T_2464, _T_2468) when _T_2469 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2470 = dshr(inflight_2, io.in.d.bits.sink) node _T_2471 = bits(_T_2470, 0, 0) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2476 = and(io.in.e.ready, io.in.e.valid) node _T_2477 = and(_T_2476, UInt<1>(0h1)) node _T_2478 = and(_T_2477, UInt<1>(0h1)) when _T_2478 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2479 = or(d_set, inflight_2) node _T_2480 = dshr(_T_2479, io.in.e.bits.sink) node _T_2481 = bits(_T_2480, 0, 0) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_109 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module FPToInt_5 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in, io.in.bits reg valid : UInt<1>, clock connect valid, io.in.valid inst dcmp of CompareRecFN_5 connect dcmp.io.a, in.in1 connect dcmp.io.b, in.in2 node _dcmp_io_signaling_T = bits(in.rm, 1, 1) node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) connect dcmp.io.signaling, _dcmp_io_signaling_T_1 node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T) node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut) node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut) node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1) node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut) node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut) node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16) node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29) node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1) node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0) node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3) node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4) node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) node _toint_ieee_T_1 = bits(in.in1, 63, 61) node _toint_ieee_T_2 = andr(_toint_ieee_T_1) node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0) node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15) node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0)) node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6) node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9) node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1) node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4) node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1) node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16) node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29) node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6) node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0) node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8) node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9) node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32) node _toint_ieee_T_12 = bits(in.in1, 63, 61) node _toint_ieee_T_13 = andr(_toint_ieee_T_12) node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0) node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14) node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15) node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0) node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17) node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2 node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2) connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11 node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4) node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1) node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2) node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0) node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1) node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14) node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf) node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17) node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4) node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5) node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2) node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2) node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7) node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2) node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7) node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2) node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16) node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29) node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11) node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0) node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13) node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14) node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32) node _toint_ieee_T_20 = bits(in.in1, 63, 61) node _toint_ieee_T_21 = andr(_toint_ieee_T_20) node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0) node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22) node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23) node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0) node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1)) node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10) node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2)) node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27) node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3)) node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29) wire toint : UInt connect toint, toint_ieee node _intType_T = bits(in.fmt, 0, 0) wire intType : UInt<1> connect intType, _intType_T node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut) node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1) node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut) node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16) node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29) node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1) node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0) node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3) node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4) node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0) node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7) node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4) node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16) node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29) node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6) node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0) node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8) node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9) node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32) node _io_out_bits_store_T_10 = bits(in.in1, 63, 61) node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10) node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0) node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12) node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13) node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0) node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15) node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2) connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4) node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2) node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1) node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14) node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf) node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17) node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4) node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5) node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2) node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2) node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7) node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7) node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16) node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29) node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11) node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0) node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13) node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14) node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32) node _io_out_bits_store_T_18 = bits(in.in1, 63, 61) node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18) node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0) node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20) node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21) node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0) node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1)) node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8) node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2)) node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25) node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3)) node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27) connect io.out.bits.store, _io_out_bits_store_T_29 node _io_out_bits_toint_T = bits(toint, 31, 0) node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) node _io_out_bits_toint_T_4 = bits(toint, 63, 0) node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) connect io.out.bits.toint, _io_out_bits_toint_T_6 connect io.out.bits.exc, UInt<1>(0h0) node _T = bits(in.rm, 0, 0) when _T : node classify_out_sign = bits(in.in1, 64, 64) node classify_out_fractIn = bits(in.in1, 51, 0) node classify_out_expIn = bits(in.in1, 63, 52) node _classify_out_fractOut_T = shl(classify_out_fractIn, 11) node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20)) node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0) node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0) node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) node classify_out_hi = cat(classify_out_sign, classify_out_expOut) node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) node classify_out_sign_1 = bits(_classify_out_T, 16, 16) node classify_out_code = bits(_classify_out_T, 15, 13) node classify_out_codeHi = bits(classify_out_code, 2, 1) node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10) node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) node _classify_out_isInf_T = bits(classify_out_code, 0, 0) node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) node classify_out_isNaN = andr(classify_out_code) node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9) node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9) node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) node classify_out_sign_2 = bits(in.in1, 64, 64) node classify_out_fractIn_1 = bits(in.in1, 51, 0) node classify_out_expIn_1 = bits(in.in1, 63, 52) node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24) node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53) node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9) node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100)) node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1) node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800)) node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1) node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0)) node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6)) node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7) node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0) node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9) node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0) node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11) node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1) node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1) node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32) node classify_out_code_1 = bits(_classify_out_T_14, 31, 29) node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23) node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) node classify_out_isNaN_1 = andr(classify_out_code_1) node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22) node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22) node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15) node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17) node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19) node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21) node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3) node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3) node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3) node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3) node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26) node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23) node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24) node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20) node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16) node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1) node classify_out_sign_4 = bits(in.in1, 64, 64) node classify_out_code_2 = bits(in.in1, 63, 61) node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1) node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52) node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2)) node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2) node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8) node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0)) node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9) node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2)) node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11) node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0)) node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0) node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0)) node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5) node classify_out_isNaN_2 = andr(classify_out_code_2) node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51) node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0)) node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5) node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51) node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2) node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28) node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30) node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32) node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34) node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4) node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4) node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4) node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4) node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39) node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36) node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37) node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2) node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33) node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2) node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29) node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2) node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2) node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1)) node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13) node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2)) node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42) node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3)) node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44) node _toint_T = shr(toint_ieee, 32) node _toint_T_1 = shl(_toint_T, 32) node _toint_T_2 = or(classify_out, _toint_T_1) connect toint, _toint_T_2 connect intType, UInt<1>(0h0) when in.wflags : node _toint_T_3 = not(in.rm) node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) node _toint_T_5 = and(_toint_T_3, _toint_T_4) node _toint_T_6 = orr(_toint_T_5) node _toint_T_7 = shr(toint_ieee, 32) node _toint_T_8 = shl(_toint_T_7, 32) node _toint_T_9 = or(_toint_T_6, _toint_T_8) connect toint, _toint_T_9 connect io.out.bits.exc, dcmp.io.exceptionFlags connect intType, UInt<1>(0h0) node _T_1 = eq(in.ren2, UInt<1>(0h0)) when _T_1 : node cvtType = bits(in.typ, 1, 1) connect intType, cvtType inst conv of RecFNToIN_e11_s53_i64_5 connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 connect conv.io.roundingMode, in.rm node _conv_io_signedOut_T = bits(in.typ, 0, 0) node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) connect conv.io.signedOut, _conv_io_signedOut_T_1 connect toint, conv.io.out node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) connect io.out.bits.exc, _io_out_bits_exc_T_3 node _T_2 = eq(cvtType, UInt<1>(0h0)) when _T_2 : inst narrow of RecFNToIN_e11_s53_i32_5 connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 connect narrow.io.roundingMode, in.rm node _narrow_io_signedOut_T = bits(in.typ, 0, 0) node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) connect narrow.io.signedOut, _narrow_io_signedOut_T_1 node _excSign_T = bits(in.in1, 64, 64) node _excSign_T_1 = bits(in.in1, 63, 61) node _excSign_T_2 = andr(_excSign_T_1) node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) node excSign = and(_excSign_T, _excSign_T_3) node _excOut_T = eq(conv.io.signedOut, excSign) node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) node excOut = cat(_excOut_T, _excOut_T_2) node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) node invalid = or(_invalid_T, _invalid_T_1) when invalid : node _toint_T_10 = shr(conv.io.out, 32) node _toint_T_11 = cat(_toint_T_10, excOut) connect toint, _toint_T_11 node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) connect io.out.bits.exc, _io_out_bits_exc_T_7 connect io.out.valid, valid node _io_out_bits_lt_T = asSInt(dcmp.io.a) node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) connect io.out.bits.lt, _io_out_bits_lt_T_5 connect io.out.bits.in, in
module FPToInt_5( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input io_in_bits_vec, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] input [64:0] io_in_bits_in3, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14] output io_out_bits_lt, // @[FPU.scala:461:14] output [63:0] io_out_bits_store, // @[FPU.scala:461:14] output [63:0] io_out_bits_toint, // @[FPU.scala:461:14] output [4:0] io_out_bits_exc // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:453:7] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_29; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst; // @[FPU.scala:453:7] wire io_out_bits_in_wen; // @[FPU.scala:453:7] wire io_out_bits_in_ren1; // @[FPU.scala:453:7] wire io_out_bits_in_ren2; // @[FPU.scala:453:7] wire io_out_bits_in_ren3; // @[FPU.scala:453:7] wire io_out_bits_in_swap12; // @[FPU.scala:453:7] wire io_out_bits_in_swap23; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7] wire io_out_bits_in_fromint; // @[FPU.scala:453:7] wire io_out_bits_in_toint; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7] wire io_out_bits_in_fma; // @[FPU.scala:453:7] wire io_out_bits_in_div; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt; // @[FPU.scala:453:7] wire io_out_bits_in_wflags; // @[FPU.scala:453:7] wire io_out_bits_in_vec; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in3; // @[FPU.scala:453:7] wire io_out_bits_lt_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint_0; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21] reg in_vec; // @[FPU.scala:466:21] assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmaCmd; // @[FPU.scala:466:21] assign io_out_bits_in_fmaCmd = in_fmaCmd; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmt; // @[FPU.scala:466:21] assign io_out_bits_in_fmt = in_fmt; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg [64:0] in_in3; // @[FPU.scala:466:21] assign io_out_bits_in_in3 = in_in3; // @[FPU.scala:453:7, :466:21] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [11:0] classify_out_expIn_1 = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_4 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] wire [51:0] classify_out_fractIn_1 = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN | toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 | _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? toint_ieee_prevUnrecoded_unrecoded_denormFract : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi = {toint_ieee_prevUnrecoded_unrecoded_rawIn_sign, toint_ieee_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded = {toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T = toint_ieee_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_1 = toint_ieee_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_2 = toint_ieee_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi = {_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded = {toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = toint_ieee_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded = {toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T = toint_ieee_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_1 = toint_ieee_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_2 = &_toint_ieee_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_3 = toint_ieee_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_4 = _toint_ieee_prevUnrecoded_T_2 ? toint_ieee_prevUnrecoded_prevUnrecoded : _toint_ieee_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded = {_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_12 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_20 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_10 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_18 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_2 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _toint_ieee_T_6 = _toint_ieee_T_5[15:0]; // @[FPU.scala:446:10, :475:107] wire _toint_ieee_T_7 = _toint_ieee_T_6[15]; // @[package.scala:132:38] wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_7}}; // @[package.scala:132:{20,38}] wire [31:0] _toint_ieee_T_9 = {_toint_ieee_T_8, _toint_ieee_T_6}; // @[package.scala:132:{15,20}] wire [63:0] _toint_ieee_T_10 = {2{_toint_ieee_T_9}}; // @[package.scala:132:15] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN | toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 | _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_1 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_1 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_1 = {toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_3 = toint_ieee_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_4 = toint_ieee_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_5 = toint_ieee_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_1 = {_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_1 = {toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_5 = toint_ieee_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_6 = toint_ieee_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_7 = &_toint_ieee_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_8 = toint_ieee_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_9 = _toint_ieee_prevUnrecoded_T_7 ? toint_ieee_prevUnrecoded_prevUnrecoded_1 : _toint_ieee_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_1 = {_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_13 = &_toint_ieee_T_12; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_14 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_15 = _toint_ieee_T_13 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_14; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_16 = {_toint_ieee_T_11, _toint_ieee_T_15}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_17 = _toint_ieee_T_16[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_18 = {2{_toint_ieee_T_17}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_2 = _toint_ieee_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_2_isZero = toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_2_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_2_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_2_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_2_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_2_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_4 = toint_ieee_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_2 = _toint_ieee_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_4 = toint_ieee_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = _toint_ieee_unrecoded_denormFract_T_4 >> toint_ieee_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_2 = _toint_ieee_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_12 = toint_ieee_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_14 = _toint_ieee_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_15 = toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_16 = toint_ieee_unrecoded_rawIn_2_isNaN | toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_17 = {11{_toint_ieee_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_2 = _toint_ieee_unrecoded_expOut_T_15 | _toint_ieee_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_4 = toint_ieee_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_5 = toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? toint_ieee_unrecoded_denormFract_2 : _toint_ieee_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_2 = {toint_ieee_unrecoded_rawIn_2_sign, toint_ieee_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_2 = {toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_2 = {_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_2 = {toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = toint_ieee_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = toint_ieee_prevRecoded_2[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = toint_ieee_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_2 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_2 = {toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_6 = toint_ieee_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_7 = toint_ieee_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_8 = toint_ieee_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_2 = {_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_2 = {toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = toint_ieee_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = toint_ieee_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = toint_ieee_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_10 = toint_ieee_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_11 = toint_ieee_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_12 = &_toint_ieee_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_13 = toint_ieee_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_14 = _toint_ieee_prevUnrecoded_T_12 ? toint_ieee_prevUnrecoded_prevUnrecoded_2 : _toint_ieee_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_2 = {_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_19 = toint_ieee_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_21 = &_toint_ieee_T_20; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_22 = toint_ieee_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_23 = _toint_ieee_T_21 ? toint_ieee_prevUnrecoded_2 : _toint_ieee_T_22; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_24 = {_toint_ieee_T_19, _toint_ieee_T_23}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_25 = _toint_ieee_T_24; // @[FPU.scala:446:10, :476:109] wire _GEN = in_typeTagOut == 2'h1; // @[package.scala:39:86] wire _toint_ieee_T_26; // @[package.scala:39:86] assign _toint_ieee_T_26 = _GEN; // @[package.scala:39:86] wire _io_out_bits_store_T_24; // @[package.scala:39:86] assign _io_out_bits_store_T_24 = _GEN; // @[package.scala:39:86] wire _classify_out_T_41; // @[package.scala:39:86] assign _classify_out_T_41 = _GEN; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_27 = _toint_ieee_T_26 ? _toint_ieee_T_18 : _toint_ieee_T_10; // @[package.scala:39:{76,86}] wire _GEN_0 = in_typeTagOut == 2'h2; // @[package.scala:39:86] wire _toint_ieee_T_28; // @[package.scala:39:86] assign _toint_ieee_T_28 = _GEN_0; // @[package.scala:39:86] wire _io_out_bits_store_T_26; // @[package.scala:39:86] assign _io_out_bits_store_T_26 = _GEN_0; // @[package.scala:39:86] wire _classify_out_T_43; // @[package.scala:39:86] assign _classify_out_T_43 = _GEN_0; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_29 = _toint_ieee_T_28 ? _toint_ieee_T_25 : _toint_ieee_T_27; // @[package.scala:39:{76,86}] wire _toint_ieee_T_30 = &in_typeTagOut; // @[package.scala:39:86] wire [63:0] toint_ieee = _toint_ieee_T_30 ? _toint_ieee_T_25 : _toint_ieee_T_29; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire _intType_T = in_fmt[0]; // @[FPU.scala:466:21, :479:35] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN | io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 | _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded = {io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T = io_out_bits_store_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = io_out_bits_store_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = io_out_bits_store_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi = {_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded = {io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = io_out_bits_store_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T = io_out_bits_store_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_1 = io_out_bits_store_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_2 = &_io_out_bits_store_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_3 = io_out_bits_store_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_4 = _io_out_bits_store_prevUnrecoded_T_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded : _io_out_bits_store_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded = {_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[15:0]; // @[FPU.scala:446:10, :480:82] wire [31:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [63:0] _io_out_bits_store_T_8 = {2{_io_out_bits_store_T_7}}; // @[FPU.scala:480:49] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN | io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 | _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_1 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = io_out_bits_store_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = io_out_bits_store_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = io_out_bits_store_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_1 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_6 = io_out_bits_store_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_7 = &_io_out_bits_store_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_9 = _io_out_bits_store_prevUnrecoded_T_7 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_1 : _io_out_bits_store_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_9 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_11 = &_io_out_bits_store_T_10; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_12 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_13 = _io_out_bits_store_T_11 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_12; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_14 = {_io_out_bits_store_T_9, _io_out_bits_store_T_13}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_15 = _io_out_bits_store_T_14[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_16 = {2{_io_out_bits_store_T_15}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_2 = _io_out_bits_store_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_2_isZero = io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_2_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_2_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_2_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_2_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_2_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_4 = io_out_bits_store_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_2 = _io_out_bits_store_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = _io_out_bits_store_unrecoded_denormFract_T_4 >> io_out_bits_store_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_2 = _io_out_bits_store_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_12 = io_out_bits_store_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_14 = _io_out_bits_store_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_15 = io_out_bits_store_unrecoded_isSubnormal_2 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_16 = io_out_bits_store_unrecoded_rawIn_2_isNaN | io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_17 = {11{_io_out_bits_store_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_2 = _io_out_bits_store_unrecoded_expOut_T_15 | _io_out_bits_store_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_5 = io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? io_out_bits_store_unrecoded_denormFract_2 : _io_out_bits_store_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_2 = {io_out_bits_store_unrecoded_rawIn_2_sign, io_out_bits_store_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_2 = {io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_2 = {_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_2 = {io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = io_out_bits_store_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevRecoded_2[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_2 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = io_out_bits_store_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = io_out_bits_store_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = io_out_bits_store_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_2 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_11 = io_out_bits_store_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_12 = &_io_out_bits_store_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_13 = io_out_bits_store_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_14 = _io_out_bits_store_prevUnrecoded_T_12 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_2 : _io_out_bits_store_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_2 = {_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_17 = io_out_bits_store_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_19 = &_io_out_bits_store_T_18; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_20 = io_out_bits_store_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_21 = _io_out_bits_store_T_19 ? io_out_bits_store_prevUnrecoded_2 : _io_out_bits_store_T_20; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_22 = {_io_out_bits_store_T_17, _io_out_bits_store_T_21}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_23 = _io_out_bits_store_T_22; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_25 = _io_out_bits_store_T_24 ? _io_out_bits_store_T_16 : _io_out_bits_store_T_8; // @[package.scala:39:{76,86}] wire [63:0] _io_out_bits_store_T_27 = _io_out_bits_store_T_26 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_25; // @[package.scala:39:{76,86}] wire _io_out_bits_store_T_28 = &in_typeTagOut; // @[package.scala:39:86] assign _io_out_bits_store_T_29 = _io_out_bits_store_T_28 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_27; // @[package.scala:39:{76,86}] assign io_out_bits_store_0 = _io_out_bits_store_T_29; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint_0 = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [62:0] _classify_out_fractOut_T = {classify_out_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] classify_out_fractOut = _classify_out_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T | _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[16]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[15:13]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [3:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[13:10]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 4'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_1 = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN_1; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN_1; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T | _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 | _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [75:0] _classify_out_fractOut_T_1 = {classify_out_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut_1 = _classify_out_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode_1 = classify_out_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T_3 = {1'h0, classify_out_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_4 = _classify_out_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_5 = {1'h0, _classify_out_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase_1 = _classify_out_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T_6 = classify_out_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_7 = classify_out_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_8 = _classify_out_expOut_T_6 | _classify_out_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_9 = classify_out_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_10 = {classify_out_expOut_expCode_1, _classify_out_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_11 = classify_out_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut_1 = _classify_out_expOut_T_8 ? _classify_out_expOut_T_10 : _classify_out_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi_2 = {classify_out_sign_2, classify_out_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T_14 = {classify_out_hi_2, classify_out_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_3 = _classify_out_T_14[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code_1 = _classify_out_T_14[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T_1 = _classify_out_T_14[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_2 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_2; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_2; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 | _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 | _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T_1 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_15 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_16 = classify_out_isInf_1 & _classify_out_T_15; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_17 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_18 = classify_out_isNormal_1 & _classify_out_T_17; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_19 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_20 = classify_out_isSubnormal_1 & _classify_out_T_19; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_21 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_22 = classify_out_isZero_1 & _classify_out_T_21; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_23 = classify_out_isZero_1 & classify_out_sign_3; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_24 = classify_out_isSubnormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_25 = classify_out_isNormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_26 = classify_out_isInf_1 & classify_out_sign_3; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_25, _classify_out_T_26}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_22, _classify_out_T_23}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_24}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_18, _classify_out_T_20}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_16}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_3 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_27 = {classify_out_hi_3, classify_out_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_2 = classify_out_code_2[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_2 = &classify_out_codeHi_2; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_2 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_2 = _classify_out_isHighSubnormalIn_T_2 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_6 = classify_out_code_2 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_3 = classify_out_codeHi_2 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_7; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_7 = _GEN_3; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_8; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_8 = _GEN_3; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_8 = _classify_out_isSubnormal_T_7 & classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_2 = _classify_out_isSubnormal_T_6 | _classify_out_isSubnormal_T_8; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_9 = ~classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_10 = _classify_out_isNormal_T_8 & _classify_out_isNormal_T_9; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_11 = classify_out_codeHi_2 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_2 = _classify_out_isNormal_T_10 | _classify_out_isNormal_T_11; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_2 = classify_out_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_4 = classify_out_code_2[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_5 = ~_classify_out_isInf_T_4; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_2 = classify_out_isSpecial_2 & _classify_out_isInf_T_5; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_2 = &classify_out_code_2; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_4 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_5 = ~_classify_out_isSNaN_T_4; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_2 = classify_out_isNaN_2 & _classify_out_isSNaN_T_5; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_2 = classify_out_isNaN_2 & _classify_out_isQNaN_T_2; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_28 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_29 = classify_out_isInf_2 & _classify_out_T_28; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_30 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_31 = classify_out_isNormal_2 & _classify_out_T_30; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_32 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_33 = classify_out_isSubnormal_2 & _classify_out_T_32; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_34 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_35 = classify_out_isZero_2 & _classify_out_T_34; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_36 = classify_out_isZero_2 & classify_out_sign_4; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_37 = classify_out_isSubnormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_38 = classify_out_isNormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_39 = classify_out_isInf_2 & classify_out_sign_4; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_2 = {_classify_out_T_38, _classify_out_T_39}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_2 = {_classify_out_T_35, _classify_out_T_36}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_2 = {classify_out_lo_hi_hi_2, _classify_out_T_37}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_2 = {classify_out_lo_hi_2, classify_out_lo_lo_2}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_2 = {_classify_out_T_31, _classify_out_T_33}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_2 = {classify_out_isQNaN_2, classify_out_isSNaN_2}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_2 = {classify_out_hi_hi_hi_2, _classify_out_T_29}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_4 = {classify_out_hi_hi_2, classify_out_hi_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_40 = {classify_out_hi_4, classify_out_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_42 = _classify_out_T_41 ? _classify_out_T_27 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [9:0] _classify_out_T_44 = _classify_out_T_43 ? _classify_out_T_40 : _classify_out_T_42; // @[package.scala:39:{76,86}] wire _classify_out_T_45 = &in_typeTagOut; // @[package.scala:39:86] wire [9:0] classify_out = _classify_out_T_45 ? _classify_out_T_40 : _classify_out_T_44; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} | _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = |_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} | _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags ? ~in_ren2 & cvtType : ~(in_rm[0]) & _intType_T; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = |_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T | _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc_0 = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt | _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt_0 = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] in_in3 <= io_in_bits_in3_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN_5 dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64_5 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32_5 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] assign io_out_bits_lt = io_out_bits_lt_0; // @[FPU.scala:453:7] assign io_out_bits_store = io_out_bits_store_0; // @[FPU.scala:453:7] assign io_out_bits_toint = io_out_bits_toint_0; // @[FPU.scala:453:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:453:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_393 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_137 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_393( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_137 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule